Electroluminescent display

Abstract

The present disclosure relates to an electroluminescent display. The electroluminescent display according to the present disclosure includes a pixel disposed on a substrate, a low resistance line disposed on one side of the pixel, a passivation layer on the low resistance line covering the entire substrate, a planarization layer on the passivation layer covering the entire substrate, a cathode contact hole exposing some of the low resistance line, an anode electrode disposed on the planarization layer, an undercut trench formed at the planarization layer disposed between the anode electrode and the cathode contact hole, a bank covering a peripheral area of the anode electrode, an emission layer on the bank, the anode electrode, and the planarization layer, and a cathode electrode on the emission layer, wherein the cathode electrode is connected to the low resistance line through the cathode contact hole.

Description

Technical Field

[0001] This disclosure relates to electroluminescent displays. In particular, this disclosure relates to an electroluminescent display that exhibits improved image quality stability by eliminating or blocking lateral leakage current between adjacent pixels. Additionally, this disclosure relates to an electroluminescent display that exhibits improved image quality stability by reducing the resistance of the cathode electrode employing an auxiliary cathode line. Background Technology

[0002] Recently, various types of displays, such as cathode ray tubes (CRTs), liquid crystal displays (LCDs), plasma display panels (PDPs), and electroluminescent displays, have been developed. These various types of displays are used to display image data of various products, such as computers, mobile phones, bank ATMs, and vehicle navigation systems, according to their unique characteristics and purposes.

[0003] Specifically, organic light-emitting diode (OLED) displays, as self-emissive displays, possess excellent optical performance such as wide viewing angles and high color reproduction, and their application areas are gradually expanding, thus making them a focus of high-quality image display devices. Due to these advantages, they have attracted considerable attention as the most suitable display device for achieving ultra-high resolution displays exceeding 4K (8K). As resolution increases, the size of the emission area occupied by a pixel also decreases. To maximize the size of the emission area, a top-emitting structure is preferred.

[0004] In top-emitting displays that offer advantages over ultra-high resolution, a transparent conductive material is preferably used for the cathode electrode. However, because transparent conductive materials have a higher sheet resistance than metallic materials, maintaining a constant cathode voltage can be difficult when implementing large-area display devices. Therefore, in large-area electroluminescent displays with top emission, a structure for connecting to signal lines with low resistance may be necessary to reduce the sheet resistance of the cathode electrode.

[0005] Furthermore, as resolution increases, the distance between pixels in an electroluminescent display becomes narrower. In this case, electrons or holes may leak laterally (or horizontally) along the functional layers, including the emitting layer (or light-emitting layer) between neighboring pixels. As a result, inaccurate color reproduction may occur.

[0006] To achieve a top-emitting electroluminescent display with large area and ultra-high resolution, many conditions must be considered, and image quality degradation can occur when not all of these conditions are met. Therefore, there is an increasing need to develop an electroluminescent display with a novel structure that achieves large area, ultra-high resolution, and does not result in image quality degradation. Summary of the Invention

[0007] To address the aforementioned problems, the present disclosure aims to provide an electroluminescent display with a large area, ultra-high resolution, and excellent image quality. Another object of the present disclosure is to provide an electroluminescent display in which the cathode voltage can be maintained constant in a top-emitting display suitable for achieving an ultra-high resolution structure. Yet another object of the present disclosure is to provide an ultra-high resolution electroluminescent display that minimizes the effects of parasitic currents between densely arranged pixels.

[0008] To achieve the above-mentioned objectives of this disclosure, the electroluminescent display according to this disclosure includes: a pixel disposed on a substrate; a low-resistance line disposed on one side of the pixel; a passivation layer on the low-resistance line covering the entire substrate; a planarization layer on the passivation layer covering the entire substrate; a cathode contact hole exposing a portion of the low-resistance line; an anode electrode disposed on the planarization layer; an undercut trench formed in the planarization layer between the anode electrode and the cathode contact hole; a dam covering the outer peripheral region of the anode electrode; an emission layer on the dam, the anode electrode, and the planarization layer; and a cathode electrode on the emission layer, wherein the cathode electrode is connected to the low-resistance line through the cathode contact hole.

[0009] In an example implementation, the electroluminescent display further includes pixel trenches formed by removing a portion of a planarization layer around the outer anode electrode.

[0010] In the example implementation, the emission layer extends to neighboring pixels through pixel trenches.

[0011] In the example implementation, cathode contact holes are formed in some areas where they overlap with low-resistance lines at the pixel trench.

[0012] In an example implementation, the cathode contact hole includes: a first hole formed at the passivation layer and having a first width; and a second hole formed at the planarization layer and having a second width narrower than the first width. An emitter layer is disposed on a number of low-resistance lines exposed corresponding to the second width. A cathode electrode is connected to the low-resistance lines exposed corresponding to the first width.

[0013] In the example implementation, the ratio of the depth of the undercut trench to the thickness of the planarization layer is any one of 1:1 to 3:4.

[0014] In the example implementation, a dam is disposed between the anode electrode and the undercut trench.

[0015] In an example implementation, the dike fills the bottom trench and covers a portion of the flattening layer.

[0016] In the example implementation, the embankment does not cover the portion of the flattening layer between the undercut trench and the cathode contact hole.

[0017] In an example implementation, the electroluminescent display further includes a thin-film transistor disposed beneath a passivation layer and connected to an anode electrode.

[0018] Additionally, the electroluminescent display according to this disclosure includes: a first pixel and a second pixel disposed adjacent to each other on a substrate; a low-resistance line disposed between the first pixel and the second pixel; a passivation layer on the low-resistance line and covering the substrate; a first planarization layer disposed on the passivation layer at the first pixel; a second planarization layer disposed on the passivation layer at the second pixel; a first anode electrode on the first planarization layer; a second anode electrode on the second planarization layer; a cathode contact hole exposing a portion of the low-resistance line between the first planarization layer and the second planarization layer; a first undercut trench formed on the first planarization layer between the first anode electrode and the cathode contact hole; a second undercut trench formed on the second planarization layer between the second anode electrode and the cathode contact hole; a first dam covering the outer peripheral region of the first anode electrode; a second dam covering the outer peripheral region of the second anode electrode; an emission layer on the first dam, the second dam, the first anode electrode, the second anode electrode, the first planarization layer, and the second planarization layer; and a cathode electrode on the emission layer, wherein the cathode electrode is connected to the low-resistance line through the cathode contact hole.

[0019] In an example implementation, the electroluminescent display further includes a pixel trench disposed between a first planarization layer and a second planarization layer, and exposing a passivation layer.

[0020] In the example implementation, the emission layer extends from the first pixel to the second pixel via a pixel trench.

[0021] In the example implementation, the cathode contact hole is formed in some portions of the pixel trench that overlap with the low-resistance line.

[0022] In an example embodiment, the cathode contact hole includes: a first hole formed at the passivation layer and having a first width; and a second hole formed between a first planarization layer and a second planarization layer and having a second width narrower than the first width. An emitter layer is disposed on a number of low-resistance lines exposed corresponding to the second width. A cathode electrode is connected to the low-resistance lines exposed corresponding to the first width.

[0023] In the example implementation, the ratio of the depth of the undercut trench to the thickness of the first planarization layer and the ratio of the depth of the undercut trench to the thickness of the second planarization layer are any one of 1:1 to 3:4.

[0024] In the example implementation, the first dike exposes a first undercut trench and a first planarization layer. The second dike exposes a second undercut trench and a second planarization layer.

[0025] In the example implementation, the first dike fills a first undercut trench. The second dike fills a second undercut trench.

[0026] In the example implementation, the first dike does not cover some of the first planarization layer between the first undercut trench and the cathode contact hole. The second dike does not cover some of the second planarization layer between the second undercut trench and the cathode contact hole.

[0027] In another embodiment, an electroluminescent display includes: a first pixel including a first transistor and a first light-emitting diode, the first light-emitting diode including a first anode, a first emitting layer, and a cathode; a second pixel including a second transistor and a second light-emitting diode, the second light-emitting diode including a second anode, a second emitting layer, and a cathode; a passivation layer covering the first transistor and the second transistor; a planarization layer between the passivation layer and the first and second light-emitting diodes; a low-resistance line between the first pixel and the second pixel; a cathode contact hole between the first pixel and the second pixel, the cathode contact hole being formed through the planarization layer and through a portion of the passivation layer and exposing a portion of the low-resistance line; and a dummy emitting layer formed in the cathode contact hole on the portion of the low-resistance line exposed through the cathode contact hole, the dummy emitting layer being electrically disconnected from the first and second emitting layers, wherein a cathode is continuously formed on the dummy emitting layer, the portion of the low-resistance line, and the sidewall of the cathode contact hole.

[0028] The electroluminescent display may further include: a first dam between the first pixel and the cathode contact hole; a second dam between the second pixel and the cathode contact hole; a first undercut trench formed in a planarization layer between the first dam and the cathode contact hole, the first undercut trench being spaced apart from the cathode contact hole; and a second undercut trench formed in a planarization layer between the second dam and the cathode contact hole, the second undercut trench being spaced apart from the cathode contact hole.

[0029] In some embodiments, the first dike fills the first undercut trench and the second dike fills the second undercut trench. In another embodiment, the first and second undercut trenches expose the passivation layer.

[0030] The electroluminescent display according to this disclosure provides a top-emitting electroluminescent display that maximizes the aperture ratio of the emitting region to the pixel region to achieve ultra-high resolution. By forming pixel trenches by removing the planarization layer between pixels, this disclosure also provides a structure capable of suppressing lateral leakage current between pixels, even when the gap between pixels narrows as ultra-high resolution is achieved. Therefore, there is no image quality degradation due to leakage current, even at ultra-high resolution. Furthermore, when realizing a top-emitting large-area electroluminescent display with a large diagonal area, the thin-film resistance of the cathode electrode can be maintained constant over the entire area of ​​the display. As a result, stable image quality can be provided by maintaining a constant cathode voltage even in a large-area electroluminescent display. That is, the electroluminescent display according to this disclosure can provide excellent image quality in both ultra-high resolution and large-area electroluminescent displays. Attached Figure Description

[0031] The accompanying drawings are included to provide a further understanding of this disclosure and are incorporated in and constitute a part of this application. The drawings illustrate embodiments of the disclosure and, together with the description, serve to illustrate the principles of the disclosure. In the drawings: Figure 1 This is a plan view showing a schematic structure of an electroluminescent display according to the present disclosure.

[0032] Figure 2 This is a circuit diagram illustrating the structure of a sub-pixel included in an electroluminescent display according to the present disclosure.

[0033] Figure 3 It is shown as follows Figure 1 A magnified planar view of the structure between two adjacent pixels arranged as shown.

[0034] Figure 4 It is along Figure 3 The cross-sectional view along the cutting line I-I' is used to illustrate an electroluminescent display according to a preferred embodiment of the present disclosure.

[0035] Figure 5 yes Figure 4 An enlarged cross-sectional view of the circular portion "M" in the image.

[0036] Figure 6 yes Figure 4 An enlarged cross-sectional view of the circular portion "N" in the image.

[0037] Figure 7 This is an enlarged cross-sectional view showing the structure of an electroluminescent display without undercut grooves according to the present disclosure.

[0038] Figure 8 This is a cross-sectional view showing the structure of an undercut trench according to another example of this disclosure.

[0039] Figure 9 This is an enlarged cross-sectional view showing the structure in which the embankment and planarization layer are formed in the same pattern in an electroluminescent display according to the present disclosure.

[0040] Figure 10 This is a cross-sectional view showing the structure of an undercut groove according to another embodiment of the present disclosure.

[0041] Figure 11 This is a cross-sectional view showing the structure of an undercut groove according to another embodiment of the present disclosure.

[0042] Figure 12 This is a plan view showing the structure of an electroluminescent display according to another embodiment of the present disclosure. Detailed Implementation

[0043] The advantages and features of this disclosure, and its implementation methods, will be illustrated by the following embodiments described with reference to the accompanying drawings. However, this disclosure may be embodied in various forms and should not be construed as limited to the embodiments set forth herein. Rather, these exemplary embodiments are provided to make this disclosure sufficiently thorough and complete to assist those skilled in the art in fully understanding its scope. Furthermore, the scope of protection of this disclosure is defined by the claims and their equivalents.

[0044] The shapes, sizes, ratios, angles, quantities, etc., shown in the accompanying drawings to describe various exemplary embodiments of this disclosure are given by way of example only. Therefore, this disclosure is not limited to the details shown. Unless otherwise specified, similar reference numerals denote similar elements throughout the specification. In the following description, detailed descriptions of related known functions or configurations may be omitted where such detailed descriptions might unnecessarily obscure the focus of this disclosure.

[0045] Exemplary embodiments of this disclosure will now be described in detail with reference to the accompanying drawings. Wherever possible, the same reference numerals will be used throughout the drawings to denote the same or similar parts. It should be noted in this specification that similar reference numerals already used to denote similar elements in other figures will be used for elements where possible. In the following description, detailed descriptions of functions and configurations known to those skilled in the art that are not related to the basic configuration of this disclosure will be omitted. The terminology described in this specification should be understood as follows.

[0046] In this specification, where terms such as “comprising,” “having,” “including,” etc. are used, one or more other elements may be added unless a term such as “only” is used. Elements described in the singular are intended to include multiple elements, and vice versa, unless the context clearly indicates otherwise.

[0047] When interpreting a component, it is interpreted as including a range of errors or tolerances, even if no explicit description of such a range of errors or tolerances is provided.

[0048] In the description of various embodiments of this disclosure, when describing positional relationships, for example, when using terms such as "on," "above," "below," "over," "below," "near," or "beside" to describe the positional relationship between two parts, one or more other parts may be located between the two parts, unless more restrictive terms such as "close to," "directly," or "adjacent to" are used. For example, when an element or layer is disposed "on" another element or layer, a third layer or element may be inserted between them. Furthermore, if a first element is described as being "on" a second element, it does not necessarily mean that the first element is located above the second element in the drawing. The upper and lower parts of the related object may change depending on the orientation of the object. Therefore, when a first element is described as being "on" a second element, depending on the orientation of the object, in the drawing or in the actual configuration, the first element may be located "below" or "above" the second element.

[0049] When describing temporal relationships, discontinuous situations may be included when the temporal order is described as such as “after,” “following,” “next,” or “before,” unless more restrictive terms such as “just,” “immediately,” or “directly” are used.

[0050] It will be understood that although the terms “first,” “second,” etc., may be used herein to describe various elements, these elements should not be limited by these terms, as they are not used to define a particular order. These terms are used only to distinguish one element from another. For example, without departing from the scope of this disclosure, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element.

[0051] In describing the various elements in this disclosure, terms such as first, second, A, B, (a), and (b) may be used. These terms are used only to distinguish one element from another and not to define a particular nature, order, sequence, or number of elements. Where an element is described as “linked,” “connected,” or “attached” to another element, unless otherwise specified, the element may be directly or indirectly connected to that other element. It will be understood that an additional element may be “inserted” between two elements described as “linked,” “connected,” or “attached” to each other.

[0052] It should be understood that the term "at least one" should be interpreted as including any and all combinations of one or more of the related listed items. For example, the meaning of "at least one of the first element, the second element, and the third element" covers combinations of all three listed elements, combinations of any two of the three elements, and the individual elements, the first element, the second element, and the third element.

[0053] Features of the various embodiments of this disclosure may be partially or wholly linked or combined with each other, and may interoperate differently with each other and be driven in a manner that will be fully understood by those skilled in the art. Embodiments of this disclosure may be implemented independently of each other, or may be implemented together in an interdependent relationship.

[0054] Hereinafter, examples of display devices according to the present disclosure will be described in detail with reference to the accompanying drawings. Wherever possible, the same reference numerals will be used throughout the drawings to denote the same or similar parts. Since the scales of the various elements shown in the drawings may differ from actual scales for ease of description, the present disclosure is not limited to the scales shown in the figures.

[0055] The present disclosure will now be described with reference to the accompanying drawings. Figure 1 This is a plan view illustrating a schematic structure of an electroluminescent display according to the present disclosure. Figure 1 In this diagram, the X-axis refers to the direction parallel to the scan lines, the Y-axis refers to the direction of the data lines, and the Z-axis refers to the height of the display device.

[0056] Reference Figure 1 The electroluminescent display includes a substrate 110, a gate (or scan) driver 200, a data pad portion 300, a source driver IC (integrated circuit) 410, a flexible film 430, a circuit board 450, and a timing controller 500.

[0057] The substrate 110 may include an electrically insulating material or a flexible material. The substrate 110 may be made of glass, metal, or plastic, but is not limited to these. When the electroluminescent display is a flexible display, the substrate 110 may be made of a flexible material such as plastic. For example, the substrate 110 may include a transparent polyimide material.

[0058] The substrate 110 may include a display area DA and a non-display area NDA. The display area DA, as the area used to represent a video image, may be defined as the majority of the central area of ​​the substrate 110, but is not limited thereto. Within the display area DA, multiple scan lines (or gate lines), multiple data lines, and multiple pixels P may be formed or disposed. Each pixel may include multiple sub-pixels SP. Each sub-pixel includes both scan lines and data lines. For example, a pixel P may include three or four sub-pixels SP.

[0059] As an area that does not represent a video image, the non-display area NDA can be defined in the outer peripheral region of the substrate 110 surrounding all or some of the display area DA. A gate driver 200 and a data pad portion 300 may be formed or disposed in the non-display area NDA.

[0060] The gate driver 200 can supply scan (or strobe) signals to the scan lines according to the gate control signal received from the timing controller 500. The gate driver 200 can be formed at a non-display area NDA outside the display area DA on the substrate 110, as a GIP (in-panel gate driver) type. GIP type means that the gate driver 200 is formed directly on the substrate 110.

[0061] The data pad portion 300 can supply data signals to the data lines according to the data control signals received from the timing controller 500. The data pad portion 300 can be fabricated as a driver chip and mounted on the flexible film 430. In addition, the flexible film 430 can be attached to the non-display area NDA on either side of the display area DA on the substrate 110, as a TAB (tape auto-bonding) type.

[0062] The source driver IC 410 receives digital video data and source control signals from the timing controller 500. The source driver IC 410 converts the digital video data into analog data voltages based on the source control signals and then supplies them to the data lines. When the source driver IC 410 is manufactured as a chip, it can be mounted on a flexible film 430 as a COF (chip-on-film) or COP (chip-on-plastic) type.

[0063] The flexible film 430 may include multiple first connection lines connecting the data pad portion 300 to the source driver IC 410 and multiple second connection lines connecting the data pad portion 300 to the circuit board 450. The flexible film 430 may be attached to the data pad portion 300 using an anisotropic conductive film, so that the data pad portion 300 can be connected to the first connection lines of the flexible film 430.

[0064] The circuit board 450 may be attached to the flexible film 430. The circuit board 450 may include multiple circuits implemented as driver chips. For example, the circuit board 450 may be a printed circuit board or a flexible printed circuit board.

[0065] The timing controller 500 can receive digital video data and timing signals from an external system board via cables from the circuit board 450. The timing controller 500 can generate gate control signals for controlling the operating timing of the gate driver 200 and source control signals for controlling the source driver IC 410 based on the timing signals. The timing controller 500 can supply gate control signals to the gate driver 200 and source control signals to the source driver IC 410. Depending on the product type, the timing controller 500 and the source driver IC 410 can be integrated into a single chip and mounted on the substrate 110.

[0066] For reference Figure 1 The planar structure of the pixel array P shown in this disclosure allows the electroluminescent display to have multiple pixels P arranged in a matrix. Each pixel P may include four sub-pixels SP. For example, a pixel P may include a red sub-pixel SPR, a green sub-pixel SPG, a blue sub-pixel SPB, and a white sub-pixel SPW. However, it is not limited to this; a pixel P may include three or five sub-pixels SP. The sub-pixels SP may be arranged at a predetermined distance (or gap) from each other. Furthermore, the pixels P may be arranged at a predetermined distance (or gap) from each other. Figure 1 An exemplary array is shown where the pixel gap between pixels P can be wider than the subpixel gap between subpixels SP. Alternatively, all subpixels SP can be arranged by subpixel gap without distinguishing between pixel gaps and subpixel gaps.

[0067] Figure 2 This is a circuit diagram illustrating the structure of a sub-pixel included in an electroluminescent display according to the present disclosure. Figure 3 It is shown as follows Figure 1 A magnified planar view of the structure between two adjacent pixels arranged as shown. Figure 4 It is along Figure 3 The cross-sectional view along cutting line I-I' is used to illustrate an electroluminescent display according to a preferred embodiment of the present disclosure. Specifically, Figure 3 Show focus Figure 1 The planar structure of the circular part "J" in the image.

[0068] Reference Figures 2 to 3 A sub-pixel SP of a light-emitting display may be defined by a scan line SL, a data line DL, and a drive current line VDD. A sub-pixel SP of a light-emitting display may include a switching thin-film transistor ST, a driving thin-film transistor DT, a light-emitting diode OLE, and a storage capacitor Cst. The drive current line VDD may be supplied with a high-level voltage to drive the light-emitting diode OLE.

[0069] The switching thin-film transistor ST and the driving thin-film transistor DT can be formed on the substrate SUB. For example, the switching thin-film transistor ST can be disposed at the intersection of the scan line SL and the data line DL. The switching thin-film transistor ST may include a switching gate electrode SG, a switching source electrode SS, and a switching drain electrode SD. The switching gate electrode SG may be connected to the scan line SL, or a part of the scan line SL, such as... Figure 3 As shown. The switching source electrode SS can be connected to the data line DL, and the switching drain electrode SD can be connected to the driving thin-film transistor DT. By supplying a data signal to the driving thin-film transistor DT, the switching thin-film transistor ST can select the pixel to be driven.

[0070] The driving thin-film transistor (DT) functions to drive the light-emitting diode (OLE) of the pixel selected by the switching thin-film transistor (ST). The driving DT may include a driving gate electrode (DG), a driving source electrode (DS), and a driving drain electrode (DD). The driving gate electrode (DG) may be connected to the switching drain electrode (SD) of the switching DT. For example, the driving gate electrode (DG) may be connected to the switching drain electrode (SD) via a drain contact hole (DH) penetrating the gate insulating layer (GI). The driving source electrode (DS) may be connected to the driving current line (VDD), and the driving drain electrode (DD) may be connected to the anode electrode (ANO) of the OLE. A storage capacitor (Cst) may be disposed between the driving gate electrode (DG) of the driving DT and the anode electrode (ANO) of the OLE.

[0071] The driving thin-film transistor DT can be positioned between the driving current line VDD and the light-emitting diode OLE. The driving thin-film transistor DT can control the amount of current flowing from the driving current line VDD to the light-emitting diode OLE based on the voltage level of the driving gate electrode DG connected to the switching drain electrode SD of the switching thin-film transistor ST.

[0072] A light-emitting diode (OLE) may include an anode electrode ANO, an emitter layer EL, and a cathode electrode CAT. The OLE emits light according to the amount of current controlled by a driving thin-film transistor (TFT) DT. In other words, the OLE can be driven by the voltage difference between a low-level voltage and a high-level voltage controlled by the TFT DT. The anode electrode ANO of the OLE can be connected to the driving drain electrode DD of the TFT DT, and the cathode electrode CAT can be connected to a low-level voltage line Vss that supplies the low-level potential voltage. That is, the OLE can be driven by a high-level voltage controlled by the TFT DT and a low-level voltage supplied from the low-level voltage line Vss.

[0073] The following is a further enlarged reference. Figure 1 The circular part "J" in Figure 3 and Figure 4The connection structure of the low-resistance line and the cathode electrode will be described. Semiconductor layers SA and DA may be formed on substrate 110. The semiconductor layers may include the switching semiconductor layer SA of the switching thin-film transistor ST and the driving semiconductor layer DA of the driving thin-film transistor DT. A gate insulating layer GI is deposited on the semiconductor layers SA and DA to cover the entire substrate 110.

[0074] Gate electrodes SG and DG may be formed on a gate insulating layer GI that overlaps with the gate line SL and semiconductor layers SA and DA. The gate electrodes may include a switching gate electrode SG of a switching thin-film transistor ST and a driving gate electrode DG of a driving thin-film transistor DT. The switching gate electrode SG may branch from the gate line SL or may be defined as a part of the gate line SL. An intermediate insulating layer ILD may be deposited on the gate line SL and the gate electrodes SG and DG to cover the entire substrate 110.

[0075] On the intermediate insulating layer (ILD), source electrodes SS and DS, drain electrodes SD and DD, a low-resistance line LL, a data line DL, and a drive current line VDD can be disposed. The source electrodes may include the switching source electrode SS of the switching thin-film transistor ST and the driving source electrode DS of the driving thin-film transistor DT. The drain electrodes may include the switching drain electrode SD of the switching thin-film transistor ST and the driving drain electrode DD of the driving thin-film transistor DT. The source electrodes SS and DS may contact one side of the semiconductor layers SA and DA via contact holes penetrating the intermediate insulating layer (ILD) and the gate insulating layer (GI). The drain electrodes SD and DD may contact the other side of the semiconductor layers SA and DA via another contact hole penetrating the intermediate insulating layer (ILD) and the gate insulating layer (GI).

[0076] The switching source electrode SS can branch from the data line DL. The switching drain electrode SD can be connected to the driving gate electrode DG and the driving thin-film transistor DT. The driving source electrode DS can branch from the driving current line VDD. The low-resistance line LL can be positioned between two adjacent pixel columns. In some cases, one low-resistance line LL can be positioned every two or three pixel columns. The low-resistance line LL can be connected to the cathode electrode CAT of the light-emitting diode OLE. Otherwise, the low-resistance line LL can be connected to the low-voltage line VSS. In some cases, the low-resistance line LL can be the low-voltage line VSS.

[0077] A passivation layer PAS can be deposited on a substrate 110 having thin-film transistors ST and DT. The passivation layer PAS can be made of an inorganic material including silicon oxide or silicon nitride. A planarization layer PL can be deposited on the passivation layer PAS. The planarization layer PL can be a thin film used to planarize the non-uniform surface of the substrate 110 on which the thin-film transistors ST and DT are formed. To planarize the non-uniform surface of the substrate 110, the planarization layer PL can be formed of an organic material. The passivation layer PAS and the planarization layer PL may include pixel contact holes PH that expose some portions of the drive drain electrode DD of the driving thin-film transistor DT.

[0078] The anode electrode ANO can be formed on the planarization layer PL covering the thin-film transistors ST and DT. The anode electrode ANO can be connected to the driving drain electrode DD of the driving thin-film transistor DT through the pixel contact hole PH formed in the planarization layer PL. Depending on the emission type of the organic light-emitting diode (OLE), the anode electrode ANO can have various structures and different materials. For example, for a bottom-emitting type that can provide light from the emitting layer EL to the substrate 110, the anode electrode ANO can be made of a transparent conductive material. For example, the anode electrode ANO of the bottom-emitting type can include oxide conductive materials such as indium zinc oxide (or IZO) or indium tin oxide (or ITO). As another example, for a top-emitting type that can provide light in the upward direction opposite to the substrate 110, the anode electrode ANO can be made of a metallic material with excellent light reflectivity.

[0079] A dam BA can be formed on the anode electrode ANO. The dam BA can cover the outer peripheral region of the anode electrode ANO and expose most of the central region of the anode electrode ANO, thus defining the emission region. In other words, the dam BA can cover a portion of the top surface at the edge of the top surface of the anode electrode ANO and the corresponding portion of the side surface, and expose most of the central region of the anode electrode ANO, so the dam BA can... Figure 4 The indicated launch area is defined.

[0080] An emitting layer EL may be deposited on the anode electrode ANO and the diaphragm BA. The emitting layer EL may also be deposited over the entire surface of the display area DA on the substrate 110, covering the anode electrode ANO and the diaphragm BA. For example, the emitting layer EL may include two or more stacked emitting portions for emitting white light. Specifically, the emitting layer EL may include a first emitting layer providing a first color of light and a second emitting layer providing a second color of light for emitting white light by combining the first color light and the second color light.

[0081] For example, the emitting layer EL may include any one of a blue emitting layer, a green emitting layer, and a red emitting layer to provide a light color corresponding to the color assigned at the pixel. Additionally, the light-emitting diode (OLE) may include functional layers to enhance the luminous efficiency and / or lifetime of the emitting layer EL.

[0082] The cathode electrode CAT can be disposed on the emitter layer EL. The cathode electrodes CAT can be stacked on the emitter layer EL to make surface contact with each other. The cathode electrodes CAT can be formed as a sheet element over the entire area of ​​the substrate 110 to collectively connect to the entire emitter layer EL disposed at all pixels. In the case of a bottom-emitting type, the cathode electrode CAT can comprise a metallic material with excellent light reflectance. For example, the cathode electrode CAT can comprise at least one of silver (Ag), aluminum (Al), molybdenum (Mo), titanium (Ti), copper (Cu), gold (Au), magnesium (Mg), calcium (Ca), or barium (Ba).

[0083] The electroluminescent display according to this disclosure may include a subpixel trench PLP formed by patterning a planarization layer PL. The subpixel trench PLP may be configured to surround individual subpixels such that any subpixel SP can be distinguished from its neighboring subpixels SP. On the planarization layer PL surrounded by the subpixel trench PLP, one of an anode electrode ANO and a dam BA is present. The dam BA may be disposed between an end of the anode electrode ANO and an end of the planarization layer PL surrounded by the subpixel trench PLP. That is, the dam BA may have a structure patterned along the outer periphery of the anode electrode ANO. Here, when a subpixel is used as a basic unit, the term "subpixel trench" is used. When a "subpixel" can be referred to as a "pixel" and a "pixel" is described as a basic unit, it can be referred to as a "pixel trench".

[0084] Additionally, the electroluminescent display according to this disclosure may include a cathode contact hole CON for connecting a low-resistance line LL and a cathode electrode CAT. The cathode contact hole CON can be formed by penetrating a planarization layer PL and a passivation layer PAS covering the low-resistance line LL. Specifically, the passivation layer PAS stacked beneath the planarization layer PL may have an undercut profile formed by over-etching the planarization layer PL.

[0085] At the cathode contact hole CON with an undercut structure, the emitter layer EL can be deposited only in the middle region of the low-resistance line LL exposed through the cathode contact hole CON. The emitter layer EL may include organic materials. When the emitter layer EL includes organic materials, it may not be stacked on the etched sidewalls at the undercut region, but rather on some exposed areas of the surface. Because this stacked portion is not connected to the emitter layer EL, it is referred to as a "dummy emitter layer DEL". On the other hand, the cathode electrode CAT stacked on the emitter layer EL may also be stacked from the undercut portion to the etched sidewalls and the top surface. As a result, the cathode electrode CAT can extend from a pixel P1 through the cathode contact hole CON to an adjacent pixel P2, and then can be connected to the low-resistance line LL.

[0086] Furthermore, the electroluminescent display according to this disclosure may include an undercut trench TR between the cathode contact hole CON and the dam BA. The undercut trench TR may be an element for preventing damage to the end of the planarization layer PL at the undercut portion forming the cathode contact hole CON.

[0087] The following section will explain in detail the sub-pixel trench PLP, cathode contact hole CON, and undercut trench TR, referring to the enlarged diagram. Figure 5 yes Figure 4 An enlarged cross-sectional view of the circular portion "M" in the image. Figure 6 yes Figure 4 An enlarged cross-sectional view of the circular portion "N" in the image.

[0088] Regardless of whether the emitting layer emits white light or light of different colors allocated to each sub-pixel, the functional layers that are part of the emitting layer can be formed as a common layer covering the entire surface of the substrate. For example, the hole injection layer and hole transport layer stacked directly above the anode electrode ANO, and the electron injection layer and electron transport layer stacked directly below the cathode electrode CAT, can be formed as a continuous common layer covering the BA and sub-pixels SP. That is, most of the emitting layer EL can be stacked on all display areas DA of the substrate 110.

[0089] As pixel density (unit, PPI: pixels per inch), which refers to the number of pixels P arranged per unit length, increases, the size of pixel P decreases, and the distance between adjacent pixels P narrows. In this situation, electrons or charges may move laterally through the functional layers connecting adjacent sub-pixels SP, thus affecting the function and / or operation of adjacent sub-pixels SP. This flow of electrons or charges between adjacent sub-pixels SP can be defined as lateral leakage current (or LLC). As lateral leakage current increases, the color information of the image may be distorted, and therefore the image quality may deteriorate.

[0090] To prevent such image quality degradation, the electroluminescent display according to this disclosure may further include sub-pixel trenches PLP formed by removing portions of the planarization layer PL to distinguish individual sub-pixels SP. The passivation layer PAS stacked beneath the planarization layer PL may be exposed through the sub-pixel trenches PLP. However, this is not a limitation. In other embodiments, the depth of the sub-pixel trenches PLP may be less than the thickness of the planarization layer PL, so that the passivation layer PAS is not exposed.

[0091] By utilizing sub-pixel trenches (PLPs), the emitter layer (EL) stacked on this portion can have longer current paths between adjacent sub-pixels (SPs). For example, as... Figure 5As indicated by the arrows, the path of lateral leakage current along the functional layer connecting adjacent sub-pixels SP can be lengthened. As a result, lateral leakage current transmitted from one sub-pixel SP to adjacent sub-pixels SP can be suppressed, thereby preventing image quality degradation. Specifically, as the depth of the sub-pixel trench PLO increases, the thickness of the emitter layer EL stacked on the etched sidewalls can decrease. In this case, the resistance in the emitter layer EL through which the lateral leakage current travels may increase, making it less likely for the lateral leakage current to flow.

[0092] Next, you can refer to Figure 6 The cross-sectional structure of the cathode contact hole CON and the undercut trench TR is described in detail. In the case of a large-area display with a long diagonal length, the area of ​​the cathode electrode can be increased, and the sheet resistance of the relatively thin cathode electrode can be increased. In the case of a top-emitting type, the cathode electrode CAT can preferably be formed of a transparent conductive material such as ITO (indium tin oxide) or IZO (indium zinc oxide). Compared with metallic materials, ITO and IZO can have relatively high sheet resistance. As the sheet resistance of the cathode electrode increases, the voltage of the cathode electrode may not be able to remain constant across the entire display screen, thus the image quality may be uneven.

[0093] To achieve an ultra-high resolution, large-area electroluminescent display, a top-emitting type is preferred, which ensures a sufficient emitting area with the same brightness using lower power consumption. Therefore, in an ultra-high resolution, large-area electroluminescent display, a low-resistance line LL is preferably included to reduce the sheet resistance of the cathode electrode. The low-resistance line LL can be connected to the cathode electrode CAT stacked on the emitting layer EL to reduce the sheet resistance of the cathode electrode CAT. Specifically, the low-resistance line LL and the cathode electrode CAT are preferably connected via cathode contact holes CON distributed uniformly above the display area.

[0094] Reference Figure 6 According to this disclosure, the electroluminescent display may include a cathode contact hole CON at the planarization layer PL where a light-emitting diode (OLE) can be disposed. By removing portions of the passivation layer PAS covering the low-resistance line LL and the planarization layer PL, the cathode contact hole CON can expose portions of the low-resistance line LL. Specifically, the passivation layer PAS may have a first hole OA1 with a first width W1. The planarization layer PL may have a second hole OA2 with a second width W2. Furthermore, the first width W1 may be wider than the second width W2, and the first hole OA1 and the second hole OA2 are configured such that their center points overlap each other.

[0095] After the anode electrode ANO is patterned to form a dam BA, the planarization layer PL exposed between the dams BA is patterned, and then the passivation layer PAS is etched, a cathode contact hole CON can be formed. Here, the passivation layer PAS can be over-etched to form a first hole OA1 that is wider than the second hole OA2 formed at the planarization layer PL. As a result, the cathode contact hole CON can be formed with an undercut structure.

[0096] After forming the cathode contact hole CON, an emitter layer EL can be deposited on the substrate 110 to cover the entire display area DA. The emitter layer EL can be formed of an organic material. The emitter layer EL can be stacked only on the area vertically exposed through the cathode contact hole CON. Furthermore, in the cathode contact hole CON, the emitter layer EL can be partially stacked on the inclined sidewalls formed by etching the planarization layer PL. The emitter layer EL can be broken at the cathode contact hole CON by the undercut structure of the cathode contact hole CON.

[0097] Subsequently, the cathode electrode CAT can be deposited on the emitter layer EL to cover the entire surface of the substrate 110. The cathode electrode CAT can be formed of a transparent conductive material such as ITO or IZO. These transparent conductive materials can be inorganic materials, and when stacked on a stepped surface, the stepped coverage is excellent. As a result, even inside the cathode contact hole CON with an undercut structure, the cathode electrode can be deposited along the etched sidewalls. Figure 6 As shown, since the cathode electrode CAT is stacked while covering all the inner surfaces of the cathode contact hole CON, it has a continuous structure that is not broken over the entire area of ​​the substrate 110.

[0098] As a result, the cathode electrode CAT can contact the low-resistance line LL exposed through the cathode contact hole CON. That is, since the emitter layer EL does not completely cover the surface of the low-resistance line LL exposed to the cathode contact hole CON, the cathode electrode CAT is connected to the low-resistance line LL.

[0099] Additionally, the undercut trench TR can be formed at the planarization layer PL located between the dam BA and the cathode contact hole CON. The undercut trench TR can be a component provided to fully maintain the structure of the cathode contact hole CON with an undercut structure.

[0100] The undercut trench TR can be a trench formed by removing a portion of the thickness of the planarization layer PL. For example, the ratio of the thickness Ha of the planarization layer PL to the depth Hb of the undercut trench TR, Ha:Hb, can have a value greater than or equal to 4:3. Furthermore, the depth Hb of the undercut trench TR can be equal to or less than the maximum thickness Ha of the planarization layer PL. That is, the ratio between the depth Hb of the undercut trench TR and the thickness Ha of the planarization layer PL can be selected from any value within the range of 4:3 ≤ Ha:Hb ≤ 1:1.

[0101] The following is for reference Figure 7 This will describe the reasons for the formation of undercut grooves (TR) and their effects. Figure 7 This is an enlarged cross-sectional view showing the structure of an electroluminescent display without undercut grooves according to the present disclosure. Figure 7 The cross-sectional structure of the cathode contact hole CON is shown in the case where no undercut trench TR is formed around the cathode contact hole CON.

[0102] Reference Figure 7 After forming the second hole OA2 by patterning the planarization layer PL without forming the undercut trench TR, the first hole OA1 is formed by patterning the passivation layer PAS to form the cathode contact hole CON. Here, as... Figure 7 As indicated by the designation "F", the end of the planarization layer PL may lift upwards from the horizontal direction. This may occur because the embankment BA does not completely cover the entire planarization layer PL, but only covers a portion of it. This could be due to the shrinkage of the etched ends of the planarization layer PL during heat treatment processes that can be performed in over-etching processes.

[0103] Under these conditions, when the emitter layer EL is deposited, it can be stacked along the etched sidewalls of the cathode contact hole CON. As a result, all low-resistance lines LL exposed to the cathode contact hole CON can be covered by the emitter layer EL. Furthermore, since the cathode electrode CAT is subsequently stacked on the emitter layer EL, the cathode electrode CAT does not need to be connected to the low-resistance lines LL.

[0104] On the other hand, such as Figure 6 As shown, when the undercut trench TR is formed, the thermal stress applied to the planarization layer PL during the etching process can be distributed through the undercut trench TR. As a result, the etched ends of the planarization layer PL do not lift up. Therefore, when the emitter layer EL is subsequently deposited, most of the low-resistance line LL in the cathode contact hole CON can be exposed. Furthermore, when the cathode electrode CAT is deposited, the cathode electrode CAT can be physically and electrically connected to the low-resistance line LL.

[0105] The following is for reference Figure 8 Another structure of the undercut groove TR according to another embodiment of the present disclosure will be described. Figure 8 This is a cross-sectional view showing the structure of an undercut trench according to another example of this disclosure. (See figure) Figure 8 As shown, according to another example, the undercut trench TR can have a structure completely filled by the embankment BA. In this case, the undercut trench TR can be disposed between the anode electrode ANO and the cathode contact hole CON. Using this structure, when forming the cathode contact hole CON with the undercut structure, the problem of the etched end of the planarization layer PL lifting does not occur.

[0106] Here, the dam BA is preferably formed to have a width smaller than the planarization layer PL exposed on the outside of the anode electrode ANO. In other words, instead of forming the dam BA to completely cover the planarization layer PL, it is preferable to form the dam BA to be spaced inwardly from the end of the planarization layer PL by a predetermined distance L.

[0107] The following is for reference Figure 9 This will explain why the embankment BA is preferred to not completely cover the planarization layer PL. Figure 9 This is an enlarged cross-sectional view showing the structure in which the embankment and planarization layer are formed in the same pattern in an electroluminescent display according to the present disclosure.

[0108] like Figure 9 As shown, when the dam BA completely covers the planarization layer PL, that is, when the end of the dam BA coincides with the end of the planarization layer PL, the etched sidewall W forming the cathode contact hole CON can have a very steep slope, and the slope length of the sidewall can also be relatively long. For example, the etched sidewall W of the cathode contact hole CON can have a length corresponding to the sum of the thickness of the dam BA and the thickness of the planarization layer PL.

[0109] Under these conditions, when the emitter layer EL is deposited, it may not cover the entire etched sidewall W. The emitter layer EL may include organic materials. The amount of emitter layer EL deposited on the etched sidewall W may be very small. Furthermore, even the cathode electrode CAT, which may include inorganic materials, may not cover the entire etched sidewall W, and its connectivity may be broken. As a result, the cathode electrode CAT and the low-resistance line LL may not be fully connected in the cathode contact hole CON.

[0110] Therefore, it is preferable that the embankment BA does not completely cover the planarization layer PL, but rather that the embankment BA exposes some portions of the planarization layer PL, such as... Figure 6 and Figure 8 As shown. Specifically, even in a structure where the embankment BA covers the bottom-cut trench TR, it is preferable not to completely cover the planarization layer PL.

[0111] Reference Figure 10 The structure of an undercut trench TR according to another example of this disclosure will be described. Figure 10 This is a cross-sectional view showing the structure of an undercut groove according to another embodiment of the present disclosure. (Refer to...) Figure 10 According to another embodiment of this disclosure, the undercut trench TR can have the same depth as the planarization layer PL. In use Figure 6 In the description, the depth Hb of the undercut trench TR is equal to the thickness Ha of the maximum planarization layer PL. That is, this is the case where the ratio between the thickness Ha of the planarization layer PL and the depth Hb of the undercut trench TR is Ha:Hb=1:1.

[0112] Reference Figure 11 The structure of an undercut trench TR according to another example of this disclosure will be described. Figure 11 As shown, the depth of the undercut trench TR can be etched to correspond to the same thickness as the planarization layer PL. Furthermore, the embankment BA can be formed to completely fill the undercut trench TR. In this case, the undercut trench TR can be positioned between the anode electrode ANO and the cathode contact hole CON. Even in this structure, when forming the cathode contact hole CON with an undercut structure, the problem of the etched end of the planarization layer PL lifting does not occur.

[0113] At this point, the dam BA is preferably formed to have a width smaller than the planarization layer PL exposed on the outside of the anode electrode ANO. For example, instead of forming the dam BA to completely cover the planarization layer PL, it is preferable to form the dam BA to be spaced inwardly from the end of the planarization layer PL by a predetermined distance L.

[0114] Reference Figure 12 The structure of an electroluminescent display according to another example of this disclosure will be described. Figure 12 This is a plan view showing the structure of an electroluminescent display according to another embodiment of the present disclosure.

[0115] Figure 12 The electroluminescent display shown can be a diagram illustrating a case of very high pixel density. For example, in the case of achieving ultra-high resolution with a pixel density of 200 DPI or higher in a large-area top-emitting electroluminescent display, all sub-pixels SP set in the display area DA can be uniformly spaced. In this case, compared with Figure 1 Unlike other methods, the spacing between pixels P may not be specifically defined.

[0116] Using this structure, low-resistance lines LL can be positioned between multiple sub-pixel columns. Cathode contact holes CON can be formed on the low-resistance lines LL, and the cathode electrode CAT and the low-resistance lines LL can be connected via the cathode contact holes CON. However, due to the very narrow spacing between sub-pixels SP, it may be difficult to form the cathode contact holes CON.

[0117] like Figure 9 As shown, the cathode contact hole CON can be formed at the intersection region K of four adjacent pixels P. For example, the cathode contact hole CON can be formed at the intersection region K of the white sub-pixel SPW of the first pixel P1, the red sub-pixel SPR of the second pixel P2, the white sub-pixel SPW of the third pixel P3, and the red sub-pixel SPR of the fourth pixel P4. In order to form the cathode contact hole CON, the region corresponding to the intersection of the four sub-pixels SP can be partially removed to ensure a square intersection region K.

[0118] The planarization layer PL and the passivation layer PAS can be patterned in a square intersection region K to form a cathode contact hole CON that exposes the low-resistance line LL disposed therebelow. Additionally, it is preferable to form an undercut trench TR between the anode electrodes ANO around the cathode contact hole CON.

[0119] The electroluminescent display according to this disclosure may include a structure in which a low-resistance line LL is disposed between two adjacent sub-pixels SP of two adjacent pixels P, and a cathode contact hole CON is provided to expose a portion of the low-resistance line LL. Specifically, the pattern for forming the cathode contact hole CON may be configured to overlap with a sub-pixel trench PLP disposed between two anode electrodes ANO on both sides.

[0120] exist Figure 3 In the diagram, to clearly illustrate the structure of the cathode contact hole CON, it is shown as having a shape protruding from the planarization layer PL on both sides. Alternatively, the cathode contact hole CON can be formed by arranging the planarization layer PL on both sides without the protruding shape and only etching the passivation layer PAS exposed between them. On the other hand, Figure 12 The structure of the low-resistance line LL is shown in a high-resolution configuration. Figure 12 The diagram illustrates a structure in which a cathode contact hole CON is formed inside each of the four sub-pixels SP in a portion where four sub-pixels SP are arranged, with a partially removed area.

[0121] The features, structures, effects, etc., described in the above-described exemplary embodiments of this disclosure are included in at least one exemplary embodiment of this disclosure, but are not necessarily limited to one exemplary embodiment. Furthermore, those skilled in the art to which this disclosure pertains can implement the features, structures, effects, etc., described in at least one exemplary embodiment in combination or modification with respect to other exemplary embodiments. Therefore, such combinations and variations should be interpreted as being included within the scope of this disclosure.

[0122] It will be apparent to those skilled in the art that various substitutions, modifications, and variations can be made within the scope of this disclosure without departing from its scope. Therefore, embodiments of this disclosure are intended to cover various substitutions, modifications, and variations of this disclosure, provided they fall within the scope of the appended claims and their equivalents. These and other changes can be made to embodiments based on the detailed description above. Generally, the terminology used in the following claims should not be construed as limiting the claims to the specific exemplary embodiments disclosed in the specification and claims, but should be interpreted to include the full scope of all possible embodiments and their equivalents. Therefore, these claims are not limited by this disclosure.

Claims

1. An electroluminescent display, the electroluminescent display comprising: A pixel, which is disposed on a substrate; A low-resistance line is disposed on one side of the pixel; A passivation layer is provided on the low-resistance line; A planarization layer on the passivation layer; A cathode contact hole that exposes a portion of the low-resistance wire; An anode electrode is disposed on the planarization layer; Undercut trench, which is formed at the planarization layer disposed between the anode electrode and the cathode contact hole; A dike that covers the outer peripheral region of the anode electrode; An emission layer is present on the dam, the anode electrode, and the planarization layer; as well as Cathode electrode, which is located on the emitter layer. The cathode electrode is connected to the low-resistance wire through the cathode contact hole. The cathode contact hole includes an undercut profile in the passivation layer. The cathode electrode extends through the cathode contact hole to another pixel adjacent to the pixel. The emitting layer is interrupted in the cathode contact hole and is disposed only in the middle region of the low-resistance line. The cathode electrode is continuously formed on the two sidewalls of the cathode contact hole, the undercut profile, and the low resistance line.

2. The electroluminescent display according to claim 1, further comprising: A pixel trench is formed by removing a portion of the planarization layer around the anode electrode on the outside of the dam.

3. The electroluminescent display according to claim 2, wherein, The emission layer extends to neighboring pixels through the pixel trench.

4. The electroluminescent display according to claim 2, wherein, The cathode contact hole is formed in the region where it intersects with the low-resistance line at the pixel trench.

5. The electroluminescent display according to claim 1, wherein, The cathode contact hole includes: A first hole, the first hole being formed at the passivation layer and having a first width; and A second hole is formed through the planarization layer and has a second width narrower than the first width. The cathode electrode contacts the low-resistance line at a location where the emission layer is not disposed.

6. The electroluminescent display according to claim 1, wherein, The ratio of the depth of the undercut groove to the thickness of the planarization layer is 1:1 to 3:

4.

7. The electroluminescent display according to claim 1, wherein, The embankment is positioned between the anode electrode and the undercut trench.

8. The electroluminescent display according to claim 1, wherein, The dike fills the undercut trench and covers a portion of the planarization layer.

9. The electroluminescent display according to claim 8, wherein, The embankment does not cover the portion of the planarization layer between the undercut trench and the cathode contact hole.

10. The electroluminescent display according to claim 1, further comprising: A thin-film transistor is disposed beneath the passivation layer and connected to the anode electrode.

11. An electroluminescent display, the electroluminescent display comprising: A first pixel and a second pixel are disposed adjacent to each other on a substrate; A low-resistance line is disposed between the first pixel and the second pixel; A passivation layer is provided on the low-resistance line; A first planarization layer is disposed on the passivation layer at the first pixel; A second planarization layer is disposed on the passivation layer at the second pixel; A first anode electrode is located on the first planarization layer; A second anode electrode is located on the second planarization layer; A cathode contact hole that exposes a portion of the low-resistance line between the first planarization layer and the second planarization layer; A first undercut trench is formed at the first planarization layer between the first anode electrode and the cathode contact hole; A second undercut trench is formed at the second planarization layer between the second anode electrode and the cathode contact hole; A first dike covers the outer peripheral region of the first anode electrode; A second dike covers the outer peripheral region of the second anode electrode; An emission layer is located on the first dam, the second dam, the first anode electrode, the second anode electrode, the first planarization layer, and the second planarization layer. as well as Cathode electrode, which is located on the emitter layer. The cathode electrode is connected to the low-resistance wire through the cathode contact hole. The cathode contact hole includes an undercut profile in the passivation layer. The cathode electrode extends from the first pixel to the second pixel through the cathode contact hole. The emitting layer is interrupted in the cathode contact hole and is disposed only in the middle region of the low-resistance line. The cathode electrode is continuously formed on the two sidewalls of the cathode contact hole, the undercut profile, and the low resistance line.

12. The electroluminescent display according to claim 11, further comprising: A pixel trench is disposed between the first planarization layer and the second planarization layer, and exposes the passivation layer.

13. The electroluminescent display according to claim 12, wherein, The emission layer extends from the first pixel to the second pixel via the pixel trench.

14. The electroluminescent display according to claim 11, wherein, The cathode contact hole includes: A first hole, the first hole being formed at the passivation layer and having a first width; and A second hole is formed between the first planarization layer and the second planarization layer, and has a second width narrower than the first width. The cathode electrode contacts the low-resistance line at a location where the emission layer is not disposed.

15. The electroluminescent display according to claim 11, wherein, The ratio of the depth of the first undercut trench to the thickness of the first planarization layer is 1:1 to 3:4, and The ratio of the depth of the second undercut groove to the thickness of the second planarization layer is 1:1 to 3:

4.

16. The electroluminescent display according to claim 11, wherein, The first dike does not cover the first bottom-cut trench and the first leveling layer, and The second dike does not cover the second bottom-cut trench and the second leveling layer.

17. The electroluminescent display according to claim 11, wherein, The first dike fills the first undercut trench, and The second embankment fills the second bottom-cut trench.

18. The electroluminescent display according to claim 17, wherein, The first embankment does not cover the portion of the first planarization layer between the first undercut trench and the cathode contact hole, and The second embankment does not cover the portion of the second planarization layer between the second undercut trench and the cathode contact hole.

19. An electroluminescent display, the electroluminescent display comprising: A first pixel, the first pixel including a first transistor and a first light-emitting diode, the first light-emitting diode including a first anode, a first emitting layer and a cathode; The second pixel includes a second transistor and a second light-emitting diode, the second light-emitting diode including a second anode, a second emitting layer and the cathode; A passivation layer covering the first transistor and the second transistor; A planarization layer is provided between the passivation layer and the first light-emitting diode and the second light-emitting diode. A low-resistance line is located between the first pixel and the second pixel; A cathode contact hole is located between the first pixel and the second pixel. The cathode contact hole is formed through the planarization layer and a portion of the passivation layer and exposes a portion of the low-resistance line. as well as A dummy emitter layer is formed of the same material as the first and second emitter layers on the portion of the low-resistance wire exposed through the cathode contact hole, and is electrically disconnected from the first and second emitter layers. The cathodes of the first pixel and the second pixel are connected to the low-resistance line through the cathode contact hole. The cathode contact hole includes an undercut profile in the passivation layer. Wherein, the cathode extends from the first pixel to the second pixel through the cathode contact hole, and The cathode is continuously formed on the dummy emission layer, the portion of the low resistance line, the undercut profile, and the sidewall of the cathode contact hole.

20. The electroluminescent display according to claim 19, further comprising: A first dike is located between the first pixel and the cathode contact hole; A second dike is located between the second pixel and the cathode contact hole; A first undercut groove is formed in the planarization layer between the first embankment and the cathode contact hole, and the first undercut groove is spaced apart from the cathode contact hole; as well as A second undercut groove is formed in the planarization layer between the second embankment and the cathode contact hole, and the second undercut groove is spaced apart from the cathode contact hole.

21. The electroluminescent display according to claim 20, wherein, The first dike fills the first undercut trench and the second dike fills the second undercut trench.

22. The electroluminescent display according to claim 20, wherein, The first undercut trench and the second undercut trench expose the passivation layer.

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