Method of manufacturing a semiconductor device

Abstract

In a method of manufacturing a semiconductor device, a semiconductor wafer made of a semiconductor material harder than silicon and having a first surface (30a) and a second surface (30b) opposite to each other is prepared, a roughened layer (32) is formed by polishing the second surface of the semiconductor wafer, a blade is pressed against the roughened layer to form vertical cracks (C) in a surface layer of the semiconductor wafer, the roughened layer is removed after the formation of the vertical cracks, a back surface electrode (33) is formed on a back surface (30c) of the semiconductor wafer on which the vertical cracks are formed, and after the formation of the back surface electrode, the first surface of the semiconductor wafer is pressed and the semiconductor wafer is split into pieces starting from the vertical cracks.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to a method for manufacturing a semiconductor device. BACKGROUND

[0002] In a conventional manufacturing method of a semiconductor device, a plurality of element regions having semiconductor elements are formed on a semiconductor wafer, and the semiconductor wafer is cut with a blade, thereby dividing the element regions into a plurality of independent chips. In a dicing process for dividing the semiconductor wafer into a plurality of independent chips, a crack can occur in the semiconductor chip, or a burr can occur in a back surface electrode that comes into contact with the blade.

[0003] JP 2007-165371 A proposes a method for manufacturing a semiconductor device that limits generation of a crack in a semiconductor chip and generation of a burr in a back surface electrode in such a dicing process. In this manufacturing method of a semiconductor device, after a V-shaped groove and a back surface electrode are sequentially formed on a back surface of a semiconductor wafer, a V-shaped groove is formed at a portion of a front surface of the semiconductor wafer that is above the V-shaped groove formed on the back surface. Then, the semiconductor wafer is irradiated with a laser beam to form a modified layer at a portion inside the semiconductor wafer and between the V-shaped grooves on the front surface and the back surface. Thereafter, a dicing tape is attached to the semiconductor wafer, and the semiconductor wafer is stretched together with the dicing tape, whereby the semiconductor wafer is split and separated starting from the V-shaped grooves and the modified layer. SUMMARY

[0004] In recent years, in the field of power semiconductor devices such as an insulated gate bipolar transistor (IGBT) and a metal oxide semiconductor field effect transistor (MOSFET), development of devices using silicon carbide (SiC) as a semiconductor material has been progressing. Since silicon carbide has a lower on-resistance and a higher breakdown voltage than silicon (Si), it is expected to improve the performance of power semiconductor devices.

[0005] However, since silicon carbide is harder than silicon, when a semiconductor device is manufactured using silicon carbide, a large load is applied to the blade in the dicing process. Therefore, as a method of manufacturing a semiconductor device using a semiconductor material that is harder than silicon, a dicing process including a scribing process and a breaking process has been proposed. The scribing process is a process of pressing a blade against a semiconductor wafer to form a vertical crack in a surface layer. The breaking process is a process of pressing a plate or the like against a surface of a semiconductor wafer opposite to a surface on which a vertical crack is formed and breaking the semiconductor wafer in a three-point bending manner with the vertical crack as a starting point. Hereinafter, the dicing process including the scribing process and the breaking process performed after the scribing process will be referred to as a "scribing and breaking process" for the sake of simplicity of explanation.

[0006] As a result of diligent research by the present inventors on a method of manufacturing a semiconductor device of this type, the present inventors have found that, in a semiconductor chip separated by a scribing and breaking process, residual stress in the vicinity of an end surface caused by dicing is greater than in a semiconductor chip dicing by a cutting process with a blade. The present inventors have also found that, if the residual stress is great, a crack will occur in a semiconductor chip mounted on another member by soldering or the like due to thermal stress.

[0007] When the manufacturing method described in JP 2007-165371 A is applied to a semiconductor device of this type, since a surface layer of a hard semiconductor wafer is cut with a blade, a great load is applied to the blade. Furthermore, since the manufacturing method requires a process of forming a V-shaped groove on a front surface of the semiconductor wafer with a blade and a process of forming a modified layer by irradiation with a laser beam, the number of processes increases and thus the manufacturing cost increases. Furthermore, since the process of forming a modified layer by irradiation with a laser beam, residual stress inside the semiconductor wafer can increase, which is worrisome.

[0008] In view of the above points, it is an object of the present disclosure to reduce residual stress in a semiconductor device caused by a dicing process in a method of manufacturing a semiconductor device using a semiconductor material that is harder than silicon.

[0009] In a method of manufacturing a semiconductor device according to one aspect of the present disclosure, a semiconductor wafer made of a semiconductor material harder than silicon and having a first surface and a second surface opposite to each other is prepared; the second surface of the semiconductor wafer is ground to form a roughened layer having a surface roughness greater than that of the second surface of the semiconductor wafer before the grinding; a blade is pressed against the roughened layer to form a vertical crack in a surface layer of the semiconductor wafer; the roughened layer is removed after the formation of the vertical crack; a back surface electrode is formed on a back surface of the semiconductor wafer on which the vertical crack is formed; and after the formation of the back surface electrode, the first surface of the semiconductor wafer is pressed and the semiconductor wafer is split into a plurality of pieces with the vertical crack as a starting point.

[0010] In the method of manufacturing the semiconductor device, a roughened layer is formed by grinding a semiconductor wafer harder than silicon, and a vertical crack is formed in the semiconductor wafer by scribe processing before the formation of the back surface electrode. Therefore, compared with a case where a vertical crack is formed on a mirror-polished surface, a vertical crack can be formed with a lower pressure, and a residual stress due to scribe processing can be reduced in a diced semiconductor device. Further, by removing the roughened layer after the formation of the vertical crack, a reduction in bending strength due to the roughened layer can be limited, and an effect of limiting a reduction in reliability is obtained. BRIEF DESCRIPTION OF DRAWINGS

[0011] The above and other objects, features and advantages of the present disclosure will become more apparent from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0012] Figure 1 is a top layout view showing an example of a semiconductor module employing a semiconductor device according to one embodiment;

[0013] Figure 2 is a cross-sectional view showing a cross-sectional structure along line II-II in Figure 1 ;

[0014] Figure 3A is an explanatory view of scribe processing according to a comparative example;

[0015] Figure 3B is an explanatory view of break processing according to the comparative example;

[0016] Figure 4 is a graph showing measurement results of residual stresses of a semiconductor device obtained by a dicing method and a semiconductor device obtained by scribe and break processing according to the comparative example;

[0017] Figure 5 corresponds to Figure 2is an enlarged view of the region V in FIG. 8, and is an explanatory view of generation of a crack caused by a residual stress in the semiconductor device due to scribe line and break processing according to the comparative example;

[0018] Figure 6A is a cross-sectional view showing processing of attaching the semiconductor wafer to the support substrate in the scribe processing of the semiconductor device according to the embodiment;

[0019] Figure 6B is a cross-sectional view showing processing after the processing shown in Figure 6A ;

[0020] Figure 6C is a cross-sectional view showing processing after the processing shown in Figure 6B ;

[0021] Figure 6D is a cross-sectional view showing processing after the processing shown in Figure 6C ;

[0022] Figure 6E is a cross-sectional view showing processing after the processing shown in Figure 6D ;

[0023] Figure 6F is a cross-sectional view showing processing after the processing shown in Figure 6E ;

[0024] Figure 6G is a cross-sectional view showing processing after the processing shown in Figure 6F ;

[0025] Figure 6H is a cross-sectional view showing processing after the processing shown in Figure 6G ;

[0026] Figure 6I is a cross-sectional view showing processing after the processing shown in Figure 6H ;

[0027] Figure 7 is a graph showing results of observation of a cross section of the back surface side formed in the processing shown in Figure 6B using a transmission electron microscope (TEM);

[0028] Figure 8 is a graph showing results of observation of a cross section of the back surface electrode after the processing shown in Figure 6E using a transmission electron microscope;

[0029] Figure 9A is a cross-sectional view showing another example of processing after the processing shown in Figure 6C ;

[0030] Figure 9B is a cross-sectional view illustrating Figure 9A processing after the processing shown in DETAILED DESCRIPTION

[0031] Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings. In the following embodiments, the same or equivalent portions are denoted by the same reference numerals for description.

[0032] (Embodiments)

[0033] A semiconductor module employing a semiconductor device according to an embodiment will be described with reference to the drawings. The semiconductor device is, for example, a power semiconductor element mainly composed of a semiconductor material harder than silicon, such as silicon carbide, and can be applied to an inverter or the like. In the present disclosure, a case where the semiconductor device is applied to a semiconductor module constituting an inverter is described as a representative example, but the present disclosure is not limited to this example and can be applied to other uses.

[0034] In Figure 1 , in order to facilitate understanding of the structure of the semiconductor module 100, the outline of the sealing resin 8 to be described later is indicated by a broken line of one long and two short, and the portion of the constituent elements of the semiconductor module 100 overlapping with the other constituent elements except for the sealing resin 8 is indicated by a broken line.

[0035] Hereinafter, in order to facilitate explanation, as indicated by arrows in Figure 1 , a direction along the left-right direction of the paper surface of Figure 1 will be referred to as an "x direction", a direction on the paper surface perpendicular to the x direction will be referred to as a "y direction", and a direction perpendicular to the paper surface (i.e., an xy plane) will be referred to as a "z direction". In the drawings after Figure 1 , the x, y, and z directions indicated by arrows and the like correspond to the x, y, and z directions in Figure 1 , respectively.

[0036] [Semiconductor Module]

[0037] As shown in Figure 1 , for example, the semiconductor module 100 includes a first lead frame 1, a second lead frame 2, a semiconductor device 3 disposed between the lead frames 1 and 2 in the z direction, a conductor block 4, a first connection member 6, a second connection member 7, a lead wire 5, and a sealing resin 8. The semiconductor device 3 includes a first semiconductor device 3a and a second semiconductor device 3b. The conductor block 4 includes a first conductor block 4a and a second conductor block 4b.

[0038] The first lead frame 1 is made of, for example, an electrically conductive material such as copper. The first lead frame 1 includes a positive plate 11 having a positive terminal P, an output plate 12 having an output terminal O, a negative plate 13 having a negative terminal N, and a plurality of signal terminals 14. The first lead frame 1 is a plate member in which the positive plate 11, the output plate 12, the negative plate 13, and the signal terminals 14 are connected by a connection portion such as a bus bar (not shown) or the like, and the connection portion has been removed during manufacturing of the semiconductor module 100 so that the positive plate 11, the output plate 12, the negative plate 13, and the signal terminals 14 are separated from each other.

[0039] The positive plate 11 has, for example, the positive terminal P protruding in the y direction from the sealing resin 8. The positive plate 11 is arranged apart from the output plate 12 in the x direction and is mounted together with the first semiconductor device 3a via a bonding material (not shown). The positive plate 11 is electrically connected to the first connection plate 21, which will be described later, via the first conductor block 4a provided on the first semiconductor device 3a. The positive plate 11 has an island portion on which the first semiconductor device 3a is mounted. The island portion has a first surface facing the first semiconductor device 3a and a second surface opposite the first surface and exposed from the sealing resin 8. Thus, when the second surface is brought into contact with a cooler (not shown), the positive plate 11 can be cooled. At this time, an insulating member (not shown) is provided between the cooler (not shown) and the exposed portion of the island portion to ensure electrical insulation between the cooler and the semiconductor module 100.

[0040] The output plate 12 has, for example, the output terminal O provided in parallel with the positive terminal P and protruding in the same direction as the positive terminal P from the sealing resin 8. The output plate 12 has the second semiconductor device 3b mounted thereon. The output plate 12 has, for example, a protruding portion 121 extending toward the positive plate 11 and extending in the z direction to approach the first connection plate 21, and the first connection plate provided on the protruding portion 121. The output plate 12 is electrically connected to the first connection plate 21 via the first connector 6 provided on the protruding portion 121. The output plate 12 is electrically connected to the second connection plate 22, which will be described later, via the second conductor block 4b provided on the second semiconductor device 3b. Like the positive plate 11, the output plate 12 has an island portion on which the second semiconductor device 3b is mounted. The island portion has a first surface facing the second semiconductor device 3b and a second surface opposite the first surface and exposed from the sealing resin 8. Thus, when the second surface is brought into contact with a cooler (not shown), the output plate 12 can be cooled.

[0041] The negative plate 13 is provided between the positive plate 11 and the output plate 12 so as to be separated from the positive plate 11 and the output plate 12. The negative plate 13 has a negative terminal N provided in parallel with the positive terminal P and the output terminal O and protruding from the sealing resin 8 in the same direction. The negative plate 13 also has an extension 131 provided in a gap between the positive plate 11 and the output plate 12 and extending in a direction opposite to the negative terminal N. The negative plate 13 is electrically connected to the second connecting plate 22 via the second connecting member 7 provided on the extension 131.

[0042] The plurality of signal terminals 14 includes a plurality of first signal terminals 14a connected to the first semiconductor device 3a via the lead wire 5 and a plurality of second signal terminals 14b connected to the second semiconductor device 3b via the lead wire 5. The plurality of signal terminals 14 is provided at a position separated from other members, on the side opposite to the terminals P, O, and N, between the positive plate 11 and the output plate 12.

[0043] The second lead frame 2 has, for example, a first connecting plate 21 and a second connecting plate 22. The second lead frame 2 is provided so as to face the first lead frame 1 across the semiconductor device 3 and the conductor block 4 in the z direction. The first connecting plate 21 is provided facing the positive plate 11 and separated from the second connecting plate 22. The first connecting plate 21 has, for example, a protruding portion 211 protruding toward the second connecting plate 22 and partially bent toward the output plate 12. The first connecting plate 21 constitutes a current path connecting the positive plate 11, the first semiconductor device 3a, the first conductor block 4a, and the output plate 12 when the first semiconductor device 3a is turned on. The second connecting plate 22 has, for example, the same shape as the first connecting plate 21 and has a protruding portion 221 protruding toward the first connecting plate 21. The second connecting plate 22 is electrically connected to the negative plate 13 via the protruding portion 221 and the second connecting member 7 provided directly below the protruding portion 221. The second connecting plate 22 constitutes a current path connecting the output plate 12, the second semiconductor device 3b, the second conductor block 4b, and the negative plate 13 when the second semiconductor device 3b is turned on. Surfaces of the first connecting plate 21 and the second connecting plate 22 opposite to surfaces facing the conductor block 4 are exposed from the sealing resin 8 in addition to the protruding portions 211 and 221. Therefore, the first connecting plate 21 and the second connecting plate 22 can be cooled by a cooler (not shown) in the same manner as the positive plate 11 and the output plate 12.

[0044] The semiconductor device 3 is configured using a semiconductor substrate made of a semiconductor material harder than silicon (for example, silicon carbide, gallium nitride (GaN), or gallium oxide (Ga203)). Hereinafter, the semiconductor material harder than silicon will be referred to as a "hard semiconductor material" for the convenience of explanation. The semiconductor device 3 constitutes, for example, a power semiconductor element in which a switching element (for example, an IGBT or a MOSFET) and a free wheel diode (FWD) are formed. In the present disclosure, a case where the semiconductor device 3 has an IGBT and an FWD will be described as a representative example, but the present disclosure is not limited to this example. The semiconductor device 3 has, for example, a structure in which an anode and a cathode of the FWD are electrically connected to an emitter of a front surface electrode as a switching element and a collector of a back surface electrode as a surface electrode, respectively. The lead wire 5 is connected to a gate electrode (not shown) of the switching element of the semiconductor device 3, and the semiconductor device 3 is turned on and off via the signal terminal 14.

[0045] For example, as shown in FIG. 1, the semiconductor device 3 is mounted on the positive plate 11 and the output plate 12 via a joining member 9 made of solder or the like, respectively. A plurality of semiconductor devices 3 are formed on a semiconductor wafer made of a hard semiconductor material having high rigidity, and are diced by a scribe and break processing to be described later. The semiconductor device 3 is in a state where residual stress caused by dicing is reduced. Details of the reduction of the residual stress and its effects will be described later. Figure 2

[0046] The conductor block 4 is made of an electrically conductive material, for example, copper. The conductor block 4 is provided on a side of the semiconductor device 3 opposite to the positive plate 11 and the output plate 12, and is connected to the semiconductor device 3 through the joining member 9. For example, as shown in FIG. 1, the conductor block 4 has a smaller planar size than the semiconductor device 3, and is connected to a portion of the semiconductor device 3 other than a portion to which the lead wire 5 is connected. The conductor block 4 is provided between the positive plate 11 and the first connecting plate 21 and between the output plate 12 and the second connecting plate 22, respectively, to secure these gaps and restrict the lead wire 5 from coming into contact with the connecting plates 21 and 22. Figure 1

[0047] The lead wire 5 is made of an electrically conductive material such as gold or aluminum, and is connected to the signal terminal 14 and the semiconductor device 3 by wire bonding.

[0048] The first connecting member 6 and the second connecting member 7 are made of an electrically conductive material, for example, copper. The first connecting member 6 and the second connecting member 7 are provided between the protrusion 121 and the protrusion 211 and between the extension 131 and the protrusion 221, respectively, and electrically connect these portions.

[0049] ​​The sealing resin 8 is made of, for example, a thermosetting resin material such as an epoxy resin, and is formed by any resin molding method.

[0050] The above is a basic configuration when the semiconductor module 100 is configured as an inverter. The semiconductor device 3 included in the semiconductor module 100 is diced from a semiconductor wafer made of a hard semiconductor material by the scribe and break processing according to the present embodiment, and the residual stress in the semiconductor device 3 is reduced compared to a semiconductor device diced by the scribe and break processing according to a comparative example which will be described later.

[0051] [Residual stress of semiconductor device]

[0052] As a result of diligent research by the present inventor, it has been found that when a semiconductor wafer made of a hard semiconductor material such as silicon carbide is diced by the scribe and break processing according to the comparative example, the residual stress in the semiconductor chip after dicing is large.

[0053] Here, the scribe and break processing according to the comparative example will be described with reference to Figure 3A and 3B The scribe and break processing includes a scribe processing for forming a vertical crack C having a predetermined depth in a semiconductor wafer W, as shown in Figure 3A , and a break processing for breaking the semiconductor wafer in a three-point bending manner with the vertical crack as a starting point, as shown in Figure 3B In the scribe processing, for example, the front surface Wa of the semiconductor wafer W is temporarily fixed on a suction work table or the like, and a blade B is pressed against the back surface Wb of the semiconductor wafer W to form the vertical crack C in the surface layer of the back surface Wb. In the break processing, for example, the semiconductor wafer W is placed on a pedestal in a state where a tape T is attached to the front surface Wa of the semiconductor wafer W, and a protective film PF is attached to the back surface Wb of the semiconductor wafer W, and the position of the front surface Wa above the vertical crack C is pressed by a break plate BP. At this time, the semiconductor wafer W is in a hollow state in which the portion where the vertical crack C is formed is separated from the pedestal, and both ends of the portion pressed by the break plate BP are supported by the pedestal. Then, the semiconductor wafer W is broken and diced in a three-point bending manner with the vertical crack as a starting point. The scribe processing according to the comparative example is performed in a state where the back surface Wb of the semiconductor wafer W is made into a mirror surface state having a very small surface roughness by a polishing process such as chemical mechanical polishing (CMP) or the like, and a back surface electrode made of a metal material is formed on the back surface Wb.

[0054] As a result of diligent research by the present inventor, it has been found that when the semiconductor wafer W is made of a hard semiconductor material, the blade pressure in the scribe processing, that is, the scribe pressure increases, and the residual stress in the semiconductor chip after dicing is high.

[0055] Specifically, for example, as shown in Figure 4 the sample S1 of the semiconductor chip obtained by dicing the semiconductor wafer W made of silicon carbide with the blade B has a maximum residual stress of about 23 MPa. Note that the sample S1 has the maximum residual stress at a position at a distance of about 2 μm from the chip end surface formed by dicing.

[0056] On the other hand, the sample S2 of the semiconductor chip obtained by dicing the semiconductor wafer W made of silicon carbide according to the comparative example has a maximum residual stress of about 68 MPa. It can be considered that the high residual stress is caused by the deformation remaining in the vicinity of the scribe line of the semiconductor wafer W because the vertical cracks C are formed in a state where the back surface Wb of the semiconductor wafer W is mirror-polished and covered with a back surface electrode made of a metal material, and the required scribe pressure is as high as about 6 N. Note that the sample S2 has the maximum residual stress at a position at a distance of about 6 μm from the chip end surface formed by dicing. Figure 4 The residual stress of the semiconductor chip shown in FIG. 6 was measured by Raman scattering spectroscopy.

[0057] When the semiconductor chip has a high residual stress, the semiconductor chip is subjected to thermal stress due to the difference in the coefficient of thermal expansion from the surrounding member when mounted on another member. When the above semiconductor module 100 is configured using the semiconductor chip SC having a high residual stress (corresponding to the semiconductor device 3), as shown in Figure 5 cracks can occur due to the thermal stress with the position having a high residual stress as a starting point. When such cracks occur, the cracks propagate toward the element region such as the IGBT, and the reliability of the semiconductor module 100 is reduced.

[0058] In order to reduce the residual stress in the semiconductor chip after dicing, it can be conceivable to adopt a cutting method using a blade. However, when the semiconductor wafer W is made of a hard semiconductor material, since the cutting method using a blade exerts a large load on the blade compared to the scribe and break processing, and increases the time required for dicing, the manufacturing cost increases. Therefore, the present inventors devised a method of reducing the residual stress in the semiconductor chip after dicing while adopting the scribe and break processing.

[0059] [Scribe and break processing]

[0060] Next, a dicing process for dividing a semiconductor wafer into several independent pieces and a dicing and breaking process for reducing residual stress will be described in the manufacturing process of the semiconductor device 3 according to this embodiment. Since the process of forming element regions 31, including switching elements, FWDs and similar elements, in the semiconductor wafer 30, which will be described later, can be performed by known semiconductor processes, a detailed description of them will be omitted in this disclosure.

[0061] First, such as Figure 6A As shown, the first surface 30a of a semiconductor wafer 30, on which the component region 31 is formed, made of a hard semiconductor material such as silicon carbide, is covered with a protective adhesive 201 and then attached to a support substrate 200, thereby temporarily fixing the semiconductor wafer 30. The support substrate 200 is, for example, a glass substrate with an adhesive film (not shown) made of LTHC manufactured by 3M. However, the support substrate 200 can be replaced by a protective tape, as long as the protective tape can support the semiconductor wafer 30. Preferably, the support substrate 200 is made of a material such as a glass substrate, which has a higher stiffness than resin materials. This is because the pressure applied to the blade of the semiconductor wafer 30 is unlikely to be avoided in the subsequent scribing process, and the scribing pressure can be reduced. The adhesive 201 is, for example, composed of any resin material that has UV curability and thermoplasticity.

[0062] Next, as Figure 6B As shown, the semiconductor wafer 30 is thinned by grinding the second surface 30b of the semiconductor wafer 30, which is located opposite to the first surface attached to the support substrate 200, using a grinding machine (not shown), such as a grinder. In this grinding process, the semiconductor wafer 30 is thinned by coarse grinding with a grinding stone, and is different from the polishing process used to form a mirror. Therefore, the surface layer of the rear surface 30c obtained by grinding the second surface 30b is a roughened layer 32 with a surface roughness greater than that of the second surface 30b before grinding. Specifically, as Figure 7 As shown, as a result of cross-sectional observation using a transmission electron microscope (TEM), the back surface 30c of the polished semiconductor wafer 30 has a roughening layer 32, which has an uneven surface of about 50 nm in the thickness direction of the wafer from the surface layer.

[0063] Subsequently, as Figure 6C As shown, a semiconductor wafer 30 attached to a support substrate 200 is placed on a stage 300, a blade B is pressed against a roughening layer 32, and a vertical crack C is formed in a dicing region between component regions 31. At this time, for example, an alignment camera or similar device (not shown) is used to align the blade B and the dicing region of the semiconductor wafer 30. The vertical crack C is formed in the surface layer of the rear surface 30c of the semiconductor wafer 30 and extends along the thickness direction of the semiconductor wafer 30.

[0064] When performing a similar scribing process on a mirror-polished silicon carbide wafer before forming the back surface electrode, a scribing pressure of approximately 2N is required. On the other hand, a semiconductor wafer 30 with a roughening layer 32 requires a scribing pressure of at least less than 2N during the scribing process because the roughening layer 32 is more fragile than a substrate made of silicon carbide. As a result, deformation in the semiconductor wafer 30 during the formation of vertical cracks is reduced, and residual stress near the scribing lines is also reduced.

[0065] Then, as Figure 6D As shown, a back surface electrode 33 is formed on the back surface 30c of a semiconductor wafer 30 by sputtering or a similar method. The portion of the back surface electrode 33 that is in contact with the roughening layer 32 is primarily composed of at least one silaneizable conductive metal material selected, for example, from the group consisting of Ni (nickel), Ti (titanium), Mo (molybdenum), Ta (tantalum), Pt (platinum), and Co (cobalt). In this disclosure, the term "primarily composed of" means that the content of the main component exceeds 50% by volume. For example, the back surface electrode 33 has a Ni / Ti / Ni / Au (gold) stacked structure from the side closest to the roughening layer 32, and the region that is in contact with the roughening layer 32 is silaneized by a next thermal oxidation process. The thickness of the back surface electrode 33 is greater than the thickness of the roughening layer 32. For example, when the depth of the roughening layer 32 is 50 nm, the back surface electrode 33 has a thickness of 100 nm. This is because, in the next process, all the roughened layers 32 are siliconized together with the rear surface electrode 33, removing the roughened layers 32 and limiting the excessive reduction in bending strength caused by the roughened layers 32. When in Figure 6D When the back surface electrode 33 formed during the processing has a Ni / Ti / Ni / Au stacked structure from the side near the roughened layer 32, after thermal oxidation, the back surface electrode 33 has a NiSi / Ti / Ni / Au stacked structure.

[0066] After that, as Figure 6E As shown, the semiconductor wafer 30 undergoes heat treatment to silicide the roughening layer 32 and the back surface electrode 33. The heat treatment can be a method of heating the entire semiconductor wafer 30 using a furnace or similar equipment, or it can be a laser annealing method that uses a laser beam to irradiate the back surface electrode 33 to locally heat the back surface 30c. The heat treatment can be performed using well-known methods. After this heat treatment, the semiconductor wafer 30 has a thickness of approximately 150 nm due to the silicided back surface electrode 33 and roughening layer 32, and the roughening layer 32 is removed, as shown. Figure 8 As shown, the excessive reduction in the bending strength of the semiconductor wafer 30 due to the residual roughening layer 32 is limited, thereby improving reliability.

[0067] Next, as Figure 6FAs shown, the dicing tape DT is attached to the surface of the rear surface electrode 33. Then, for example by irradiation with a laser beam, the semiconductor wafer 30, adhesive 201, and support substrate 200 are separated from each other to expose the first surface 30a, as... Figure 6G As shown.

[0068] Subsequently, as Figure 6H As shown, a protective tape PT is attached to the first surface 30a of the semiconductor wafer 30, and the semiconductor wafer 30 is mounted on a stage 400. At this time, the semiconductor wafer 30 is aligned using a camera or similar device (not shown) such that the portion forming the vertical crack C is located above a gap provided in the stage 400. Then, the portion of the first surface 30a above the portion forming the vertical crack C is pressed by a breaking plate BP, and the vertical crack C propagates in the thickness direction of the semiconductor wafer 30 in a three-point bending manner to split the semiconductor wafer 30. By repeating this breaking process according to the number of scribing lines in which the vertical crack C is formed, the semiconductor wafer 30 is divided into multiple semiconductor devices 3.

[0069] After the above disconnection process, the protective tape PT is peeled off, and the adhesive strength of the dicing tape DT is reduced by, for example, ultraviolet irradiation. Then, as... Figure 6I As shown, the separated semiconductor device 3 (semiconductor chip) is picked up by a pickup device (not shown).

[0070] When a semiconductor wafer 30 made of hard semiconductor material is diced using the dicing and breaking process described above, the dicing pressure is reduced compared to the comparative example, and a semiconductor device with reduced residual stress near the end formed by dicing can be obtained. Compared to the cutting method using blade B, the dicing and breaking process according to this embodiment can limit the load applied to blade B and shorten the dicing time. Furthermore, forming a modification layer by laser beam irradiation is not necessary, and the manufacturing cost of the semiconductor device 3 can be reduced.

[0071] In the above description, the silicide formation of the rear surface electrode 33 is used as an example of the process for removing the roughened layer 32; however, the process for removing the roughened layer 32 is not limited to this example. For example, in Figure 6C After the scribing process shown, the roughened layer 32 can be removed by mechanical polishing, such as chemical mechanical polishing. Figure 9A As shown. In this case, subsequently, as Figure 9B As shown, a rear surface electrode 33 is formed on the rear surface 30c of the polished semiconductor wafer 30, and then heat treatment is performed. Subsequent processing is the same as above. Even after such processing, because the scribing pressure during the scribing process is reduced and the roughening layer 32 is removed, it is possible to obtain a wafer that is in the same condition as the one obtained through... Figures 6A-6IThe dicing process shown produces semiconductor devices 3 in a similar state as the semiconductor device 3.

[0072] (Other Embodiments)

[0073] Although the present disclosure is made in accordance with the above-described embodiments, it should be understood that the present disclosure is not limited to these embodiments and structures. The present disclosure encompasses various modifications and variations within the equivalent scope. Furthermore, various combinations and modes, and other combinations and modes including only one element, more elements, or less elements are also within the scope and concept of the present disclosure.

[0074] The constituent elements of each of the above-described embodiments are not necessarily essential, unless it is explicitly stated that the constituent element is essential in the above-described embodiments, or unless the constituent element is apparently essential in principle. The numbers, values, totals, ranges, and the like referred to in the description of the above-described embodiments are not necessarily limited to such specific numbers, values, ranges, and the like, unless they are specifically described as essential or understood as essential in principle. Furthermore, in each of the above-described embodiments, when referring to the shape of an element or the positional relationship between elements, the present disclosure is not limited to a specific shape or positional relationship, unless otherwise specifically stated, or unless the present disclosure is limited to a specific shape or positional relationship in principle.

Claims

1. A method of manufacturing a semiconductor device, comprising: preparing a semiconductor wafer made of a semiconductor material harder than silicon and having a first surface and a second surface opposite to each other; forming a roughened layer by lapping the second surface of the semiconductor wafer, the roughened layer having a surface roughness greater than a surface roughness of the second surface of the semiconductor wafer before lapping; pressing a blade against the roughened layer to form vertical cracks in a surface layer of the semiconductor wafer; removing the roughened layer after forming the vertical cracks; forming a back surface electrode on a back surface of the semiconductor wafer on which the vertical cracks are formed; after forming the back surface electrode, pressing the first surface of the semiconductor wafer and cleaving the semiconductor wafer into a plurality of pieces with the vertical cracks as starting points.

2. The manufacturing method according to claim 1, wherein, The forming of the roughened layer is performed in a state where a protective tape or a support substrate is attached to the first surface of the semiconductor wafer to protect the first surface.

3. The production method according to claim 1 or 2, wherein The removing of the roughened layer includes removing the roughened layer by polishing.

4. The method of manufacturing according to claim 1 or 2, wherein the preparing of the semiconductor wafer includes preparing the semiconductor wafer made of silicon carbide, and the removing of the roughened layer includes silicidizing the back surface electrode and the roughened layer after forming the back surface electrode covering the roughened layer.

5. The method of manufacturing according to claim 4, wherein the forming of the back surface electrode includes forming the back surface electrode in which a portion in contact with the roughened layer is mainly composed of at least one metal material selected from the group consisting of nickel, titanium, molybdenum, tantalum, platinum, and cobalt, wherein the term "mainly composed of" means that a content of a main component exceeds 50% by volume, and the removing of the roughened layer includes silicidizing the back surface electrode and the roughened layer by heat treatment.

6. The manufacturing method according to claim 4, wherein, The forming of the back surface electrode includes forming the back surface electrode having a thickness greater than a thickness of the roughened layer. The forming of the back surface electrode includes forming the back surface electrode having a thickness greater than a thickness of the roughened layer.

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