Semiconductor memory device

Abstract

A semiconductor storage device of an embodiment includes a memory cell array. The memory cell array includes a plurality of sub-arrays. The sub-arrays include a plurality of memory portions, a plurality of first semiconductor layers electrically connected to the plurality of memory portions, a plurality of first gate electrodes respectively facing the plurality of first semiconductor layers, a first wiring electrically connected to the plurality of first semiconductor layers, a plurality of second wirings connected to the plurality of first gate electrodes, a plurality of second semiconductor layers electrically connected to first end portions of the plurality of second wirings, a plurality of second gate electrodes facing the plurality of second semiconductor layers, and a third wiring electrically connected to the plurality of second semiconductor layers. The memory cell array includes a plurality of fourth wirings extending in one direction across the plurality of sub-arrays and connected to the plurality of second gate electrodes.

Description

[0001] This application is based on and claims the priority interest of Japanese Patent Application No. 2021-205591, filed on December 17, 2021, the contents of which are incorporated herein by reference in their entirety. Technical Field

[0002] This embodiment relates to semiconductor memory devices. Background Technology

[0003] With the increasing integration of semiconductor memory devices, research has been conducted on the three-dimensionalization of semiconductor memory devices. Summary of the Invention

[0004] One implementation provides a semiconductor memory device capable of high integration.

[0005] One embodiment of a semiconductor memory device includes a memory cell array. The memory cell array includes a plurality of subarray strings arranged in a first direction. Each of the plurality of subarray strings includes a plurality of subarrays arranged in a second direction intersecting the first direction. Each of the plurality of subarrays includes a plurality of memory units, a plurality of first semiconductor layers, a plurality of first gate electrodes, a first wiring, a plurality of second wirings, a plurality of second semiconductor layers, a plurality of second gate electrodes, and a third wiring. The plurality of memory units are arranged in a third direction intersecting the first and second directions. The plurality of first semiconductor layers are arranged in the third direction and electrically connected to the plurality of memory units. The plurality of first gate electrodes are arranged in the third direction and face each of the plurality of first semiconductor layers. The first wirings extend in the third direction and are electrically connected to the plurality of first semiconductor layers. The plurality of second wirings are arranged in the third direction, extend in the first direction, and are connected to the plurality of first gate electrodes. The plurality of second semiconductor layers are arranged in the third direction and are electrically connected to a first end of the plurality of second wirings in the first direction. The plurality of second gate electrodes are arranged in the third direction and face the plurality of second semiconductor layers. The third wiring extends in the third direction and is electrically connected to a plurality of second semiconductor layers. Each of the plurality of subarray strings has a plurality of fourth wirings. The plurality of fourth wirings extend in the second direction, spanning at least two of the plurality of subarrays arranged in the second direction, and are connected to at least two of the plurality of second gate electrodes.

[0006] Based on the above structure, a highly integrated semiconductor memory device can be provided. Attached Figure Description

[0007] Figure 1 This is a schematic perspective view showing a portion of the structure of the semiconductor memory device according to the first embodiment.

[0008] Figure 2 It represents the storage cell array layer L. MCAA schematic plan view of the structure.

[0009] Figure 3 This indicates the subarray MCA S A schematic circuit diagram of a portion of the structure.

[0010] Figure 4 It represents the storage cell array layer L. MCA A schematic plan view of a portion of the structure.

[0011] Figure 5 This represents the subarray string MCA C A schematic 3D diagram of a portion of the structure.

[0012] Figure 6 This represents the subarray string MCA C A schematic XY cross-sectional view of a portion of the structure.

[0013] Figure 7 This represents the subarray string MCA C A schematic XY cross-sectional view of a portion of the structure.

[0014] Figure 8 This represents the subarray string MCA C A schematic XY cross-sectional view of a portion of the structure.

[0015] Figure 9 It is along line A-A′ Figure 7 and Figure 8 The structure shown is cut off, and a schematic XZ cross-section is observed along the direction of the arrow.

[0016] Figure 10 It is along line B-B' Figure 7 and Figure 8 The diagram shows a schematic YZ cross-section of the structure, viewed along the direction of the arrow.

[0017] Figure 11 This indicates a hook-up region R. HU A schematic XY cross-sectional view of a portion of the structure.

[0018] Figure 12 It is along the C-C′ line Figure 11 The structure shown is cut off, and a schematic XZ cross-section is observed along the direction of the arrow.

[0019] Figure 13 It represents transistor layer L T A schematic plan view of the structure.

[0020] Figure 14 This is a schematic plan view showing the structure of the sensing amplifier unit (SAU).

[0021] Figure 15 This is a schematic circuit diagram showing a portion of the structure of the sense amplifier unit (SAU).

[0022] Figure 16 It represents transistor layer L T A schematic plan view of a portion of the structure.

[0023] Figure 17 This is a schematic circuit diagram used to explain the readout operation of the semiconductor memory device according to the first embodiment.

[0024] Figure 18 It is a schematic circuit diagram used to illustrate the readout action.

[0025] Figure 19 It is a schematic circuit diagram used to illustrate the readout action.

[0026] Figure 20 It is a schematic circuit diagram used to illustrate the readout action.

[0027] Figure 21 It is a schematic circuit diagram used to illustrate the readout action.

[0028] Figure 22 It is a schematic circuit diagram used to illustrate the readout action.

[0029] Figure 23 This refers to the memory cell array layer L of the semiconductor memory device according to the second embodiment. MCA A schematic plan view of the structure.

[0030] Figure 24 This indicates the subarray MCA S A schematic XY cross-sectional view of a portion of the structure.

[0031] Figure 25 This indicates the subarray MCA S A schematic XY cross-sectional view of a portion of the structure.

[0032] Figure 26 This indicates the subarray MCA S A schematic XY cross-sectional view of a portion of the structure.

[0033] Figure 27 It is along line B-B' Figure 25 and Figure 26 The structure shown is cut off, and a schematic XZ cross-section is observed along the direction of the arrow.

[0034] Figure 28It is along line D-D′ Figure 25 and Figure 26 The diagram shows a schematic YZ cross-section of the structure, viewed along the direction of the arrow.

[0035] Figure 29 This refers to the memory cell array layer L of the semiconductor memory device according to the third embodiment. MCA A schematic plan view of the structure.

[0036] Figure 30 This indicates the subarray MCA S A schematic XY cross-sectional view of a portion of the structure.

[0037] Figure 31 This indicates the subarray MCA S A schematic XY cross-sectional view of a portion of the structure.

[0038] Figure 32 It is along the E-E′ line Figure 30 and Figure 31 The structure shown is cut off, and a schematic XZ cross-section is observed along the direction of the arrow. Detailed Implementation

[0039] Next, the semiconductor memory device according to the embodiments will be described in detail with reference to the accompanying drawings. Furthermore, the following embodiments are merely examples and are not intended to limit the scope of the invention. Additionally, the following drawings are schematic, and for ease of explanation, some structures may be omitted. Also, sometimes the same reference numerals are used for parts common to multiple embodiments, and descriptions are omitted.

[0040] Furthermore, when "semiconductor memory device" is mentioned in this specification, it sometimes means a memory die, and sometimes it means a storage system including a controller die, such as a memory chip, memory card, or SSD (Solid State Drive). Further, it sometimes also means the structure of a host computer, such as a smartphone, tablet computer, or personal computer.

[0041] Furthermore, in this specification, when it is mentioned that the first structure is "electrically connected" to the second structure, it can mean that the first structure is directly connected to the second structure, or that the first structure is connected to the second structure via wiring, semiconductor components, or transistors. For example, in the case of three transistors connected in series, even if the second transistor is in the off state, the first transistor is "electrically connected" to the third transistor.

[0042] In addition, in this specification, the predetermined direction parallel to the top surface of the substrate is referred to as the X direction, the direction parallel to the top surface of the substrate and perpendicular to the X direction is referred to as the Y direction, and the direction perpendicular to the top surface of the substrate is referred to as the Z direction.

[0043] In addition, in this specification, the direction along the predetermined surface is sometimes referred to as the first direction, the direction along the predetermined surface and intersecting the first direction is referred to as the second direction, and the direction intersecting the predetermined surface is referred to as the third direction. These first, second, and third directions may correspond to any of the X, Y, and Z directions, or they may not correspond to each other.

[0044] Furthermore, in this specification, the terms "upper" and "lower" are used with the substrate as a reference. For example, the direction away from the substrate along the Z direction is called "upper," and the direction closer to the substrate along the Z direction is called "lower." Additionally, when referring to a structure as "below" or "lower end," it refers to the substrate-side surface or end of that structure; when referring to "upper" or "upper end," it refers to the surface or end of that structure opposite to the substrate. Furthermore, surfaces intersecting the X or Y direction are called "side surfaces," etc.

[0045] [First Implementation]

[0046] [structure]

[0047] Figure 1 This is a schematic perspective view showing a portion of the structure of the semiconductor memory device according to the first embodiment. The semiconductor memory device according to this embodiment includes a semiconductor substrate (substrate) Sub and a memory cell array layer L disposed above the semiconductor substrate Sub. MCA And the transistor layer L between these T The following sections will explain these structures in turn.

[0048] [Semiconductor Substrate]

[0049] The semiconductor substrate Sub is, for example, a silicon (Si) semiconductor substrate containing p-type impurities such as boron (B). A memory cell array layer L can also be disposed on the semiconductor substrate Sub. MCA It is part of the peripheral circuit that controls the structure within it.

[0050] [Storage cell array layer L] MCA ]

[0051] Figure 2 It represents the storage cell array layer L. MCA A schematic plan view of the structure. Storage cell array layer L MCA It has two common wiring regions R arranged in the Y direction WCThese two wiring common areas R WC Each has multiple subarray strings MCA arranged in the X direction C These multiple subarray strings MCA C Each has multiple subarrays MCA arranged in the Y direction. S Additionally, in each subarray string MCA C A connection area R is provided at the end in the Y direction. HU .

[0052] Figure 3 This indicates the subarray MCA S A schematic circuit diagram of a portion of the structure. Subarray MCA S It has multiple storage layers ML0 to ML3, multiple bit lines BL connected to these multiple storage layers ML0 to ML3, multiple global bit lines GBL electrically connected to the multiple bit lines BL, and plate lines PL connected to the multiple storage layers ML0 to ML3.

[0053] Storage layers ML0 to ML3 each have multiple word lines WL0 to WL2 and multiple memory cells MC connected to these word lines WL0 to WL2. Each memory cell MC has a transistor TrC and a capacitor CpC. The source electrode of transistor TrC is connected to bit line BL. The drain electrode of transistor TrC is connected to capacitor CpC. The gate electrode of transistor TrC is connected to any one of word lines WL0 to WL2. One electrode of capacitor CpC is connected to the drain electrode of transistor TrC. The other electrode of capacitor CpC is connected to board line PL.

[0054] In addition, each bit line BL is connected to multiple memory cells MC corresponding to multiple memory layers ML0 to ML3. Furthermore, each bit line BL is connected to the global bit line GBL.

[0055] In addition, memory layers ML0 to ML3 each have multiple transistors TrL0a, TrL0b, TrL1a, TrL1b, TrL2a, TrL2b, TrL3a, and TrL3b (hereinafter sometimes referred to as "transistors TrL") corresponding to multiple word lines WL0 to WL2. The drain electrode of transistor TrL is connected to any one of the word lines WL0 to WL2. The source electrode of transistor TrL is connected to row select lines Rx0a, Rx0b, Rx1a, Rx1b, Rx2a, and Rx2b (hereinafter sometimes referred to as "row select lines Rx"). The gate electrode of transistor TrL is connected to main word lines MWL0a, MWL0b, MWL1a, MWL1b, MWL2a, MWL2b, MWL3a, and MWL3b (hereinafter sometimes referred to as "main word lines MWL").

[0056] Furthermore, the row select line Rx is connected to multiple transistors TrL corresponding to the multiple memory layers ML0 to ML3. Additionally, the main word lines MWL0a, MWL1a, MWL2a, and MWL3a are commonly connected to all transistors TrL0a, TrL1a, TrL2a, and TrL3a corresponding to memory layers ML0 to ML3, respectively. Similarly, the main word lines MWL0b, MWL1b, MWL2b, and MWL3b are commonly connected to all transistors TrL0b, TrL1b, TrL2b, and TrL3b corresponding to memory layers ML0 to ML3, respectively.

[0057] Figure 4 It represents the storage cell array layer L. MCA A schematic plan view of a portion of the structure. In the common wiring area R... WC In the middle, multiple row selection lines Rx are arranged in multiple subarrays MCA along the X direction. S They share a common ground connection. These multiple row select lines Rx are each connected to a driver circuit (not shown). Additionally, in the common wiring area R... WC In the middle, multiple main word lines (MWL) are arranged in multiple subarrays (MCA) along the Y direction. S They share a common ground connection. These multiple main word lines (MWL) are connected via connection area R. HU The structure in the diagram is connected to the driver circuit DRV described later. MWL .

[0058] Figure 5 This represents the subarray string MCA C A schematic 3D diagram of a portion of the structure. Figure 6 This represents the subarray string MCA C A schematic XY cross-sectional view of a portion of the structure. Furthermore, in Figure 6 A portion of the structure (insulating layers 121 and 151, described later) has been omitted. Figure 7 and Figure 8 This represents the subarray string MCA C A schematic XY cross-sectional view of a portion of the structure. Furthermore... Figure 7 and Figure 8 The XY cross-sections at different height positions are shown. Figure 9 It is along line A-A′ Figure 7 and Figure 8 The diagram shows a schematic YZ cross-section of the structure, viewed along the direction of the arrow. Figure 10 It is along line B-B' Figure 7 and Figure 8 The structure shown is cut off, and a schematic XZ cross-section is observed along the direction of the arrow.

[0059] like Figure 5 As shown, the subarray string MCAC It has multiple memory layers ML0 to ML3 arranged in the Z direction and multiple global bit lines GBL disposed below them. In addition, an insulating layer 103 of silicon oxide (SiO2) or the like is disposed between the multiple memory layers ML0 to ML3.

[0060] like Figure 6 As shown, storage layers ML0 to ML3 have storage cell regions R MC , and respectively set in the storage cell region R in the X direction MC Transistor regions R on one side and the other side TrL and the main character line area R MWL Transistor region R TrL They are respectively set in the storage unit area R MC With the main character line area R MWL between.

[0061] In storage cell region R MC A plurality of insulating layers 101 and a plurality of conductive layers 102 are arranged alternately in the Y direction. For example... Figure 5 As shown, these multiple insulating layers 101 and multiple conductive layers 102 extend in the X and Z directions, and divide the storage layers ML0 to ML3 in the Y direction.

[0062] The insulating layer 101 may contain, for example, silicon oxide (SiO2).

[0063] The conductive layer 102 may include, for example, a stacked structure of titanium nitride (TiN) and tungsten (W). The conductive layer 102 may serve as, for example, a plate line PL (…). Figure 3 To fulfill its function.

[0064] In addition, for example, Figure 6 As shown, in the storage cell region R MC A plurality of conductive layers 104 are disposed between the insulating layer 101 and the conductive layer 102. The plurality of conductive layers 104 are arranged in the X direction and extend in the Z direction, passing through the plurality of storage layers ML0 to ML3.

[0065] The conductive layer 104 may include, for example, a stacked structure of indium tin oxide (ITO), titanium nitride (TiN), and tungsten (W). The conductive layer 104 may serve as, for example, a bit line BL (…). Figure 3 To perform its function. Multiple transistors TrC corresponding to the multiple bits BL contained in the memory layers ML0 to ML3 are provided.

[0066] In storage cell region R MC In, for example Figure 6As shown, the storage layers ML0 to ML3 include a plurality of transistor structures 110 disposed corresponding to a plurality of conductive layers 104, a conductive layer 120 disposed between the plurality of transistor structures 110 and the insulating layer 101, and a plurality of capacitor structures 130 disposed between the plurality of transistor structures 110 and the conductive layer 102.

[0067] For example, Figure 8 and Figure 9 As shown, the transistor structure 110 includes an insulating layer 111 disposed on the outer peripheral surface of the conductive layer 104, a conductive layer 112 disposed on the outer peripheral surface of the insulating layer 111, an insulating layer 113 disposed on the upper, lower and outer peripheral surfaces of the conductive layer 112, and a semiconductor layer 114 disposed on the upper, lower and outer peripheral surfaces of the insulating layer 113.

[0068] In addition, in such Figure 8 In the illustrated XY cross-section, the outer peripheral surface of the insulating layer 111 may, for example, be formed along a circle centered on the center position of the conductive layer 104. Additionally, the side surface of one side (the conductive layer 102 side) of the conductive layer 112, insulating layer 113, and semiconductor layer 114 in the Y direction may also be formed along a circle centered on the center position of the conductive layer 104. Furthermore, the two side surfaces of the conductive layer 112, insulating layer 113, and semiconductor layer 114 in the X direction may be formed in a straight line along the side surface of the insulating layer 115.

[0069] The insulating layer 111 may contain, for example, silicon oxide (SiO2). The insulating layer 111 extends throughout the entire periphery and surrounds the outer peripheral surface of the conductive layer 104.

[0070] Conductive layer 112, for example, serves as a transistor TrC ( Figure 3 The gate electrode functions as a conductor. The conductive layer 112 includes, for example, a stacked structure of titanium nitride (TiN) and tungsten (W). The conductive layer 112 extends throughout the entire periphery, surrounding the outer peripheral surface of the insulating layer 111. Figure 8 As shown, multiple conductive layers 112 arranged in the X direction are commonly connected to a conductive layer 120 extending in the X direction.

[0071] Insulating layer 113, for example, serves as transistor TrC ( Figure 3 The gate insulating film of the conductive layer 112 functions. The insulating layer 113 contains, for example, silicon oxide (SiO2). The insulating layer 113 covers the two sides of the conductive layer 112 in the X direction and one side (the side of the conductive layer 102) in the Y direction.

[0072] Semiconductor layer 114, for example, serves as transistor TrC ( Figure 3The channel region functions as a semiconductor layer. The semiconductor layer 114 can be, for example, a semiconductor containing at least one element selected from gallium (Ga) and aluminum (Al), indium (In), zinc (Zn), and oxygen (O), or other oxide semiconductors. The semiconductor layer 114 covers both sides of the conductive layer 112 in the X direction and one side (the conductive layer 102 side) in the Y direction, separated by the insulating layer 113. Figure 9 As shown, multiple semiconductor layers 114 arranged in the Z direction are commonly connected to a conductive layer 104 extending in the Z direction. Figure 7 As shown, an insulating layer 115, such as silicon oxide (SiO2), is disposed between two adjacent semiconductor layers 114 in the X direction.

[0073] Conductive layer 120, for example, serves as word line WL ( Figure 3 ) to perform its function. For example, Figure 8 As shown, the conductive layer 120 extends in the X direction and is connected to a plurality of conductive layers 112 arranged in the X direction. The conductive layer 120 may have, for example, a stacked structure of titanium nitride (TiN) and tungsten (W). Furthermore, for example, Figure 9 As shown, the top and bottom of the conductive layer 120 are covered by an insulating layer 121 of silicon oxide (SiO2) or the like. The insulating layer 121 is connected to the insulating layers 111 and 113.

[0074] For example, Figure 9 As shown, the capacitor structure 130 includes a conductive layer 131, a conductive layer 132 disposed on the top, bottom, and sides of the conductive layer 131 in the Y direction, an insulating layer 133 disposed on the top, bottom, and sides of the conductive layer 132 in the Y direction, a conductive layer 134 disposed on the top, bottom, and sides of the insulating layer 133 in the Y direction, an insulating layer 135 disposed on the top, bottom, and sides of the conductive layer 134 in the Y direction, a conductive layer 136 disposed on the top, bottom, and sides of the insulating layer 135 in the Y direction, and a conductive layer 137 disposed on the top, bottom, and sides of the conductive layer 136 in the Y direction.

[0075] Conductive layers 131, 132, 136, and 137 serve as capacitor CpC. Figure 3 The electrode on one side of the conductive layer 102 functions. Conductive layers 131 and 137 contain, for example, tungsten (W). Conductive layers 132 and 136 contain, for example, titanium nitride (TiN). Conductive layers 131, 132, 136, and 137 are connected to conductive layer 102.

[0076] Insulating layers 133 and 135 serve as capacitor CpC ( Figure 3 The insulating layer 133 and 135 can be, for example, aluminum oxide (Al2O3) or other insulating metal oxides.

[0077] Conductive layer 134, for example, serves as capacitor CpC ( Figure 3 The other electrode functions. The conductive layer 134 includes, for example, indium tin oxide (ITO). The conductive layer 134 is insulated from the conductive layers 131, 132, 136, and 137 through insulating layers 133 and 135. The conductive layer 134 is connected to the side of the semiconductor layer 114 in the Y direction.

[0078] For example, Figure 6 As shown, in transistor region R TrL A plurality of insulating layers 105 are provided, arranged in the Y direction. These plurality of insulating layers 105 extend in the Z direction, passing through a plurality of storage layers ML0 to ML3.

[0079] The insulating layer 105 may contain, for example, silicon oxide (SiO2).

[0080] Additionally, in the transistor region R TrL Multiple conductive layers 106 are disposed between insulating layers 105. The multiple conductive layers 106 are arranged in the Y direction, penetrating multiple storage layers ML0 to ML3, and extending in the Z direction (see reference). Figure 10 ).

[0081] The conductive layer 106 may include, for example, a stacked structure of indium tin oxide (ITO), titanium nitride (TiN), and tungsten (W). The conductive layer 106 may serve as, for example, a row selection line Rx. Figure 3 To perform its function. Multiple row select lines Rx are provided corresponding to multiple transistors TrL contained in memory layers ML0 to ML3.

[0082] In transistor region R TrL In, for example Figure 6 As shown, the storage layers ML0 to ML3 have multiple transistor structures 140 disposed corresponding to the multiple conductive layers 106.

[0083] For example, Figure 8 and Figure 10 As shown, the transistor structure 140 includes an insulating layer 141 disposed on the outer peripheral surface of the conductive layer 106, a conductive layer 142 disposed on the outer peripheral surface of the insulating layer 141, an insulating layer 143 disposed on the upper, lower and outer peripheral surfaces of the conductive layer 142, and a semiconductor layer 144 disposed on the upper, lower and outer peripheral surfaces of the insulating layer 143.

[0084] In addition, in such Figure 8In the illustrated XY cross-section, the outer peripheral surface of the insulating layer 141 may, for example, be formed along a circle centered on the center position of the conductive layer 106. Furthermore, the side surface of one side (the conductive layer 120 side) of the conductive layer 142, the insulating layer 143, and the semiconductor layer 144 in the X direction may also be formed along a circle centered on the center position of the conductive layer 106. Additionally, the two side surfaces of the conductive layer 142, the insulating layer 143, and the semiconductor layer 144 in the Y direction may be formed as straight lines along the side surface of the insulating layer 105.

[0085] The insulating layer 141 may contain, for example, silicon oxide (SiO2). The insulating layer 141 extends throughout the entire periphery and surrounds the outer peripheral surface of the conductive layer 106.

[0086] Conductive layer 142, for example, serves as a transistor TrL ( Figure 3 The gate electrode functions as a conductor. The conductive layer 142 includes, for example, a stacked structure of titanium nitride (TiN) and tungsten (W). The conductive layer 142 extends throughout the entire periphery, surrounding the outer peripheral surface of the insulating layer 141. Figure 8 As shown, multiple conductive layers 142 arranged in the Y direction are commonly connected to a conductive layer 150 extending in the Y direction.

[0087] Insulating layer 143, for example, serves as transistor TrL ( Figure 3 The gate insulating film of the conductive layer 142 functions. The insulating layer 143 contains, for example, silicon oxide (SiO2). The insulating layer 143 covers the two sides of the conductive layer 142 in the Y direction and one side (the side of the conductive layer 120) in the X direction.

[0088] Semiconductor layer 144, for example, serves as transistor TrL ( Figure 3 The channel region functions as a semiconductor layer. The semiconductor layer 144 can be, for example, a semiconductor containing at least one element selected from gallium (Ga) and aluminum (Al), indium (In), zinc (Zn), and oxygen (O), or other oxide semiconductors. The semiconductor layer 144 covers both sides of the conductive layer 142 in the Y direction and one side (the conductive layer 120 side) in the X direction, separated by the insulating layer 143. Figure 10 As shown, multiple semiconductor layers 144 arranged in the Z direction are commonly connected to a conductive layer 106 extending in the Z direction. Figure 8 As shown, an insulating layer 105 is provided between two adjacent semiconductor layers 144 in the Y direction. Furthermore, the semiconductor layers 144 are connected to the ends of the conductive layer 120 in the X direction.

[0089] In the main character line area R MWL In, for example Figure 6 As shown, the storage layers ML0 to ML3 have conductive layers 150 extending in the Y direction along the plurality of transistor structures 140.

[0090] Conductive layer 150 ( Figure 8 For example, as the main word line MWL ( Figure 3 ) To perform its function. In the common wiring area R WC ( Figure 2 , Figure 4 In this structure, the conductive layer 150 spans multiple subarrays MCA arranged in the Y direction. S And extending along the Y direction. Additionally, the conductive layer 150 and these multiple sub-arrays MCA S The multiple conductive layers 142 contained therein are connected. For example, in the subarray string MCA C Includes 128 subarrays MCA S And in the subarray MCA S When there are 64 word lines WL (conductive layer 120) arranged along the Y direction, conductive layer 150 is connected to 8192 (=128 × 64) conductive layers 142. Conductive layer 150 may have, for example, a stacked structure of titanium nitride (TiN) and tungsten (W). Furthermore, for example... Figure 10 As shown, the top and bottom of the conductive layer 150 are covered by an insulating layer 151 of silicon oxide (SiO2) or the like. The insulating layer 151 is connected to the insulating layer 141 and the insulating layer 143.

[0091] In addition, such as Figure 5 As shown, multiple global bit lines (GBLs) are disposed below the storage layers ML0 to ML3. The global bit lines (GBLs) extend in the Y direction and are arranged in the X direction. The global bit lines (GBLs) may include, for example, a stacked structure of titanium nitride (TiN) and tungsten (W). The global bit lines (GBLs) are connected to the lower ends of the multiple conductive layers 104 arranged in the Y direction.

[0092] In addition, such as Figure 5 As shown, etch blocks 109 are provided between storage layers ML0 to ML3 and multiple global bit lines GBL. The etch blocks 109 are correspondingly provided with insulating layers 101, 102, 105, and 106, and are connected to their lower ends. The etch blocks 109 have a shape that follows the shape of the lower end of the corresponding structure. For example, the etch block 109 corresponding to insulating layer 101 extends in the X direction corresponding to insulating layer 101. Similarly, the etch block 109 corresponding to conductive layer 102 extends in the X direction corresponding to conductive layer 102.

[0093] In addition, an insulating layer 103a is provided between the storage layers ML0 to ML3 and the etch barrier 109 (see reference). Figure 9 Insulating layer 103a may, for example, contain a material different from other insulating layers 103. For example, insulating layer 103a may also contain silicon oxide (SiOC) or the like.

[0094] Figure 11 It represents the connected region R. HU A schematic XY cross-sectional view of a portion of the structure. Furthermore, in Figure 11 Some structures (insulating layers 121 and 151) are omitted. Figure 12 It is along the C-C′ line Figure 11 The structure shown is cut off, and a schematic XZ cross-section is observed along the direction of the arrow.

[0095] In the connected region R HU In, for example Figure 11 As shown, storage layers ML0 to ML3 each have a platform portion T of the conductive layer 150. The platform portion T is, for example, a portion on the upper surface of the conductive layer 150 that does not overlap with other conductive layers 150 when viewed from above. Figure 11 In the example, the platform portion T is disposed at the end of the conductive layer 150 in the Y direction.

[0096] In addition, for example, Figure 11 As shown, in the connected region R HU Multiple contact electrodes 107 are provided, arranged in the X direction. For example... Figure 12 As shown, the contact electrode 107 extends in the Z direction and is connected to the platform portion T of the conductive layer 150 at its lower end. Furthermore, a plurality of contact electrodes 107 arranged in the X direction are connected to conductive layers 150 disposed at different heights. The contact electrodes 107 may include, for example, a stacked structure of titanium nitride (TiN) and tungsten (W).

[0097] Furthermore, contact electrode 107 is connected to all memory layers ML0-ML3. Therefore, a main word line region R... MWL The number of contact electrodes 107 included is only the number of storage layers ML0 to ML3 arranged in the Z direction.

[0098] [Transistor layer L] T ]

[0099] In transistor layer L T ( Figure 1 ) is equipped with a storage cell array layer L MCA It is part of the peripheral circuitry controlled by the structure in the transistor layer. To implement such a peripheral circuitry, a portion of the transistor layer L... T It contains multiple transistors, wiring, etc. These multiple transistors, for example, are integrated into a semiconductor substrate Sub( Figure 1 The surface of the channel is used as the channel area.

[0100] Figure 13 It represents transistor layer L T A schematic plan view of the structure. Transistor layer LT It has a common area R with two wirings WC ( Figure 2 The two sensing amplifier regions R are set accordingly. SA These two sensing amplifier regions R SA Each has multiple subarray strings MCA C Correspondingly, multiple sensing amplifier modules (SAMs) are arranged. Each of these multiple sensing amplifier modules (SAMs) has multiple sensing amplifier units (SAUs) arranged in the Y direction. Viewed from above, these multiple sensing amplifier units (SAUs) are respectively positioned adjacent to two sub-arrays (MCAs) along the Y direction. S ( Figure 2 (overlapping areas)

[0101] Additionally, the two sensing amplifier regions R are arranged in the Y direction. SA Multiple driver circuits DRV are arranged between them. MWL These multiple driver circuits DRV MWL With multiple sub-arrays MCA respectively S ( Figure 2 Set accordingly.

[0102] Figure 14 This is a schematic plan view showing the structure of a sense amplifier unit (SAU). The sense amplifier unit (SAU) has multiple sense amplifiers (SA) arranged in the X and Y directions. In the illustrated example, four sense amplifiers (SA) are arranged in the Y direction.

[0103] exist Figure 14 The diagram illustrates multiple data input / output signal lines IO and / IO (in... Figure 14 In this example, the data input / output signal lines are IO<0> to IO<7> and / IO<0> to / IO<7>. The sensing amplifier SA is connected to one of the multiple data input / output signal lines IO and one of the multiple data input / output signal lines / IO.

[0104] Figure 15 This is a schematic circuit diagram showing a portion of the structure of the sense amplifier unit (SAU). Figure 15 The image illustrates a portion of the multiple sense amplifiers SA contained in a sense amplifier unit SAU.

[0105] As described above, when viewed from the Z direction, the sensing amplifier unit SAU is positioned adjacent to the two subarrays MCA in the Y direction. S Overlapping regions. The following will discuss these two subarrays, MCA. S The global bit line (GBL) corresponding to one side is called the global bit line (GBL). CAdditionally, the global bit line (GBL) corresponding to the other side is called the global bit line (GBL). T The multiple sense amplifiers SA contained in the sense amplifier unit SAU are respectively connected to the global bit line GBL. C GBL T .

[0106] In addition, Figure 15 The diagram shows the supply voltage V. DD voltage supply line W VDD Supply voltage V DD Half the size of the voltage V DD / 2 voltage supply line W VDD / 2 and the supply of grounding voltage V SS voltage supply line W VSS These voltage supply lines W VDD W VDD / 2 W VSS All sense amplifiers SA are commonly connected to the sense amplifier unit SAU.

[0107] In addition, Figure 15 The diagram shows the signal supply lines W that provide the enable signals SAEP and SAEN to the sensing amplifier SA. SAEP W SAEN And the signal supply line W that provides the equalization signal EQL EQL These signal supply lines W SAEP W SAEN W EQL All sense amplifiers SA are commonly connected to the sense amplifier unit SAU.

[0108] In addition, Figure 15 The diagram shows a portion of the multiple column selection lines (CSL) (in Figure 15 In the example, the column selection lines are CSL0 and CSL1. For example, see reference... Figure 14 As explained, the sensing amplifier unit SAU according to this embodiment includes a plurality of sensing amplifiers SA arranged in the X and Y directions. Here, for example, the four sensing amplifiers SA in the 2n+1th group (n is an integer greater than or equal to 0) from the negative side of the X direction, and the four sensing amplifiers SA in the 2n+2th group from the negative side of the X direction are grouped together. In this case, the sensing amplifier unit SAU has a plurality of such groups. Column selection lines CSL are provided corresponding to these plurality of groups. These plurality of column selection lines CSL are commonly connected to the eight sensing amplifiers SA contained in the corresponding group.

[0109] In addition, Figure 15 The diagram shows a portion of multiple data input / output signal lines IO and / IO (in... Figure 15 In the example, the data input / output signal lines are IO<0> to IO<3> and / IO<0> to / IO<3>. Multiple data input / output signal lines IO and / IO are commonly connected to all groups arranged in the X direction.

[0110] The sensing amplifier unit (SAU) includes: equalizer circuit C EQ When in standby mode, it accesses the global bit line GBL. C GBL T The voltage is balanced; amplifier circuit C SUP C SUN Its global bit line GBL is used in readout operations, etc. C GBL T The signal is differentially amplified; and the switching circuit C... SW It enables the global bit line GBL in read operations, etc. C GBL T It is connected to the data input / output signal lines IO and / IO.

[0111] Equalizer circuit C EQ On signal supply line W EQL When the voltage is "H (high level)", the global bit line GBL is affected. C GBL T The voltage is equalized. That is, the global bit line (GBL) is made equalized. C GBL T They are interconnected. Additionally, the global bit line GBL is enabled. C GBL T With voltage supply line W VDD / 2 Conduction.

[0112] In addition, equalizer circuit C EQ On signal supply line W EQL When the voltage is "L (low level)", the global bit line GBL is deactivated. C GBL T Voltage equalization. That is, equalizing the global bit line GBL. C GBL T Mutual electrical disconnection. Additionally, the global bit line GBL... C GBL T From voltage supply line W VDD / 2 Electrical disconnection.

[0113] Equalizer circuit C EQ It has the ability to set global bit line GBL C GBL T The transistor Tr11 between them is set in the global bit line GBL. C and voltage supply line WVDD / 2 The transistor Tr12 between and set on the global bit line GBL T and voltage supply line W VDD / 2 Transistor Tr13 is located between transistors Tr11, Tr12, and Tr13. Transistors Tr11, Tr12, and Tr13 are, for example, NMOS type field-effect transistors. The gate electrodes of transistors Tr11, Tr12, and Tr13 are connected to the signal supply line W. EQL .

[0114] Amplifier circuit C SUP C SUN On signal supply line W SAEP The voltage is "L", and the signal supply line W SAEN When the voltage is "H", the global bit line GBL is... C GBL T The signal is differentially amplified.

[0115] Amplifier circuit C SUP It has the ability to set global bit line GBL C Transistor Tr21 between node N0 and global bit line GBL is set. T The transistor Tr22 between node N0 and the voltage supply line W VDD Transistor Tr23 is located between these transistors. Transistors Tr21, Tr22, and Tr23 are, for example, PMOS field-effect transistors. The gate electrode of transistor Tr21 is connected to the global bit line GBL. T The gate electrode of transistor Tr22 is connected to the global bit line GBL. C The gate electrode of transistor Tr23 is connected to the signal supply line W. SAEP .

[0116] Amplifier circuit C SUN It has the ability to set global bit line GBL C Transistor Tr31 between node N1 and the global bit line GBL T Transistor Tr32 connects to node N1. Node N1 is electrically connected to the voltage supply line W via transistor Tr33. VSS Transistors Tr31, Tr32, and Tr33 are, for example, NMOS field-effect transistors. The gate electrode of transistor Tr31 is connected to the global bit line GBL. T The gate electrode of transistor Tr32 is connected to the global bit line GBL. C The gate electrode of transistor Tr33 is connected to the signal supply line W. SAEN .

[0117] Switching circuit C SW It has the ability to set global bit line GBL CTransistor Tr41, which is connected to the data input / output signal lines IO and / IO, and is set on the global bit line GBL. T Transistor Tr42 is connected to the data input / output signal lines IO and / IO. Transistors Tr41 and Tr42 are, for example, NMOS field-effect transistors. The gate electrodes of transistors Tr41 and Tr42 are connected to multiple column select lines CSL.

[0118] Figure 16 It represents transistor layer L T A schematic plan view of a portion of the structure. Data input / output signal lines IO and / IO are located in the sense amplifier region R. SA Multiple sense amplifier units (SAUs) arranged in the X direction are connected in a common manner. Additionally, multiple column selection lines (CSLs) are located in the sense amplifier region R. SA The common ground is connected to multiple sense amplifier units (SAU) arranged in the Y direction. Additionally, the signal supply line W... SAEP W SAEN Each sensing amplifier unit (SAU) is set independently.

[0119] [Read the action]

[0120] Figure 17 It is a subarray MCA used in the readout operation of the semiconductor memory device according to the first embodiment. S A schematic circuit diagram illustrating the action.

[0121] During a read operation, one of several memory layers ML0 to ML3 is selected. In the illustrated example, memory layer ML0 is selected. When selecting memory layers ML0 to ML3, for example, a voltage V is supplied to the main word line MWL0a corresponding to the memory layer ML0 that is the target of the read operation, from among the multiple main word lines MWL0a, MWL1a, MWL2a, and MWL3a. ON ′, supply voltage V to other main word lines MWL1a, MWL2a, and MWL3a OFF Additionally, for example, a voltage V is supplied to the main word line MWL0b corresponding to the memory layer ML0 that is the object of the read operation, among the multiple main word lines MWL0b, MWL1b, MWL2b, and MWL3b. OFF ′, supply voltage V to other main word lines MWL1b, MWL2b, and MWL3b ON ′.

[0122] Voltage V ON For example, it has the magnitude to which the transistor TrL is turned on (ON). Voltage V OFFFor example, it has the magnitude to which the transistor TrL is in the off (OFF) state. For example, in the case where the transistor TrL is an NMOS transistor, the voltage V ON 'Specific voltage V OFF Large. Additionally, for example, in the case where transistor TrL is a PMOS transistor, the voltage V... ON 'Specific voltage V OFF 'Small.' Furthermore, an example of an NMOS transistor TrL will be illustrated below.

[0123] Additionally, during the readout operation, one of the multiple word lines WL0 to WL2 is selected. In the illustrated example, word line WL0 is selected. When selecting word lines WL0 to WL2, for example, a voltage V is supplied to the row selection line Rx0a corresponding to the word line WL0 that is the target of the readout operation, one of the multiple row selection lines Rx0a, Rx1a, and Rx2a. ON Supply voltage V to other main word lines Rx1a and Rx2a OFF Additionally, for example, a voltage V can be supplied to multiple row selection lines Rx0b, Rx1b, and Rx2b. OFF .

[0124] Voltage V ON For example, it has the magnitude to which the transistor TrC is turned on. Voltage V OFF For example, it has the magnitude to which transistor TrC is in the off state. For example, in the case where transistor TrC is an NMOS transistor, the voltage V ON Specific voltage V OFF Large. Additionally, for example, when transistor TrC is a PMOS transistor, the voltage V... ON Specific voltage V OFF Small. Furthermore, an example of an NMOS transistor with transistor TrC will be illustrated below.

[0125] Here, a voltage V is supplied via transistor TrL0a to the word line WL0 (hereinafter referred to as "select word line WL0") connected to the memory cell MC (hereinafter referred to as "select memory cell MC") that is the object of the read operation. ON Therefore, the transistor TrC in the selected memory cell MC becomes active. Simultaneously, the voltage of the global bit line GBL changes, or current flows through the global bit line GBL. By detecting this voltage change or current flow, the data stored in the selected memory cell MC can be read.

[0126] Additionally, a voltage V is supplied via transistor TrL0a to word lines WL1 and WL2 (hereinafter referred to as "non-selection word lines WL1, WL2, etc.") other than the select word line WL0 corresponding to the same memory layer ML0 as the select memory cell MC. OFFTherefore, the transistor TrC in the memory cell MC becomes cut off.

[0127] Additionally, voltage V is supplied via transistors TrL1b, TrL2b, and TrL3b to the non-selection word lines WL0, WL1, and WL2 corresponding to memory layers ML1, ML2, and ML3 that are different from the selected memory cell MC. OFF Therefore, the transistor TrC in the memory cell MC becomes cut off.

[0128] Figures 18-22 This is a schematic circuit diagram used to explain the operation of the sense amplifier unit SAU in the readout operation of the semiconductor memory device according to the first embodiment.

[0129] like Figure 18 As shown, in the standby state before performing the read operation, the column select line CSL and the signal supply line W... SAEP W SAEN W EQL The voltages are "L, H, L, H". In this state, transistors Tr11, Tr12, and Tr13 are on, and the global bit line GBL... C GBL T The voltage is equalized to voltage V DD / 2.

[0130] When reading out actions, such as Figure 19 As shown, disable the global bit line GBL. C GBL T Voltage equalization. For example, supplying the signal to line W. EQL The voltage is set to "L". Simultaneously, transistors Tr11, Tr12, and Tr13 are in the off state.

[0131] Additionally, when reading out actions, such as Figure 20 As shown, data is read from the memory cell MC using the global bit line GBL. For example, refer to... Figure 17 As explained, one of the multiple memory layers ML0 to ML3 is selected, and one of the multiple word lines WL0 to WL2 is selected, so that the transistor TrC is turned on in all the corresponding memory cells MC.

[0132] In addition, Figure 20 The diagram shows the two global bit lines GBL selected corresponding to the sense amplifier unit SAU. C GBL T Global Bitline (GBL) T The corresponding subarray MCA S For example. Therefore, in Figure 20 In the example, Global Bitline (GBL) CThe voltage is maintained at voltage V. DD / 2, Global Bitline GBL T Voltage fluctuations. However, it is also possible to choose to use the global bit line GBL. C Corresponding subarray MCA S In this case, the global bit line GBL... C Voltage fluctuations, global bit line GBL T The voltage is maintained at voltage V. DD / 2.

[0133] In addition, Figure 20 The capacitor CpC for selecting the memory cell MC is shown in the figure. DD An example where charging has been performed. In this case, the voltage of the global bit line GBL becomes a voltage V. DD / 2 large. However, the capacitor CpC of the selected memory cell MC can also be discharged to ground voltage V. SS In this case, the voltage of the global bit line GBL becomes the voltage V. DD / 2 small.

[0134] Additionally, when reading out actions, such as Figure 21 As shown, for the global bit line GBL C GBL T The signal is differentially amplified. For example, the signal supply line W is made... SAEP The voltage is "L", and the signal supply line W is made... SAEN The voltage is "H". Simultaneously, transistors Tr23 and Tr33 become ON.

[0135] Here, in Figure 21 In the example, Global Bitline (GBL) T The voltage ratio of voltage V DD / 2 large. Therefore, when transistors Tr23 and Tr33 are in the ON state, transistors Tr22 and Tr31 are in the ON state, and transistors Tr21 and Tr32 are in the OFF state. Accompanying this, the global bit line GBL... T The voltage increases to voltage V DD Additionally, the global bit line GBL... C The voltage decreases to the ground voltage V SS .

[0136] In addition, as referenced Figure 16 As explained, signal supply line W SAEP W SAEN It is set independently of the sensing amplifier unit (SAU). In conjunction with Figure 21 In the corresponding steps, only the signal supply line W corresponding to the selected sense amplifier unit SAU is supplied. SAEPThe voltage is "L". Additionally, only the signal supply line W corresponding to the selected sense amplifier unit SAU is used. SAEN The voltage is "H".

[0137] Additionally, when reading out actions, such as Figure 22 As shown, make the global bit line GBL C GBL T Enables the data input / output signal lines IO and / IO. For example, enables one of the multiple column select lines CSL (in... Figure 22 In this example, the voltage of the column select line (CSL0) is "H". Simultaneously, transistor Tr41 becomes active, and the global bit line GBL... C The data input / output signal lines / IO are turned on. Additionally, transistor Tr42 is turned on, and the global bit line GBL is activated. T And the data input / output signal lines (IO) are turned on.

[0138] [Effect]

[0139] For reference Figure 4 As explained, in the semiconductor memory device according to the first embodiment, multiple row select lines Rx are respectively located in the wiring common region R WC In the multiple subarrays MCA arranged along the X direction S They share a common ground connection. Additionally, these multiple row select lines Rx are each connected to a driver circuit (not shown). Based on this structure, for example with a subarray MCA... S Compared to setting a row selection line Rx, this can significantly reduce the circuit area required for the driver circuit.

[0140] In addition, if according to Figure 4 As explained, in the semiconductor memory device according to the first embodiment, multiple main word lines MWL are respectively located in the wiring common region R. WC In the multiple subarrays MCA arranged along the Y direction S They share a common ground connection. These multiple main word lines (MWL) are respectively connected to the reference... Figure 13 The driver circuit DRV described above MWL Based on such a structure, for example with subarray MCA S And setting up the driver circuit DRV MWL Compared to the previous situation, it can significantly reduce the driver circuit DRV. MWL The required circuit area.

[0141] Additionally, as referenced Figure 5 As explained above, the semiconductor memory device according to this embodiment includes multiple memory layers ML0 to ML3 arranged in the Z direction. Additionally, as referred to... Figure 12 As explained earlier, each of these multiple storage layers ML0 to ML3 has a conductive layer 150. Furthermore, contact electrodes 107 are connected to these conductive layers 150. Here, for example, in each subarray MCA... S When contact electrodes 107 are provided corresponding to all memory layers ML arranged in the Z direction, the larger the number of memory layers ML arranged in the Z direction, the more contact electrodes 107 are required, and the larger the area required to configure the contact electrodes 107 becomes. Accompanying this, sometimes the subarray string MCA... C The area will increase.

[0142] For example, a structure is envisioned where contact electrodes 107 are arranged along the conductive layer 150 in the Y direction, and the spacing of the contact electrodes 107 in the Y direction is the same as the spacing of the conductive layer 120. Additionally, a structure is envisioned, for example, in the subarray MCA... S The case where there are 64 word lines WL (conductive layer 120) arranged along the Y direction.

[0143] For example, if there are 64 memory layers ML arranged along the Z direction, 64 contact electrodes 107 are required. In this case, even if the 64 contact electrodes are arranged in a row along the Y direction, these 64 contact electrodes can be accommodated in each subarray MCA. S Within the range.

[0144] However, for example, if there are 128 memory layers ML arranged along the Z direction, 128 contact electrodes 107 are required. In this case, when the 128 contact electrodes are arranged in a row along the Y direction, it is impossible to accommodate these 128 contact electrodes in each subarray MCA. S Within this range. In this case, consider dividing the 128 contact electrodes into two columns, 64 in each column in the Y direction. In this case, the width of the area in the X direction required to configure the contact electrodes 107 becomes twice that of the case with 64 layers. Thus, the entire subarray MCA S The width in the X direction will increase, and the subarray string MCA C The area will increase.

[0145] Furthermore, for example, if the number of memory layers ML arranged in the Z direction is 256, 256 contact electrodes 107 are required. In this case, for the same reason, the width of the area required to configure the contact electrodes 107 in the X direction becomes four times that in the case of 64 layers. Thus, the entire subarray MCA... S The width in the X direction will increase, and the subarray string MCA C The area will increase.

[0146] Therefore, in the semiconductor memory device according to the first embodiment, the conductive layer 150 is respectively in the wiring common region R WC In the middle, multiple subarrays MCA are arranged across the Y direction. S And it extends in the Y direction. Additionally, in each subarray string MCA C A connection area R is set at the end in the Y direction. HU Contact electrodes 107 are configured here. In such a structure, as the number of storage layers ML arranged in the Z direction increases, the connection region R... HU The area will increase. However, compared with the MCA in each subarray... S Unlike the case where the contact electrodes 107 are set for all storage layers ML arranged in the Z direction, the subarray MCA S The area does not increase. Therefore, the effects of area increase, as described above, can be significantly suppressed. For example, in the subarray string MCA C Includes 128 subarrays MCA S In this case, it is possible to convert the subarray string to MCA C The increase in area was suppressed to a factor of 1 / 128.

[0147] [Second Implementation]

[0148] Next, the semiconductor memory device according to the second embodiment will be described. In the following description, the same reference numerals are used for the same parts as in the first embodiment, and the description is omitted.

[0149] Figure 23 This refers to the memory cell array layer L of the semiconductor memory device according to the second embodiment. MCA The schematic plan view of the structure is shown. The semiconductor memory device according to the second embodiment is configured in basically the same way as that according to the first embodiment. However, the semiconductor memory device according to the second embodiment includes a subarray MCA. S ′ to replace the linked region R HU .

[0150] Figure 24 This indicates the subarray MCA S A schematic XY cross-sectional view of a portion of the structure. Furthermore, in Figure 24 Some structures (insulating layers 121 and 151) are omitted. Figure 25 and Figure 26 This indicates the subarray MCA S A schematic XY cross-sectional view of a portion of the structure. Furthermore... Figure 25 and Figure 26 The XY profiles at different heights are shown. Figure 27 It is along line B-B' Figure 25 and Figure 26 The structure shown is cut off, and a schematic XZ cross-section is observed along the direction of the arrow. Figure 28 It is along line D-D′ Figure 25 and Figure 26 The diagram shows a schematic YZ cross-section of the structure, viewed along the direction of the arrow.

[0151] like Figures 24-28 As shown, subarray MCA S Basically with subarray MCA S It is constructed in the same way.

[0152] However, in the subarray MCA S The main character area R of ′ MWL In the middle, the storage layers ML0 to ML3 have a platform section T with a conductive layer 150.

[0153] Additionally, in the subarray MCA S The main character area R of ′ MWL Multiple contact electrodes 107 are provided, arranged in the Y direction. For example... Figure 27 As shown, the contact electrode 107 extends in the Z direction and is connected at its lower end to the platform portion T of the conductive layer 150. Additionally, as... Figure 28 As shown, multiple contact electrodes 107 arranged in the Y direction are connected to conductive layers 150 disposed at different height positions.

[0154] In addition, Figure 23 In the example, each subarray string MCA C Each has a subarray MCA S However, for example, when the number of storage layers ML arranged along the Z direction is more than a predetermined number, it is also possible to increase the number of subarray strings MCA. C The included subarray MCA S The number of ''. Based on this method, even with an increase in the number of storage layers ML arranged in the Z direction, the subarray MCA can be suppressed. S The width in the X direction is increased, thereby suppressing the MCA of the subarray string. C The area increases.

[0155] For example, Figures 24-26 As shown, a structure is envisioned where the spacing of the contact electrodes 107 in the Y direction is the same as the spacing of the conductive layer 120. Additionally, for example, a structure is envisioned in the subarray MCA... S The case where there are 64 word lines WL (conductive layer 120) arranged along the Y direction.

[0156] For example, if there are 64 memory layers ML arranged along the Z direction, 64 contact electrodes 107 are required. In this case, even if the 64 contact electrodes are arranged in a row along the Y direction, these 64 contact electrodes can be accommodated in a subarray MCA. S Within the range of ′. In this case, each subarray string MCA C Each has a subarray MCA S That's it.

[0157] On the other hand, for example, if there are 128 memory layers ML arranged along the Z direction, 128 contact electrodes 107 are required. In this case, when the 128 contact electrodes are arranged in a row in the Y direction, it is impossible to accommodate these 128 contact electrodes in the subarray MCA. S Within the range of ′. In this case, each subarray string MCA C It can also have two sub-arrays MCA. S Alternatively, it can be done in one of the subarrays MCA. S The contact electrodes 107 are configured to correspond to the storage layers ML of layers 1 to 64, on the other side of the subarray MCA. S Contact electrodes 107 are configured corresponding to the memory layers ML from layers 65 to 128. This allows for suppression of the subarray MCA. S Increasing the width in the X direction can suppress the MCA of the subarray string. C The area increases.

[0158] [Third Implementation]

[0159] Next, the semiconductor memory device according to the third embodiment will be described. In the following description, the same reference numerals are used for the same parts as in the first embodiment, and the description is omitted.

[0160] Figure 29 This refers to the memory cell array layer L of the semiconductor memory device according to the third embodiment. MCA A schematic plan view of the structure. The semiconductor memory device according to the third embodiment is configured in essentially the same way as that according to the first embodiment. However, the semiconductor memory device according to the third embodiment includes a subarray MCA. S "to replace the subarray MCA" S Furthermore, the semiconductor memory device according to the third embodiment does not have a connection region R. HU .

[0161] Figure 30 and Figure 31 This indicates the subarray MCA S A schematic XY cross-sectional view of a portion of the structure. Furthermore, in Figure 30 and Figure 31 Some structures (insulating layers 121 and 151) are omitted. Figure 32 It is along the E-E′ line Figure 30 and Figure 31 The structure shown is cut off, and a schematic XZ cross-section is observed along the direction of the arrow.

[0162] like Figure 30 As shown, subarray MCA S "Basically with subarray MCA" S It is constructed in the same way.

[0163] However, in the subarray MCA S "Main word line area R MWL In the middle, the storage layers ML0 to ML3 have a platform section T with a conductive layer 150.

[0164] Additionally, in the subarray MCA S "Main word line area R MWL Multiple contact electrodes 107 are provided, arranged in the X direction. For example... Figure 32 As shown, the contact electrode 107 extends in the Z direction and is connected at its lower end to the platform portion T of the conductive layer 150. Furthermore, a plurality of contact electrodes 107 arranged in the Y direction are connected to conductive layers 150 disposed at different height positions.

[0165] In addition, such as Figure 31 As shown, in the subarray MCA S "Main word line area R MWL Multiple wirings 160 extending in the Y direction and arranged in the X direction are provided. In the illustrated example, viewed from the Z direction, contact electrodes 107 are respectively positioned overlapping one of the wirings 160. Figure 32 As shown, contact electrode 107 is electrically connected to these wirings.

[0166] In the third embodiment, wiring 160 functions as the main word line (MWL). Therefore, in the third embodiment, conductive layer 150 can span multiple sub-arrays (MCA) arranged in the Y direction. S Extending in the Y direction, it can also be done in only one subarray MCA. S It extends along the Y direction within the range.

[0167] [Other Implementation Methods]

[0168] The semiconductor memory devices according to the first to third embodiments have been described above. However, the semiconductor memory devices according to these embodiments are merely examples, and the specific structure, operation, etc., can be appropriately adjusted.

[0169] For example, in the semiconductor memory devices according to the first to third embodiments, the global bit line GBL is located below the memory layers ML0 to ML3. However, this structure is merely an example, and the specific structure can be appropriately adjusted. For example, the global bit line GBL may also be located above the memory layers ML0 to ML3.

[0170] Furthermore, in the above description, a configuration was used where two adjacent channel regions in a plurality of transistors TrC arranged in the Z direction are adjacent to each other, sandwiching each other. Similarly, a configuration was used where two adjacent channel regions in a plurality of transistors TrL arranged in the Z direction are adjacent to each other, sandwiching each other. However, for example, a configuration could also be used where two adjacent gate electrodes in a plurality of transistors TrC arranged in the Z direction are adjacent to each other, sandwiching each other. Likewise, a configuration could also be used where two adjacent gate electrodes in a plurality of transistors TrL arranged in the Z direction are adjacent to each other, sandwiching each other.

[0171] Furthermore, the above description illustrates an example of using a capacitor CpC as a storage unit connected to the transistor configuration 110. However, the storage unit may not necessarily be a capacitor CpC. For example, the storage unit may also contain ferroelectric, ferromagnetic, chalcogenide materials such as GeSbTe, or other materials, utilizing the properties of these materials to record data. For example, in any of the configurations described above, the insulating layer between the electrodes forming the capacitor CpC may contain any of these materials.

[0172] [other]

[0173] Several embodiments of the present invention have been described above, but these embodiments are merely illustrative and not intended to limit the scope of the invention. These new embodiments can be implemented in a wide variety of other ways, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included within the scope and spirit of the invention, and are included within the scope of the invention as described in the claims and its equivalents.

Claims

1. A semiconductor memory device, Equipped with a storage unit array, The storage cell array has multiple sub-array strings arranged in the first direction. Each of the plurality of subarray strings has a plurality of subarrays arranged in a second direction that intersects the first direction. Each of the multiple sub-arrays has: Multiple storage units are arranged in a third direction that intersects the first direction and the second direction; A plurality of first semiconductor layers are arranged in the third direction and electrically connected to the plurality of memory units; A plurality of first gate electrodes are arranged in the third direction and are respectively facing the plurality of first semiconductor layers; A first wiring extends in the third direction and is electrically connected to the plurality of first semiconductor layers; Multiple second wirings are arranged in the third direction, extend in the first direction, and are connected to the multiple first gate electrodes; A plurality of second semiconductor layers are arranged in the third direction and electrically connected to the first end of the plurality of second wirings in the first direction; A plurality of second gate electrodes are arranged in the third direction and face the plurality of second semiconductor layers; as well as The third wiring, extending in the third direction, is electrically connected to the plurality of second semiconductor layers. Each of the plurality of subarray strings has a plurality of fourth wirings, which extend in the second direction across at least two of the plurality of subarrays arranged in the second direction and are electrically connected to the second gate electrode in at least two of the plurality of subarrays arranged in the second direction.

2. The semiconductor memory device according to claim 1, The plurality of fourth wirings are arranged in the third direction.

3. The semiconductor memory device according to claim 1, The plurality of fourth wirings are arranged in the first direction.

4. The semiconductor memory device according to claim 1, Between at least two of the plurality of subarrays arranged along the first direction, the plurality of third wirings are commonly grounded.

5. The semiconductor memory device according to claim 1, Each of the multiple sub-arrays has: A plurality of third semiconductor layers are arranged in the third direction and electrically connected to the second end of the plurality of second wirings in the first direction; A plurality of third gate electrodes are arranged in the third direction and facing the plurality of third semiconductor layers; and The fifth wiring extends in the third direction and is electrically connected to the plurality of third semiconductor layers. Each of the plurality of subarray strings has a plurality of sixth wirings, which extend in the second direction across at least two of the plurality of subarrays arranged in the second direction and are connected to at least two of the plurality of third gate electrodes.

6. The semiconductor memory device according to claim 5, The plurality of sixth wirings are arranged in the third direction.

7. The semiconductor memory device according to claim 5, The plurality of sixth wirings are arranged in the first direction.

8. The semiconductor memory device according to claim 5, Between at least two of the plurality of subarrays arranged along the first direction, the plurality of fifth wirings are commonly grounded.

9. The semiconductor memory device according to claim 1, comprising: Multiple sensing amplifier units are arranged corresponding to the multiple subarrays; and Multiple signal supply lines are provided, corresponding to the multiple sub-arrays. Each of the plurality of sensing amplifier units has a plurality of amplification circuits that are commonly connected to one of the plurality of signal supply lines. The plurality of amplifier circuits are configured to amplify the signal of the first wiring based on one of the signals from the plurality of signal supply lines.

10. The semiconductor memory device according to claim 1, At least one of the plurality of storage units is a capacitor.

11. The semiconductor memory device according to claim 1, The plurality of first semiconductor layers are respectively facing one side and the other side of the plurality of first gate electrodes in the third direction.

12. The semiconductor memory device according to claim 1, At least one of the plurality of second semiconductor layers faces one side and the other side of one side of the plurality of second gate electrodes in the third direction.

13. The semiconductor memory device according to claim 1, At least one of the plurality of first semiconductor layers and at least one of the plurality of second semiconductor layers each comprise an oxide semiconductor.

14. The semiconductor memory device according to claim 1, At least one of the plurality of first semiconductor layers and at least one of the plurality of second semiconductor layers each contain at least one element selected from gallium (Ga) and aluminum (Al), indium (In), zinc (Zn), and oxygen (O).

15. A semiconductor memory device, Equipped with a storage unit array, The storage cell array has multiple sub-array strings arranged in the first direction. Each of the plurality of subarray strings has a plurality of subarrays arranged in a second direction that intersects the first direction. Each of the multiple sub-arrays has: Multiple storage units are arranged in a third direction that intersects the first direction and the second direction; A plurality of first semiconductor layers are arranged in the third direction and electrically connected to the plurality of memory units; A plurality of first gate electrodes are arranged in the third direction and are respectively facing the plurality of first semiconductor layers; A first wiring extends in the third direction and is electrically connected to the plurality of first semiconductor layers; Multiple second wirings are arranged in the third direction, extend in the first direction, and are connected to the multiple first gate electrodes; A plurality of second semiconductor layers are arranged in the third direction and electrically connected to the first end of the plurality of second wirings in the first direction; A plurality of second gate electrodes are arranged in the third direction and face the plurality of second semiconductor layers; as well as The third wiring, extending in the third direction, is electrically connected to the plurality of second semiconductor layers. Between at least two of the plurality of subarrays arranged along the first direction, the plurality of third wirings are commonly grounded.

16. The semiconductor memory device according to claim 15, Each of the multiple sub-arrays has: A plurality of third semiconductor layers are arranged in the third direction and electrically connected to the second end of the plurality of second wirings in the first direction; A plurality of third gate electrodes are arranged in the third direction and facing the plurality of third semiconductor layers; and The fifth wiring extends in the third direction and is electrically connected to the plurality of third semiconductor layers. Between at least two of the plurality of subarrays arranged along the first direction, the plurality of fifth wirings are commonly grounded.

17. The semiconductor memory device according to claim 15, comprising: Multiple sensing amplifier units are arranged corresponding to the multiple subarrays; and Multiple signal supply lines are provided, corresponding to the multiple sub-arrays. Each of the plurality of sensing amplifier units has a plurality of amplification circuits that are commonly connected to one of the plurality of signal supply lines. The plurality of amplifier circuits are configured to amplify the signal of the first wiring based on one of the signals from the plurality of signal supply lines.

18. The semiconductor memory device according to claim 15, At least one of the plurality of storage units is a capacitor.

19. The semiconductor memory device according to claim 15, The plurality of first semiconductor layers are respectively facing one side and the other side of the plurality of first gate electrodes in the third direction.

20. The semiconductor memory device according to claim 15, At least one of the plurality of second semiconductor layers faces one side and the other side of one side of the plurality of second gate electrodes in the third direction.

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