Analog-to-Digital Conversion Circuit and Method with Fast Tracking Mechanism

Abstract

This application relates to an analog-to-digital conversion circuit and method with a fast tracking mechanism. An analog-to-digital conversion circuit with a fast tracking mechanism. The positive and negative terminal capacitor arrays receive positive and negative terminal input voltages and output positive and negative terminal output voltages. A first comparator compares the positive and negative terminal output voltages according to a reference voltage to generate a first comparison result. A second comparator compares the positive and negative terminal output voltages to generate a second comparison result. When the difference between the positive and negative terminal output voltages is outside a preset range according to the first comparison result, the control circuit does not perform level boosting. The control circuit sets the voltage drop and rise tracking directions of the positive and negative terminal capacitor arrays, and switches the capacitor enable combinations according to a set of digital codes according to the second comparison result in each switching stage, and outputs the corresponding digital code as a digital output signal when the positive and negative terminal output voltages are equal.

Description

Technical Field

[0001] The present invention relates to analog-to-digital conversion technology, and more particularly to an analog-to-digital conversion circuit and method with a fast tracking mechanism. Background Art

[0002] An analog-to-digital conversion circuit is a circuit that converts a continuous analog signal or physical quantity (usually voltage) into a digital signal. The analog-to-digital conversion circuit can be implemented by various different architectures. Among them, the traditional digital slope analog-to-digital conversion circuit linearly samples the input signal and then, regardless of the magnitude relationship of the signal levels, increases the signal level and tracks the input signal by gradually switching the capacitors in the capacitor array. Therefore, such an analog-to-digital conversion circuit has a slow operating speed, resulting in an excessive overall consumption of time. Summary of the Invention

[0003] In view of the problems of the prior art, an object of the present invention is to provide an analog-to-digital conversion circuit and method with a fast tracking mechanism to improve the prior art.

[0004] The present invention includes an analog-to-digital conversion (ADC) circuit with a fast tracking mechanism, including: a positive terminal capacitor array, a negative terminal capacitor array, a first comparator, a second comparator, and a control circuit. The positive terminal capacitor array is configured to receive a positive terminal input voltage and output a positive terminal output voltage. The negative terminal capacitor array is configured to receive a negative terminal input voltage and output a negative terminal output voltage. The first comparator is configured to compare the positive terminal output voltage and the negative terminal output voltage according to a reference voltage to generate a first comparison result. The second comparator is configured to compare the positive terminal output voltage and the negative terminal output voltage to generate a second comparison result. The control circuit is configured to receive the first comparison result and the second comparison result. Wherein, in the initial stage, according to the first comparison result, when the difference between the positive terminal output voltage and the negative terminal output voltage is outside a preset range related to the reference voltage, the control circuit does not increase the levels of the positive terminal output voltage and the negative terminal output voltage; when the positive terminal output voltage is greater than the negative terminal output voltage, the control circuit sets the corresponding voltage drop tracking direction for the positive terminal capacitor array and sets the corresponding voltage rise tracking direction for the negative terminal capacitor array, and when the negative terminal output voltage is greater than the positive terminal output voltage, the control circuit sets the corresponding voltage rise tracking direction for the positive terminal capacitor array and sets the corresponding voltage drop tracking direction for the negative terminal capacitor array, and in each of the multiple switching stages after the initial stage, according to the second comparison result, the control circuit switches the capacitor enable combinations of the positive terminal capacitor array and the negative terminal capacitor array with a set of digital codes, and when the positive terminal output voltage and the negative terminal output voltage are equal, outputs the corresponding digital code as a digital output signal.

[0005] The present invention also includes an analog-to-digital conversion method with a fast tracking mechanism, comprising: enabling a positive terminal capacitor array to receive a positive terminal input voltage and output a positive terminal output voltage; enabling a negative terminal capacitor array to receive a negative terminal input voltage and output a negative terminal output voltage; enabling a first comparator to compare the positive terminal output voltage and the negative terminal output voltage according to a reference voltage to generate a first comparison result; enabling a second comparator to compare the positive terminal output voltage and the negative terminal output voltage to generate a second comparison result; enabling a control circuit to receive the first comparison result and the second comparison result; enabling the control circuit, in an initial stage, according to the first comparison result, when the difference between the positive terminal output voltage and the negative terminal output voltage is outside a preset range related to the reference voltage, not to perform level boosting on the positive terminal output voltage and the negative terminal output voltage; enabling the control circuit, when the positive terminal output voltage is greater than the negative terminal output voltage, to set the corresponding voltage drop tracking direction of the positive terminal capacitor array and set the corresponding voltage rise tracking direction of the negative terminal capacitor array, and when the negative terminal output voltage is greater than the positive terminal output voltage, to set the corresponding voltage rise tracking direction of the positive terminal capacitor array and set the corresponding voltage drop tracking direction of the negative terminal capacitor array; enabling the control circuit, in each of a plurality of switching stages after the initial stage, according to the second comparison result, to switch the capacitance enabling combinations of the positive terminal capacitor array and the negative terminal capacitor array with a set of digital codes; and enabling the control circuit to output the corresponding digital code as a digital output signal when the positive terminal output voltage and the negative terminal output voltage are equal.

[0006] Regarding the features, implementation and effects of this application, the following provides a detailed description of the preferred embodiments in conjunction with the drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1 shows a block diagram of an analog-to-digital conversion circuit with a fast tracking mechanism in an embodiment of the present invention;

[0008] Figure 2 shows a more detailed circuit diagram of the positive terminal capacitor array in an embodiment of the present invention;

[0009] Figure 3 shows a more detailed circuit diagram of the positive terminal capacitor array in another embodiment of the present invention;

[0010] Figure 4A and Figure 4B shows a schematic diagram of the variation of the positive terminal output voltage and the negative terminal output voltage with Figure 1 the operation of the analog-to-digital conversion circuit in an embodiment of the present invention;

[0011] Figure 5A and Figure 5B shows a schematic diagram of the variation of the positive terminal output voltage and the negative terminal output voltage with Figure 1 the operation of the analog-to-digital conversion circuit in another embodiment of the present invention; ​​​​​

[0012] Figure 6A and Figure 6B shows a schematic diagram of the positive output voltage and the negative output voltage varying with the operation of the analog-to-digital conversion circuit in another embodiment of the present invention; and Figure 1 and

[0013] Figure 7 shows a flowchart of an analog-to-digital conversion method with a fast tracking mechanism in an embodiment of the present invention. Detailed Embodiment

[0014] An object of the present invention is to provide an analog-to-digital conversion circuit and method with a fast tracking mechanism, which determines whether to perform level boosting according to the difference between the positive output voltage and the negative output voltage, and can speed up the operation speed by not performing level boosting when the difference is large.

[0015] Please refer to Figure 1 . Figure 1 shows a block diagram of an analog-to-digital conversion circuit 100 with a fast tracking mechanism in an embodiment of the present invention. The analog-to-digital conversion circuit 100 includes: a positive terminal capacitor array 110, a negative terminal capacitor array 120, a first comparator 130, a second comparator 140, and a control circuit 150.

[0016] The positive terminal capacitor array 110 receives a positive terminal input voltage Vip and outputs a positive terminal output voltage Va. More specifically, in an embodiment, the positive terminal capacitor array 110 is connected to an analog signal source through a switch Sip to receive the positive terminal input voltage Vip during the sampling phase, and at the end of the sampling phase, since the switch Sip is disconnected from the analog signal source, the positive terminal output voltage Va is generated by switching the internal capacitor enabling combination.

[0017] The negative terminal capacitor array 120 receives a negative terminal input voltage Vin and outputs a negative terminal output voltage Vb. More specifically, in an embodiment, the negative terminal capacitor array 120 is connected to an analog signal source through a switch Sin to receive the negative terminal input voltage Vin during the sampling phase, and at the end of the sampling phase, since the switch Sin is disconnected from the analog signal source, the negative terminal output voltage Vb is generated by switching the internal capacitor enabling combination.

[0018] The first comparator 130 compares the positive terminal output voltage Va and the negative terminal output voltage Vb according to a reference voltage Vr to generate a first comparison result CR1.

[0019] The second comparator 140 compares the positive terminal output voltage Va and the negative terminal output voltage Vb to generate a second comparison result CR2.

[0020] ​​The control circuit 150 receives the first comparison result CR1 and the second comparison result CR2, and controls the positive terminal capacitor array 110 and the negative terminal capacitor array 120 to switch the capacitor enabling combination accordingly.

[0021] In the initial stage, the control circuit 150 determines whether the difference between the positive terminal output voltage Va and the negative terminal output voltage Vb is within a preset range related to the reference voltage Vr according to the first comparison result CR1 generated by the first comparator 130, so as to decide whether to perform level boosting.

[0022] In an embodiment, the first comparator 130 includes a positive terminal comparator 160 and a negative terminal comparator 170. The positive terminal comparator 160 compares the positive terminal output voltage Vip and the reference voltage Vr to generate the positive terminal comparison result CP included in the first comparison result CR1. The negative terminal comparator 170 compares the negative terminal input voltage Vin and the reference voltage Vr to generate the negative terminal comparison result CN included in the first comparison result CR1.

[0023] The control circuit 150 sets the range between the positive value and the negative value of the reference voltage Vr as the preset range, and determines whether the difference between the positive terminal output voltage Vip and the negative terminal output voltage Vin is within the preset range according to the first comparison result CR1. More specifically, when the above difference is represented by Vi, the condition that the difference is within the preset range can be expressed as -Vr ≤ Vi ≤ Vr. And the condition that the difference is outside the preset range can be expressed as Vi < -Vr or Vi > Vr. In a numerical example, the reference voltage Vr can be, for example but not limited to, 100 millivolts (mV).

[0024] It should be noted that the structure of the above first comparator 130 and the setting method of the preset range are only an example. In other embodiments, the first comparator 130 can achieve the purpose of comparing the difference between the positive terminal output voltage Vip and the negative terminal output voltage Vin through other structures and settings of the preset range.

[0025] Hereinafter, the operation of the analog-to-digital conversion circuit 100 will be described in the case where the difference between the positive terminal output voltage Va and the negative terminal output voltage Vb is outside the preset range.

[0026] When the difference between the positive terminal output voltage Va and the negative terminal output voltage Vb is outside the preset range and has a large value, the control circuit 150 determines whether the positive terminal output voltage Va is much greater than the negative terminal output voltage Vb (Va >> Vb) or the negative terminal output voltage Vb is much greater than the positive terminal output voltage Va (Vb >> Va). Therefore, the control circuit 150 determines that there is already a large gap between the positive terminal output voltage Va and the negative terminal output voltage Vb, and does not perform level boosting.

[0027] When the positive terminal output voltage Va is greater than the negative terminal output voltage Vb, the control circuit 150 sets the positive terminal capacitor array 110 to correspond to the voltage drop tracking direction and sets the negative terminal capacitor array 120 to correspond to the voltage rise tracking direction, and when the negative terminal output voltage Vb is greater than the positive terminal output voltage Va, it sets the positive terminal capacitor array 110 to correspond to the voltage rise tracking direction and sets the negative terminal capacitor array 120 to correspond to the voltage drop tracking direction.

[0028] Further, in each of the multiple switching stages after the initial stage, the control circuit 150 switches the positive terminal capacitor array 110 and the negative terminal capacitor array 120 according to the second comparison result CR2 generated by the second comparator 140 with a set of digital codes DC, so as to output the corresponding set of digital codes as the digital output signal DOUT when the positive terminal output voltage Va and the negative terminal output voltage Vb are equal.

[0029] More specifically, the capacitors in the positive terminal capacitor array 110 and the negative terminal capacitor array 120 are in a disabled state initially. After receiving the positive terminal input voltage Vip and the negative terminal input voltage Vin, the control circuit 150 continuously adjusts the digital code DC according to the first comparison result CR1 to switch the enabled combination of the capacitors in the positive terminal capacitor array 110 and the negative terminal capacitor array 120. In one embodiment, the digital code DC switches the capacitors included in the positive terminal capacitor array 110 and the negative terminal capacitor array 120 in the form of thermometer coding in each switching stage.

[0030] When there is a set of digital codes DC that makes the positive terminal output voltage Va and the negative terminal output voltage Vb equal, this set of digital codes DC is the analog-to-digital conversion result of the positive terminal input voltage Vip and the negative terminal input voltage Vin, and is output as the digital output signal DOUT.

[0031] It should be noted that in practice, the term "equal" can be that the difference between the positive terminal output voltage Va and the negative terminal output voltage Vb is less than a specific range, and this specific range is, for example, but not limited to, the magnitude of the least significant bit (LSB). Therefore, the control circuit 150 can output the corresponding set of digital codes as the digital output signal DOUT when the difference between the positive terminal output voltage Va and the negative terminal output voltage Vb is less than the magnitude of the least significant bit.

[0032] Please refer to Figure 2 。 Figure 2 FIG. shows a more detailed circuit diagram of the positive terminal capacitor array 110 in an embodiment of the present invention. The following will be described in conjunction with Figure 2 , taking the positive terminal capacitor array 110 as an example, to illustrate the operation of the capacitor array corresponding to the voltage drop tracking direction or the voltage rise tracking direction.

[0033] The positive terminal capacitor array 110 includes a plurality of capacitors and a capacitor switching circuit 200.

[0034] In this embodiment, the capacitors included in the positive terminal capacitor array 110 are capacitors C0 to C9. Capacitors C0 to C9 respectively have a first terminal and a second terminal, and the first terminal receives the positive terminal input voltage Vip and outputs the positive terminal output voltage Va.

[0035] The capacitor switching circuit 200 is electrically coupled to the above capacitors, electrically couples the second terminal to the common mode voltage Vcm in the initial stage, and in each switching stage after the initial stage, according to the second comparison result CR2, uses the digital code DC to electrically couple the second terminal of at least one of the capacitors C0 to C9 to the negative reference voltage Vrn to enable in the corresponding voltage drop tracking direction, and electrically couples the second terminal of at least one of the capacitors C0 to C9 to the positive reference voltage Vrp to enable in the corresponding voltage rise tracking direction.

[0036] It should be noted that, except that the first terminal of the negative terminal capacitor array 120 receives the negative terminal input voltage Vin and outputs the negative terminal output voltage Vb, it may have the same structure and operation as the positive terminal capacitor array 110, so it will not be described again.

[0037] Please refer to Figure 3 . Figure 3 FIG. shows a more detailed circuit diagram of the positive terminal capacitor array 110 in another embodiment of the present invention. The following will be combined with Figure 3 , taking the positive terminal capacitor array 110 as an example, to illustrate the structure of the comparison capacitor array and the operation of the fast tracking mechanism. The negative terminal capacitor array 120 may have the same structure and operation as the positive terminal capacitor array 110, and will not be described again.

[0038] The positive terminal capacitor array 110 includes a plurality of capacitor pairs and a capacitor switching circuit 200.

[0039] In this embodiment, the capacitor pairs included in the positive terminal capacitor array 110 are capacitor pairs CP0 to CP9. The capacitor pairs CP'0 to CP9 respectively have a first unit capacitor CC0 and a second unit capacitor CC1 with equal capacitance values. The first unit capacitor CC0 and the second unit capacitor CC1 respectively have a first terminal and a second terminal. The first terminal receives the positive terminal input voltage Vip and outputs the positive terminal output voltage Va.

[0040] The capacitor switching circuit 200 is electrically coupled to the above-mentioned capacitor pairs. In the initial stage, the second ends of the first unit capacitor CC0 and the second unit capacitor CC1 of each capacitor pair are electrically coupled to the common-mode voltage Vcm. And in each switching stage after the initial stage, according to the second comparison result, when corresponding to the voltage drop tracking direction, the second end of the first unit capacitor CC0 of at least one of the capacitor pairs is electrically coupled to the negative reference voltage Vrn to enable, and when corresponding to the voltage rise tracking direction, the second end of the second unit capacitor CC1 of at least one of the capacitor pairs is electrically coupled to the positive reference voltage Vrp to enable.

[0041] It should be noted that, in addition to the first end receiving the negative terminal input voltage Vin and outputting the negative terminal output voltage Vb as described above, the negative terminal capacitor array 120 can have the same structure and operation as the positive terminal capacitor array 110, so it will not be described separately.

[0042] Moreover, the number of the above-mentioned capacitors and capacitor pairs is only an example. In other embodiments, the number of capacitors and capacitor pairs can be any value of two or more.

[0043] Please refer to Figure 4A and Figure 4B . Figure 4A and Figure 4B respectively show schematic diagrams of the positive terminal output voltage Va and the negative terminal output voltage Vb changing with the operation of the analog-to-digital conversion circuit 100 in an embodiment of the present invention. In Figure 1 and Figure 4A and Figure 4B , the positive terminal output voltage Va is shown by a solid line segment, and the negative terminal output voltage Vb is shown by a dotted line.

[0044] As Figure 4A and Figure 4B shown, the time interval T1 corresponds to the sampling completion stage. Figure 1 The positive terminal capacitor array 110 and the negative terminal capacitor array 120 of

[0045] The time interval T2 corresponds to the initial stage. At this time, the control circuit 150 determines, based on the first comparison result CR1 generated by the first comparator 130, that the difference between the positive terminal output voltage Va and the negative terminal output voltage Vb is outside the preset range related to the reference voltage Vr, so as to decide not to perform level boosting. Among them, Figure 4A and Figure 4B the positive value +Vr and the negative value -Vr of the reference voltage Vr are also shown.

[0046] The time interval T3 corresponds to multiple switching stages after the initial stage. During Figure 4A this period, since the positive terminal output voltage Va is greater than the negative terminal output voltage Vb, the control circuit 150 sets the positive terminal capacitor array 110 to correspond to the voltage drop tracking direction and sets the negative terminal capacitor array 120 to correspond to the voltage rise tracking direction. In contrast, during Figure 4B this period, since the negative terminal output voltage Vb is greater than the positive terminal output voltage Va, the control circuit 150 sets the positive terminal capacitor array 110 to correspond to the voltage rise tracking direction and sets the negative terminal capacitor array 120 to correspond to the voltage drop tracking direction.

[0047] Furthermore, the control circuit 150 switches the positive terminal capacitor array 110 and the negative terminal capacitor array 120 with a set of digital codes DC according to the second comparison result CR2 generated by the second comparator 140 in each switching stage.

[0048] In the time interval T4, the difference between the positive terminal output voltage Va and the negative terminal output voltage Vb will be equal, causing Figure 1 the control circuit 150 to generate a digital output signal DOUT.

[0049] The operation of the analog-to-digital conversion circuit 100 will be described below for the case where the difference between the positive terminal output voltage Va and the negative terminal output voltage Vb is within the preset range.

[0050] When the difference between the positive terminal output voltage Va and the negative terminal output voltage Vb is within the preset range and has a small value, the control circuit 150 determines whether the positive terminal output voltage Va is slightly greater than the negative terminal output voltage Vb (Va > Vb) or the negative terminal output voltage Vb is slightly greater than the positive terminal output voltage Va (Vb > Va). Therefore, the control circuit 150 determines that there is a small gap between the positive terminal output voltage Va and the negative terminal output voltage Vb, and level boosting is required. Among them, level boosting can be achieved, for example, but not limited to, by changing the common-mode voltage provided to the positive terminal capacitor array 110 and the negative terminal capacitor array 110 as described above.

[0051] In one embodiment, the control circuit 150 performs positive level boosting on the larger one of the positive terminal output voltage Va and the negative terminal output voltage Vb and negative level boosting on the smaller one.

[0052] Moreover, as in the aforementioned operation where the difference between the positive terminal output voltage Vip and the negative terminal output voltage Vin is outside the preset range, when the positive terminal output voltage Va is greater than the negative terminal output voltage Vb, the control circuit 150 sets the positive terminal capacitor array 110 corresponding to the voltage drop tracking direction and sets the negative terminal capacitor array 120 corresponding to the voltage rise tracking direction. When the negative terminal output voltage Vb is greater than the positive terminal output voltage Va, the control circuit 150 sets the positive terminal capacitor array 110 corresponding to the voltage rise tracking direction and sets the negative terminal capacitor array 120 corresponding to the voltage drop tracking direction. And in each of the multiple switching stages after the initial stage, according to the second comparison result CR2, the control circuit 150 switches the capacitance enabling combinations of the positive terminal capacitor array 110 and the negative terminal capacitor array 120 with the digital code DC.

[0053] Please refer to Figure 5A and Figure 5B . Figure 5A and Figure 5B respectively show schematic diagrams of the changes in the positive terminal output voltage Va and the negative terminal output voltage Vb with the operation of the analog-to-digital conversion circuit 100 of the present invention in another embodiment. In Figure 1 , the positive terminal output voltage Va is shown as a solid line segment, and the negative terminal output voltage Vb is shown as a dotted line. Figure 5A and Figure 5B , the positive terminal output voltage Va is shown as a solid line segment, and the negative terminal output voltage Vb is shown as a dotted line.

[0054] As Figure 5A and Figure 5B shown, the time interval T1 corresponds to the sampling completion stage. The time interval T2 corresponds to the initial stage. The control circuit 150 determines, according to the first comparison result CR1 generated by the first comparator 130, that the difference between the positive terminal output voltage Va and the negative terminal output voltage Vb is within the preset range related to the reference voltage Vr, so as to decide to perform level boosting, and perform positive level boosting on the larger one of the positive terminal output voltage Va and the negative terminal output voltage Vb and negative level boosting on the smaller one.

[0055] The time interval T3 corresponds to multiple switching stages after the initial stage. In Figure 5A , since the positive terminal output voltage Va is greater than the negative terminal output voltage Vb, the control circuit 150 sets the positive terminal capacitor array 110 corresponding to the voltage drop tracking direction and sets the negative terminal capacitor array 120 corresponding to the voltage rise tracking direction. Conversely, in Figure 5B , since the negative terminal output voltage Vb is greater than the positive terminal output voltage Va, the control circuit 150 sets the positive terminal capacitor array 110 corresponding to the voltage rise tracking direction and sets the negative terminal capacitor array 120 corresponding to the voltage drop tracking direction.

[0056] Further, in each switching stage, the control circuit 150 switches the positive terminal capacitor array 110 and the negative terminal capacitor array 120 with a set of digital codes DC according to the second comparison result CR2 generated by the second comparator 140.

[0057] In the time interval T4, the difference between the positive terminal output voltage Va and the negative terminal output voltage Vb will be equal, causing Figure 1 the control circuit 150 to generate a digital output signal DOUT.

[0058] In another embodiment, the control circuit 150 performs a positive level boost on the positive terminal output voltage Va and a negative level boost on the negative terminal output voltage Vb, so that the positive terminal output voltage Va is greater than the negative terminal output voltage Vb.

[0059] Moreover, the control circuit 150 sets the positive terminal capacitor array 110 to correspond to the voltage drop tracking direction and sets the negative terminal capacitor array 120 to correspond to the voltage rise tracking direction, and in each of the multiple switching stages after the initial stage, switches the capacitance enable combinations of the positive terminal capacitor array 110 and the negative terminal capacitor array 120 with digital codes DC according to the second comparison result CR2.

[0060] Please refer to Figure 6A and Figure 6B . Figure 6A and Figure 6B respectively show, in another embodiment of the present invention, schematic diagrams of the variation of the positive terminal output voltage Va and the negative terminal output voltage Vb with Figure 1 the operation of the analog-to-digital conversion circuit 100. In Figure 6A and Figure 6B , the positive terminal output voltage Va is shown as a solid line segment, and the negative terminal output voltage Vb is shown as a dotted line.

[0061] As Figure 6A and Figure 6B shown, the time interval T1 corresponds to the sampling completion stage. The time interval T2 corresponds to the initial stage. The control circuit 150 determines, according to the first comparison result CR1 generated by the first comparator 130, that the difference between the positive terminal output voltage Va and the negative terminal output voltage Vb is within a preset range related to the reference voltage Vr, decides to perform a level boost, performs a positive level boost on the positive terminal output voltage Va, and performs a negative level boost on the negative terminal output voltage Vb, so that the positive terminal output voltage Va is greater than the negative terminal output voltage Vb.

[0062] The time interval T3 corresponds to multiple switching stages after the initial stage. In Figure 6A and Figure 6B , the control circuit 150 sets the positive terminal capacitor array 110 to correspond to the voltage drop tracking direction and sets the negative terminal capacitor array 120 to correspond to the voltage rise tracking direction.

[0063] Further, in each switching stage, the control circuit 150 switches the positive terminal capacitor array 110 and the negative terminal capacitor array 120 with a set of digital codes DC according to the second comparison result CR2 generated by the second comparator 140.

[0064] In the time interval T4, the difference between the positive terminal output voltage Va and the negative terminal output voltage Vb will be equal, causing Figure 1 the control circuit 150 to generate a digital output signal DOUT.

[0065] Therefore, the analog-to-digital conversion circuit of the present invention can determine whether to perform level boosting according to the difference between the positive terminal output voltage and the negative terminal output voltage. When the difference is large, the operation speed can be increased because level boosting is not performed.

[0066] Please refer to Figure 7 . Figure 7 FIG. shows a flowchart of an analog-to-digital conversion method 700 with a fast tracking mechanism according to an embodiment of the present invention.

[0067] In addition to the aforementioned device, the present invention further discloses an analog-to-digital conversion method 700 with a fast tracking mechanism, which is applied to, for example, but not limited to Figure 1 the analog-to-digital conversion circuit 100. One embodiment of the analog-to-digital conversion method 700 is as shown in Figure 5A and Figure 5B and includes the following steps:

[0068] In step S710, the positive terminal capacitor array 110 receives the positive terminal input voltage Vip and outputs the positive terminal output voltage Va.

[0069] In step S720, the negative terminal capacitor array 120 receives the negative terminal input voltage Vip and outputs the negative terminal output voltage Vb.

[0070] In step S730, the first comparator 130 compares the positive terminal output voltage Va and the negative terminal output voltage Vb to generate a first comparison result CR1.

[0071] In step S740, the second comparator 140 compares the positive terminal output voltage Va and the negative terminal output voltage Vb to generate a second comparison result CR2.

[0072] In step S750, it is determined whether it is the initial stage.

[0073] In step S755, when it is in the initial stage, the control circuit 150 determines whether the difference between the positive terminal output voltage Va and the negative terminal output voltage Vb is within a preset range related to the reference voltage according to the first comparison result CR1.

[0074] In step S760, when the difference between the positive terminal output voltage Va and the negative terminal output voltage Vb is outside the preset range, the control circuit 150 does not perform level boosting on the positive terminal output voltage Va and the negative terminal output voltage Vb.

[0075] In step S770, when the difference between the positive terminal output voltage Va and the negative terminal output voltage Vb is within the preset range, the control circuit 150 performs level boosting on the positive terminal output voltage Va and the negative terminal output voltage Vb.

[0076] In step S780, the control circuit 150 sets the voltage tracking directions of the positive terminal capacitor array 110 and the negative terminal capacitor array 120.

[0077] More specifically, when the positive terminal output voltage Va is greater than the negative terminal output voltage Vb, the control circuit 150 sets the positive terminal capacitor array 110 to correspond to the voltage drop tracking direction and sets the negative terminal capacitor array 120 to correspond to the voltage rise tracking direction, and when the negative terminal output voltage Vb is greater than the positive terminal output voltage Va, the control circuit 150 sets the positive terminal capacitor array 110 to correspond to the voltage rise tracking direction and sets the negative terminal capacitor array 120 to correspond to the voltage drop tracking direction.

[0078] In step S785, when it is not in the initial stage, the control circuit 150 determines whether the positive terminal output voltage Va and the negative terminal output voltage Vb are equal according to the second comparison result CR.

[0079] In step S790, when the positive terminal output voltage Va and the negative terminal output voltage Vb are not equal, the control circuit 150 switches the capacitor enabling combinations of the positive terminal capacitor array 110 and the negative terminal capacitor array 120 with a set of digital codes DC according to the second comparison result CR2 in each of the multiple switching stages. The process will return to step S730 to continue the comparison.

[0080] In step S795, when the positive terminal output voltage Va and the negative terminal output voltage Vb are equal, the control circuit 150 outputs the corresponding set of digital codes DC as the digital output signal DOUT when the positive terminal output voltage Va and the negative terminal output voltage Vb are equal.

[0081] It should be noted that the above embodiments are only examples. In other embodiments, those with ordinary knowledge in the art can make changes without departing from the spirit of the present invention.

[0082] In summary, the analog-to-digital conversion circuit and method with a fast tracking mechanism in the present invention determine whether to perform level boosting according to the magnitude of the difference between the positive terminal output voltage and the negative terminal output voltage, and can accelerate the operation speed by not performing level boosting when the difference is large.

[0083] Although the embodiments of the present application are as described above, these embodiments are not intended to limit the present application. Those of ordinary skill in the art can make changes to the technical features of the present application based on the explicit or implicit content of the present application. All such changes may fall within the scope of patent protection sought by the present application. In other words, the scope of patent protection of the present application shall be determined by the scope of the patent application defined in this specification.

[0084]

Symbol Explanation

[0085] 100: Analog-to-digital conversion circuit

[0086] 110: Positive terminal capacitor array

[0087] 120: Negative terminal capacitor array

[0088] 130: First comparator

[0089] 140: Second comparator

[0090] 150: Control circuit

[0091] 160: Positive terminal comparator

[0092] 170: Negative terminal comparator

[0093] 200: Capacitor switching circuit

[0094] 700: Analog-to-digital conversion method

[0095] S710~S795: Steps

[0096] C0~C9: Capacitors

[0097] CC0: First unit capacitor

[0098] CC1: Second unit capacitor

[0099] CN: Negative terminal comparison result

[0100] CP: Positive terminal comparison result

[0101] CP0~CP9: Capacitor pairs

[0102] CR1: First comparison result

[0103] CR2: Second comparison result

[0104] DC: Digital code

[0105] DOUT: Digital output signal

[0106] Sin, Sip: Switches

[0107] T1~T4: Time intervals

[0108] Va: Positive terminal output voltage

[0109] Vb: Negative terminal output voltage

[0110] Vcm: Common-mode voltage

[0111] Vin: Negative terminal input voltage

[0112] Vip: Positive terminal input voltage

[0113] Vr: Reference voltage

[0114] Vrn: Negative reference voltage

[0115] Vrp: Positive reference voltage.

Claims

1. An analog-to-digital conversion circuit with a fast tracking mechanism, comprising: A positive terminal capacitor array configured to receive a positive terminal input voltage and output a positive terminal output voltage; A negative terminal capacitor array configured to receive a negative terminal input voltage and output a negative terminal output voltage; A first comparator configured to compare the positive terminal output voltage and the negative terminal output voltage according to a reference voltage to generate a first comparison result; A second comparator configured to compare the positive terminal output voltage and the negative terminal output voltage to generate a second comparison result; And A control circuit configured to receive the first comparison result and the second comparison result; Wherein the control circuit, in an initial stage, according to the first comparison result, when a difference between the positive terminal output voltage and the negative terminal output voltage is outside a preset range related to the reference voltage, does not perform level boosting on the positive terminal output voltage and the negative terminal output voltage; The control circuit sets the positive terminal capacitor array corresponding to a voltage drop tracking direction and sets the negative terminal capacitor array corresponding to a voltage rise tracking direction when the positive terminal output voltage is greater than the negative terminal output voltage, and sets the positive terminal capacitor array corresponding to the voltage rise tracking direction and sets the negative terminal capacitor array corresponding to the voltage drop tracking direction when the negative terminal output voltage is greater than the positive terminal output voltage, and in each of a plurality of switching stages after the initial stage, according to the second comparison result, switches a capacitor enabling combination of the positive terminal capacitor array and the negative terminal capacitor array with a set of digital codes, and outputs the corresponding set of digital codes as a digital output signal when the positive terminal output voltage and the negative terminal output voltage are equal.

2. The analog-to-digital conversion circuit according to claim 1, wherein the first comparator comprises: A positive terminal comparator configured to compare the positive terminal output voltage and the reference voltage to generate a positive terminal comparison result included in the first comparison result; And A negative terminal comparator configured to compare the negative terminal output voltage and the reference voltage to generate a negative terminal comparison result included in the first comparison result; Wherein the control circuit is configured to set a range between a positive value and a negative value of the reference voltage as the preset range, and judge whether the difference between the positive terminal output voltage and the negative terminal output voltage is within the preset range according to the first comparison result.

3. The analog-to-digital conversion circuit according to claim 1, wherein each of the positive terminal capacitor array and the negative terminal capacitor array comprises: A plurality of capacitors, each having a first terminal and a second terminal, the first terminal being configured to receive the positive terminal input voltage or the negative terminal input voltage and output the positive terminal output voltage or the negative terminal output voltage; And a capacitor switching circuit, electrically coupled to the plurality of capacitors, configured to electrically couple the second terminal to a common-mode voltage during the initial stage, and during each of the plurality of switching stages after the initial stage, according to the second comparison result, use the set of digital codes to electrically couple the second terminal of at least one of the plurality of capacitors to a negative reference voltage for enabling when corresponding to the voltage drop tracking direction, and electrically couple the second terminal of at least one of the plurality of capacitors to a positive reference voltage for enabling when corresponding to the voltage rise tracking direction.

4. The analog-to-digital conversion circuit according to claim 1, wherein each of the positive terminal capacitor array and the negative terminal capacitor array includes: A plurality of capacitor pairs, each having a first unit capacitor and a second unit capacitor with equal capacitance values, the first unit capacitor and the second unit capacitor each having a first terminal and a second terminal, the first terminal being configured to receive the positive terminal input voltage or the negative terminal input voltage and output the positive terminal output voltage or the negative terminal output voltage; A capacitor switching circuit, electrically coupled to the plurality of capacitor pairs, configured to electrically couple the second terminals of the first unit capacitor and the second unit capacitor of each of the plurality of capacitor pairs to a common-mode voltage during the initial stage, and during each of the plurality of switching stages after the initial stage, according to the second comparison result, use the set of digital codes to electrically couple the second terminal of at least one of the first unit capacitors of the plurality of capacitor pairs to a negative reference voltage for enabling when corresponding to the voltage drop tracking direction, and electrically couple the second terminal of at least one of the second unit capacitors of the plurality of capacitor pairs to a positive reference voltage for enabling when corresponding to the voltage rise tracking direction.

5. The analog-to-digital conversion circuit according to claim 1, wherein during the initial stage, according to the first comparison result, when the difference between the positive terminal output voltage and the negative terminal output voltage is within the preset range related to the reference voltage, the control circuit performs positive level boosting on the larger one of the positive terminal output voltage and the negative terminal output voltage and negative level boosting on the smaller one; When the positive terminal output voltage is greater than the negative terminal output voltage, the control circuit sets the positive terminal capacitor array to correspond to the voltage drop tracking direction and sets the negative terminal capacitor array to correspond to the voltage rise tracking direction, and when the negative terminal output voltage is greater than the positive terminal output voltage, the control circuit sets the positive terminal capacitor array to correspond to the voltage rise tracking direction and sets the negative terminal capacitor array to correspond to the voltage drop tracking direction, and during each of the plurality of switching stages after the initial stage, according to the second comparison result, uses a set of digital codes to switch a capacitor enabling combination of the positive terminal capacitor array and the negative terminal capacitor array.

6. The analog-to-digital conversion circuit according to claim 1, wherein the control circuit, in the initial stage and based on the first comparison result, when the difference between the positive-terminal output voltage and the negative-terminal output voltage is within the preset range related to the reference voltage, performs a positive level boost on the positive-terminal output voltage and a negative level boost on the negative-terminal output voltage, so that the positive-terminal output voltage is greater than the negative-terminal output voltage; The control circuit sets the positive-terminal capacitor array to correspond to the voltage drop tracking direction and sets the negative-terminal capacitor array to correspond to the voltage rise tracking direction, and in each of a plurality of switching stages after the initial stage, switches a capacitor enabling combination of the positive-terminal capacitor array and the negative-terminal capacitor array according to the second comparison result with a set of digital codes.

7. An analog-to-digital conversion method with a fast tracking mechanism, comprising: causing a positive-terminal capacitor array to receive a positive-terminal input voltage and output a positive-terminal output voltage; causing a negative-terminal capacitor array to receive a negative-terminal input voltage and output a negative-terminal output voltage; causing a first comparator to compare the positive-terminal output voltage and the negative-terminal output voltage according to a reference voltage to generate a first comparison result; causing a second comparator to compare the positive-terminal output voltage and the negative-terminal output voltage to generate a second comparison result; causing a control circuit to receive the first comparison result and the second comparison result; causing the control circuit, in an initial stage and based on the first comparison result, when a difference between the positive-terminal output voltage and the negative-terminal output voltage is outside a preset range related to the reference voltage, not to perform a level boost on the positive-terminal output voltage and the negative-terminal output voltage; causing the control circuit to set the positive-terminal capacitor array to correspond to a voltage drop tracking direction and set the negative-terminal capacitor array to correspond to a voltage rise tracking direction when the positive-terminal output voltage is greater than the negative-terminal output voltage, and set the positive-terminal capacitor array to correspond to the voltage rise tracking direction and set the negative-terminal capacitor array to correspond to the voltage drop tracking direction when the negative-terminal output voltage is greater than the positive-terminal output voltage; causing the control circuit to switch a capacitor enabling combination of the positive-terminal capacitor array and the negative-terminal capacitor array according to the second comparison result with a set of digital codes in each of a plurality of switching stages after the initial stage; and causing the control circuit to output the corresponding set of digital codes as a digital output signal when the positive-terminal output voltage and the negative-terminal output voltage are equal.

8. The analog-to-digital conversion method according to claim 7, further comprising: causing a positive-terminal comparator included in the first comparator to compare the positive-terminal output voltage and the reference voltage to generate a positive-terminal comparison result included in the first comparison result; and causing a negative-terminal comparator included in the first comparator to compare the negative-terminal output voltage and the reference voltage to generate a negative-terminal comparison result included in the first comparison result; causing the control circuit to set a range between a positive value and a negative value of the reference voltage as the preset range, and judge whether the difference between the positive-terminal output voltage and the negative-terminal output voltage is within the preset range according to the first comparison result.

9. The analog-to-digital conversion method according to claim 7, wherein each of the positive terminal capacitor array and the negative terminal capacitor array includes a plurality of capacitors and a capacitor switching circuit, wherein the plurality of capacitors respectively have a first terminal and a second terminal, the capacitor switching circuit is electrically coupled to the plurality of capacitors, and the analog-to-digital conversion method includes: Causing the first terminals of the plurality of capacitors to receive the positive terminal input voltage or the negative terminal input voltage and output the positive terminal output voltage or the negative terminal output voltage; Causing the capacitor switching circuit to electrically couple the second terminals to a common mode voltage in the initial stage; And Causing the capacitor switching circuit to electrically couple at least one of the second terminals of the plurality of capacitors to a negative reference voltage for enabling according to the second comparison result in each of the plurality of switching stages after the initial stage in accordance with the set of digital codes when corresponding to the voltage decreasing tracking direction, and electrically couple at least one of the second terminals of the plurality of capacitors to a positive reference voltage for enabling when corresponding to the voltage increasing tracking direction.

10. The analog-to-digital conversion method according to claim 7, wherein each of the positive terminal capacitor array and the negative terminal capacitor array includes a plurality of capacitor pairs and a capacitor switching circuit, the plurality of capacitor pairs respectively have a first unit capacitor and a second unit capacitor with equal capacitance values, the first unit capacitor and the second unit capacitor respectively have a first terminal and a second terminal, the capacitor switching circuit is electrically coupled to the plurality of capacitor pairs, and the analog-to-digital conversion method includes: Causing the first terminals of the first unit capacitor and the second unit capacitor of the plurality of capacitor pairs to receive the positive terminal input voltage or the negative terminal input voltage and output the positive terminal output voltage or the negative terminal output voltage; Causing the capacitor switching circuit to electrically couple the second terminals of the first unit capacitor and the second unit capacitor of each of the plurality of capacitor pairs to a common mode voltage in the initial stage; And Causing the capacitor switching circuit to electrically couple at least one of the second terminals of the first unit capacitor of the plurality of capacitor pairs to a negative reference voltage for enabling according to the second comparison result in each of the plurality of switching stages after the initial stage in accordance with the set of digital codes when corresponding to the voltage decreasing tracking direction, and electrically couple at least one of the second terminals of the second unit capacitor of the plurality of capacitor pairs to a positive reference voltage for enabling when corresponding to the voltage increasing tracking direction.

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