Position detection magnetic sensor chip

Abstract

The application discloses a position detection magnetic sensing chip, which is used for improving the accuracy of data collection of an integrated magnetic switch chip. The application comprises the position detection magnetic sensing chip, which comprises a ground pin GND, an enable receiving pin TRI, an enable sending pin TRO and an output pin OUT; a power supply module is connected with a Wheatstone bridge, a low-offset amplifier, a first Schmitt trigger and a time adjustment module; a first transistor is connected with the Wheatstone bridge, the low-offset amplifier, an enable logic module EN Logic and the ground pin GND; the low-offset amplifier is connected with the first Schmitt trigger, the Wheatstone bridge, the enable logic module and the time adjustment module; a second transistor is connected with the time adjustment module, the output pin OUT, the first Schmitt trigger and the output pin OUT; and the enable logic module is connected with the enable receiving pin TRI, the enable sending pin TRO and the time adjustment module.

Description

TECHNICAL FIELD

[0001] Embodiments of the present application relate to the field of magnetic switches, and in particular to a position detection magnetic sensing chip. BACKGROUND

[0002] A magnetic switch is a component that controls switching through a magnetic signal. The magnetic signal possessed by the magnetic switch has strong penetrating power, and can easily penetrate and achieve complete signal transmission for common obstacles such as plastic, metal, wood, rock, and other non-magnetic materials, and is not affected by dust, oil stains, smoke, and background light in the environment during signal transmission. The above characteristics make the magnetic switch widely used in various non-contact control systems with its unique advantages, and specific applications involve multiple fields such as military defense, medical electronics, industrial control, consumer electronics, etc. At present, magnetic switches can be divided into two categories: the first category is a non-integrated magnetic switch represented by a reed switch and an electromagnetic induction coil, and the second category is an integrated magnetic switch developed by combining a magnetic sensitive element represented by a Hall effect device and a magnetoresistance effect device with a microelectronic process. The traditional non-integrated magnetic switch is gradually replaced by the integrated magnetic switch due to its disadvantages such as large size, short service life, and low sensitivity.

[0003] Nowadays, it is generally required in industry to measure various non-electric physical quantities such as temperature, pressure, and liquid level height, which all need to be converted into analog electric signals by a transmitter before being transmitted to a control room or display device hundreds of meters away. The most widely used in industrial detection is a 4-20mA current transmitter, and the reason for using a current signal is that it is not easily disturbed. Moreover, the internal resistance of the current source is infinite, and the wire resistance is connected in series in the loop without affecting the accuracy, and can be transmitted for hundreds of meters on ordinary twisted pair lines. In industrial applications, the distance between the measuring device and the control room or display device can be tens to hundreds of meters, and two-wire 4-20mA current transmitters are generally used for cost considerations. The upper limit is 20mA because of the requirement for explosion protection: the spark energy caused by the on-off of 20mA current is not enough to ignite gas; the reason for not taking 0mA as the lower limit is to be able to detect a broken wire. The measured device and the signal conditioning circuit power consumption must be less than 4mA, otherwise the transmitter cannot output a 4mA zero potential.

[0004] There are some non-contact liquid level detection schemes for detecting the liquid level height in an industrial water storage device, such as radar liquid level detection, infrared liquid level detection, and ultrasonic liquid level detection, but the above schemes have problems such as high cost, slow response speed, low sensitivity, and the need for regular maintenance and short service life.

[0005] The traditional low-power magnetic switch liquid level detection scheme uses a dry reed tube. An industrial water storage device has a magnetic float inside. The dry reed tubes are arranged in a cascade along the wall surface of the device at equal intervals. The dry reed tube detects the external magnetic field and realizes the open circuit through mechanical movement, which is an ideal switching device in the electrical field. Its structure is simple, the manufacturing process is simple, and the power consumption is low. It is widely used in liquid level detection, but it also has low precision and sensitivity, poor reliability, and cannot meet the real-time high-precision detection of the liquid level.

[0006] To improve the shortcomings of the dry reed tube liquid level detection scheme, the industry proposes to use a traditional integrated magnetic switch chip to replace the dry reed tube. The integrated magnetic switch chip periodically detects the external magnetic field according to the wake-up-sleep cycle. The internal timer sets each chip to be in the wake-up state only once. Low-power high-precision liquid level detection can be achieved. However, in the application process, it is found that the clock frequency of the internal timer of the traditional integrated magnetic switch chip has randomness, and there is a probability that multiple chips are in the wake-up state at the same time, that is, the co-frequency phenomenon. Since there is no communication function between the cascade chips, the co-frequency phenomenon cannot be eliminated. The co-frequency phenomenon may cause large GND fluctuations, port sampling voltage V ADC is disturbed, resulting in false reporting of liquid level height and reducing the accuracy of data collection of the integrated magnetic switch chip. SUMMARY

[0007] The application discloses a position detection magnetic sensing chip for improving the accuracy of data collection of the integrated magnetic switch chip.

[0008] The first aspect of the application provides a position detection magnetic sensing chip, comprising:

[0009] a Wheatstone bridge, a low-offset amplifier, a first Schmitt trigger, a power supply module, a time adjustment module, an enable logic module EN Logic, a first transistor NMOS, and a second transistor NMOS;

[0010] The position detection magnetic sensing chip includes a ground pin GND, an enable receiving pin TRI, an enable sending pin TRO, and an output pin OUT.

[0011] The power supply module is connected with the Wheatstone bridge, the low-offset amplifier, the first Schmitt trigger, and the time adjustment module, respectively.

[0012] The first transistor NMOS is connected with the Wheatstone bridge, the low-offset amplifier, the enable logic module EN Logic, and the ground pin GND, respectively.

[0013] The low-offset amplifier is connected with the first Schmitt trigger, the Wheatstone bridge, the enable logic module EN Logic, and the time adjustment module, respectively.

[0014] The second transistor NMOS is connected with the time adjustment module, the output pin OUT, the first Schmitt trigger and the output pin OUT respectively.

[0015] The enable logic module EN Logic is connected with the enable receiving pin TRI, the enable sending pin TRO and the time adjustment module respectively.

[0016] Optionally, the time adjustment module comprises a clock module OSC and a trimming module Trim TOP.

[0017] The clock module OSC is connected with the power supply module, the Wheatstone bridge, the low-offset amplifier and the trimming module Trim TOP respectively.

[0018] The trimming module Trim TOP is connected with the output pin OUT, the second transistor NMOS and the enable receiving pin TRI respectively.

[0019] Optionally, the trimming module Trim TOP comprises a low-offset comparator, a Trim Logic&T_sensor module, a counter count and a clock start monitoring module.

[0020] The low-offset comparator is connected with the Trim Logic&T_sensor module and the counter count respectively.

[0021] The clock module OSC is connected with the Trim Logic&T_sensor module, the clock start monitoring module and the counter count respectively.

[0022] The enable receiving pin TRI is connected with the Trim Logic&T_sensor module and the counter count respectively.

[0023] The clock start monitoring module is connected with the counter count and the output pin OUT respectively.

[0024] Optionally, the clock start monitoring module comprises a TRIM EN module and a second Schmitt trigger.

[0025] The TRIM EN module is connected with the counter count, the clock module OSC and the second Schmitt trigger respectively.

[0026] The second Schmitt trigger is connected with the output pin OUT.

[0027] Optionally, the power supply module comprises a power supply voltage pin VCC and a reference voltage module VREG.

[0028] The power supply voltage pin VCC is connected with the reference voltage module VREG.

[0029] The reference voltage module VREG is connected with the Wheatstone bridge, the low-offset amplifier, the time adjustment module and the first Schmitt trigger, respectively.

[0030] Optionally, the Wheatstone bridge is composed of the magnetic sensitive element R1, the magnetic sensitive element R2, the magnetic sensitive element R3 and the magnetic sensitive element R4.

[0031] The magnetic sensitive element R1, the magnetic sensitive element R2, the magnetic sensitive element R3 and the magnetic sensitive element R4 are sequentially connected to form the bridge.

[0032] Optionally, the interfaces of the magnetic sensitive element R1 and the magnetic sensitive element R2 are connected with the low-offset amplifier.

[0033] The interfaces of the magnetic sensitive element R3 and the magnetic sensitive element R4 are connected with the low-offset amplifier.

[0034] The interfaces of the magnetic sensitive element R2 and the magnetic sensitive element R3 are connected with the first transistor NMOS.

[0035] The interfaces of the magnetic sensitive element R1 and the magnetic sensitive element R4 are respectively connected with the power supply module, the low-offset amplifier and the time adjustment module.

[0036] Optionally, the magnetic sensitive element R1, the magnetic sensitive element R2, the magnetic sensitive element R3 and the magnetic sensitive element R4 are Hall magnetoresistance, AMR magnetoresistance, GMR magnetoresistance or TMR magnetoresistance.

[0037] The first aspect of the application provides a cascaded chip of a position detection magnetic sensing chip, which comprises an MCU module, an integrated magnetic switch chip group, a resistor R5 and a third transistor NMOS.

[0038] The MCU module comprises an IN_LH interface and a START interface.

[0039] The IN_LH interface of the MCU module is connected with the first end of the resistor R5.

[0040] The IN_LH interface of the MCU module is connected with the output pin OUT of each integrated magnetic switch chip in the integrated magnetic switch chip group.

[0041] The IN_LH interface of the MCU module is connected with the third transistor NMOS.

[0042] The integrated magnetic switch chip group and the third transistor NMOS are connected.

[0043] The third transistor NMOS is grounded.

[0044] The START interface of the MCU module is connected with the integrated magnetic switch chip group.

[0045] The second end of the resistor R5 is connected with the power supply VCC.

[0046] The ground pin GND of each integrated magnetic switch chip in the integrated magnetic switch chip set is grounded;

[0047] The power supply module of each integrated magnetic switch chip in the integrated magnetic switch chip set is connected to the power supply VCC.

[0048] Optionally, the clock input pin TRI of the first integrated magnetic switch chip in the integrated magnetic switch chip set is connected to the START interface of the MCU module;

[0049] The clock sending pin TRO of the first integrated magnetic switch chip is connected to the clock input pin TRI of the second integrated magnetic switch chip;

[0050] The clock sending pin TRO of the n-1th integrated magnetic switch chip is connected to the clock input pin TRI of the nth integrated magnetic switch chip.

[0051] From the above technical solutions, the embodiments of the present application have the following advantages:

[0052] In the present application, the position detection magnetic sensor chip specifically includes a Wheatstone bridge, a low-offset amplifier, a first Schmitt trigger, a power supply module, a time adjustment module, an enable logic module EN Logic, a first transistor NMOS, and a second transistor NMOS. The position detection magnetic sensor chip includes a ground pin GND, an enable receiving pin TRI, an enable sending pin TRO, and an output pin OUT. The connection modes of the various modules in the position detection magnetic sensor chip are as follows: the power supply module is connected to the Wheatstone bridge, the low-offset amplifier, the first Schmitt trigger, and the time adjustment module. The first transistor NMOS is connected to the Wheatstone bridge, the low-offset amplifier, the enable logic module EN Logic, and the ground pin GND. The low-offset amplifier is connected to the first Schmitt trigger, the Wheatstone bridge, the enable logic module EN Logic, and the time adjustment module. The second transistor NMOS is connected to the time adjustment module, the output pin OUT, the first Schmitt trigger, and the output pin OUT. The enable logic module EN Logic is connected to the enable receiving pin TRI, the enable sending pin TRO, and the time adjustment module. The voltage induced by the Wheatstone bridge is amplified by the low-offset amplifier, and after the amplified voltage is greater than the threshold value of the Schmitt trigger, the Schmitt trigger is flipped. The power supply module serves as a power supply, the time adjustment module is the on-chip clock of the chip, the enable logic module EN Logic determines the enable working mode of the chip according to the signal input from the TRI pin, the time adjustment module is the core of the chip, realizes high-precision adjustment of the clock, and the system calibration function is completed through the logic module EN Logic and the time adjustment module, thereby improving the accuracy of data acquisition of the integrated magnetic switch chip. BRIEF DESCRIPTION OF DRAWINGS

[0053] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the embodiments or prior art description will be briefly introduced. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without any creative effort on the basis of these drawings.

[0054] Figure 1 A chip system architecture schematic diagram of the position detection magnetic sensing chip in the present application;

[0055] Figure 2 A key waveform schematic diagram of the position detection magnetic sensing chip in the present application in the pulse width enable mode;

[0056] Figure 3 A key waveform schematic diagram of the position detection magnetic sensing chip in the present application in the pulse width level enable mode;

[0057] Figure 4 A key waveform schematic diagram of the position detection magnetic sensing chip in the present application in the pulse enable mode;

[0058] Figure 5 A power-up flow schematic diagram of the position detection magnetic sensing chip in the present application;

[0059] Figure 6 A structure schematic diagram of the negative feedback digital trimming loop in the Trim TOP of the position detection magnetic sensing chip in the present application;

[0060] Figure 7 A waveform diagram of the time adjustment module of the position detection magnetic sensing chip in the present application in the clock calibration mode;

[0061] Figure 8 A chip system architecture schematic diagram of the cascade chip in the present application;

[0062] Figure 9 A key signal waveform schematic diagram of the cascade chip in the present application;

[0063] Figure 10 A key signal waveform schematic diagram of the cascade chip in the present application. DETAILED DESCRIPTION

[0064] In the following description, for purposes of explanation and not limitation, specific details are set forth such as particular architectures, techniques, etc. in order to provide a thorough understanding of the embodiments of the present application. However, it will be apparent to those skilled in the art that the present application can be practiced in other embodiments that depart from these specific details. In other instances, detailed descriptions of well-known methods, devices, circuits, and

[0065] It is to be understood that the terminology "includes", "has", "holds", "contains" or "comprising", "including", "having" and the like, when used in the present specification and in the accompanying claims, are used in the sense of "including but not limited to", "including but not limited to", "including but not limited to" and "including but not limited to" respectively, and should be construed as specifically setting forth the stated features, integers, steps or components but not precluding one or more additional features, integers, steps, components and / or groups thereof.

[0066] It is also to be understood that the terminology "and / or" as used in the specification and in the claims, means any one of the associated listed items, or a combination of any two or more of the associated listed items, and includes all possible combinations thereof.

[0067] As used in the specification and in the claims, the term "if" can be interpreted as meaning "when", or "once", or "in response to a determination", or "in response to a detection" depending on the context. Similarly, the phrase "if it is determined" or "if [a described condition or event] is detected" can be interpreted as meaning "once it is determined" or "in response to the determination", or "once [the described condition or event] is detected" or "in response to the detection [of the described condition or event]", depending on the context.

[0068] In addition, the terms "first", "second", "third", etc. as used in the description of the specification and the claims, are only used to distinguish between different instances of description, and cannot be understood as indicating or implying relative importance.

[0069] Reference in the specification to "one embodiment" or "some embodiments" means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the application. The appearances of the phrase "in one embodiment" or "in some embodiments" in various places in the specification are not necessarily all referring to the same embodiment, although it can. The terms "including", "containing", "comprising", "having" and variations thereof in the specification are meant to encompass the item listed thereafter, but do not exclude the presence of one or more additional items.

[0070] In the prior art, it is generally required in industry to measure various non-electric physical quantities, such as temperature, pressure, liquid level, etc., and the physical quantities are converted into analog electric signals by transmitters to be transmitted to a control room or display device several hundred meters away. The most widely used in industrial detection is a 4-20mA current transmitter, and the reason for using current signal is that it is not easy to be disturbed. And the internal resistance of the current source is infinite, and the wire resistance is connected in series in the loop without affecting the accuracy, and it can be transmitted for hundreds of meters on ordinary twisted pair. In industrial applications, the distance between the measuring device and the control room or display device may be tens to hundreds of meters, and two-wire 4-20mA current transmitters are generally used for cost considerations. The upper limit is 20mA because of the requirement of explosion protection: the spark energy caused by the on-off of 20mA current is not enough to ignite gas; the reason for not taking 0mA as the lower limit is to be able to detect the broken wire. The measured device and the signal conditioning circuit power consumption must be less than 4mA, otherwise the transmitter cannot output 4mA zero potential.

[0071] There are some non-contact liquid level detection schemes for detecting the liquid level in industrial water storage devices, such as radar liquid level detection, infrared liquid level detection, ultrasonic liquid level detection, etc., but the main defects of the above schemes are: (1) the above schemes have high cost, slow response speed, low sensitivity and need regular maintenance, and short service life. (2) The liquid level range measured by the above schemes generally does not exceed 20m, when the liquid level height to be measured and its accuracy requirement is higher, the power consumption will exceed the minimum current (4mA) of the 4-20mA transmitter, which cannot meet the high-precision liquid level measurement requirements of industrial large-scale liquid storage devices.

[0072] The traditional low-power magnetic switch liquid level detection scheme is to use a dry reed tube, an industrial water storage device is placed inside a magnetic float, and the dry reed tube is arranged in cascade along the device wall surface at equal intervals. The dry reed tube detects the external magnetic field and realizes the circuit breaking through mechanical movement, which is an ideal switching device in electrical terms. Its structure is simple, the manufacturing process is simple, and the power consumption is low, and it is widely used in liquid level detection, but it also has disadvantages: (1) low precision and sensitivity, poor reliability, and cannot meet the real-time high-precision detection of liquid level. (2) Since it is a mechanical moving switch, it has a short service life, is sensitive to vibration, has a large volume and is difficult to integrate.

[0073] In order to improve the shortcomings of the dry reed liquid level detection scheme, the industry proposes to use a traditional integrated magnetic switch chip to replace the dry reed. The integrated magnetic switch chip periodically detects the external magnetic field according to the wake-up-sleep cycle, and the internal timer sets each chip to be in the wake-up state only once. Low-power high-precision liquid level detection can be achieved. However, in the application process, it is found that the clock frequency of the internal timer of the traditional integrated magnetic switch chip has randomness, and there is a probability that multiple chips are in the wake-up state at the same time, that is, the co-frequency phenomenon. Since there is no communication function between the cascade chips, the co-frequency phenomenon cannot be eliminated. The co-frequency phenomenon may cause the following problems: (1) The co-frequency phenomenon will cause a large instantaneous current, causing the power supply chip to overload, and if the power supply chip does not have an overcurrent limit, it may be burned out. (2) The co-frequency phenomenon causes the chip supply voltage to drop, which may cause the chip to reset abnormally. (3) The co-frequency phenomenon causes the GND to fluctuate greatly, the port sampling voltage VADC is disturbed, and the liquid level height is reported incorrectly.

[0074] Based on this, the application discloses a position detection magnetic sensing chip for improving the accuracy of data acquisition of an integrated magnetic switch chip.

[0075] The technical solutions in the application will be described clearly and completely below in combination with the drawings in the embodiments of the application. Obviously, the described embodiments are only part of the embodiments of the application, not all. Based on the embodiments in the application, all other embodiments obtained by those skilled in the art without creative labor are within the scope of protection of the application.

[0076] Please refer to Figure 1 、 Figure 2 、 Figure 3 、 Figure 4 、 Figure 5 、 Figure 6 、 Figure 7 、 Figure 8 、 Figure 9 and Figure 10 , the application provides an embodiment of a position detection magnetic sensing chip, comprising:

[0077] a Wheatstone bridge, a low-offset amplifier, a first Schmitt trigger, a power supply module, a time adjustment module, an enable logic module EN Logic, a first transistor NMOS, and a second transistor NMOS;

[0078] The position detection magnetic sensing chip includes a ground pin GND, an enable receiving pin TRI, an enable sending pin TRO, and an output pin OUT;

[0079] The power supply module is connected with the Wheatstone bridge, the low-offset amplifier, the first Schmitt trigger, and the time adjustment module, respectively;

[0080] The first transistor NMOS is connected with the Wheatstone bridge, the low-offset amplifier, the enable logic module EN Logic and the ground pin GND respectively.

[0081] The low-offset amplifier is connected with the first Schmitt trigger, the Wheatstone bridge, the enable logic module EN Logic and the time adjustment module respectively.

[0082] The second transistor NMOS is connected with the time adjustment module, the output pin OUT, the first Schmitt trigger and the output pin OUT respectively.

[0083] The enable logic module EN Logic is connected with the enable receiving pin TRI, the enable sending pin TRO and the time adjustment module respectively.

[0084] Optionally, the time adjustment module comprises a clock module OSC and a trimming module Trim TOP.

[0085] The clock module OSC is connected with the power supply module, the Wheatstone bridge, the low-offset amplifier and the trimming module Trim TOP respectively.

[0086] The trimming module Trim TOP is connected with the output pin OUT, the second transistor NMOS and the enable receiving pin TRI respectively.

[0087] Optionally, the trimming module Trim TOP comprises a low-offset comparator, a Trim Logic&T_sensor module, a counter count and a clock start monitoring module.

[0088] The low-offset comparator is connected with the Trim Logic&T_sensor module and the counter count respectively.

[0089] The clock module OSC is connected with the Trim Logic&T_sensor module, the clock start monitoring module and the counter count respectively.

[0090] The enable receiving pin TRI is connected with the Trim Logic&T_sensor module and the counter count respectively.

[0091] The clock start monitoring module is connected with the counter count and the output pin OUT respectively.

[0092] Optionally, the clock start monitoring module comprises a TRIM EN module and a second Schmitt trigger.

[0093] The TRIM EN module is connected with the counter count, the clock module OSC and the second Schmitt trigger respectively.

[0094] The second Schmitt trigger is connected with the output pin OUT.

[0095] The second aspect of the application provides a cascaded chip of a position detection magnetic sensing chip, the cascaded chip comprising an MCU module, an integrated magnetic switch chip group, a resistor R5 and a third transistor NMOS;

[0096] The MCU module comprises an IN_LH interface and a START interface;

[0097] The IN_LH interface of the MCU module is connected with a first end of the resistor R5;

[0098] The IN_LH interface of the MCU module is connected with an output pin OUT of each integrated magnetic switch chip in the integrated magnetic switch chip group;

[0099] The IN_LH interface of the MCU module is connected with the third transistor NMOS;

[0100] The integrated magnetic switch chip group and the third transistor NMOS are connected;

[0101] The third transistor NMOS is grounded;

[0102] The START interface of the MCU module is connected with the integrated magnetic switch chip group;

[0103] A second end of the resistor R5 is connected with a power supply VCC;

[0104] A ground pin GND of each integrated magnetic switch chip in the integrated magnetic switch chip group is grounded;

[0105] A power supply module of each integrated magnetic switch chip in the integrated magnetic switch chip group is connected with the power supply VCC.

[0106] Optionally, a clock input pin TRI of a first integrated magnetic switch chip in the integrated magnetic switch chip group is connected with the START interface of the MCU module;

[0107] A clock sending pin TRO of the first integrated magnetic switch chip is connected with a clock input pin TRI of a second integrated magnetic switch chip;

[0108] A clock sending pin TRO of an n-1th integrated magnetic switch chip is connected with a clock input pin TRI of an nth integrated magnetic switch chip.

[0109] Please refer to Figure 2 , Figure 2 It is a key waveform schematic diagram of a duty mode in the position detection magnetic sensing chip.

[0110] When the high level time TP of the pin TRI (enabling receiving pin TRI) input signal is greater than the set threshold value T0 and less than the set threshold value T1 (T0 < TP < T1), the pulse width enabling working mode (Duty Mode) is entered, and the position detection magnetic sensing chip enters periodic wake-up-sleep: in the wake-up state, internal circuit modules are enabled to work, an external magnetic field is detected, the magnetic field detection result is refreshed and sent to the pin OUT (output pin OUT); in the sleep state, each circuit module is closed, and only the built-in low-power clock works; in this mode, the pin TR0 (enabling sending pin TRO) is always 0.

[0111] Wherein, TRI(i) is the input voltage waveform signal of the pin TRI of the i-th chip, TRO(i) is the input voltage waveform signal of the pin TRO of the i-th chip, i represents the chip number of the cascaded multiple chips, Icc(i) represents the current power consumption of the i-th chip, and OUT(i) represents the output of the i-th chip.

[0112] Please refer to Figure 3 , Figure 3 It is a key waveform schematic diagram in the pulse width level enabling mode (Active Mode) of the position detection magnetic sensing chip.

[0113] When the high level time TP of the pin TRI input signal is greater than the set threshold value T0 and less than the set threshold value T1 (T0 < TP < T1), the pulse width enabling working mode (Duty Mode) is entered, and the chip enters periodic wake-up-sleep: in the wake-up state, internal circuit modules are enabled to work, an external magnetic field is detected, the magnetic field detection result is refreshed and sent to the pin OUT; in the sleep state, each circuit module is closed, and only the built-in low-power clock works; in this mode, the pin TR0 is always 0.

[0114] Please refer to Figure 4 , Figure 4 It is a key waveform schematic diagram in the pulse enabling (cascaded mode) of the position detection magnetic sensing chip.

[0115] When the high level time TP of the pin TRI input signal is less than the set threshold value T0 (0 < TP < T0), the pulse enabling working mode (cascaded mode) is entered, and the chip enters periodic wake-up-sleep: in the wake-up state, internal circuit modules are enabled to work, an external magnetic field is detected, the magnetic field detection result is refreshed and sent to the pin OUT; in the sleep state, each circuit module is closed, and only the built-in low-power clock works; when entering the sleep state, the TR0 sends a pulse signal to the outside.

[0116] Please refer to Figure 5 , Figure 5 It is a power-on flow schematic diagram of the position detection magnetic sensing chip.

[0117] After the power-on of the chip, the OUT pin enters a signal receiving state. When the input signal of the OUT pin is pulled low from high level and the low level time TOUTL is greater than T2 (TOUTL > T2), the clock calibration mode is entered. After the clock calibration time TCAL, the input signal of the OUT pin is pulled high again, and the chip exits the clock calibration mode. The enable receiving pin TRI enters a signal receiving state, and the working mode entered is determined according to the high level time Tp of the input signal.

[0118] Please refer to Figure 6 and Figure 7 , Figure 6 The structure diagram of a negative feedback digital trimming loop (DIG_TRIM_LOOP) in a trimming module Trim TOP, Figure 7 The waveform diagram of the time adjustment module in the clock calibration mode.

[0119] The negative feedback digital trimming loop (DIG_TRIM_LOOP) includes a system calibration function and a temperature compensation function. The position detection magnetic sensing chip enters the clock calibration mode. The standard clock signal filled from the TRI pin and the internal OSC signal are input into a counter (Counter) together. The counting result is sent into a comparator and compared with a reference potential DREF. The comparator output Comparator out signal is sent to a trim logic & T sensor module. The trim logic & T sensor module reads out the required Trimming_Data according to the comparison result and sends it into the OSC, thereby completing the chip clock system calibration. The trim logic & T sensor module integrates a temperature sensing circuit. When the external temperature changes, it will automatically send the required Trimming_Data to the OSC, thereby completing the chip clock temperature compensation.

[0120] The low-power clock OSC is started, and the OSC_OK signal is pulled high. The TRIM EN module transmits the TRIM_EN signal to the counter (Counter). OUTL That is, the time when the chip OUT pin is pulled low, T2 is a time specified by any designer, CAL The clock calibration time.

[0121] Please refer to Figure 8 , Figure 9 and Figure 10 , Figure 8 The structure of the cascaded chip, Figure 9 and Figure 10 The key signal waveform schematic diagram.

[0122] The cascade mode high-precision low-power liquid level detection scheme includes an MCU, a pull-up resistor, a magnetic float, a plurality of equally spaced series of chips, and an NMOS. The START pin of the MCU is connected to the TRI(1) pin of the first chip U1, the TR0(i) of the ith chip Ui is connected to the TRI(i-1) pin of the (i-1)th chip Ui-1(i=2~n), and the last chip Un is connected to the gate of the NMOS. The output pin OUT of all magnetic switch chips and the drain of the NMOS are connected to the INT_LH pin of the MCU and the pull-up resistor R. The START pin of the MCU sends a detection enable signal, and the INT_LH receives a liquid level measurement signal. The chip TRI pin receives a pulse signal Trigger sent by the START pin of the MCU or the TRO pin of the previous chip to enable, and the chip detects the external magnetic field. If the external magnetic field exceeds the set threshold, the chip OUT pin is pulled low, otherwise it remains high.

[0123] The liquid level detection process is as follows: the magnetic switch chip is arranged along the device wall surface at an interval of 1 centimeter, the START pin of the MCU sends a pulse signal to the TRI(1) pin, the Trigger first magnetic switch chip U1 is enabled, the internal analog module wakes up to detect the external magnetic field, and after the detection is completed, it goes to sleep, at the same time, TRO(1) sends a pulse enable signal to TRI(2), Trigger the second magnetic switch chip U2 to enable, repeat the above process until the last nth magnetic switch chip Un completes the external magnetic field detection, TRO(n) sends a pulse enable signal to the open drain NMOS to turn on, and the pull-up resistor R connected to the drain of the NMOS will be pulled to GND, and the INT_LH pin voltage of the MCU will be pulled to GND, and after the pulse signal sent by TRO(n) disappears, the time when the measurement is pulled high again is T S2E . The liquid surface has a magnetic float, when the liquid level reaches a certain height, the magnetic switch Ui near the float will be closed, and the pull-up resistor connected to the OUT(i) pin of the magnetic switch chip Ui will be pulled to GND, and the INT_LH pin voltage of the MCU will be pulled to GND, and after the magnetic switch chip Ui completes the detection, the time when the measurement is pulled low is TX, and the total height of the liquid level device is FS_Height, then the measured liquid level height is:

[0124]

[0125] The above liquid level detection has a link self-checking function, when the following conditions are met:

[0126] T S2E >Tmax∪T S2E <Tmin

[0127] When the above conditions are met, the link exception is reported. In the liquid level detection scheme, the MCU detects the time ratio of the liquid level terminal and the last terminal, which can determine the liquid level height, without the need for a linear resistance string and an external ADC resistance measurement, and has a link self-checking function, combining simplicity and reliability.

[0128] Optionally, the power supply module includes a power supply voltage pin VCC and a reference voltage module VREG.

[0129] The power supply voltage pin VCC is connected with the reference voltage module VREG.

[0130] The reference voltage module VREG is connected with the Wheatstone bridge, the low-offset amplifier, the time adjustment module and the first Schmitt trigger, respectively.

[0131] Optionally, the Wheatstone bridge is composed of a magnetic sensitive element R1, a magnetic sensitive element R2, a magnetic sensitive element R3 and a magnetic sensitive element R4.

[0132] The magnetic sensitive element R1, the magnetic sensitive element R2, the magnetic sensitive element R3 and the magnetic sensitive element R4 are connected in sequence to form the bridge.

[0133] Optionally, the interfaces of the magnetic sensitive element R1 and the magnetic sensitive element R2 are connected with the low-offset amplifier.

[0134] The interfaces of the magnetic sensitive element R3 and the magnetic sensitive element R4 are connected with the low-offset amplifier.

[0135] The interfaces of the magnetic sensitive element R2 and the magnetic sensitive element R3 are connected with the first transistor NMOS.

[0136] The interfaces of the magnetic sensitive element R1 and the magnetic sensitive element R4 are connected with the power supply module, the low-offset amplifier and the time adjustment module, respectively.

[0137] Optionally, the magnetic sensitive element R1, the magnetic sensitive element R2, the magnetic sensitive element R3 and the magnetic sensitive element R4 are Hall magnetoresistance, AMR magnetoresistance, GMR magnetoresistance or TMR magnetoresistance.

[0138] In the present application, the terms "upper", "lower", "left", "right", "front", "back", "top", "bottom", "inner", "outer", "middle", "vertical", "horizontal", "lateral", "longitudinal" and the like indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, and are only used to illustrate the relative positional relationship between the components or constituent parts, and do not particularly limit the specific installation orientation of the components or constituent parts.

[0139] In addition, the above-mentioned partial terms can be used to represent other meanings in addition to the orientation or positional relationship, for example, the term "upper" can also be used to represent a certain dependent relationship or connection relationship in some cases. For those of ordinary skill in the art, the specific meanings of these terms in the present application can be understood according to the specific circumstances.

[0140] In addition, the terms "mount", "set", "provided with", "connected", "connected" should be broadly understood. For example, it can be a fixed connection, a detachable connection, or a monolithic structure; it can be a mechanical connection, or an electrical connection; it can be directly connected, or indirectly connected through an intermediate medium, or internal communication between two devices, elements or components. For those of ordinary skill in the art, the specific meanings of the above terms in the present application can be understood according to the specific circumstances.

[0141] In addition, the structure, proportion, size, etc. drawn in the drawings attached in the present application are only used to cooperate with the disclosed content of the specification, for those skilled in the art to understand and read, and do not have a technical substantive meaning, any modification of the structure, change of the proportion relationship or adjustment of the size, without affecting the effect and the purpose that can be achieved by the present application, still should fall within the scope of the technical content disclosed by the present application.

Claims

1. A position detection magnetic sensing chip, characterized by, The application relates to a position detection magnetic sensor chip. The position detection magnetic sensor chip comprises a Wheatstone bridge, a low-offset amplifier, a first Schmitt trigger, a power supply module, a time adjustment module, an enable logic module EN Logic, a first transistor NMOS and a second transistor NMOS. The position detection magnetic sensor chip comprises a ground pin GND, an enable receiving pin TRI, an enable sending pin TRO and an output pin OUT. The power supply module is connected with the Wheatstone bridge, the low-offset amplifier, the first Schmitt trigger and the time adjustment module respectively. The first transistor NMOS is connected with the Wheatstone bridge, the low-offset amplifier, the enable logic module EN Logic and the ground pin GND respectively. The low-offset amplifier is connected with the first Schmitt trigger, the Wheatstone bridge, the enable logic module EN Logic and the time adjustment module respectively. The second transistor NMOS is connected with the time adjustment module, the output pin OUT, the first Schmitt trigger and the output pin OUT respectively. The enable logic module EN Logic is connected with the enable receiving pin TRI, the enable sending pin TRO and the time adjustment module respectively.

2. The position detection magnetic sensor chip according to claim 1, wherein The time adjustment module comprises a clock module OSC and a trimming module Trim TOP. The clock module OSC is connected with the power supply module, the Wheatstone bridge, the low-offset amplifier and the trimming module Trim TOP respectively. The trimming module Trim TOP is connected with the output pin OUT, the second transistor NMOS and the enable receiving pin TRI respectively.

3. The position detection magnetic sensor chip according to claim 2, wherein The trimming module Trim TOP comprises a low-offset comparator, a Trim Logic&T_sensor module, a counter count and a clock start monitoring module. The low-offset comparator is connected with the Trim Logic&T_sensor module and the counter count respectively. The clock module OSC is connected with the Trim Logic&T_sensor module, the clock start monitoring module and the counter count respectively. The enable receiving pin TRI is connected with the Trim Logic&T_sensor module and the counter count respectively. The clock start monitoring module is connected with the counter count and the output pin OUT respectively.

4. The position detection magnetic sensor chip according to claim 3, wherein The clock start monitoring module comprises a TRIM EN module and a second Schmitt trigger. The TRIM EN module is connected with the counter count, the clock module OSC and the second Schmitt trigger respectively. The second Schmitt trigger is connected with the output pin OUT.

5. The position detection magnetic sensor chip according to claim 1, wherein The power supply module comprises a power supply voltage pin VCC and a reference voltage module VREG. The power supply voltage pin VCC is connected with the reference voltage module VREG. The reference voltage module VREG is connected with the Wheatstone bridge, the low-offset amplifier, the time adjustment module and the first Schmitt trigger respectively.

6. The position detection magnetic sensor chip according to any one of claims 1 to 5, characterized in that, The Wheatstone bridge is composed of a magnetic sensitive element R1, a magnetic sensitive element R2, a magnetic sensitive element R3 and a magnetic sensitive element R4. The magnetic sensitive element R1, the magnetic sensitive element R2, the magnetic sensitive element R3 and the magnetic sensitive element R4 are sequentially connected to form a bridge.

7. The position detection magnetic sensor chip according to claim 6, wherein The interfaces of the magnetic sensitive element R1 and the magnetic sensitive element R2 are connected with the low-offset amplifier. The interfaces of the magnetic sensitive element R3 and the magnetic sensitive element R4 are connected with the low-offset amplifier. The interfaces of the magnetic sensitive element R2 and the magnetic sensitive element R3 are connected with the first transistor NMOS. The interfaces of the magnetic sensitive element R1 and the magnetic sensitive element R4 are respectively connected with the power supply module, the low-offset amplifier and the time adjustment module.

8. The position detection magnetic sensor chip according to claim 6, wherein The magnetic sensitive element R1, the magnetic sensitive element R2, the magnetic sensitive element R3 and the magnetic sensitive element R4 are Hall magnetoresistance, AMR magnetoresistance, GMR magnetoresistance or TMR magnetoresistance.

9. The position detection magnetic sensor chip according to claim 1, wherein The cascade chip comprises an MCU module, an integrated magnetic switch chip group, a resistor R5 and a third transistor NMOS. The MCU module comprises an IN_LH interface and a START interface. The IN_LH interface of the MCU module is connected with the first end of the resistor R5. The IN_LH interface of the MCU module is connected with the output pin OUT of each integrated magnetic switch chip in the integrated magnetic switch chip group. The IN_LH interface of the MCU module is connected with the third transistor NMOS. The integrated magnetic switch chip group and the third transistor NMOS are connected. The third transistor NMOS is grounded. The START interface of the MCU module and the integrated magnetic switch chip group are connected. The second end of the resistor R5 is connected with a power supply VCC. The ground pin GND of each integrated magnetic switch chip in the integrated magnetic switch chip group is grounded. The power supply module of each integrated magnetic switch chip in the integrated magnetic switch chip group is connected with the power supply VCC.

10. The position detection magnetic sensor chip according to claim 9, wherein The clock input pin TRI of the first integrated magnetic switch chip in the integrated magnetic switch chip group is connected with the START interface of the MCU module. The clock sending pin TRO of the first integrated magnetic switch chip is connected with the clock input pin TRI of the second integrated magnetic switch chip. The clock sending pin TRO of the n-1th integrated magnetic switch chip is connected with the clock input pin TRI of the nth integrated magnetic switch chip.

Images