Chip synchronous clock between circuit jump fault test method

Abstract

The application discloses a kind of chip synchronous clock between circuit jump fault test method, in chip synchronous clock test circuit, pulse_ctrl module is connected behind PLL output clock, the pulse_ctrl module generates internal clock and reset;Including divider module, the divider module includes frequency division circuit, to generate frequency division clock;Still including syn_occ module, the syn_occ module controls the pulse output of frequency division clock;Pulse_ctrl module outputs clock_out as the reference clock of chip frequency division circuit;When fault test, the output signal div_rstn of pulse_ctrl module controls the reset end rstn of frequency division circuit, and participates in the test clock generation of sync_occ module.The application realizes the test of synchronous clock between circuit jump fault, and the clock path under test mode and the clock path under chip function mode are completely identical, the circuit area and timing convergence overhead of test logic are reduced, and the test coverage of circuit fault is improved.

Description

TECHNICAL FIELD

[0001] The application discloses a chip synchronous clock circuit transition fault test method and relates to the technical field of integrated circuit fault test. BACKGROUND

[0002] With the high-speed development of integrated circuit design and process, the SOC chip scale is getting larger and larger, and the required clock quantity is getting more and more. A typical clock structure is that a high-frequency clock is output by a PLL, and then various coefficient frequency division is performed on the high-frequency clock, so as to obtain the working frequency required by each functional module. The frequencies of various frequency division clocks are different (for example, 2 frequency division and 3 frequency division), but they may be synchronous clocks, and the logic path between these synchronous clock domains needs to be tested.

[0003] In the testability design, different frequency clocks usually use independent on-chip clock controllers (OCCs). Since the clocks output by the independent OCCs do not have deterministic phase relationship, the transition faults between the different clock domains cannot be tested. SUMMARY

[0004] The application aims to solve the technical problem of the prior art, and provides a chip synchronous clock circuit transition fault test method, so as to overcome the test problem of the transition faults between the synchronous clock domains in the prior art testability design, and realize the transition fault test between the synchronous clocks.

[0005] The application adopts the following technical scheme to solve the above technical problem:

[0006] A chip synchronous clock circuit transition fault test method, in the test method, a pulse_ctrl module is connected behind a PLL output clock in a chip synchronous clock test circuit, the pulse_ctrl module generates an internal clock and a reset;

[0007] The test circuit further comprises a divider module, and the divider module comprises a frequency division circuit, and is used to generate a frequency division clock;

[0008] The test circuit further comprises a syn_occ module, and the syn_occ module controls the pulse output of the frequency division clock;

[0009] The pulse_ctrl module outputs a clock_out as a reference clock of a chip frequency division circuit;

[0010] The output signal div_rstn of the pulse_ctrl module controls the reset terminal rstn of the divider circuit and participates in the test clock generation of the sync_occ module.

[0011] As a further preferred solution, the pulse_ctrl module outputs 0 at the scan chain shift stage, outputs 0 at the clock_out, and the time when div_rstn changes from 0 to 1 at the scan chain capture stage is adjustable. The number of pulse_ctrl / clock_out output pulses in the pulse_ctrl module is configurable.

[0012] As a further preferred solution, the time interval from when pulse_ctrl / div_rstn becomes 1 to when pulse_ctrl / clock_out starts to output in the pulse_ctrl module is configurable.

[0013] As a further preferred solution, in the pulse_ctrl module, the reset of all divider circuits and the reference clock input occur at the same time during the scan chain capture stage, and the phase relationship between the output clocks is determined. During the scan chain capture stage, pulse_ctrl / div_rstn controls the operation of syn_occ, and pulse_ctrl / div_rstn is stable before the clock edge without clock synchronization and timing constraints.

[0014] As a further preferred solution, in the pulse_ctrl module, the pulse_ctrl circuit scan chain shift enable signal is not clock-constrained.

[0015] As a further preferred solution, in the divider module, the clock output of the divider circuit is 0 during the scan chain shift stage, the reference clock of the divider circuit is 0 when the reset terminal changes, and there is no timing constraint between the reset terminal and the clock.

[0016] As a further preferred solution, in the pulse_ctrl module, the div_rstn output of the pulse_ctrl module is generated by three registers. The first register r0 is used to capture the signal value of the inverted scan_shift_enable, and the capture clock is the shift clock of the scan chain. The second and third registers r1 and r2 are both synchronous registers, and the synchronization clock is the output clock of the PLL.

[0017] As a further preferred solution, in the syn_occ module, the clock_out output clock of the sync_occ module is the scan chain shift clock during the scan chain shift stage, and is the internally generated test clock during the scan capture stage.

[0018] In the cp_ctrl submodule of the syn_occ module, in the scan chain shift stage, the register r[7:0] sequentially shifts into the value of scan_in; in the scan chain capture stage, after div_rstn becomes 1, r[7:0] controls the output of the test clock pulse, when r[0] is 1, the test clock output pulse, when r[0] is 0, the test clock outputs 0.

[0019] Further, the r register in the cp_ctrl submodule, r[7:0] is an application instance, and the bit width thereof can be configured according to specific requirements.

[0020] Compared with the prior art, the technical scheme of the present application has the following technical effects:

[0021] The control circuit design of the present application realizes the test of the circuit jump fault between the synchronous clocks. The clock path in the test mode and the clock path in the chip function mode are completely consistent, the circuit to be tested and the functional circuit are consistent, the circuit area and the timing convergence overhead of the test logic are reduced, and the test coverage of the circuit fault is improved. BRIEF DESCRIPTION OF DRAWINGS

[0022] Figure 1 is a structural schematic diagram of the clock control design of the present application.

[0023] Figure 2 is a structural schematic diagram of the pulse_ctrl module of the present application.

[0024] Figure 3 is a structural schematic diagram of the sync_occ module of the present application.

[0025] Figure 4 is a structural schematic diagram of the cp_ctrl submodule of the present application.

[0026] Figure 5 is a timing schematic diagram of the clock control design of the present application. DETAILED DESCRIPTION

[0027] The embodiments of the present application will be described in detail below, and examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference signs represent the same or similar elements or elements having the same or similar functions throughout. The embodiments described below by referring to the accompanying drawings are exemplary and are only used to explain the present application, and cannot be interpreted as a limitation of the present application.

[0028] The technical scheme of the present application will be further described in detail below in combination with the accompanying drawings:

[0029] The application discloses a test circuit for circuit jump fault between chip synchronous clocks, and the specific design of the circuit is shown in the figure Figure 1 The pulse_ctrl module connected behind the PLL output clock outputs clock_out as the reference clock of the chip frequency division circuit. In the test mode (scan_mode=1), the output signal div_rstn of the pulse_ctrl module controls the reset end rstn of the frequency division circuit (clk_divider) and participates in the test clock generation of the sync_occ module.

[0030] The above Figure 1 The specific design of the pulse_ctrl module in the test circuit is shown in the figure Figure 2 The div_rstn output of the pulse_ctrl module is generated by three registers (r0, r1 and r2). The r0 register captures the signal value of scan_shift_enable inversion, and the capture clock is the scan chain shift clock (scan_shift_clock). The r1 and r2 registers are synchronous registers, and the synchronous clock is the PLL output clock (pll_clock). In the scan chain shift stage (scan_shift_enable=1), the div_rstn output value is 0, and in the scan chain capture stage (scan_shift_enable=0), the time when the div_rstn output changes from 0 to 1 can be controlled by controlling the time when the scan chain shift clock pulse is generated.

[0031] The clock_out output of the pulse_ctrl module is controlled by pll_clock_counter / clk_en, and the working principle of pll_clock_counter is as follows: in the scan chain shift stage, since div_rstn=0, pll_clock_counter is in the reset state, and the output clock_en=0. In the scan chain capture stage, after div_rstn=1, pll_clock_counter starts to count pll_clock.

[0032] When the count value of pll_clock_counter is less than pulse_delay_cfg, clock_en=0;

[0033] When the count value of pll_clock_counter is greater than or equal to pulse_delay_cfg and less than the sum of pulse_delay_cfg and pll_cnt_cfg, clock_en=1;

[0034] When the count value of pll_clock_counter is greater than the sum of pluse_delay_cfg and pll_cnt_cfg, clock_en=0.

[0035] pulse_delay_cfg controls the time interval from div_rstn=1 to the first pulse output by pluse_ctrl, and its value can be flexibly configured.

[0036] pulse_cnt_cfg controls the number of clock_out pulses, and its value can be flexibly configured.

[0037] The above Figure 1 The sync_occ module in the test circuit, the specific design of the circuit is as shown in Figure 3 The clock_out output clock of the sync_occ module, in the scan chain shift stage, it is the scan chain shift clock (scan_shift_clock); in the scan capture stage, it is the internally generated test clock.

[0038] The above Figure 3 The cp_ctrl submodule in the module, the specific design of the circuit is as shown in Figure 4 In the scan chain shift stage, the registers r[7:0] sequentially shift into the values of scan_in. In the scan chain capture stage, after div_rstn becomes 1, r[7:0] controls the output of the test clock pulse, when r[0] is 1, the test clock output pulse, when r[0] is 0, the test clock outputs 0 (i.e. no pulse is output).

[0039] Figure 5 The timing diagram of the test circuit of the application, in the scan chain shift stage, the chip scan chain shifts in the state values required for testing. In the scan chain capture stage, the time point of the first shift clock pulse p1 controls the time interval between t1 and t2, and the pulse_delay_cfg value controls the time interval t2 between t2 and t3. After the shift of r[7:0] is completed, the number and position of the registers with state 1 control the number and distribution of the captured clock output clock_out. The r register in the cp_ctrl submodule, r[7:0] is an application example, and its bit width can be configured according to specific requirements.

[0040] The above detailed description of the embodiments of the present application is made with reference to the accompanying drawings, but the present application is not limited to the above-described embodiments, and various changes can be made within the knowledge of those skilled in the art without departing from the spirit of the present application. The above description is only a preferred embodiment of the present application, and is not intended to limit the present application in any form. Although the present application has been disclosed with reference to the preferred embodiments, it is not intended to limit the present application, and any person skilled in the art can make some changes or modifications to the above-mentioned disclosed technical content to obtain equivalent embodiments, as long as they do not depart from the technical solution of the present application. Any simple modification, equivalent replacement and improvement of the above embodiments, as long as they do not depart from the technical solution of the present application, are within the protection scope of the present application.

Claims

1. A method for testing circuit transition faults between chip synchronous clocks, characterized in that: In the aforementioned test method, in the chip synchronous clock test circuit, a pulse_ctrl module is connected after the PLL output clock. The pulse_ctrl module generates an internal clock and a reset. The pulse_ctrl module outputs div_rstn as 0 during the scan chain shifting phase; outputs clock_out as 0 during the scan chain shifting phase; and the timing when div_rstn output changes from 0 to 1 during the scan chain capture phase is adjustable. In the pulse_ctrl module, the number of pulses output by pulse_ctrl / clock_out is configurable; the time interval from when pulse_ctrl / div_rstn becomes 1 to when pulse_ctrl / clock_out starts outputting is configurable. The test circuit also includes a divider module, which includes a frequency divider circuit for generating a frequency-divided clock. The test circuit also includes a syn_occ module, which controls the pulse output of the frequency divider clock; The pulse_ctrl module outputs clock_out as the reference clock for the chip's frequency divider circuit; During fault testing, the output signal div_rstn of the pulse_ctrl module controls the reset terminal rstn of the frequency divider circuit and participates in the test clock generation of the sync_occ module.

2. The method for testing circuit transition faults between chip synchronous clocks as described in claim 1, characterized in that, The In the pulse_ctrl module: During the scan chain capture phase, the reset of all frequency divider circuits and the reference clock input occur at the same time, and the phase relationship between the output clocks is determined. During the scan chain capture phase, pulse_ctrl / div_rstn controls the operation of syn_occ. pulse_ctrl / div_rstn stabilizes before the clock edge and does not perform clock synchronization or timing constraints.

3. The method for testing circuit transition faults between chip synchronous clocks as described in claim 1, characterized in that, The In the pulse_ctrl module: the pulse_ctrl circuit scan chain shift enable signal is not clock-constrained.

4. The method for testing circuit transition faults between chip synchronous clocks as described in claim 1, characterized in that, In the divider module: The clock output of the frequency divider circuit is 0 during the scan chain shifting stage; When the reset terminal of the frequency divider circuit changes, its reference clock becomes 0. No timing constraints are applied between the reset pin and the clock.

5. The method for testing circuit transition faults between chip synchronous clocks as described in claim 1, characterized in that, The In the pulse_ctrl module, the div_rstn output of the pulse_ctrl module is generated by 3 registers; The first register r0 is used to capture the inverted value of scan_shift_enable signal, and the capture clock is the shift clock of the scan chain; The second and third registers, r1 and r2, are both synchronization registers, and the synchronization clock is the output clock of the PLL.

6. The method for testing circuit transition faults between chip synchronous clocks as described in claim 1, characterized in that, In the syn_occ module, the clock_out output clock of the sync_occ module is the scan chain shift clock during the scan chain shift stage; and the clock is the internally generated test clock during the scan capture stage.

7. The method for testing circuit transition faults between chip synchronous clocks as described in claim 6, characterized in that, In the cp_ctrl submodule of the syn_occ module: During the scan chain shifting phase, registers r[7:0] are sequentially shifted into the values ​​of scan_in; During the scan chain capture phase, after div_rstn becomes 1, r[7:0] controls the output of the test clock pulse. When r[0] is 1, the test clock outputs a pulse, and when r[0] is 0, the test clock outputs 0.

8. The method for testing circuit transition faults between chip synchronous clocks as described in claim 7, characterized in that, The r register in the cp_ctrl submodule, r[7:0] is an application example, and its bit width can be configured according to specific requirements.

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