A test method to prevent damage to wafer testing equipment

Abstract

This invention provides a testing method to prevent damage to wafer testing equipment, comprising the following steps: providing a wafer to be tested, the wafer including multiple chips; measuring the power consumption of each measurement item to be tested during functional testing of the chips, and identifying the screening test item, which is the test item with the highest power consumption; testing the dynamic power consumption of the screening test item during operation, screening out chips with abnormal dynamic power consumption, and performing functional testing on chips with normal dynamic power consumption. This invention measures the power consumption of each test item of the chip, determines the test item with the highest power consumption, and measures the dynamic power consumption of this test item of all chips before functional testing, thus screening out chips with abnormal power supply as well as chips with normal power supply but abnormal operation, thereby screening out all abnormal chips in advance and avoiding problems caused by excessive current during later functional testing. This effectively protects the probe card and testing equipment, improves the lifespan of the probe card, and ensures product delivery time.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a testing method for preventing damage to wafer testing equipment. Background Technology

[0002] Currently, in wafer-level testing, a probe card is typically used to connect the testing equipment to the wafer under test. The testing equipment applies a certain voltage signal to the chip through the probe card and performs electrical tests.

[0003] Normally, the operating current of a healthy chip on a wafer is in the milliamp range or below, which is within the current tolerance range of the test equipment and probe cards. However, in reality, the presence of faulty chips on the wafer can cause short circuits, malfunctions, and other issues, resulting in extremely high power currents. During functional testing, these chips will draw a significant amount of current through the test equipment and probe cards, potentially damaging the test equipment and requiring it to be returned for repair. However, this repair process is time-consuming and disrupts normal wafer testing. Simultaneously, the high current can cause instantaneous oxidation of the probe tips, leading to probe burn-out. Removing the oxide from the probe tips is necessary, but this process causes wear and tear on the tips, reducing their lifespan. Summary of the Invention

[0004] The purpose of this invention is to provide a testing method to prevent damage to wafer testing equipment, which can screen out chips with abnormal power current and malfunctions before performing functional tests, thereby effectively protecting the testing equipment and probe cards.

[0005] To address the above problems, this invention provides a testing method for preventing damage to wafer testing equipment, comprising the following steps:

[0006] Step S1: Provide a wafer to be tested, the wafer to be tested comprising multiple chips;

[0007] Step S2: Measure the power consumption of each measurement item that needs to be tested during the functional test of the chip, and identify the filter test items, which are the test items with the highest power consumption; and

[0008] Step S3: Test the dynamic power consumption of the screening test items during operation, screen out the chips with abnormal dynamic power consumption, and perform functional tests on the chips with normal dynamic power consumption.

[0009] Optionally, the wafer to be tested needs to undergo functional testing using wafer testing equipment.

[0010] Furthermore, the wafer testing equipment includes a testing station and a probe station. The probe station includes a probe card and a main unit that are electrically connected. During electrical measurement, the wafer to be tested is placed on the main unit. The probe card is electrically connected to the wafer to be tested through the probes of the probe card. At the same time, the wafer to be tested is electrically connected to the testing station through the probe card.

[0011] Optionally, all of the aforementioned chip arrays are distributed.

[0012] Optionally, step S2 includes:

[0013] Before placing the wafer under test on the testing machine and performing functional testing, the power consumption of at least one of the chips is tested for each measurement item that needs to be tested during functional testing, so as to obtain the power consumption values ​​of each test item in all the chips; and

[0014] Based on the power consumption values ​​of all test items, identify the highest power consumption value and the test item with the highest power consumption, thereby identifying the test items to filter.

[0015] Optionally, step S3 includes:

[0016] The screening test items are performed on all the chips of the wafer to be tested to measure the dynamic power consumption of all the chips during the operation of the screening test items;

[0017] The abnormal chip is determined based on the dynamic power consumption;

[0018] Functional tests were performed on the chip with normal dynamic power consumption.

[0019] Further steps for identifying abnormal chips include:

[0020] The chip whose dynamic power consumption exceeds a preset value is determined to be an abnormal chip; and

[0021] The chip whose dynamic power consumption is less than the preset value is determined to be a normal chip.

[0022] Furthermore, the functional testing of the chip with normal dynamic power consumption specifically includes:

[0023] The wafer to be tested is placed on a prober stand and electrically connected to the probe card and the test stand via the probes to perform functional tests on all the normal chips.

[0024] Compared with the prior art, the present invention has the following beneficial effects:

[0025] This invention provides a testing method to prevent damage to wafer testing equipment, comprising the following steps: Step S1: Providing a wafer to be tested, the wafer including multiple chips; Step S2: Measuring the power consumption of each measurement item to be tested during functional testing of the chips, and identifying the screening test item, the screening test item being the test item with the highest power consumption; Step S3: Testing the dynamic power consumption of the screening test item during operation, screening out chips with abnormal dynamic power consumption, and performing functional testing on chips with normal dynamic power consumption. This invention measures the power consumption of each test item of the chip, determines the test item with the highest power consumption, and measures the dynamic power consumption of all chips for this test item before functional testing. This can screen out chips with abnormal power supply, as well as chips with normal power supply but abnormal operation, thus screening out all abnormal chips in advance, avoiding problems caused by excessive current during later functional testing. This effectively protects the probe card and testing equipment, improves the lifespan of the probe card, and ensures product delivery time. Attached Figure Description

[0026] Figure 1 This is a flowchart illustrating a testing method for preventing damage to wafer testing equipment according to an embodiment of the present invention. Detailed Implementation

[0027] The following will provide a more detailed description of a testing method for preventing damage to wafer testing equipment according to the present invention. The invention will now be described in more detail with reference to the accompanying drawings, which illustrate preferred embodiments of the invention. It should be understood that those skilled in the art can modify the invention described herein while still achieving its advantageous effects. Therefore, the following description should be understood as being of general knowledge to those skilled in the art and is not intended to limit the invention.

[0028] For clarity, not all features of the actual embodiments are described. In the following description, well-known functions and structures are not detailed in detail, as they would obscure the invention with unnecessary detail. It should be understood that in the development of any actual embodiment, numerous implementation details must be made to achieve the developer's specific objectives, such as changes from one embodiment to another according to limitations related to the system or business. Furthermore, it should be understood that such development work may be complex and time-consuming, but is merely routine work for those skilled in the art.

[0029] To make the objectives and features of the present invention more apparent and understandable, the specific embodiments of the present invention will be further described below with reference to the accompanying drawings. It should be noted that the drawings are all in a very simplified form and use non-precise ratios, and are only used to conveniently and clearly assist in illustrating the objectives of the embodiments of the present invention.

[0030] Figure 1This is a flowchart illustrating a testing method for preventing damage to wafer testing equipment provided in this embodiment. Figure 1 As shown in the figure, this embodiment provides a testing method for preventing damage to wafer testing equipment, including the following steps:

[0031] Step S1: Provide a wafer to be tested, the wafer to be tested comprising multiple chips;

[0032] Step S2: Measure the power consumption of each measurement item that needs to be tested during the functional test of the chip, and find the screening test items, which are the test items with the highest power consumption;

[0033] Step S3: Test the dynamic power consumption of the screening test items during operation, screen out the chips with abnormal dynamic power consumption, and perform functional tests on the chips with normal dynamic power consumption.

[0034] The following is a detailed description of a test method for preventing damage to wafer testing equipment provided in this embodiment.

[0035] First, step S1 is performed, providing a wafer to be tested, which includes multiple chips.

[0036] The wafer to be tested needs to undergo functional testing using wafer testing equipment, which includes a testing platform and a probe platform. The probe platform includes a probe card and a main unit that are electrically connected. During electrical measurement, the wafer to be tested is placed on the main unit, and the probe card is electrically connected to the wafer to be tested through its probes. At the same time, the wafer to be tested is electrically connected to the testing platform through the probe card.

[0037] The wafer to be tested includes multiple chips, all of which are arranged in an array, and most of the chips require functional testing.

[0038] Next, step S2 is executed to measure the power consumption of each measurement item that needs to be tested during the functional test of the chip, and to identify the screening test items, which are the test items with the highest power consumption.

[0039] In detail, firstly, before placing the wafer to be tested on the test bench and performing functional testing, the power consumption of at least one of the chips is tested for each measurement item that needs to be tested during functional testing, so as to obtain the power consumption value of each test item in all the chips.

[0040] Next, based on the power consumption values ​​of all test items, the highest power consumption value and the test item with the highest power consumption are identified, thereby finding the test items to filter.

[0041] Next, step S3 is executed to test the dynamic power consumption of the screening test item during operation, screen out the chips with abnormal dynamic power consumption, and perform functional tests on the chips with normal dynamic power consumption.

[0042] This step specifically includes:

[0043] All chips on the wafer to be tested are subjected to the screening test items to measure the power supply short-circuit current, i.e., dynamic power consumption, of the chips during the screening test items. All chips whose dynamic power consumption is above a preset value are identified as abnormal chips; all chips whose dynamic power consumption is below the preset value are identified as normal chips.

[0044] This step identifies faulty chips with abnormal power supply current and malfunctions, preventing issues such as probe burn-out during later functional testing due to excessive current and damage to the test equipment board. It effectively protects the probe card and test equipment, extends the lifespan of the probe card, and ensures timely chip delivery.

[0045] Next, all the abnormal chips on the wafer under test are identified;

[0046] Next, the wafer to be tested is placed on the probe machine platform, and the wafer to be tested is electrically connected to the probe card and the test machine platform through the probes to perform functional tests on all the normal chips.

[0047] In existing technologies, only the current of the chip during a power short circuit is tested to screen out abnormal chips with extremely high current during short circuits. Then, functional tests are performed on the screened, normal chips. This method does not completely eliminate abnormal chips, leaving some undetected. This can lead to problems such as probe burn-out due to excessive current during later functional tests, and damage to the test equipment's circuit boards. In contrast, the testing method of this embodiment, which prevents damage to wafer testing equipment, screens out all abnormal chips, effectively protecting the probe cards and test equipment from damage caused by high currents.

[0048] In summary, this invention provides a testing method to prevent damage to wafer testing equipment, comprising the following steps: Step S1: providing a wafer to be tested, the wafer including multiple chips; Step S2: measuring the power consumption of each measurement item to be tested during functional testing of the chips, and identifying the screening test item, the screening test item being the test item with the highest power consumption; Step S3: testing the dynamic power consumption of the screening test item during operation, screening out chips with abnormal dynamic power consumption, and performing functional testing on chips with normal dynamic power consumption. This invention measures the power consumption of each test item of the chip, determines the test item with the highest power consumption, and measures the dynamic power consumption of all chips for this test item before functional testing. This can screen out chips with abnormal power supply, as well as chips with normal power supply but abnormal operation, that is, screening out all abnormal chips in advance, avoiding problems caused by excessive current during later functional testing, effectively protecting probe cards and testing equipment, improving probe card lifespan, and ensuring product delivery time.

[0049] Furthermore, it should be noted that, unless otherwise specified or indicated, the terms "first" and "second" in the specification are used only to distinguish the various components, elements, steps, etc. in the specification, and are not used to indicate the logical or sequential relationships between the various components, elements, steps, etc.

[0050] It is understood that although the present invention has been disclosed above with reference to preferred embodiments, these embodiments are not intended to limit the present invention. For any person skilled in the art, many possible variations and modifications can be made to the technical solutions of the present invention based on the disclosed technical content, or equivalent embodiments can be modified accordingly, without departing from the scope of the present invention. Therefore, any simple modifications, equivalent changes, and modifications made to the above embodiments based on the technical essence of the present invention without departing from the content of the present invention shall still fall within the protection scope of the present invention.

Claims

1. A testing method for preventing damage to wafer testing equipment, characterized in that, Includes the following steps: Step S1: Provide a wafer to be tested, the wafer to be tested comprising multiple chips; Step S2: Before placing the wafer to be tested on the test machine and performing functional testing, test the power consumption of at least one chip for each measurement item that needs to be tested during functional testing, so as to obtain the power consumption value of each test item in all chips; find the highest power consumption value and the test item with the highest power consumption based on the power consumption value of all test items, thereby finding the screening test items; as well as Step S3: Perform the screening test on all the chips of the wafer to be tested to measure the dynamic power consumption of all the chips during the screening test; determine the abnormal chips based on the dynamic power consumption; and perform functional tests on the chips with normal dynamic power consumption.

2. The testing method for preventing damage to wafer testing equipment as described in claim 1, characterized in that, The wafer to be tested needs to undergo functional testing using wafer testing equipment.

3. The testing method for preventing damage to wafer testing equipment as described in claim 2, characterized in that, The wafer testing equipment includes a testing station and a probe station. The probe station includes a probe card and a main unit that are electrically connected. During electrical measurement, the wafer to be tested is placed on the main unit. The probe card is electrically connected to the wafer to be tested through the probes of the probe card. At the same time, the wafer to be tested is electrically connected to the testing station through the probe card.

4. The testing method for preventing damage to wafer testing equipment as described in claim 1, characterized in that, All of the aforementioned chip arrays are distributed as follows.

5. The test method for preventing damage to wafer testing equipment as described in claim 1, characterized in that, The steps for identifying faulty chips include: The chip whose dynamic power consumption exceeds a preset value is determined to be an abnormal chip; and The chip whose dynamic power consumption is less than the preset value is determined to be a normal chip.

6. The test method for preventing damage to wafer testing equipment as described in claim 1, characterized in that, The functional testing of the chip with normal dynamic power consumption specifically includes: The wafer to be tested is placed on a prober stand and electrically connected to the probe card and the test stand via the probes to perform functional tests on all the normal chips.

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