Low-offset bandgap voltage reference with negative feedback loop offset cancellation

Abstract

The present invention discloses a low-offset bandgap voltage reference with a negative feedback loop offset cancellation mechanism, comprising a fully differential chopping main operational amplifier A1, a single-ended output auxiliary operational amplifier A2, a frequency compensation and low-pass filter module, and a bandgap reference core circuit. This circuit eliminates the offset voltage of the operational amplifier and reduces the gain error of the bandgap reference caused by insufficient operational amplifier gain, thereby significantly improving the accuracy of the bandgap reference output voltage.

Description

Technical Field

[0001] The invention belongs to the technical field of bandgap reference voltage sources, and in particular relates to a low-offset bandgap reference voltage source with a negative feedback loop offset elimination mechanism. Background Art

[0002] A bandgap reference voltage source is a commonly used high-precision reference voltage source in integrated circuits (ICs). It provides a voltage independent of temperature and process variations for other IC circuit modules. The output accuracy and temperature characteristics of a bandgap reference voltage source affect the accuracy of subsequent circuits. The gain error and offset voltage of the operational amplifier in the bandgap reference circuit affect not only the output voltage accuracy but also the temperature characteristics of the bandgap reference output voltage. Therefore, to improve the accuracy and temperature resistance of the bandgap reference voltage source, while also increasing the gain of the operational amplifier and reducing amplifier process fluctuations, thereby reducing the offset voltage, it is necessary to develop a low-offset bandgap reference voltage source with a negative feedback loop offset cancellation mechanism. Summary of the Invention

[0003] The object of the present invention is to provide a low-offset bandgap reference voltage source with a negative feedback loop offset cancellation mechanism, wherein the circuit cancels the offset voltage of an operational amplifier and reduces the gain error caused by insufficient gain of the operational amplifier.

[0004] The technical solution adopted by the present invention is a low-offset bandgap reference voltage source with a negative feedback loop offset elimination mechanism. The bandgap reference voltage source circuit includes a fully differential chopping main operational amplifier A1, a single-ended output auxiliary operational amplifier A2, a frequency compensation and low-pass filter module with the function of eliminating high-frequency offset voltage and noise, and a bandgap reference core circuit.

[0005] The present invention is also characterized in that:

[0006] The bandgap reference core circuit includes P-type MOS tubes MP1 and MP2, PNP bipolar transistors Q1 and Q2, and resistors R1, R2, and R3. The bases and collectors of transistors Q1 and Q2 are connected together, and the collectors of transistors Q1 and Q2 are connected to GND. The emitter of transistor Q1 is connected to the N1 port of the fully differential chopper main operational amplifier A1 and resistor R1 respectively. The other end of resistor R1 is connected to the drain of MOS tube MP1 and V REF port; the emitter of transistor Q2 is connected to resistor R3, the other end of resistor R3 is respectively connected to the P1 port of the fully differential chopper main operational amplifier A1 and resistor R2, the other end of resistor R2 is connected to the drain of MOS tube MP2; the sources of MOS tubes MP1 and MP2 are connected to VDD, and the gates of MOS tubes MP1 and MP2 are connected to the output OUT port of the single-ended output auxiliary operational amplifier A2;

[0007] The fully differential chopper main operational amplifier A1 includes P-type MOS tubes MP3, MP4, MP5, MP6, MP7, MP8, MP9, MP10, MP11, MP12, MP13, MP14, MP15, MP16, N-type MOS tubes MN1, MN2, MN3, MN4, MN5, chopper 1 and chopper 2; the sources of the MOS tubes MP3, MP7, MP8, MP11 and MP12 are connected to VDD, the sources of the MOS tubes MN3, MN4 and MN5 are connected to GND, and the drains of the MOS tubes MP13 and MP16 are connected to GND; the gates of the MOS tubes MP3, MP7, MP8, MP11 and MP12 are connected to bias The gates of MOS tubes MP4, MP9, and MP10 are connected to the bias voltage BIAS2, the gates of MOS tubes MN1 and MN2 are connected to the bias voltage BIAS3, and the gates of MOS tubes MP14 and MP15 are connected to the common mode voltage VCM; the drain of MOS tube MP3 is connected to the source of MOS tube MP4, the drain of MOS tube MP4 is connected to the sources of MOS tubes MP5 and MP6, the gate of MOS tube MP5 is connected to the P1 port after passing through chopper 1, the gate of MOS tube MP6 is connected to the N1 port after passing through chopper 1, the drain of MOS tube MP5 is connected to the drain of MOS tube MN4, and the drain of MOS tube MP6 is connected to the MOS tube The drain of MOS transistor MP7 is connected to the source of MOS transistor MP9, the drain of MOS transistor MP9 is connected to the drain of MOS transistor MN1, the drain of MOS transistor MN1 is connected to the OUT+ port after passing through chopper 2, the source of MOS transistor MN1 is connected to the drain of MOS transistor MN3; the drain of MOS transistor MP8 is connected to the source of MOS transistor MP10, the drain of MOS transistor MP10 is connected to the drain of MOS transistor MN2, the drain of MOS transistor MN2 is connected to the OUT- port after passing through chopper 2, the source of MOS transistor MN2 is connected to the drain of MOS transistor MN4; the drain of MOS transistor MP11 is connected to the sources of MOS transistors MP13 and MP14, The drain of MOS transistor MP12 is connected to the source of MOS transistors MP15 and MP16; the drains of MOS transistors MP14 and MP15 are connected to the drain and gate of MOS transistor MN5; the gates of MOS transistors MP13 and MP16 are connected to the drains of MOS transistors MN1 and MN2, respectively; the gate of MOS transistor MN5 is connected to the gates of MOS transistors MN3 and MN4; the P1 port and N1 port of the fully differential chopper main operational amplifier A1 are connected to the P3 port and N3 port of the single-ended output auxiliary operational amplifier A2, respectively; and the negative output port and positive output port of the fully differential chopper main operational amplifier A1 are connected to the N2 port and P2 port of the single-ended output auxiliary operational amplifier A2, respectively.

[0008] The single-ended output auxiliary operational amplifier A2 includes P-type MOS tubes MP17, MP18, MP19, MP20, MP21, MP22, MP23, MP24, MP25, MP26, and N-type MOS tubes MN6, MN7, MN8, and MN9. The sources of the MOS tubes MP17, MP18, MP21, and MP25 are connected to VDD, and the sources of the MOS tubes MN8 and MN9 are connected to GND. The gates of the MOS tubes MP21 and MP25 are connected to the bias voltage BIAS1, and the gates of the MOS tubes MP20, MP22, and MP26 are connected to Bias voltage BIAS2, the gates of MOS transistors MN6 and MN7 are connected to bias voltage BIAS3, the gates of MOS transistors MP8 and MP9 are connected to bias voltage BIAS4; the drain of MOS transistor MP21 is connected to the source of MP22, the drain of MOS transistor MP22 is connected to the sources of MOS transistors MP23 and MP24, the gate of MOS transistor MP23 is connected to the P3 port, the gate of MOS transistor MP24 is connected to the PN port, the drain of MOS transistor MP23 is connected to the drain of MOS transistor MN8, the drain of MOS transistor MP24 is connected to the MOS transistor MN9 The drain of MOS tube MP17 is connected to the source of MP19, the drain of MOS tube MP19 is connected to the drain of MOS tube MN6, the gate of MOS tube MP17 is connected to the drain of MOS tube MN6, the source of MOS tube MN6 is connected to the drain of MOS tube MN8; the drain of MOS tube MP18 is connected to the source of MP20, the drain of MOS tube MP20 is connected to the drain of MOS tube MN7 and the OUT output port, the source of MOS tube MN7 is connected to the drain of MN9; the drain of MOS tube MP25 is connected to the source of MP26, MOS The drain of MOS tube MP26 is connected to the source of MP27 and the source of MP28, the gate of MOS tube MP27 is connected to the N2 port, the gate of MOS tube MP28 is connected to the P2 port, the drain of MOS tube MP27 is connected to the drain of MN9, and the drain of MOS tube MP28 is connected to the drain of MN8; the N2 port and P2 port of the single-ended output auxiliary operational amplifier A2 are respectively connected to the CN port and CP port of the frequency compensation and low-pass filter module, and the OUT output port of the single-ended output auxiliary operational amplifier A2 is connected to the COUT port of the frequency compensation and low-pass filter module;

[0009] The single frequency compensation and low-pass filter module includes capacitors C1, C2, and C3; one end of capacitor C1 is connected to the CP port, and the other end is connected to GND; one end of capacitor C2 is connected to the CN port, and the other end is connected to GND; one end of capacitor C3 is connected to the CN port, and the other end is connected to the COUT port;

[0010] The beneficial effect of the present invention is to provide a low-offset bandgap reference voltage source with a negative feedback loop offset cancellation mechanism. Compared with the prior art, it has the following advantages:

[0011] (1) The circuit adopts a dual op amp cascade structure, which increases the gain of the feedback loop and reduces the gain error of the feedback loop.

[0012] (2) The offset voltage of the fully differential chopper main operational amplifier A1 is eliminated by using chopping technology.

[0013] (3) The offset voltage of operational amplifier A2 is greatly reduced by utilizing the negative feedback loop offset elimination mechanism.

[0014] (4) The frequency compensation and low-pass filter module used in the circuit can not only eliminate high-frequency offset voltage and noise with a low-pass filter structure, but also form a feedforward Miller compensation structure with the P3 and N3 ports of the single-ended output auxiliary operational amplifier A2 to ensure the stability of the feedback loop. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 The present invention is a circuit diagram of a low-offset bandgap reference voltage source with a negative feedback loop offset elimination mechanism;

[0016] Figure 2 is a circuit diagram of the fully differential chopping main operational amplifier A1 of the present invention;

[0017] Figure 3 1 is a circuit diagram of a single-ended output auxiliary operational amplifier A2 of the present invention;

[0018] Figure 4 is a circuit diagram of the frequency compensation and low-pass filter module of the present invention;

[0019] Figure 5 It is a diagram illustrating the negative feedback loop imbalance elimination mechanism of the present invention. DETAILED DESCRIPTION

[0020] The present invention will be described in detail below with reference to the accompanying drawings and specific embodiments.

[0021] The circuit structure of the low offset bandgap reference voltage source with negative feedback loop offset elimination mechanism of the present invention is as follows: Figure 1 As shown,

[0022] The bandgap reference voltage source circuit includes a fully differential chopping main operational amplifier A1, a single-ended output auxiliary operational amplifier A2, a frequency compensation and low-pass filter module, and a bandgap reference core circuit.

[0023] Bandgap reference core circuit such as Figure 1As shown, it includes P-type MOS tubes MP1 and MP2, PNP bipolar transistors Q1 and Q2, and resistors R1, R2, and R3; the bases and collectors of transistors Q1 and Q2 are connected together, and the collectors of transistors Q1 and Q2 are connected to GND; the emitter of transistor Q1 is connected to the N1 port of the full-differential chopper main operational amplifier A1 and the resistor R1 respectively, and the other end of the resistor R1 is connected to the drain of the MOS tube MP1 and V REF port; the emitter of transistor Q2 is connected to resistor R3, the other end of resistor R3 is respectively connected to the P1 port of the fully differential chopper main operational amplifier A1 and resistor R2, the other end of resistor R2 is connected to the drain of MOS tube MP2; the sources of MOS tubes MP1 and MP2 are connected to VDD, and the gates of MOS tubes MP1 and MP2 are connected to the output OUT port of the single-ended output auxiliary operational amplifier A2;

[0024] The fully differential chopper main operational amplifier A1 is as follows Figure 2As shown, it includes P-type MOS tubes MP3, MP4, MP5, MP6, MP7, MP8, MP9, MP10, MP11, MP12, MP13, MP14, MP15, MP16, N-type MOS tubes MN1, MN2, MN3, MN4, MN5, chopper 1 and chopper 2; the source electrodes of the MOS tubes MP3, MP7, MP8, MP11 and MP12 are connected to VDD, the source electrodes of the MOS tubes MN3, MN4 and MN5 are connected to GND, and the drain electrodes of the MOS tubes MP13 and MP16 are connected to GND; the gate electrodes of the MOS tubes MP3, MP7, MP8, MP11 and MP12 are connected to the bias voltage BIAS 1. The gates of MOS transistors MP4, MP9, and MP10 are connected to the bias voltage BIAS2, the gates of MOS transistors MN1 and MN2 are connected to the bias voltage BIAS3, and the gates of MOS transistors MP14 and MP15 are connected to the common mode voltage VCM; the drain of MOS transistor MP3 is connected to the source of MOS transistor MP4, the drain of MOS transistor MP4 is connected to the sources of MOS transistors MP5 and MP6, the gate of MOS transistor MP5 is connected to the P1 port after passing through chopper 1, the gate of MOS transistor MP6 is connected to the N1 port after passing through chopper 1, the drain of MOS transistor MP5 is connected to the drain of MOS transistor MN4, and the drain of MOS transistor MP6 is connected to the drain of MOS transistor MN3. The drain of MOS tube MP7 is connected to the source of MOS tube MP9, the drain of MOS tube MP9 is connected to the drain of MOS tube MN1, the drain of MOS tube MN1 is connected to the OUT+ port after passing through chopper 2, the source of MOS tube MN1 is connected to the drain of MOS tube MN3; the drain of MOS tube MP8 is connected to the source of MOS tube MP10, the drain of MOS tube MP10 is connected to the drain of MOS tube MN2, the drain of MOS tube MN2 is connected to the OUT- port after passing through chopper 2, the source of MOS tube MN2 is connected to the drain of MOS tube MN4; the drain of MOS tube MP11 is connected to the sources of MOS tubes MP13 and MP14, MO The drain of S transistor MP12 is connected to the source of MOS transistors MP15 and MP16; the drains of MOS transistors MP14 and MP15 are connected to the drain and gate of MOS transistor MN5; the gates of MOS transistors MP13 and MP16 are connected to the drains of MOS transistors MN1 and MN2, respectively; the gate of MOS transistor MN5 is connected to the gates of MOS transistors MN3 and MN4; the P1 port and N1 port of the fully differential chopper main operational amplifier A1 are connected to the P3 port and N3 port of the single-ended output auxiliary operational amplifier A2, respectively; the negative output port and positive output port of the fully differential chopper main operational amplifier A1 are connected to the N2 port and P2 port of the single-ended output auxiliary operational amplifier A2, respectively;

[0025] The single-ended output auxiliary operational amplifier A2 is as follows Figure 3As shown, it includes P-type MOS transistors MP17, MP18, MP19, MP20, MP21, MP22, MP23, MP24, MP25, and MP26, and N-type MOS transistors MN6, MN7, MN8, and MN9; the sources of the MOS transistors MP17, MP18, MP21, and MP25 are connected to VDD, and the sources of the MOS transistors MN8 and MN9 are connected to GND; the gates of the MOS transistors MP21 and MP25 are connected to the bias voltage BIAS1, and the gates of the MOS transistors MP20, MP22, and MP26 are connected to the bias voltage BIA S2, the gates of MOS transistors MN6 and MN7 are connected to bias voltage BIAS3, and the gates of MOS transistors MP8 and MP9 are connected to bias voltage BIAS4; the drain of MOS transistor MP21 is connected to the source of MP22, the drain of MOS transistor MP22 is connected to the sources of MOS transistors MP23 and MP24, the gate of MOS transistor MP23 is connected to the P3 port, the gate of MOS transistor MP24 is connected to the PN port, the drain of MOS transistor MP23 is connected to the drain of MOS transistor MN8, and the drain of MOS transistor MP24 is connected to the drain of MOS transistor MN9 The drain of MOS transistor MP17 is connected to the source of MP19, the drain of MOS transistor MP19 is connected to the drain of MOS transistor MN6, the gate of MOS transistor MP17 is connected to the drain of MOS transistor MN6, the source of MOS transistor MN6 is connected to the drain of MOS transistor MN8; the drain of MOS transistor MP18 is connected to the source of MP20, the drain of MOS transistor MP20 is connected to the drain of MOS transistor MN7 and the OUT output port, the source of MOS transistor MN7 is connected to the drain of MN9; the drain of MOS transistor MP25 is connected to the source of MP26, and the gate of MOS transistor MP The drain of 26 is connected to the source of MP27 and the source of MP28, the gate of MOS tube MP27 is connected to the N2 port, the gate of MOS tube MP28 is connected to the P2 port, the drain of MOS tube MP27 is connected to the drain of MN9, and the drain of MOS tube MP28 is connected to the drain of MN8; the N2 port and P2 port of the single-ended output auxiliary operational amplifier A2 are respectively connected to the CN port and CP port of the frequency compensation and low-pass filter module, and the OUT output port of the single-ended output auxiliary operational amplifier A2 is connected to the COUT port of the frequency compensation and low-pass filter module;

[0026] Frequency compensation and low-pass filter modules such as Figure 4 As shown, it includes capacitors C1, C2 and C3; one end of capacitor C1 is connected to the CP port, and the other end is connected to GND; one end of capacitor C2 is connected to the CN port, and the other end is connected to GND; one end of capacitor C3 is connected to the CN port, and the other end is connected to the COUT port;

[0027] The fully differential chopper main operational amplifier A1 detects the potential at the lower end of the resistor R1 and the potential error at the lower end of the resistor R2, and finally feeds back to the gates of the MOS tubes MP1 and MP2 through the single-ended output auxiliary operational amplifier A2. Through the negative feedback mechanism, a current proportional to the temperature is generated on the main branches R1 and R2 of the bandgap reference core circuit. REF The zero temperature coefficient reference voltage of the port is equal to the sum of the positive temperature coefficient voltage on R1 and the negative temperature coefficient voltage on the PNP bipolar transistor Q1. Since two operational amplifiers are cascaded in the negative feedback loop, the loop gain of the negative feedback loop is greatly improved, and the gain error of the bandgap reference voltage source caused by insufficient gain of the operational amplifier is reduced.

[0028] Chopper 1 of the fully differential chopper main operational amplifier A1 modulates the input signal and the low-frequency offset voltage and noise in A1 to a high frequency. Chopper 2 at the output end of A1 only demodulates the input signal. Finally, the high-frequency offset voltage and noise are filtered out through the frequency compensation and low-pass filtering of the low-pass filter module. Finally, the offset voltage and low-frequency noise of the fully differential chopper main operational amplifier A1 are eliminated.

[0029] The diagram below illustrates the mechanism of eliminating the negative feedback loop offset. Figure 5 As shown, the offset voltage of the single-ended output auxiliary operational amplifier A2 is equivalent to V at the input of A2. OS_A2 , the gain of the main operational amplifier A1 is A V1 , since both operational amplifiers A1 and A2 are in a negative feedback loop, we can get V OS_A2 The offset voltage generated at the input of A1 is V OS_A2 / A V1 , and finally the offset voltage of A2 is V OS_A2 The reference output voltage V REF The error generated by the port is V OS_A2 / (A V1 · R3) · (R3 + R2), because the gain of the main operational amplifier A1 is A V1 Therefore, the negative feedback loop offset cancellation mechanism greatly reduces the impact of the offset voltage of operational amplifier A2 on the bandgap reference output voltage.

[0030] Capacitor C3 in the frequency compensation and low-pass filter module and the P3 and N3 input terminals of operational amplifier A2 also establish a large capacitance at the negative output terminal of A1 using the feedforward Miller compensation mechanism. At the same time, due to the large capacitance of capacitors C1 and C2 in the frequency compensation and low-pass filter module, the output pole of the main operational amplifier A1 is ultimately pushed to an extremely low frequency, thereby ensuring the stability of the entire negative feedback loop.

Claims

1. A low-offset bandgap voltage reference with a negative feedback loop offset cancellation mechanism, characterized in that: The circuit of the bandgap reference voltage source includes a fully differential chopping main operational amplifier A1, a single-ended output auxiliary operational amplifier A2, a frequency compensation and low-pass filter module capable of eliminating high-frequency offset voltage and noise, and a bandgap reference core circuit; The bandgap reference core circuit includes P-type MOS transistors MP1 and MP2, PNP bipolar transistors Q1 and Q2, and resistors R1, R2, and R3. The bases and collectors of the transistors Q1 and Q2 are connected together, and the collectors of the transistors Q1 and Q2 are connected to GND. The emitter of the transistor Q1 is connected to the N1 port of the fully differential chopper main operational amplifier A1 and one end of the resistor R1, respectively. The other end of the resistor R1 is connected to the drain of the MOS transistor MP1 and V REF port; the emitter of the transistor Q2 is connected to the resistor R3, the other end of the resistor R3 is respectively connected to the P1 port of the fully differential chopper main operational amplifier A1 and the resistor R2, and the other end of the resistor R2 is connected to the drain of the MOS transistor MP2; the sources of the MOS transistors MP1 and MP2 are connected to VDD, and the gates of the MOS transistors MP1 and MP2 are connected to the OUT output port of the single-ended output auxiliary operational amplifier A2; The fully differential chopper main operational amplifier A1 includes P-type MOS tubes MP3, MP4, MP5, MP6, MP7, MP8, MP9, MP10, MP11, MP12, MP13, MP14, MP15, MP16, N-type MOS tubes MN1, MN2, MN3, MN4, MN5, chopper 1 and chopper 2; the sources of the MOS tubes MP3, MP7, MP8, MP11 and MP12 are connected to VDD, the sources of the MOS tubes MN3, MN4 and MN5 are connected to GND, and the drains of the MOS tubes MP13 and MP16 are connected to GND; the MOS tubes MP3, MP7, MP8, The gates of MP11 and MP12 are connected to the bias voltage BIAS1, the gates of the MOS transistors MP4, MP9, and MP10 are connected to the bias voltage BIAS2, the gates of the MOS transistors MN1 and MN2 are connected to the bias voltage BIAS3, and the gates of the MOS transistors MP14 and MP15 are connected to the common mode voltage VCM; the drain of the MOS transistor MP3 is connected to the source of the MOS transistor MP4, the drain of the MOS transistor MP4 is connected to the sources of the MOS transistors MP5 and MP6, the gate of the MOS transistor MP5 is connected to the P1 port after passing through the chopper 1, and the gate of the MOS transistor MP6 is connected to the N1 port after passing through the chopper 1. The drain of the MOS transistor MP5 is connected to the drain of the MOS transistor MN4, the drain of the MOS transistor MP6 is connected to the drain of the MOS transistor MN3; the drain of the MOS transistor MP7 is connected to the source of the MOS transistor MP9, the drain of the MOS transistor MP9 is connected to the drain of the MOS transistor MN1, the drain of the MOS transistor MN1 is connected to the positive output port after passing through the chopper 2, the source of the MOS transistor MN1 is connected to the drain of the MOS transistor MN3; the drain of the MOS transistor MP8 is connected to the source of the MOS transistor MP10, the drain of the MOS transistor MP10 is connected to the drain of the MOS transistor MN2, and the MOS transistors are connected to the positive output port. The drain of the S transistor MN2 is connected to the negative output port after passing through the chopper 2. The source of the MOS transistor MN2 is connected to the drain of the MOS transistor MN4. The drain of the MOS transistor MP11 is connected to the sources of the MOS transistors MP13 and MP14. The drain of the MOS transistor MP12 is connected to the sources of the MOS transistors MP15 and MP16. The drains of the MOS transistors MP14 and MP15 are connected to the drain and gate of the MOS transistor MN5. The gates of the MOS transistors MP13 and MP16 are connected to the drains of the MOS transistors MN1 and MN2, respectively. The gate of the MOS transistor MN5 is connected to the gates of the MOS transistors MN3 and MN4.The P1 port and N1 port of the fully differential chopping main operational amplifier A1 are respectively connected to the P3 port and N3 port of the single-ended output auxiliary operational amplifier A2, and the negative output port and positive output port of the fully differential chopping main operational amplifier A1 are respectively connected to the N2 port and P2 port of the single-ended output auxiliary operational amplifier A2; The single-ended output auxiliary operational amplifier A2 includes P-type MOS transistors MP17, MP18, MP19, MP20, MP21, MP22, MP23, MP24, MP25, and MP26, and N-type MOS transistors MN6, MN7, MN8, and MN9; the sources of the MOS transistors MP17, MP18, MP21, and MP25 are connected to VDD, and the sources of the MOS transistors MN8 and MN9 are connected to GND; the gates of the MOS transistors MP21 and MP25 are connected to the bias voltage BIAS1, and the gates of the MOS transistors MP20, MP22, and MP26 are connected to the bias voltage BIAS2. The gates of the MOS transistors MN6 and MN7 are connected to the bias voltage BIAS3, and the gates of the MOS transistors MN8 and MN9 are connected to the bias voltage BIAS4; the drain of the MOS transistor MP21 is connected to the source of MP22, the drain of the MOS transistor MP22 is connected to the sources of the MOS transistors MP23 and MP24, the gate of the MOS transistor MP23 is connected to the P3 port, the gate of the MOS transistor MP24 is connected to the N3 port, the drain of the MOS transistor MP23 is connected to the drain of the MOS transistor MN8, and the drain of the MOS transistor MP24 is connected to the drain of the MOS transistor MN9; the M The drain of the OS transistor MP17 is connected to the source of MP19, the drain of the MOS transistor MP19 is connected to the drain of the MOS transistor MN6, the gate of the MOS transistor MP17 is connected to the drain of the MOS transistor MN6, the source of the MOS transistor MN6 is connected to the drain of the MOS transistor MN8; the drain of the MOS transistor MP18 is connected to the source of MP20, the drain of the MOS transistor MP20 is connected to the drain of the MOS transistor MN7 and the OUT output port, the source of the MOS transistor MN7 is connected to the drain of MN9; the drain of the MOS transistor MP25 is connected to the source of MP26, the MOS transistor MP2 The drain of the MOS transistor MP6 is connected to the source of the MOS transistor MP27 and the source of the MOS transistor MP28, the gate of the MOS transistor MP27 is connected to the N2 port, the gate of the MOS transistor MP28 is connected to the P2 port, the drain of the MOS transistor MP27 is connected to the drain of MN9, and the drain of the MOS transistor MP28 is connected to the drain of MN8; the N2 port and the P2 port of the single-ended output auxiliary operational amplifier A2 are respectively connected to the CN port and the CP port of the frequency compensation and low-pass filter module, and the OUT output port of the single-ended output auxiliary operational amplifier A2 is connected to the COUT port of the frequency compensation and low-pass filter module.

2. The low-offset bandgap reference voltage source with a negative feedback loop offset cancellation mechanism according to claim 1, wherein: The frequency compensation and low-pass filter include capacitors C1, C2 and C3; one end of the capacitor C1 is connected to the CP port and the other end is connected to GND; one end of the capacitor C2 is connected to the CN port and the other end is connected to GND; one end of the capacitor C3 is connected to the CN port and the other end is connected to the COUT port.

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