Watchdog control system and control method

Abstract

The present invention provides a watchdog control system and a control method. The system includes a watchdog circuit, a single-chip microcomputer, and a processor. The watchdog circuit includes a counter and a control element. The counter includes a first counting pulse output terminal, a second counting pulse output terminal, and a first reset input terminal. The processor includes a first dog-feeding signal output terminal and a second reset input terminal. The single-chip microcomputer includes a second dog-feeding signal output terminal and a third reset input terminal. The first dog-feeding signal output terminal is connected to the control element. The control element is respectively connected to the first counting pulse output terminal and the first reset input terminal. The second dog-feeding signal output terminal is connected to the first reset input terminal. The second counting pulse output terminal is connected to the third reset input terminal. The third reset input terminal is connected to the second reset input terminal. The present invention realizes that even when the single-chip microcomputer is abnormal, it can be reset by the processor, endowing the control system with multiple guarantees and improving the effectiveness of the counter reset control.

Description

Technical Field

[0001] The present invention relates to the field of computer technology, and in particular to a watchdog control system and a control method. Background Art

[0002] During the process of electronic circuit design, due to its own reasons or external interference factors, the server has a certain probability of program runaway and jamming, resulting in the downtime of the server and incalculable losses. At this time, it is necessary for the server to be able to automatically correct errors and restart the server to ensure the normal operation of the server.

[0003] In the prior art, some scholars use BMC (Baseboard Management Controller) to monitor and reset the CPU (Central Processing Unit); however, with the development of edge scenarios, servers are increasingly applied to edge scenarios. Such servers are sensitive to cost requirements, while the cost of BMC is very high. To reduce costs, some related scholars use MCU (Micro Control Unit) to replace BMC and add a watchdog chip. The specific structure is as Figure 1 shown.

[0004] In this structure, the MCU is respectively connected to the CPU and the watchdog chip, and can implement functions such as the power-on timing sequence of the entire server system, voltage and current monitoring, and fan control, and can realize the reset of the CPU through the reset signal sent by the watchdog chip, thereby realizing the reset control of the entire server system. When the MCU crashes, the reset control function of the server system cannot be realized, resulting in poor control reliability. Summary of the Invention

[0005] The present invention provides a watchdog control system and a control method to solve the defect in the prior art that when the MCU crashes, the reset control function of the server system cannot be realized, resulting in poor control reliability, and to improve the control reliability of the server system.

[0006] The present invention provides a watchdog control system, including a watchdog circuit, a single-chip microcomputer, and a processor;

[0007] The watchdog circuit includes a counter and a control element;

[0008] The counter includes a first counting pulse output terminal, a second counting pulse output terminal, and a first reset input terminal. The processor includes a first dog feeding signal output terminal and a second reset input terminal. The single-chip microcomputer includes a second dog feeding signal output terminal and a third reset input terminal;

[0009] The first dog feeding signal output terminal is connected to the control element, and the control element is respectively connected to the first counting pulse output terminal and the first reset input terminal;

[0010] The second dog feeding signal output terminal is connected to the first reset input terminal, the second counting pulse output terminal is connected to the third reset input terminal, and the third reset input terminal is connected to the second reset input terminal;

[0011] Wherein, the processor is used to output a first dog feeding signal through the first dog feeding signal output terminal, and the control element is used to determine the input signal of the first reset input terminal according to the first dog feeding signal and the pulse signal output from the first counting pulse output terminal;

[0012] The single-chip microcomputer is used to output a second dog feeding signal through the second dog feeding signal output terminal;

[0013] The counter is used to determine a reset signal according to the input signal and the second dog feeding signal, and output the reset signal to the third reset input terminal through the second counting pulse output terminal to perform reset control on the single-chip microcomputer, and / or transmit the reset signal to the second reset input terminal through the third reset input terminal to perform reset control on the processor.

[0014] According to a watchdog control system provided by the present invention, the control element includes a field effect transistor;

[0015] The gate of the field effect transistor is connected to the first dog feeding signal output terminal, the drain of the field effect transistor is respectively connected to the first counting pulse output terminal and the first reset input terminal, and the source of the field effect transistor is connected to a grounding device;

[0016] When the first dog feeding signal is output from the first dog feeding signal output terminal, the field effect transistor is in an off state, and the field effect transistor is used to control the connection between the first counting pulse output terminal and the first reset input terminal, and input the input signal determined according to the pulse signal output from the first counting pulse output terminal to the first reset input terminal;

[0017] When the first dog feeding signal is not output from the first dog feeding signal output terminal, the field effect transistor is in an on state, and the field effect transistor is used to control both the first counting pulse output terminal and the first reset input terminal to be connected to the grounding device.

[0018] According to a watchdog control system provided by the present invention, the watchdog circuit further includes a pull-up resistor;

[0019] The first end of the pull-up resistor is connected to the gate of the field effect transistor, and the second end of the pull-up resistor is connected to the power supply of the processor;

[0020] When the first watchdog signal is output at the first watchdog signal output end, the pull-up resistor is used to pull down the level signal of the gate, so that the field effect transistor is in an off state;

[0021] When the first watchdog signal is not output at the first watchdog signal output end, the pull-up resistor is used to pull up the level signal of the gate, so that the field effect transistor is in a conducting state.

[0022] According to a watchdog control system provided by the present invention, the watchdog circuit further includes a first capacitor;

[0023] The first end of the first capacitor is connected to the gate of the field effect transistor, and the second end of the first capacitor is connected to the first watchdog signal output end;

[0024] The first capacitor is used to transmit the AC signal in the first watchdog signal to the gate of the field effect transistor.

[0025] According to a watchdog control system provided by the present invention, the watchdog circuit further includes a second capacitor;

[0026] The first end of the second capacitor is connected to the first counting pulse output end, and the second end of the second capacitor is respectively connected to the drain of the field effect transistor and the first reset input end;

[0027] The second capacitor is used to transmit the AC signal in the pulse signal output from the first counting pulse output end to the drain of the field effect transistor, and / or transmit the AC signal in the pulse signal output from the first counting pulse output end to the first reset input end.

[0028] According to a watchdog control system provided by the present invention, the watchdog circuit further includes a third capacitor and a fourth capacitor;

[0029] The first end of the third capacitor is connected to the first counting pulse output end, the second end of the third capacitor is connected to the first reset input end, and the third capacitor is used to transmit the AC signal in the pulse signal output from the first counting pulse output end to the first reset input end;

[0030] The first end of the fourth capacitor is connected to the first reset input end, and the second end of the fourth capacitor is connected to the second watchdog signal output end. The fourth capacitor is used to transmit the AC signal in the second watchdog signal to the first reset input end.

[0031] A watchdog control system provided by the present invention, the counter further includes a plurality of third counting pulse output terminals;

[0032] The plurality of third counting pulse output terminals are the counting pulse output terminals in the counter except the first counting pulse output terminal and the second counting pulse output terminal;

[0033] The third counting pulse output terminal is connected to the input / output interface of the processor;

[0034] The processor is used to determine the dog feeding state of the single-chip microcomputer according to the pulse signal output by the third counting pulse output terminal; the dog feeding state includes normal dog feeding or abnormal dog feeding.

[0035] A watchdog control system provided by the present invention, the counter further includes a fourth counting pulse output terminal;

[0036] The fourth counting pulse output terminal is obtained by selecting from the plurality of third counting pulse output terminals according to the control requirements of the watchdog control system;

[0037] When the single-chip microcomputer is in the abnormal dog feeding state, the fourth counting pulse output terminal is connected to the interrupt pin of the processor. When the pulse signal output by the fourth counting pulse output terminal is the target signal, the processor executes the interrupt task;

[0038] The interrupt task includes reading the counting state of the counter, calculating the reset trigger time according to the counting state, and when the current time meets the reset trigger time, outputting the first dog feeding signal through the first dog feeding signal output terminal, recording the working log of the processor, and obtaining one or more of the fault logs of the single-chip microcomputer.

[0039] A watchdog control system provided by the present invention, the watchdog circuit further includes a voltage stabilizing component;

[0040] The first end of the voltage stabilizing component is respectively connected to the second dog feeding signal output terminal and the first reset input terminal, and the second end of the voltage stabilizing component is connected to the grounding device;

[0041] The voltage stabilizing component includes a voltage stabilizing diode and a resistor, and the voltage stabilizing diode and the resistor are connected;

[0042] The voltage stabilizing component is used to protect the counter through the voltage stabilizing diode and the resistor.

[0043] A watchdog control system provided by the present invention, the counter further includes a clock pulse input terminal, a first clock pulse output terminal, a second clock pulse output terminal and a clock generator;

[0044] The clock generator includes a first resistor, a second resistor, and a fifth capacitor;

[0045] A first end of the first resistor is connected to the clock pulse input terminal, a first end of the second resistor is connected to the first clock pulse output terminal, a first end of the fifth capacitor is connected to the second clock pulse output terminal, and a second end of the first resistor is respectively connected to a second end of the second resistor and a second end of the fifth capacitor.

[0046] The present invention further provides a control method for a watchdog control system, including: determining an input signal of a first reset input terminal of the counter according to a first watchdog signal output from a first watchdog signal output terminal of a processor and a pulse signal output from a first counting pulse output terminal of the counter;

[0047] Determining a reset signal according to the input signal and a second watchdog signal output from a second watchdog signal output terminal of a single-chip microcomputer;

[0048] Outputting the reset signal to the third reset input terminal through the second counting pulse output terminal to perform a reset control on the single-chip microcomputer, and / or transmitting the reset signal to the second reset input terminal through the third reset input terminal to perform a reset control on the processor.

[0049] The watchdog control system and control method provided by the present invention determine an input signal of a first reset input terminal of a counter according to a first watchdog signal output from a first watchdog signal output terminal of a processor and a pulse signal output from a first counting pulse output terminal of the counter; then determine a reset signal according to the input signal and a second watchdog signal output from a second watchdog signal output terminal of a single-chip microcomputer; and finally output the reset signal to a third reset input terminal through a second counting pulse output terminal to perform a reset on the single-chip microcomputer, and / or transmit the reset signal to a second reset input terminal through the third reset input terminal to perform a reset control on the processor, so as to realize a reset control on the single-chip microcomputer and / or the processor; meanwhile, a control element is added to control a conduction state of a circuit between the counter and the processor, so that even when the single-chip microcomputer is abnormal, the processor can be reset, endowing the control system with multiple guarantees and improving the effectiveness of the counter reset control. Description of the Drawings

[0050] In order to more clearly illustrate the technical solutions in the present invention or the prior art, the following will briefly introduce the drawings required for use in the description of the embodiments or the prior art. Obviously, the drawings in the following description are some embodiments of the present invention. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0051] Figure 1 is one of the schematic structural diagrams of the watchdog control system provided by the prior art;

[0052] Figure 2 is another schematic structural diagram of the watchdog control system provided by the prior art;

[0053] Figure 3 is the schematic structural diagram of the watchdog control system provided by the present invention;

[0054] Figure 4 is the timing diagram of the counter in the watchdog control system provided by the present invention;

[0055] Figure 5 is the circuit diagram of the watchdog circuit in the watchdog control system provided by the present invention;

[0056] Figure 6 is the schematic flow diagram of the control method of the watchdog control system provided by the present invention.

[0057] Reference numerals:

[0058] 301: Counter; 302: Control element; 303: Processor; 304: Single-chip microcomputer. Detailed implementation manners

[0059] To make the objectives, technical solutions and advantages of the present invention clearer, the technical solutions in the present invention will be clearly and completely described below with reference to the accompanying drawings in the present invention. Apparently, the described embodiments are some but not all of the embodiments of the present invention. All other embodiments obtained by those of ordinary skill in the art based on the embodiments in the present invention without making creative efforts shall fall within the protection scope of the present invention.

[0060] Generally, the server uses BMC to monitor and reset the CPU, and the specific architecture is as Figure 2 shown. The state of the CPU is monitored by BMC, and BMC performs the overall machine operation and maintenance externally through the management interface. When the CPU crashes, BMC collects the error information of the CPU, notifies the operation and maintenance personnel, and the operation and maintenance personnel confirm the fault phenomenon, collect logs, perform fault diagnosis, and then reset the CPU after there is no problem.

[0061] However, with the development of edge scenarios, servers are increasingly applied to edge scenarios. Such servers are sensitive to cost requirements, while the cost of BMC is very high. In view of this situation, relevant enterprises are all launching solutions without BMC and using MCU to replace the functions of BMC. At this time, MCU not only needs to implement some functions of BMC, but also must ensure its own reliability. Similarly, it is particularly important to satisfy that when an abnormal reset occurs, the CPU performs fault recording work.

[0062] However, this existing technology cannot meet the current application requirements. Specifically, the microcontroller (i.e., MCU) controls the power supply switch and power-on timing of the CPU and detects the working state of the CPU. If the microcontroller malfunctions and resets suddenly, the CPU does not have enough time to record logs, and it is also impossible to determine that the fault is caused by the MCU, which is not conducive to later maintenance. At the same time, after a failure occurs in the server field, it is necessary to maintain the scene for the operation and maintenance personnel to diagnose the fault phenomenon.

[0063] In addition, in some existing technologies, a CPLD (Complex Programmable Logic Device) is used to implement the reset control of the server. However, this control method makes the interaction complex, similar to the reset method of CPU + MCU. If the CPLD or MCU freezes, the entire system cannot be reset, just like the reset control scheme using the MCU to replace the BMC. Moreover, the reliability of the MCU and CPLD is lower than that of a simple counter.

[0064] In another part of the existing technologies, VHDL (Very High Speed Integrated Circuit Hardware Description Language) is used to implement the reset control, and the above-mentioned problems still exist. It still corresponds to a single master control. When applied to specific server fields, the CPLD or microcontroller cannot be removed, and the reliability of the microcontroller or CPLD cannot be guaranteed. Moreover, its watchdog circuit and counter circuit are separated. The watchdog counter requires a clock, and after notifying the CPU, it resets the circuit after counting 3 times, which cannot meet the requirements of troubleshooting and operation and maintenance for a long time. And introducing a clock also poses a reliability problem, and the control system is also slightly complex, resulting in a higher cost.

[0065] As Figure 1 shown in the architecture block diagram of MCU + CPU, the biggest difference between it and the BMC is that the MCU has weak functions and no external maintenance interface. It needs to communicate with the outside through the communication interface with the CPU and utilize the functions of the CPU to communicate with the outside. The MCU completes functions such as the power-on timing of the entire system, voltage and current monitoring, and fan control. At this time, if the MCU cannot feed the dog for various reasons, it will cause the watchdog to be unable to reset the MCU. Since the MCU controls the power-on timing of the CPU, the entire system cannot be reset. In addition, for the watchdog implemented by using devices such as CPLD or microcontroller, there are more CPLD or microcontroller in the solution. When the microcontroller or CPLD of the watchdog freezes, a new fault mode will be introduced, making the entire system even more complex and unable to effectively solve the problem.

[0066] In the classic circuit composed of a CPU, a microcontroller, and a watchdog, usually the microcontroller monitors the CPU, and the watchdog monitors the microcontroller. More comprehensively, the watchdog can notify the CPU in advance through a counter that the watchdog is about to reset. When the following situation occurs: the CPU is normal, the microcontroller crashes, and the watchdog works normally. At this time, the watchdog notifies the CPU to reset the microcontroller. The CPU prepares for the reset, but the microcontroller may not be able to be reset. Even if it can be reset, the CPU cannot save the on-site state in such a process and cannot wait for the debugging or operation and maintenance personnel to locate and solve the problem.

[0067] Therefore, in the prior art, when the MCU crashes, the reset control function of the server system cannot be realized, which leads to poor control reliability. The prior art cannot solve this situation, or new CPLD or microcontroller needs to be introduced to solve this problem, but this will increase the control cost. In view of the above problems, this embodiment provides a watchdog control system to improve the control reliability of the server system while reducing the control cost. The following will be combined with Figure 3 Describe the watchdog control system of the present invention.

[0068] As Figure 3 shown, it is a schematic structural diagram of the watchdog control system provided by this embodiment. The watchdog control system includes: a counter 301, a control element 302, a processor 303, and a microcontroller 304, where:

[0069] The watchdog circuit includes a counter 301 and a control element 302;

[0070] Among them, the counter 301 can be an MC74HC4060 chip, which is composed of 14 master-slave flip-flops and an oscillator. The output of each flip-flop is fed to the next flip-flop, and the frequency of each output is half of the previous output.

[0071] Optionally, the frequency of the oscillator can be controlled by a crystal oscillator or an externally connected RC circuit. This embodiment does not make specific limitations on this.

[0072] Among them, the control element 302 mainly functions to control the conduction state of the line between the counter 301 and the processor 303 in the system.

[0073] The processor can be the CPU in the edge server, and the microcontroller can be the MCU.

[0074] The counter 301 includes a first counting pulse output terminal, a second counting pulse output terminal, and a first reset input terminal. The processor 303 includes a first dog feeding signal output terminal and a second reset input terminal. The microcontroller 304 includes a second dog feeding signal output terminal and a third reset input terminal;

[0075] Among them, the counter includes multiple pins, specifically including multiple counting pulse output terminals, a reset input terminal, a clock pulse input terminal, and a clock pulse output terminal. As Figure 4 shown in the timing diagram of each pin of the counter 301, where RS is the first reset input terminal, MR is the counting state of the counter, and Q3 to Q13 are all counting pulse output terminals. The pulse timing changes of different counting pulse output terminals and the reset input terminal are different in different oscillation periods.

[0076] Optionally, the first counting pulse output terminal of the counter 301 is used to cooperate with the first watchdog signal output terminal to input a reset signal to the reset input terminal of the counter at an appropriate time, so as to trigger the counter to perform reset control on the processor and / or the single-chip microcomputer. The first counting pulse output terminal can be selected and set among the Q4-Q14 pins of the counter 301 according to the reset control requirements. Specifically, the setting of the first counting pulse output terminal can first determine the reset period according to the reset requirements of the watchdog control system, and then determine the corresponding first counting pulse output terminal according to the reset period. This embodiment does not make specific limitations on this. Exemplarily, in this embodiment, the Q13 pin with a longer time period can be selected as the first counting pulse output terminal of the counter 301, and a longer reset period can be obtained. This embodiment does not make specific limitations on this, so that the CPU can have sufficient time to record logs before the reset signal arrives, and the maintenance personnel can have sufficient time for troubleshooting and on-site maintenance.

[0077] The second counting pulse output terminal is used to output a reset signal to the processor and / or the single-chip microcomputer to perform reset control on the processor and / or the single-chip microcomputer when the reset input terminal of the counter receives a reset signal.

[0078] Similarly, the second counting pulse output terminal can also be selected among the Q4-Q14 pins (excluding the selected first counting pulse output terminal) of the counter 301 chip. Exemplarily, in this embodiment, the Q14 pin can be selected as the second counting pulse output terminal of the counter 301. This embodiment does not make specific limitations on this.

[0079] Among them, the first reset input terminal of the counter 301 can be the RESET (reset) pin of the counter 301 chip, which is used to receive the watchdog signal output by the single-chip microcomputer 304 and the input signal determined according to the watchdog signal output by the CPU and the pulse signal output by the first counting pulse output terminal, so as to form a reset signal in response. Among them, the first watchdog signal output terminal of the processor 303 outputs a first watchdog signal to the counter 301, and the second reset input terminal receives the reset signal output by the single-chip microcomputer 304.

[0080] Among them, the second watchdog signal output terminal of the single-chip microcomputer 304 outputs a second watchdog signal to the counter 301, and the third reset input terminal receives the reset signal output by the counter 301 and simultaneously transmits it to the processor 303 (hereinafter also referred to as the CPU) to reset the CPU.

[0081] As Figure 5 Shown is a schematic diagram of the watchdog circuit in the watchdog control system, where U1 is the counter 301, Q1 is the control element 302, input point A is the second watchdog signal output terminal of the single-chip microcomputer 304, input point B is the first watchdog signal output terminal of the processor 303, and output point C is the second counting pulse output terminal of the counter 301.

[0082] The first watchdog signal output terminal is connected to the control element 302, and the control element 302 is respectively connected to the first counting pulse output terminal and the first reset input terminal;

[0083] The second watchdog signal output terminal is connected to the first reset input terminal, the second counting pulse output terminal is connected to the third reset input terminal, and the third reset input terminal is connected to the second reset input terminal;

[0084] Among them, the processor 303 is used to output a first watchdog signal through the first watchdog signal output terminal, and the control element 302 is used to determine the input signal of the first reset input terminal according to the first watchdog signal and the pulse signal output by the first counting pulse output terminal;

[0085] Among them, the control element 302 determines the input signal of the first reset input terminal by judging whether both the first watchdog signal and the pulse signal output by the first counting pulse output terminal are high-level, so as to realize the reset control of the edge server at a specific time.

[0086] Specifically, if both the first watchdog signal and the pulse signal output by the first counting pulse output terminal change from low level to high level, the input signal of the first reset input terminal is high level; if one of the first watchdog signal and the pulse signal output by the first counting pulse output terminal is low level or both are low level, the input signal is low level.

[0087] The single-chip microcomputer 304 is used to output a second watchdog signal through the second watchdog signal output terminal;

[0088] The RESET port of the counter 301 is directly connected to the reset pin of the MCU. At any time, the MCU only needs to transmit the second watchdog signal to directly reset the counter 301 without being affected by other factors.

[0089] The counter 301 is used to determine a reset signal according to the input signal and the second watchdog signal, and output the reset signal to the third reset input terminal through the second counting pulse output terminal to perform reset control on the single-chip microcomputer 304, and / or transmit the reset signal to the second reset input terminal through the third reset input terminal to perform reset control on the processor 303.

[0090] Among them, the counter 301 may receive one or more of the input signal given by the CPU through internal logic and the second watchdog signal transmitted by the MCU to determine the reset signal. Specifically, for the reset control of the counter 301, it may be reset according to the input signal transmitted by a single CPU; it may also be reset according to the second watchdog signal transmitted by a single MCU; it may also be reset when receiving both the input signal and the second watchdog signal at the same time.

[0091] Among them, the second counting pulse output terminal may be connected to the single-chip microcomputer 304, and the third reset input terminal of the single-chip microcomputer may be connected to the second reset input terminal of the processor 303. Therefore, it can both send a reset signal to the single-chip microcomputer 304 for reset and send a reset signal to the processor 303 for reset.

[0092] Generally speaking, under the background of the prior art, the following improvements are made in this embodiment: First, both the CPU and the single-chip microcomputer 304 are connected with watchdog signals. The CPU watchdog signal is only valid for watchdog feeding at a certain specific time interval, and at other times, the CPU watchdog signal is invalid. The watchdog signal of the single-chip microcomputer 304 is always valid; Second, the watchdog does not use a dedicated chip, but uses the counter 301 to realize the functions of the watchdog and counting by using the counter 301. Here, the watchdog feeding is equivalent to clearing the counter 301, and no dedicated watchdog chip and additional single-chip microcomputer 304 or CPLD are used, ensuring the reliability of the system. Finally, the counter 301 is connected to the RESET pin of the MCU to reset the MCU, and the MCU can clear the counter 301 to realize watchdog feeding; while having the above functions, the CPU can also reset the watchdog (clear the counter 301), and the watchdog signal of the CPU is controlled by the counter 301 periodically and can realize watchdog feeding in a specific time period. With this feature, it can effectively prevent the problem that the CPU feeds the watchdog disorderly, resulting in the MCU being unable to restart. When the CPU runs away, in the long time dimension with uncertain pin levels, it just happens to encounter a time interval when the CPU watchdog signal is valid once, and the probability is very small. Continuously encountering the time interval when the CPU watchdog signal is valid can almost be considered not to occur.

[0093] In summary, this embodiment can implement the design of the watchdog by only adding one counter 301 and some resistor-capacitor components. It reduces the system components and, while ensuring the reliability of the entire system, enables the CPU to determine the system reset time according to its own status of the service, which is convenient for system operation and maintenance as well as debugging.

[0094] For the watchdog control system provided in this embodiment, the input signal of the first reset input end of the counter is determined by the first watchdog signal output from the first watchdog signal output end of the processor and the pulse signal output from the first counting pulse output end of the counter; then the reset signal is determined according to the input signal and the second watchdog signal output from the second watchdog signal output end of the single-chip microcomputer; finally, the reset signal is output to the third reset input end through the second counting pulse output end to reset the single-chip microcomputer, and / or the reset signal is transmitted to the second reset input end through the third reset input end to perform reset control on the processor, so as to implement reset control on the single-chip microcomputer and / or the processor; at the same time, a control element is added to control the conduction state of the circuit between the counter and the processor, so that even when the single-chip microcomputer is abnormal, the processor can be used for reset, providing multiple guarantees for the control system and improving the effectiveness of the counter reset control.

[0095] Based on the above embodiment, in this embodiment, the control element 302 includes a field-effect transistor; the gate of the field-effect transistor is connected to the first watchdog signal output end, the drain of the field-effect transistor is respectively connected to the first counting pulse output end and the first reset input end, and the source of the field-effect transistor is connected to the grounding device; when the first watchdog signal is output from the first watchdog signal output end, the field-effect transistor is in an off state, and the field-effect transistor is used to control the connection between the first counting pulse output end and the first reset input end, and input the input signal determined according to the pulse signal output from the first counting pulse output end to the first reset input end; when the first watchdog signal is not output from the first watchdog signal output end, the field-effect transistor is in a conducting state, and the field-effect transistor is used to control both the first counting pulse output end and the first reset input end to be connected to the grounding device.

[0096] Among them, the control element 302 may include a field effect transistor 2N7002 MOSFET (Metal Oxide Semiconductor Field Effect Transistor). 2N7002 is an N-channel MOSFET used to reduce the on-resistance. This type of MOSFET includes three terminals, namely the source (S, Source), the gate (G, Gate electrode), and the drain (D, Drain). These three terminals are equivalent to the emitter, base, and collector terminals of a BJT (Bipolar Junction Transistor).

[0097] The properties of the MOSFET can be simply defined by the movement of electronic charge carriers. Conduction can occur between two terminals such as the source and the drain with the help of electrons. Once a voltage is applied to the gate terminal of the MOSFET, the charge carriers will flow from the source to the drain. Similarly, when the forward voltage outside the gate terminal increases, it will attract several electrons, which helps to expand the conduction path between the source and the drain. Therefore, the conductivity of the MOSFET mainly depends on the voltage intensity applied to the gate terminal.

[0098] Among them, the gate of the field effect transistor 2N7002 MOSFET can receive the first watchdog signal, and its minimum on-voltage is 1V. The drain can receive the pulse signal output from the first counting pulse output terminal. The conduction or cutoff of the field effect transistor is determined according to the first watchdog signal and the pulse signal output from the first counting pulse output terminal.

[0099] As Figure 5 shown, when the CPU outputs the first watchdog signal, the field effect transistor is off. At this time, the high-level signal output from the first counting pulse output terminal flows out from the first counting pulse output terminal and reaches the RESET pin of the counter (i.e., the first reset input terminal), and then the counter 301 is reset; when the gate of the field effect transistor does not receive the first watchdog signal, the field effect transistor is in the on state, and the signal directly flows into the grounding device, that is, the level signal is 0, and the counter 301 cannot be reset.

[0100] In this embodiment, the gate of the field effect transistor in the control element 302 is connected to the first watchdog signal output terminal, and it is determined whether the field effect transistor is in the on state according to the first watchdog signal; its drain is respectively connected to the first counting pulse output terminal and the first reset input terminal, and when the field effect transistor is in the off state and the first counting pulse output terminal outputs a high-level signal, the counter 301 is reset; the source of the field effect transistor is connected to the grounding device, and the counter 301 cannot be reset when the field effect transistor is off. The control element 302 is used to realize the reset of the counter 301 through the field effect transistor when the first watchdog signal is output at the first watchdog signal output terminal, ensuring the reliability of the system.

[0101] Based on the above embodiment, the watchdog circuit in this embodiment further includes a pull-up resistor; the first end of the pull-up resistor is connected to the gate of the field effect transistor, and the second end of the pull-up resistor is connected to the power supply of the processor 303; when the first watchdog signal is output at the first watchdog signal output terminal, the pull-up resistor is used to pull down the level signal of the gate to make the field effect transistor in the off state; when the first watchdog signal is not output at the first watchdog signal output terminal, the pull-up resistor is used to pull up the level signal of the gate to make the field effect transistor in the on state.

[0102] Among them, the function of the pull-up resistor is to clamp an uncertain signal at a high level through a resistor, and the resistor also plays a role in current limiting. On the wire connected to the pull-up resistor, when the external component is not connected, the voltage at the input port can be pulled up to a high level through the pull-up resistor; if the external component is enabled, that is, the high level set by the pull-up resistor is cancelled, so that the pin can maintain a definite logic level even when the external component is not connected. The pull-up resistor can be set between the logic gate and its input terminal for information configuration, selection, or error detection and correction of external device signals.

[0103] Optionally, the resistance value of the pull-up resistor can be set in combination with the characteristics of the switching transistor and the input characteristics of the subsequent circuit. For example, in this embodiment, the resistance value of the pull-up resistor R2 in the watchdog control system circuit can be set to 500 KΩ, and this embodiment does not make specific limitations on this.

[0104] In the watchdog control system, the pull-up resistor is directly connected in parallel to the path between the gate of the field effect transistor and the power supply of the processor 303. When the first watchdog signal output terminal of the CPU outputs the first watchdog signal, the pull-up resistor pulls down the level signal of the gate of the field effect transistor, resulting in the field effect transistor not meeting the conduction condition, the field effect transistor disconnects, the first counting pulse output terminal is connected to the first reset input terminal, and the counter 301 is reset when a high level signal is output at the first counting pulse output terminal; when the first watchdog signal output terminal does not output the first watchdog signal, the pull-up resistor raises the level signal of the gate of the field effect transistor to meet the conduction condition of the field effect transistor, the field effect transistor conducts, and the signal directly flows into the grounding device, and the counter 301 cannot be reset.

[0105] In this embodiment, by setting a pull-up resistor in the watchdog circuit, according to whether the first watchdog signal output terminal outputs the first watchdog signal, the level signal of the gate of the field effect transistor is pulled down / raised, and the conduction condition of the field effect transistor is used to control whether its gate is in the conduction state, so as to control the counter 301 to perform precise reset at the appropriate time.

[0106] Based on the above embodiment, in this embodiment, the watchdog circuit further includes a first capacitor; the first end of the first capacitor is connected to the gate of the field effect transistor, and the second end of the first capacitor is connected to the first watchdog signal output terminal; the first capacitor is used to transmit the AC signal in the first watchdog signal to the gate of the field effect transistor.

[0107] As Figure 5 shown, the capacitance of the first capacitor C1 is set according to the actual circuit requirements. Exemplarily, in this embodiment, 1 uF can be set as the typical capacitance of the first capacitor C1 in the watchdog control system circuit, and this embodiment does not make specific limitations on this.

[0108] Among them, the first capacitor C1 realizes the function of protecting the circuit with its characteristic of blocking direct current and passing alternating current. If the first capacitor C1 is not added to the circuit, when an abnormality occurs, a first watchdog signal that is only high level or only low level may cause the watchdog control system to keep feeding the dog or never feed the dog, resulting in abnormal situations during the reset process of the counter 301; after adding the first capacitor C1, the first capacitor C1 will only transmit the watchdog signal when the conditions are met, that is, when the first watchdog signal changes from low level to high level or from high level to low level, ensuring the stability of the watchdog control system circuit.

[0109] Specifically, the first capacitor C1 can ensure that when the single-chip microcomputer 304 or the CPU crashes, the high level or low level output separately by its pin will not feed the dog. Only when the first watchdog signal output by the CPU first watchdog signal output terminal changes from high to low, it is transmitted to the gate of the field effect transistor to feed the dog.

[0110] In this embodiment, a first capacitor is provided in the watchdog circuit to protect the circuit. The first capacitor only transmits the AC signal in the first dog-feeding signal to the gate of the field-effect transistor, so as to avoid the situation that the watchdog control system circuit keeps feeding the dog or never feeds the dog after the single-chip microcomputer 304 or the CPU crashes, ensure the stability of the watchdog control system circuit, and avoid disorderly dog-feeding.

[0111] On the basis of the above embodiment, the watchdog circuit in this embodiment further includes a second capacitor; the first end of the second capacitor is connected to the first counting pulse output terminal, and the second end of the second capacitor is respectively connected to the drain of the field-effect transistor and the first reset input terminal; the second capacitor is used to transmit the AC signal in the pulse signal output by the first counting pulse output terminal to the drain of the field-effect transistor, and / or transmit the AC signal in the pulse signal output by the first counting pulse output terminal to the first reset input terminal.

[0112] As Figure 5 shown, the capacitance of the second capacitor C5 is set according to the actual circuit requirements. Exemplarily, in this embodiment, 1 uF can be set as the typical capacitance of the second capacitor C5 in the watchdog control system circuit, and this embodiment does not make specific limitations on this.

[0113] Among them, the second capacitor C5 realizes the function of protecting the circuit with its characteristic of blocking direct current and passing alternating current. If the second capacitor C5 is not added to the circuit, when an abnormality occurs, a pulse signal that is solely high level or solely low level may cause the watchdog control system to keep resetting disorderly or never resetting, resulting in abnormal situations during the reset process of the counter 301; after adding the second capacitor C5, the second capacitor C5 will only transmit the pulse signal when the conditions are met, that is, when the pulse signal output by the first counting pulse output terminal changes from low level to high level or when the pulse signal output by the first counting pulse output terminal changes from high level to low level, ensuring the stability of the watchdog control system circuit.

[0114] Specifically, the second capacitor C5 can ensure that the high level or low level output separately by the pin of the pulse signal output by the first counting pulse output terminal after the counter crashes will not be transmitted. Only when the level of the single-chip microcomputer 304 changes from low to high, the first dog-feeding signal output by the CPU changes from high to low, and at the same time, during this interval, the pulse signal output by the first counting pulse output terminal changes from low to high, can the signal be transmitted to the drain of the field-effect transistor and / or the first reset input terminal to perform effective dog-feeding.

[0115] Optionally, the interval time is the CPU response time, that is, the time from sending the watchdog signal to the reset of the counter 301. The interval time can be set according to the actual requirements of the circuit, and this embodiment does not specifically limit it.

[0116] In this embodiment, a second capacitor is provided in the watchdog circuit to protect the circuit. The second capacitor only transmits the AC signal in the pulse signal output from the first counting pulse output terminal to the drain of the field effect transistor, and / or transmits the AC signal in the pulse signal output from the first counting pulse output terminal to the first reset input terminal, so as to avoid the situation that the watchdog control system circuit keeps feeding the dog or never feeds the dog after the single-chip microcomputer 304 or the CPU crashes, ensure the stability of the watchdog control system circuit, and avoid disorderly dog feeding.

[0117] Based on the above embodiment, the watchdog circuit in this embodiment further includes a third capacitor and a fourth capacitor; the first end of the third capacitor is connected to the first counting pulse output terminal, the second end of the third capacitor is connected to the first reset input terminal, and the third capacitor is used to transmit the AC signal in the pulse signal output from the first counting pulse output terminal to the first reset input terminal; the first end of the fourth capacitor is connected to the first reset input terminal, the second end of the fourth capacitor is connected to the second watchdog signal output terminal, and the fourth capacitor is used to transmit the AC signal in the second watchdog signal to the first reset input terminal.

[0118] Optionally, the capacitance of the third capacitor C2 is set according to the actual circuit requirements. Exemplarily, in this embodiment, 100 nF can be set as the typical capacitance of the third capacitor C2 in the watchdog control system circuit, and this embodiment does not specifically limit it.

[0119] Similarly, the capacitance of the fourth capacitor C3 can also be set according to the actual circuit requirements. Exemplarily, in this embodiment, 1 μF can be set as the typical capacitance of the fourth capacitor C3 in the watchdog control system circuit, and this embodiment does not specifically limit it.

[0120] Among them, the third capacitor C2 plays a role in protecting the circuit with its characteristic of blocking direct current and passing alternating current. If the third capacitor C2 is not added to the circuit, when an abnormality occurs, a pulse signal that is only high level or only low level may cause the watchdog control system to keep feeding the dog or never feed the dog, resulting in abnormal situations during the reset process of the counter 301; after adding the third capacitor C2, the third capacitor C2 will only transmit the pulse signal when the conditions are met, that is, when the pulse signal output from the first counting pulse output terminal changes from low level to high level or the pulse signal output from the first counting pulse output terminal changes from high level to low level, ensuring the stability of the watchdog control system circuit.

[0121] Specifically, the third capacitor C2 can ensure that after the single-chip microcomputer 304 or the CPU crashes, the high level or low level output separately by its pin will not be reset. Only when the level of the single-chip microcomputer 304 changes from low to high, the CPU signal changes from high to low, and at the same time, during this interval, the pulse signal output from the first counting pulse output terminal changes from low to high, and is transmitted to the first reset input terminal for effective reset.

[0122] Similarly, the fourth capacitor C3 plays a role in protecting the circuit with its characteristic of blocking direct current and passing alternating current, ensuring the stability of the watchdog control system circuit.

[0123] Specifically, the fourth capacitor C3 can ensure that after the single-chip microcomputer 304 or the CPU crashes, the high level or low level output separately by its pin will not be reset. Only when the level of the second watchdog signal output from the second watchdog signal output terminal of the single-chip microcomputer 304 changes from low to high, and is transmitted to the first reset input terminal for effective reset.

[0124] In this embodiment, by setting the third capacitor and the fourth capacitor in the watchdog circuit, the circuit is protected. The third capacitor only transmits the alternating current signal in the pulse signal output from the first counting pulse output terminal to the first reset input terminal, and the fourth capacitor only transmits the alternating current signal in the second watchdog signal output from the second watchdog signal output terminal to the first reset input terminal, so as to avoid the situation that the watchdog control system circuit keeps feeding the dog or never feeds the dog after the single-chip microcomputer 304 or the CPU crashes, ensure the stability of the watchdog control system circuit, and avoid disorderly dog feeding.

[0125] Based on the above embodiment, in this embodiment, the counter 301 further includes a plurality of third counting pulse output terminals; the plurality of third counting pulse output terminals are the counting pulse output terminals in the counter 301 except the first counting pulse output terminal and the second counting pulse output terminal; the third counting pulse output terminals are connected to the input / output interface of the processor 303; the processor 303 is used to determine the dog feeding state of the single-chip microcomputer 304 according to the pulse signal output from the third counting pulse output terminals; the dog feeding state includes normal dog feeding or abnormal dog feeding.

[0126] Optionally, the input / output port of the processor 303 can be the GPIO (General Purpose Input / Output Port) pin of the CPU itself, or the GPIO pin extended by the CPU through an IC chip. This embodiment does not make a specific limitation on this. Optionally, when selecting the third counting pulse output terminal of the counter 301, it can be set to the remaining part (excluding the selected first counting pulse output terminal and the second counting pulse output terminal) among the Q4 - Q14 pins of the counter 301 chip.

[0127] During normal operation, the first watchdog signal output by the CPU remains unchanged. The microcontroller 304 detects the CPU through the communication port to ensure that the CPU operates in a normal state. After a short delay, the microcontroller 304 performs the watchdog function.

[0128] Optionally, the duration of the short delay can be set according to actual requirements. Specifically, in this embodiment, the short delay time of the microcontroller 304 can be set to 0.2 s, but this embodiment does not specifically limit this.

[0129] By connecting to the interface of the CPU input, the CPU can detect the changes in the pulse signals of each pin of the counter 301 to observe whether the microcontroller 304 performs the watchdog function normally. Specifically, if the microcontroller 304 performs the watchdog function normally, after the counter 301 is reset, the third counting pulse output terminals are all at a low level; if the watchdog function of the microcontroller 304 is abnormal, there may be a situation where the watchdog is required at a certain moment, but the pulse signal of the third counting pulse output terminal is still at a high level.

[0130] Taking the oscillation period of the counter MC74HC4060 as an example, with the first counting pulse output terminal as Q13 and the second counting pulse output terminal as Q14, only Q4 can be high after the 16th pulse among the 16 pulses, and Q5 - Q12 are all low. By reading the states of Q4 - Q12, the CPU can know that the microcontroller 304 performs the watchdog function normally and all works are normal.

[0131] In this embodiment, by setting the counting pulse output terminals of the counter 301 other than the first counting pulse output terminal and the second counting pulse output terminal as multiple third counting pulse output terminals and connecting them to the input / output interface of the processor 303, the processor 303 can determine the watchdog state of the microcontroller 304 according to the pulse signals output by the third counting pulse output terminals, realizing the monitoring of the watchdog state of the microcontroller 304 by the processor 303 and ensuring the stability of the watchdog control system circuit.

[0132] Based on the above embodiment, the counter 301 in this embodiment further includes a fourth counting pulse output terminal; the fourth counting pulse output terminal is obtained by selecting from the multiple third counting pulse output terminals according to the control requirements of the watchdog control system; when the microcontroller 304 has an abnormal watchdog situation, the fourth counting pulse output terminal is connected to the interrupt pin of the processor 303, and when the pulse signal output by the fourth counting pulse output terminal is a target signal, the processor 303 executes an interrupt task;

[0133] Specifically, the fourth counting pulse output terminal can be selected from the pins of the third counting pulse output terminal according to actual requirements. Exemplarily, in this embodiment, the Q5 pin can be selected as the fourth counting pulse output terminal of the counter 301, and this embodiment does not make specific limitations thereto.

[0134] In the state where the single-chip microcomputer 304 abnormally feeds the dog, by connecting to the interrupt pin of the CPU, the fourth counting pulse output terminal outputs an interrupt signal to the CPU, and after receiving the interrupt signal, the CPU starts to execute the interrupt task.

[0135] The interrupt task includes reading the counting state of the counter 301, calculating the reset trigger time according to the counting state, and when the current time meets the reset trigger time, outputting the first watchdog signal through the first watchdog signal output terminal, recording the working log of the processor 303, and obtaining one or more of the fault logs of the single-chip microcomputer 304.

[0136] Taking the first counting pulse output terminal of the counter 301 as Q13, the second counting pulse output terminal as Q14, and the fourth counting pulse output terminal as Q5 as an example, when the CPU detects that the single-chip microcomputer 304 is abnormal and cannot feed the dog, Q5 - Q12 increases as the number of pulses increases. Q5 can be connected to the interrupt pin of the CPU. When Q5 is high, the system does not feed the dog normally, the CPU enters the interrupt, and then reads the state.

[0137] According to the timing change of Q13, it can be calculated that a reset is performed after 16,384 pulses, that is, it can be calculated that if the CPU does not feed the dog, the system will be reset after the reset waiting time, and the CPU can process according to the specific service during the reset waiting time. If it is necessary to maintain the on-site status for operation and maintenance or R & D personnel to solve problems, the CPU needs to send the rising edge of the watchdog signal before the rising edge of Q13 arrives (8192 pulses) at the interval time, so that the MOSFET gate level is guaranteed to be at least lower than the interval time (less than the gate voltage) for a low level, ensuring that the RESET pin of the counter 301 appears at a high level, realizing the clearing of the counter 301, and repeating this process until the fault is eliminated.

[0138] Taking the oscillation period of the counter 301 as 0.0096 s as an example, the reset waiting time of the CPU can be calculated to be 156 seconds.

[0139] Among them, the interval time is the reset trigger time. Taking the typical capacitance of the third capacitor C2 in the watchdog control system circuit as 100 nF and the resistance value of the pull-up resistor R2 as 500 KΩ as an example, it can be calculated that the voltage reaches 1 V in about 200 ms, reaching the minimum voltage of 1 V for the gate of the field-effect transistor 2N7002 to conduct. For conservatism, the interval time is taken as 100 ms here.

[0140] In this embodiment, a fourth counting pulse output terminal is selected and obtained from multiple third counting pulse output terminals and connected to the interrupt pin of the processor 303, so that the processor 303 can enter an interrupt after receiving the pulse signal output by the fourth counting pulse output terminal, realizing tasks including reading the counting status of the counter 301, calculating the reset trigger time according to the counting status, and when the current time meets the reset trigger time, outputting a first watchdog signal through the first watchdog signal output terminal, recording the working log of the processor 303, and obtaining one or more tasks in the fault log of the single-chip microcomputer 304 after the abnormal watchdog feeding of the single-chip microcomputer 304, facilitating the timely processing of interrupt tasks, and further improving the reliability of the edge server.

[0141] Based on the above embodiment, the watchdog circuit in this embodiment further includes a voltage stabilizing component; the first end of the voltage stabilizing component is respectively connected to the second watchdog signal output terminal and the first reset input terminal, and the second end of the voltage stabilizing component is connected to a grounding device; the voltage stabilizing component includes a voltage stabilizing diode and a resistor, and the voltage stabilizing diode and the resistor are connected; the voltage stabilizing component is used to protect the counter 301 through the voltage stabilizing diode and the resistor.

[0142] As Figure 5 shown, the voltage stabilizing diode D1 in the voltage stabilizing component is connected in parallel on the communication path between the second watchdog signal output terminal of the single-chip microcomputer 304 and the RESET pin of the counter 301, playing a role in protecting the circuit.

[0143] Specifically, on the one hand, the voltage stabilizing diode D1 protects the pins of the counter 301 from overvoltage damage. On the other hand, using its one-way conductivity, when the fourth capacitor C3 is negative voltage, the clamping voltage ensures that the pins will not be damaged due to too low voltage.

[0144] Optionally, the reverse breakdown voltage of the voltage stabilizing diode can be selected according to actual needs. For example, in this embodiment, 5V can be selected as the reverse breakdown voltage of the voltage stabilizing diode D1, and this embodiment does not make specific limitations on this.

[0145] Similarly, the resistance value of the resistor R1 in the voltage stabilizing component can also be selected according to actual needs. For example, in this embodiment, 500KΩ can be selected as the resistance value of the resistor R1 in the voltage stabilizing component, and this embodiment does not make specific limitations on this.

[0146] In this embodiment, by connecting in parallel a voltage stabilizing component composed of a voltage stabilizing diode and a resistor between the second watchdog signal output terminal and the first reset input terminal of the watchdog circuit, the functions of protecting the counter 301 and the fourth resistor are realized, ensuring the stability of the watchdog control system circuit.

[0147] Based on the above embodiments, the counter 301 in this embodiment further includes a clock pulse input terminal, a first clock pulse output terminal, a second clock pulse output terminal, and a clock generator; the clock generator includes a first resistor, a second resistor, and a fifth capacitor; a first end of the first resistor is connected to the clock pulse input terminal, a first end of the second resistor is connected to the first clock pulse output terminal, a first end of the fifth capacitor is connected to the second clock pulse output terminal, and a second end of the first resistor is respectively connected to a second end of the second resistor and a second end of the fifth capacitor.

[0148] As Figure 5 shown, the clock pulse input terminal, the first clock pulse output terminal, and the second clock pulse output terminal of the counter 301 are respectively the OSCIN, OSC1, and OSC2 ports of the counter.

[0149] Among them, the clock generator is used to determine the oscillation period of the counter 301, and its calculation formula is as follows:

[0150] T = 2.2RC;

[0151] where T represents the oscillation period of the counter 301, and R and C respectively represent the resistance value and capacitance value in the clock generator.

[0152] Optionally, the resistance value selection of the first resistor R3 can be determined according to the actual requirements of the oscillation period of the counter 301. For example, in this embodiment, the resistance value of the first resistor R3 can be selected as 100 KΩ, and this embodiment does not make specific limitations on this.

[0153] Similarly, the resistance value selection of the second resistor R4 can be determined according to the actual requirements of the oscillation period of the counter 301. For example, in this embodiment, the resistance value of the second resistor R4 can be selected as 20 KΩ, and this embodiment does not make specific limitations on this.

[0154] Similarly, the capacitance value selection of the fifth capacitor C4 can be determined according to the actual requirements of the oscillation period of the counter 301. For example, in this embodiment, the capacitance value of the fifth capacitor C4 can be selected as 220 nF, and this embodiment does not make specific limitations on this.

[0155] Taking the resistance value of the first resistor R3 as 100 KΩ, the resistance value of the second resistor R4 as 20 KΩ, and the capacitance value of the fifth capacitor C4 as 220 nF as an example, according to the calculation formula, the oscillation period of the counter 301 is 0.00968 seconds.

[0156] In this embodiment, by setting a clock pulse input terminal, a first clock pulse output terminal, a second clock pulse output terminal, and a clock generator for the counter 301, the oscillation period of the counter 301 can be determined, and the reset waiting time of the CPU can be adaptively configured, which helps to ensure the stability of the watchdog control system circuit and the accuracy of the reset control.

[0157] The following combines Figure 6 to describe the control method of the watchdog control system provided in this embodiment. The control method of the watchdog control system described below can be mutually corresponding and referred to with the watchdog control system described above.

[0158] As Figure 6 shown, it is a schematic flowchart of the control method of the watchdog control system provided in this embodiment.

[0159] Step 601, determine the input signal of the first reset input terminal of the counter according to the first watchdog signal output by the first watchdog signal output terminal of the processor and the pulse signal output by the first counting pulse output terminal of the counter;

[0160] Among them, the control element determines the input signal of the first reset input terminal by judging whether both the first watchdog signal and the pulse signal output by the first counting pulse output terminal are high level, so as to realize the reset control of the edge server at a specific time.

[0161] Specifically, if both the first watchdog signal and the pulse signal output by the first counting pulse output terminal change from low level to high level, the input signal of the first reset input terminal is high level; if one of the first watchdog signal and the pulse signal output by the first counting pulse output terminal is low level or both are low level, the input signal is low level.

[0162] Step 602, determine the reset signal according to the input signal and the second watchdog signal output by the second watchdog signal output terminal of the single-chip microcomputer;

[0163] Step 603, output the reset signal to the third reset input terminal through the second counting pulse output terminal to perform reset control on the single-chip microcomputer, and / or transmit the reset signal to the second reset input terminal through the third reset input terminal to perform reset control on the processor.

[0164] Among them, the counter can receive one or more of the input signal given by the CPU through internal logic and the second watchdog signal transmitted by the MCU to determine the reset signal. Specifically, the counter reset control can be to perform reset according to the input signal transmitted by a single CPU; it can also be to perform reset according to the second watchdog signal transmitted by a single MCU; it can also be to perform reset when receiving the input signal and the second watchdog signal at the same time.

[0165] Among them, the second counting pulse output terminal can be connected to the single-chip microcomputer, and the third reset input terminal of the single-chip microcomputer can be connected to the second reset input terminal of the processor. Therefore, it can reset the single-chip microcomputer by sending a reset signal and can also reset the processor by sending a reset signal.

[0166] The control method of the watchdog control system provided by this embodiment determines the input signal of the first reset input terminal of the counter according to the first watchdog signal output by the first watchdog signal output terminal of the processor and the pulse signal output by the first counting pulse output terminal of the counter; then determines the reset signal according to the input signal and the second watchdog signal output by the second watchdog signal output terminal of the single-chip microcomputer; finally, outputs the reset signal to the third reset input terminal through the second counting pulse output terminal to reset the single-chip microcomputer, and / or transmits the reset signal to the second reset input terminal through the third reset input terminal to perform reset control on the processor, so as to realize reset control on the watchdog circuit, the single-chip microcomputer and the processor in the watchdog system; at the same time, a control element is added to control the conduction state of the circuit between the counter and the processor, so that even when the single-chip microcomputer is abnormal, it can be reset by the processor, endowing the control system with multiple guarantees and improving the effectiveness of the counter reset control.

[0167] The device embodiments described above are merely illustrative. The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed to multiple network units. Some or all of the modules can be selected according to actual needs to achieve the purpose of the solution of this embodiment. Those of ordinary skill in the art can understand and implement it without creative efforts.

[0168] Through the description of the above embodiments, those skilled in the art can clearly understand that each embodiment can be implemented by means of software plus a necessary general hardware platform, and of course, it can also be implemented by hardware. Based on this understanding, the above technical solutions, in essence, or the part that contributes to the prior art can be embodied in the form of a software product. This computer software product can be stored in a computer-readable storage medium, such as ROM / RAM, magnetic disk, optical disk, etc., and includes several instructions for causing a computer device (which can be a personal computer, a server, or a network device, etc.) to execute the methods described in each embodiment or some parts of the embodiments.

[0169] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that they can still modify the technical solutions described in the foregoing embodiments, or perform equivalent replacements for some of the technical features; and these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A watchdog control system, characterized in that, it includes a watchdog circuit, a single-chip microcomputer and a processor; the watchdog circuit includes a counter and a control element; the counter includes a first counting pulse output terminal, a second counting pulse output terminal and a first reset input terminal, the processor includes a first dog-feeding signal output terminal and a second reset input terminal, and the single-chip microcomputer includes a second dog-feeding signal output terminal and a third reset input terminal; the first dog-feeding signal output terminal is connected to the control element, and the control element is respectively connected to the first counting pulse output terminal and the first reset input terminal; the second dog-feeding signal output terminal is connected to the first reset input terminal, the second counting pulse output terminal is connected to the third reset input terminal, and the third reset input terminal is connected to the second reset input terminal; wherein, the processor is configured to output a first dog-feeding signal through the first dog-feeding signal output terminal, and the control element is configured to determine the input signal of the first reset input terminal according to the first dog-feeding signal and the pulse signal output by the first counting pulse output terminal; the single-chip microcomputer is configured to output a second dog-feeding signal through the second dog-feeding signal output terminal; the counter is configured to determine a reset signal according to the input signal and the second dog-feeding signal, and output the reset signal to the third reset input terminal through the second counting pulse output terminal to perform reset control on the single-chip microcomputer, and / or transmit the reset signal to the second reset input terminal through the third reset input terminal to perform reset control on the processor; the control element includes a field effect transistor; the gate of the field effect transistor is connected to the first dog-feeding signal output terminal, the drain of the field effect transistor is respectively connected to the first counting pulse output terminal and the first reset input terminal, and the source of the field effect transistor is connected to a grounding device; when the first dog-feeding signal is output from the first dog-feeding signal output terminal, the field effect transistor is in an off state, and the field effect transistor is configured to control the first counting pulse output terminal to communicate with the first reset input terminal, and input the input signal determined according to the pulse signal output by the first counting pulse output terminal to the first reset input terminal; when the first dog-feeding signal is not output from the first dog-feeding signal output terminal, the field effect transistor is in a conducting state, and the field effect transistor is configured to control both the first counting pulse output terminal and the first reset input terminal to be connected to the grounding device; the watchdog circuit further includes a pull-up resistor; the first end of the pull-up resistor is connected to the gate of the field effect transistor, and the second end of the pull-up resistor is connected to the power supply of the processor; when the first dog-feeding signal is output from the first dog-feeding signal output terminal, the pull-up resistor is configured to pull down the level signal of the gate to make the field effect transistor in an off state; when the first dog-feeding signal is not output from the first dog-feeding signal output terminal, the pull-up resistor is configured to pull up the level signal of the gate to make the field effect transistor in a conducting state.

2. The watchdog control system according to claim 1, characterized in that, the watchdog circuit further includes a first capacitor; a first end of the first capacitor is connected to the gate of the field effect transistor, and a second end of the first capacitor is connected to the first dog feeding signal output terminal; the first capacitor is used for transmitting an AC signal in the first dog feeding signal to the gate of the field effect transistor.

3. The watchdog control system according to claim 1, characterized in that, the watchdog circuit further includes a second capacitor; a first end of the second capacitor is connected to the first counting pulse output terminal, and a second end of the second capacitor is respectively connected to the drain of the field effect transistor and the first reset input terminal; the second capacitor is used for transmitting an AC signal in the pulse signal output from the first counting pulse output terminal to the drain of the field effect transistor, and / or transmitting an AC signal in the pulse signal output from the first counting pulse output terminal to the first reset input terminal.

4. The watchdog control system according to claim 1, characterized in that, the watchdog circuit further includes a third capacitor and a fourth capacitor; a first end of the third capacitor is connected to the first counting pulse output terminal, a second end of the third capacitor is connected to the first reset input terminal, and the third capacitor is used for transmitting an AC signal in the pulse signal output from the first counting pulse output terminal to the first reset input terminal; a first end of the fourth capacitor is connected to the first reset input terminal, a second end of the fourth capacitor is connected to the second dog feeding signal output terminal, and the fourth capacitor is used for transmitting an AC signal in the second dog feeding signal to the first reset input terminal.

5. The watchdog control system according to any one of claims 1-4, characterized in that, the counter further includes a plurality of third counting pulse output terminals; the plurality of third counting pulse output terminals are the counting pulse output terminals in the counter except the first counting pulse output terminal and the second counting pulse output terminal; the third counting pulse output terminal is connected to the input / output interface of the processor; the processor is used for determining the dog feeding state of the single-chip microcomputer according to the pulse signal output from the third counting pulse output terminal; the dog feeding state includes normal dog feeding or abnormal dog feeding.

6. The watchdog control system according to claim 5, characterized in that, the counter further includes a fourth counting pulse output terminal; the fourth counting pulse output terminal is obtained by selecting from the plurality of third counting pulse output terminals according to the control requirements of the watchdog control system; when the single-chip microcomputer is in the case of abnormal dog feeding, the fourth counting pulse output terminal is connected to the interrupt pin of the processor, and when the pulse signal output from the fourth counting pulse output terminal is a target signal, the processor executes an interrupt task; The interruption task includes reading the counting status of the counter, calculating the reset trigger time according to the counting status, and when the current time meets the reset trigger time, outputting the first watchdog signal through the first watchdog signal output terminal, recording the working log of the processor, and obtaining one or more of the fault logs of the single-chip microcomputer.

7. The watchdog control system according to any one of claims 1-4, characterized in that, the watchdog circuit further includes a voltage stabilizing component; the first end of the voltage stabilizing component is respectively connected to the second watchdog signal output terminal and the first reset input terminal, and the second end of the voltage stabilizing component is connected to a grounding device; the voltage stabilizing component includes a voltage stabilizing diode and a resistor, and the voltage stabilizing diode and the resistor are connected; the voltage stabilizing component is used to protect the counter through the voltage stabilizing diode and the resistor.

8. The watchdog control system according to any one of claims 1-4, characterized in that, the counter further includes a clock pulse input terminal, a first clock pulse output terminal, a second clock pulse output terminal, and a clock generator; the clock generator includes a first resistor, a second resistor, and a fifth capacitor; the first end of the first resistor is connected to the clock pulse input terminal, the first end of the second resistor is connected to the first clock pulse output terminal, the first end of the fifth capacitor is connected to the second clock pulse output terminal, and the second end of the first resistor is respectively connected to the second end of the second resistor and the second end of the fifth capacitor.

9. A control method for a watchdog control system, characterized in that, applied to the watchdog control system according to any one of claims 1 to 8, including: determining the input signal of the first reset input terminal of the counter according to the first watchdog signal output by the first watchdog signal output terminal of the processor and the pulse signal output by the first counting pulse output terminal of the counter; determining a reset signal according to the input signal and the second watchdog signal output by the second watchdog signal output terminal of the single-chip microcomputer; outputting the reset signal to the third reset input terminal through the second counting pulse output terminal to perform reset control on the single-chip microcomputer, and / or transmitting the reset signal to the second reset input terminal through the third reset input terminal to perform reset control on the processor.

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