Pixel circuit and display

Abstract

This application provides a pixel circuit and display, including: a reset module, a compensation module, a driving module, a data writing module, an anode potential control module, and a light-emitting device; the reset module, compensation module, data writing module, and anode potential control module are respectively connected to the driving module, and the driving module is connected to the light-emitting device; a first reset signal input terminal of the reset module and a second reset signal input terminal of the anode potential control module are used to connect to an initialization signal line; at least one of the first and second reset signal input terminals is also connected to a capacitor. By setting a capacitor at at least one of the first and second reset signal input terminals to maintain the potential until the next frame is refreshed, and by connecting the initialization signal line, the OLED display screen can be zoned and controlled, enhancing the uniformity of the OLED display screen.

Description

Technical Field

[0001] This application relates to the field of display technology, and in particular to a pixel circuit and a display. Background Technology

[0002] For OLED (Organic Light-Emitting Diode) displays, the reset signal input to the Vinit terminal is different at different refresh rates to ensure optimal image quality. However, related technologies cannot perform zoned control of the display area. Therefore, when entering zoned frequency conversion mode, the image quality of different areas varies, resulting in poor uniformity of the OLED display. Summary of the Invention

[0003] The purpose of this application is to provide a pixel circuit and a display to enhance the uniformity of OLED display images.

[0004] The specific technical solution is as follows:

[0005] In a first aspect, embodiments of this application provide a pixel circuit, the circuit comprising:

[0006] Reset module, compensation module, drive module, data writing module, anode potential control module, and light-emitting device;

[0007] The reset module, the compensation module, the data writing module, and the anode potential control module are respectively connected to the driving module, and the driving module is connected to the light-emitting device;

[0008] The first reset signal input terminal of the reset module and the second reset signal input terminal of the anode potential control module are used to connect to the initialization signal line; at least one of the reset signal input terminals and the second reset signal input terminal is also connected to a capacitor.

[0009] In one possible implementation, the first reset signal input terminal and the second reset signal input terminal are used to connect to the same initialization signal line; the first reset signal input terminal is also connected to the first terminal of the second capacitor, and the second terminal of the second capacitor is connected to the positive power supply signal line; the second reset signal input terminal is also connected to the first terminal of the third capacitor, and the second terminal of the third capacitor is connected to the positive power supply signal line.

[0010] In one possible implementation, the first reset signal input terminal is used to connect to the first initialization signal line, and the second reset signal input terminal is used to connect to the third initialization signal line; the first reset signal input terminal is also connected to the first end of the second capacitor, and the second end of the second capacitor is connected to the positive power supply signal line.

[0011] In one possible implementation, the first reset signal input terminal is used to connect to the third initialization signal line connection, and the second reset signal input terminal is used to connect to the second initialization signal line connection; the second reset signal input terminal is also connected to the first terminal of the third capacitor, and the second terminal of the third capacitor is connected to the positive power supply signal line.

[0012] In one possible implementation, the first reset signal input terminal is used to connect to the first initialization signal line, and the second reset signal input terminal is used to connect to the second initialization signal line; the first reset signal input terminal is also connected to the first end of the second capacitor, and the second end of the second capacitor is connected to the positive power supply signal line; the second reset signal input terminal is also connected to the first end of the third capacitor, and the second end of the third capacitor is connected to the positive power supply signal line.

[0013] In one possible implementation, the data writing module includes a fourth transistor, the compensation module includes a second transistor, and the driving module includes a third transistor, a fifth transistor, and a sixth transistor.

[0014] The gate of the second transistor is connected to the gate control signal terminal, the first terminal of the second transistor is connected to the second terminal of the third transistor and the first terminal of the sixth transistor, and the second terminal of the second transistor is connected to the reset module.

[0015] The gate of the third transistor is connected to the reset module, and the first terminal of the third transistor is connected to the second terminal of the fourth transistor and the second terminal of the fifth transistor, respectively.

[0016] The gate of the fourth transistor is connected to the gate control signal terminal, and the first terminal of the fourth transistor is connected to the data signal voltage terminal.

[0017] The gate of the fifth transistor is connected to the scan control signal terminal, and the first terminal of the fifth transistor is connected to the power supply voltage terminal.

[0018] The gate of the sixth transistor is connected to the scan control signal terminal, the second terminal of the sixth transistor is connected to the anode of the light-emitting device and the anode potential control module, and the cathode of the light-emitting device is connected to the negative terminal of the power supply.

[0019] In one possible implementation, the reset module includes a first transistor and a first capacitor, and the anode potential control module includes a seventh transistor;

[0020] The gate of the first transistor is connected to the reset signal control terminal, the first terminal of the first transistor is connected to the second terminal of the first capacitor, and the second terminal of the first transistor is connected to the first reset signal input terminal.

[0021] The first terminal of the first capacitor is connected to the power supply voltage terminal;

[0022] The gate of the seventh transistor is connected to the gate control signal terminal, the first terminal of the seventh transistor is connected to the anode of the light-emitting device, and the second terminal of the seventh transistor is connected to the second reset signal input terminal.

[0023] In one possible implementation, the reset module includes a first transistor, an eighth transistor, and a first capacitor, and the anode potential control module includes a seventh transistor;

[0024] The gate of the first transistor is connected to the reset signal control terminal, the first terminal of the first transistor is connected to the second terminal of the first capacitor, and the second terminal of the first transistor is connected to the first terminal of the eighth transistor.

[0025] The first terminal of the first capacitor is connected to the power supply voltage terminal;

[0026] The gate of the eighth transistor is connected to the reset signal control terminal, and the second terminal of the eighth transistor is connected to the first reset signal input terminal.

[0027] The gate of the seventh transistor is connected to the gate control signal terminal, the first terminal of the seventh transistor is connected to the anode of the light-emitting device, and the second terminal of the seventh transistor is connected to the second reset signal input terminal.

[0028] In one possible implementation, the anode potential control module includes a seventh transistor and a ninth transistor; the reset module includes a first transistor and a first capacitor.

[0029] The gate of the seventh transistor is connected to the gate control signal terminal, the first terminal of the seventh transistor is connected to the anode of the light-emitting device, and the second terminal of the seventh transistor is connected to the first terminal of the ninth transistor.

[0030] The gate of the ninth transistor is connected to the gate control signal terminal, and the second terminal of the ninth transistor is connected to the second reset signal input terminal;

[0031] The gate of the first transistor is connected to the reset signal control terminal, the first terminal of the first transistor is connected to the second terminal of the first capacitor, and the second terminal of the first transistor is connected to the first reset signal input terminal.

[0032] The first terminal of the first capacitor is connected to the power supply voltage terminal.

[0033] In one possible implementation, the gate of the second transistor is specifically connected to the first gate control signal terminal; the gate of the fourth transistor is specifically connected to the second gate control signal terminal; and the gate of the seventh transistor is specifically connected to the second gate control signal terminal.

[0034] In one possible implementation, the data writing module further includes a tenth transistor, the gate of which is connected to a second reset signal control terminal, the second terminal of which is connected to a third reset signal input terminal, the first terminal of which is connected to the second terminal of a fourth transistor, and the gate of which is specifically connected to a first reset signal control terminal.

[0035] Secondly, embodiments of this application provide a pixel circuit, the circuit comprising:

[0036] Reset module, compensation module, drive module, data writing module, anode potential control module, and light-emitting device;

[0037] The reset module, the compensation module, the data writing module, and the anode potential control module are respectively connected to the driving module, and the driving module is connected to the light-emitting device;

[0038] The first reset signal input terminal of the reset module, the second reset signal input terminal of the anode potential control module, and the third reset signal input terminal of the data writing module are used to connect to the initialization signal line; the third reset signal input terminal is also connected to a capacitor.

[0039] In one possible implementation, the data writing module includes a fourth transistor, a tenth transistor, and a fourth capacitor;

[0040] The gate of the fourth transistor is connected to the control signal terminal of the second gate, the first terminal of the fourth transistor is connected to the data signal voltage terminal, and the second terminal of the fourth transistor is connected to the driving module.

[0041] The gate of the tenth transistor is connected to the second reset signal control terminal, the first terminal of the tenth transistor is connected to the third reset signal input terminal, and the second terminal of the tenth transistor is connected to the second terminal of the fourth transistor.

[0042] The first terminal of the fourth capacitor is connected to the power supply voltage terminal, and the second terminal of the fourth capacitor is connected to the first terminal of the tenth transistor.

[0043] In one possible implementation, the data writing module further includes an eleventh transistor, the gate of which is connected to a first reset signal control terminal, the first terminal of which is connected to a third reset signal input terminal, and the second terminal of which is connected to the second terminal of the fourth capacitor and the first terminal of the tenth transistor, respectively.

[0044] Thirdly, embodiments of this application provide a display, including a first driving chip, a pixel circuit as described in any of the first aspects above, and a pixel circuit as described in any of the second aspects above, wherein the first driving chip provides a gate driving signal and a scan control signal to the pixel circuit.

[0045] In one possible implementation, the display further includes a second driver chip that provides initialization signals to the pixel circuit partitions via initialization signal lines.

[0046] In one possible implementation, the second driver chip is connected to multiple first initialization signal lines, each of which is connected to a first reset signal input terminal and a second reset signal input terminal of a pixel circuit in at least one row of pixels, wherein the second driver chip independently provides an initialization signal through each of the first initialization signal lines.

[0047] In one possible implementation, the second driver chip is connected to multiple first initialization signal lines, each of which is connected to a first reset signal input terminal of a pixel circuit in at least one row of pixels. The first driver chip is also connected to a third initialization signal line, which is connected to a second reset signal input terminal of the pixel circuit in each of the pixel rows. The second driver chip provides an initialization signal independently through each of the first initialization signal lines.

[0048] In one possible implementation, the second driver chip is connected to multiple second initialization signal lines, each of which is connected to a second reset signal input terminal of a pixel circuit in at least one pixel row. The first driver chip is connected to a third initialization signal line, which is connected to a first reset signal input terminal of the pixel circuit in each pixel row. The second driver chip provides an initialization signal independently through each of the second initialization signal lines.

[0049] In one possible implementation, the second driver chip is connected to multiple first initialization signal lines and multiple second initialization signal lines. Each first initialization signal line is connected to a first reset signal input terminal of a pixel circuit in at least one row of pixels, and each second initialization signal line is connected to a second reset signal input terminal of a pixel circuit in at least one row of pixels. The second driver chip provides an initialization signal independently through each of the first initialization signal lines and each of the second initialization signal lines.

[0050] In one possible implementation, the first driver chip provides an initialization signal to the pixel circuit via an initialization signal line.

[0051] Beneficial effects of the embodiments in this application:

[0052] This application provides a pixel circuit and display, including: a reset module, a compensation module, a driving module, a data writing module, an anode potential control module, and a light-emitting device. The reset module, the compensation module, the data writing module, and the anode potential control module are respectively connected to the driving module, and the driving module is connected to the light-emitting device. The first reset signal input terminal of the reset module and the second reset signal input terminal of the anode potential control module are used to connect to an initialization signal line. At least one of the first reset signal input terminals and the second reset signal input terminal is also connected to a capacitor. By setting a capacitor at at least one of the first reset signal input terminals of the reset module and the second reset signal input terminal of the anode potential control module to maintain the potential until the next frame is refreshed, and by connecting the initialization signal line, the OLED display screen can be zoned and controlled to enhance the uniformity of the OLED display screen.

[0053] Of course, implementing any product or method of this application does not necessarily require achieving all of the advantages described above at the same time. Attached Figure Description

[0054] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other embodiments can be obtained based on these drawings.

[0055] Figure 1 This is an OLED pixel circuit in related technologies;

[0056] Figure 2 for Figure 1The timing diagram of the pixel circuit initialization stage and signal writing stage is shown.

[0057] Figure 3 for Figure 1 A schematic diagram of the display structure corresponding to the pixel circuit shown;

[0058] Figure 4 This is a schematic diagram of a first structure of a pixel circuit provided in an embodiment of this application;

[0059] Figure 5 This is a schematic diagram of a second structure of the pixel circuit provided in an embodiment of this application;

[0060] Figure 6 This is a schematic diagram of a third structure of the pixel circuit provided in an embodiment of this application;

[0061] Figure 7a This is a schematic diagram of a fourth structure of the pixel circuit provided in an embodiment of this application;

[0062] Figure 7b for Figure 7a The timing diagram of the pixel circuit initialization stage and signal writing stage is shown.

[0063] Figure 8a This is a schematic diagram of a fifth structure of the pixel circuit provided in an embodiment of this application;

[0064] Figure 8b for Figure 8a The timing diagram of the pixel circuit initialization stage and signal writing stage is shown.

[0065] Figure 9a A schematic diagram of a sixth structure of a pixel circuit provided in an embodiment of this application;

[0066] Figure 9b for Figure 9a The timing diagram of the pixel circuit initialization stage and signal writing stage is shown.

[0067] Figure 10a A schematic diagram of a seventh structure of a pixel circuit provided in an embodiment of this application;

[0068] Figure 10b for Figure 10a The timing diagram of the pixel circuit initialization stage and signal writing stage is shown.

[0069] Figure 11 This is a schematic diagram of an eighth structure of a pixel circuit provided in an embodiment of this application;

[0070] Figure 12a A schematic diagram of a ninth structure of a pixel circuit provided in an embodiment of this application;

[0071] Figure 12b for Figure 12a The timing diagram of the pixel circuit initialization stage and signal writing stage is shown.

[0072] Figure 13a A schematic diagram of the tenth structure of the pixel circuit provided in the embodiments of this application;

[0073] Figure 13b for Figure 13a The timing diagram of the pixel circuit initialization stage and signal writing stage is shown.

[0074] Figure 14a This is an eleventh structural schematic diagram of a pixel circuit provided in an embodiment of this application;

[0075] Figure 14b for Figure 14a The timing diagram of the pixel circuit initialization stage and signal writing stage is shown.

[0076] Figure 15a This is a schematic diagram of the twelfth structure of the pixel circuit provided in the embodiments of this application;

[0077] Figure 15b for Figure 15a The timing diagram of the pixel circuit initialization stage and signal writing stage is shown.

[0078] Figure 16 This is a schematic diagram of the thirteenth structure of the pixel circuit provided in the embodiments of this application;

[0079] Figure 17a This is a schematic diagram of the fourteenth structure of the pixel circuit provided in the embodiments of this application;

[0080] Figure 17b for Figure 17a The timing diagram of the pixel circuit initialization stage and signal writing stage is shown.

[0081] Figure 18a This is a schematic diagram of the fifteenth structure of the pixel circuit provided in the embodiments of this application;

[0082] Figure 18b for Figure 18a The timing diagram of the pixel circuit initialization stage and signal writing stage is shown.

[0083] Figure 19a This is a schematic diagram of the sixteenth structure of the pixel circuit provided in the embodiments of this application;

[0084] Figure 19b for Figure 19a The timing diagram of the pixel circuit initialization stage and signal writing stage is shown.

[0085] Figure 20a This is a schematic diagram of the seventeenth structure of the pixel circuit provided in the embodiments of this application;

[0086] Figure 20b for Figure 20a The timing diagram of the pixel circuit initialization stage and signal writing stage is shown.

[0087] Figure 21a This is a schematic diagram of the eighteenth structure of the pixel circuit provided in the embodiments of this application;

[0088] Figure 21b for Figure 21a The timing diagram of the pixel circuit initialization stage and signal writing stage is shown.

[0089] Figure 22a This is a schematic diagram of the nineteenth structure of the pixel circuit provided in the embodiments of this application;

[0090] Figure 22b for Figure 22a The timing diagram of the pixel circuit initialization stage and signal writing stage is shown.

[0091] Figure 23a This is a schematic diagram of the twentieth structure of the pixel circuit provided in the embodiments of this application;

[0092] Figure 23b for Figure 23a The timing diagram of the pixel circuit initialization stage and signal writing stage is shown.

[0093] Figure 24a This is a schematic diagram of the twenty-first structure of the pixel circuit provided in the embodiments of this application;

[0094] Figure 24b for Figure 24a The timing diagram of the pixel circuit initialization stage and signal writing stage is shown.

[0095] Figure 25 This is a schematic diagram of a first structure of another pixel circuit provided in an embodiment of this application;

[0096] Figure 26a This is a schematic diagram of a second structure of a pixel circuit provided in an embodiment of this application;

[0097] Figure 26b for Figure 26a The timing diagram of the pixel circuit initialization stage and signal writing stage is shown.

[0098] Figure 27a This is a schematic diagram of a third structure of a pixel circuit provided in an embodiment of this application;

[0099] Figure 27b for Figure 27a The timing diagram of the pixel circuit initialization stage and signal writing stage is shown.

[0100] Figure 28 This is a schematic diagram of a first structure of a display provided in an embodiment of this application;

[0101] Figure 29 This is a schematic diagram of a second structure of a display provided in an embodiment of this application;

[0102] Figure 30 This is a schematic diagram of a third structure of a display provided in an embodiment of this application;

[0103] Figure 31 This is a schematic diagram of a fourth structure of a display provided in an embodiment of this application;

[0104] Figure 32 A schematic diagram of a fifth structure of a display provided in an embodiment of this application;

[0105] Figure 33 A schematic diagram of a sixth structure of a display provided in an embodiment of this application;

[0106] Figure 34a A schematic diagram of a seventh structure of a display provided in an embodiment of this application;

[0107] Figure 34b for Figure 34a The timing diagrams for the corresponding initialization and signal writing phases are shown in the design.

[0108] Figure 35a A schematic diagram of an eighth structure of a display provided in an embodiment of this application;

[0109] Figure 35b for Figure 35a The timing diagrams for the corresponding initialization and signal writing phases are shown in the design.

[0110] Figure 36 A ninth structural schematic diagram of a display provided in an embodiment of this application;

[0111] Figure 37 A schematic diagram of a tenth structure of a display provided in an embodiment of this application;

[0112] Figure 38 This is an eleventh structural schematic diagram of a display provided in an embodiment of this application;

[0113] Figure 39 This is a schematic diagram of the twelfth structure of the display provided in the embodiments of this application;

[0114] Figure 40 This is a schematic diagram of the thirteenth structure of the display provided in this application embodiment. Detailed Implementation

[0115] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art based on this application are within the scope of protection of this application.

[0116] First, a brief explanation of the OLED (Organic Light-Emitting Diode) pixel circuitry in related technologies will be provided. For example... Figure 1 The diagram shows an OLED pixel circuit from related technologies, consisting of 7 transistors and 1 storage capacitor, hence the abbreviation 7T1C structure. Many similar circuit structures exist, including 6T1C, 5T2C, 8T1C, 8T2C, and 9T2C. Here, VDD is the power supply voltage, Vdata is the data signal voltage, Reset is the reset signal control terminal, Vinit is the reset signal input terminal, Gate is the gate control signal terminal, EM is the scan control signal terminal, and VSS is the negative power supply terminal. Vinit is a fixed voltage used to reset point N1 of the pixel circuit and the anode of the light-emitting device. The timing diagrams for the initialization and signal writing phases of this pixel circuit are shown below. Figure 2 As shown. During the initialization phase, Reset is low, transistor T1 is turned on, and Vinit resets point N1; during the signal writing phase, Gate is low, transistor T7 is turned on, and Vinit resets the anode of the light-emitting device. Figure 3 This is a simplified schematic diagram of a display corresponding to the aforementioned pixel circuit. The display includes a driver chip and the aforementioned pixel circuit. The driver chip is connected to an initialization signal line, which is connected to the reset signal input terminal Vinit of the pixel circuit in each pixel row. The driver chip provides initialization signals to the pixel circuits through the initialization signal line, and also provides gate drive signals and scan control signals to the pixel circuits. Vinit is output through the driver chip, enters from all sides, and is short-circuited to each pixel circuit in the OLED display.

[0117] For OLED displays, to ensure optimal image quality, the reset signal input to the Vinit terminal differs at different refresh rates. However, the pixel circuit and display design described above cannot perform zoned control of the display area. Therefore, when entering zoned frequency conversion mode, the image quality varies in different areas, resulting in poor uniformity of the OLED display image.

[0118] To enhance the uniformity of OLED display images, embodiments of this application provide a pixel circuit and a display.

[0119] Next, a pixel circuit 1 provided in the embodiments of this application will be described in detail. See [link to relevant documentation]. Figure 4 The pixel circuit 1 includes:

[0120] The system includes a reset module 11, a compensation module 12, a drive module 13, a data writing module 14, an anode potential control module 15, and a light-emitting device 16.

[0121] The reset module 11, the compensation module 12, the data writing module 14 and the anode potential control module 15 are respectively connected to the driving module 13, and the driving module 13 is connected to the light-emitting device 16;

[0122] The first reset signal input terminal of the reset module 11 and the second reset signal input terminal of the anode potential control module 15 are used to connect to the initialization signal line; at least one of the first reset signal input terminal and the second reset signal input terminal is also connected to a capacitor.

[0123] exist Figure 4 In the dashed box, the second and third capacitors can be configured in three ways: a second capacitor can be set at the first reset signal input terminal and no capacitor can be set at the second reset signal input terminal; a third capacitor can be set at the second reset signal input terminal and no capacitor can be set at the first reset signal input terminal; or a second capacitor can be set at the first reset signal input terminal and a third capacitor can be set at the second reset signal input terminal.

[0124] Taking the example of setting capacitors at all reset signal input terminals, compared with pixel circuit designs in related technologies, when the reset signal control terminal is turned on, the drive signal points of the pixel circuit are reset, for example, for... Figure 7a The N2 point is reset; when the gate control signal terminal is turned on, the anode of the light-emitting device is reset, and the two capacitors set at the reset signal input terminal are charged so that the potential can be maintained even after the reset signal control terminal and the gate control signal terminal are turned off, until the next frame is refreshed.

[0125] In this embodiment, a capacitor is provided at at least one of the first reset signal input terminals of the reset module and the second reset signal input terminal of the anode potential control module to maintain the potential until the next frame is refreshed. Based on this, the OLED display screen can be partitioned and controlled by the connection method of the initialization signal line to enhance the uniformity of the OLED display screen.

[0126] In one possible implementation, see Figure 5The data writing module 14 includes a fourth transistor T4, the compensation module 12 includes a second transistor T2, and the driving module 13 includes a third transistor T3, a fifth transistor T5, and a sixth transistor T6.

[0127] The gate of the second transistor T2 is connected to the gate control signal terminal, the first terminal of the second transistor T2 is connected to the second terminal of the third transistor T3 and the first terminal of the sixth transistor T6 respectively, and the second terminal of the second transistor T2 is connected to the reset module 11.

[0128] The gate of the third transistor T3 is connected to the reset module 11, and the first terminal of the third transistor T3 is connected to the second terminal of the fourth transistor T4 and the second terminal of the fifth transistor T5, respectively.

[0129] The gate of the fourth transistor T4 is connected to the gate control signal terminal Gate, and the first terminal of the fourth transistor T4 is connected to the data signal voltage terminal Vdata.

[0130] The gate of the fifth transistor T5 is connected to the scan control signal terminal EM, and the first terminal of the fifth transistor T5 is connected to the power supply voltage terminal VDD.

[0131] The gate of the sixth transistor T6 is connected to the scan control signal terminal EM, the second terminal of the sixth transistor T6 is connected to the anode of the light-emitting device OLED and the anode potential control module 15, and the cathode of the light-emitting device OLED is connected to the negative terminal of the power supply VSS.

[0132] In one possible implementation, see Figure 6 The reset module 11 includes a first transistor T1 and a first capacitor C1, and the anode potential control module 15 includes a seventh transistor T7;

[0133] The gate of the first transistor T1 is connected to the reset signal control terminal Reset, the first terminal of the first transistor T1 is connected to the second terminal of the first capacitor C1, and the second terminal of the first transistor T1 is connected to the first reset signal input terminal.

[0134] The first terminal of the first capacitor C1 is connected to the power supply voltage terminal VDD;

[0135] The gate of the seventh transistor T7 is connected to the gate control signal terminal Gate, the first terminal of the seventh transistor T7 is connected to the anode of the light-emitting device OLED, and the second terminal of the seventh transistor T7 is connected to the second reset signal input terminal.

[0136] In one possible implementation, the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 are all P-type transistors;

[0137] The first terminal of the first transistor T1 is the source of the P-type transistor, and the second terminal of the first transistor T1 is the drain of the P-type transistor.

[0138] The first terminal of the second transistor T2 is the source of the P-type transistor, and the second terminal of the second transistor T2 is the drain of the P-type transistor.

[0139] The first terminal of the third transistor T3 is the source of the P-type transistor, and the second terminal of the third transistor T3 is the drain of the P-type transistor.

[0140] The first terminal of the fourth transistor T4 is the source of the P-type transistor, and the second terminal of the fourth transistor T4 is the drain of the P-type transistor.

[0141] The first terminal of the fifth transistor T5 is the source of the P-type transistor, and the second terminal of the fifth transistor T5 is the drain of the P-type transistor.

[0142] The first terminal of the sixth transistor T6 is the source of the P-type transistor, and the second terminal of the sixth transistor T6 is the drain of the P-type transistor.

[0143] The first terminal of the seventh transistor T7 is the source of the P-type transistor, and the second terminal of the seventh transistor T7 is the drain of the P-type transistor.

[0144] It is understood that any transistor in the circuit of this application can be an N-type transistor or a P-type transistor, whichever is chosen according to the actual situation; the first terminal of the transistor is the source or drain, and the second terminal of the transistor is the drain or source corresponding to the first terminal. It is understood that the transistor can be a P-type transistor or an N-type transistor, whichever is chosen according to the actual situation, but the device connection method of the circuit needs to be adjusted accordingly, and the alternative solution is still within the protection scope of this application.

[0145] It is understood that the transistors used in the circuit of this application can be MOS transistors (metal-oxide-semiconductor field-effect transistors), TFT transistors (thin film transistors), or other types of transistors. The specific choice can be made according to the actual situation. The alternative solutions are still within the protection scope of this application. The connection method of TFT transistors or other types of transistors can be referred to the connection method of MOS transistors, which will not be repeated here.

[0146] In one possible implementation, see Figure 7a The first reset signal input terminal and the second reset signal input terminal are used to connect to the same initialization signal line; the first reset signal input terminal is also connected to the first terminal of the second capacitor C2, and the second terminal of the second capacitor C2 is connected to the positive power supply signal line VDD; the second reset signal input terminal is also connected to the first terminal of the third capacitor C3, and the second terminal of the third capacitor C3 is connected to the positive power supply signal line VDD.

[0147] Figure 7a The timing diagrams for the pixel circuit initialization and signal writing stages are shown below. Figure 7b As shown, during the initialization phase, the Reset signal control terminal is low, the first transistor T1 is turned on, and the N2 point of the pixel circuit is reset through the first reset signal input terminal Vinit. During the signal writing phase, the Gate control signal terminal is low, the seventh transistor T7 is turned on, and the anode of the OLED light-emitting device is reset through the second reset signal input terminal Vinit. Simultaneously, the two capacitors at the reset signal input terminals are charged, ensuring that the voltage remains even after the Reset signal control terminal and the Gate control signal terminal are turned off, until the next frame is refreshed.

[0148] In this embodiment, the first reset signal input terminal and the second reset signal input terminal are connected to the same initialization signal line; the first reset signal input terminal is connected to the second capacitor, and the second reset signal input terminal is connected to the third capacitor.

[0149] In one possible implementation, see Figure 8a The first reset signal input terminal is used to connect to the first initialization signal line, and the second reset signal input terminal is used to connect to the third initialization signal line; the first reset signal input terminal is also connected to the first end of the second capacitor C2, and the second end of the second capacitor C2 is connected to the positive power supply signal line VDD.

[0150] Figure 8aThe timing diagrams for the pixel circuit initialization and signal writing stages are shown below. Figure 8b As shown, during the initialization phase, the reset signal control terminal Reset is low, the first transistor T1 is turned on, and the N2 point of the pixel circuit is reset through the first reset signal input terminal Vinit1. At the same time, the second capacitor set at the first reset signal input terminal is charged, so that the potential can be maintained even after the reset signal control terminal Reset is turned off, until the next frame is refreshed.

[0151] In this embodiment, the first reset signal input terminal and the second reset signal input terminal are connected to different initialization signal lines; the first reset signal input terminal is connected to the second capacitor, and the second reset signal input terminal is not provided with a capacitor.

[0152] In one possible implementation, see Figure 9a The first reset signal input terminal is used to connect to the third initialization signal line, and the second reset signal input terminal is used to connect to the second initialization signal line; the second reset signal input terminal is also connected to the first terminal of the third capacitor C3, and the second terminal of the third capacitor C3 is connected to the positive power supply signal line VDD.

[0153] Figure 9a The timing diagrams for the pixel circuit initialization and signal writing stages are shown below. Figure 9b As shown, during the signal writing phase, the gate control signal terminal (Gate) is at a low level, the seventh transistor (T7) is turned on, and the anode of the OLED is reset through the second reset signal input terminal (Vinit2). Simultaneously, the third capacitor at the second reset signal input terminal is charged, ensuring that the potential is maintained even after the gate control signal terminal (Gate) is turned off until the next frame is refreshed.

[0154] In this embodiment, the first reset signal input terminal and the second reset signal input terminal are connected to different initialization signal lines; the second reset signal input terminal is connected to a third capacitor, and the first reset signal input terminal is not equipped with a capacitor.

[0155] In one possible implementation, see Figure 10a The first reset signal input terminal is used to connect to the first initialization signal line, and the second reset signal input terminal is used to connect to the second initialization signal line; the first reset signal input terminal is also connected to the first end of the second capacitor C2, and the second end of the second capacitor C2 is connected to the positive power supply signal line VDD; the second reset signal input terminal is also connected to the first end of the third capacitor C3, and the second end of the third capacitor C3 is connected to the positive power supply signal line VDD.

[0156] Figure 10a The timing diagrams for the pixel circuit initialization and signal writing stages are shown below. Figure 10b As shown, during the initialization phase, the Reset signal control terminal is low, the first transistor T1 is turned on, and the N2 point of the pixel circuit is reset through the first reset signal input terminal Vinit1. During the signal writing phase, the Gate control signal terminal is low, the seventh transistor T7 is turned on, and the anode of the OLED light-emitting device is reset through the second reset signal input terminal Vinit2. Simultaneously, the two capacitors at the reset signal input terminals are charged, ensuring that the voltage remains even after the Reset signal control terminal and the Gate control signal terminal are turned off, until the next frame is refreshed.

[0157] In this embodiment, the first reset signal input terminal and the second reset signal input terminal are connected to different initialization signal lines; the first reset signal input terminal is connected to the second capacitor, and the second reset signal input terminal is connected to the third capacitor.

[0158] The gates of the second transistor, the fourth transistor, and the seventh transistor can be connected to the same gate control signal terminal (using the same gate control signal source), or they can be connected to different gate control signal terminals. In one possible implementation, the gate of the second transistor is specifically connected to the first gate control signal terminal; the gate of the fourth transistor is specifically connected to the second gate control signal terminal; and the gate of the seventh transistor is specifically connected to the second gate control signal terminal.

[0159] In one possible implementation, the pixel circuit in the embodiments of this application can be as follows: Figure 11 ,and Figure 6 Compared to the pixel circuit shown, the gate of the second transistor T2 is specifically connected to the first gate control signal terminal NGate; the gate of the fourth transistor T4 is specifically connected to the second gate control signal terminal PGate; and the gate of the seventh transistor T7 is specifically connected to the second gate control signal terminal PGate.

[0160] In one possible implementation, the pixel circuit in the embodiments of this application can be as follows: Figure 12a ,and Figure 7a Compared to the pixel circuit shown, the gate of the second transistor T2 is specifically connected to the first gate control signal terminal NGate; the gate of the fourth transistor T4 is specifically connected to the second gate control signal terminal PGate; and the gate of the seventh transistor T7 is specifically connected to the second gate control signal terminal PGate.

[0161] Figure 12a The timing diagrams for the pixel circuit initialization and signal writing stages are shown below. Figure 12bAs shown, during the initialization phase, the first reset signal control terminal NReset is high, the first transistor T1 is turned on, and the N2 point of the pixel circuit is reset through the first reset signal input terminal Vinit. During the signal writing phase, the second gate control signal terminal PGate is low, the seventh transistor T7 is turned on, and the anode of the OLED light-emitting device is reset through the second reset signal input terminal Vinit. Simultaneously, the two capacitors at the reset signal input terminals are charged, ensuring that the voltage remains constant even after the first reset signal control terminal NReset and the second gate control signal terminal PGate are turned off, until the next frame is refreshed.

[0162] In one example, in Figure 12a In the pixel circuit shown, the first transistor T1 is an N-type transistor, the seventh transistor T7 is a P-type transistor, the second transistor T2 is an N-type transistor, and the fourth transistor T4 is a P-type transistor. During the signal writing phase, the second gate control signal terminal PGate is low, and the fourth transistor T4 is turned on; the first gate control signal terminal NGate is high, and the second transistor T2 is turned on. At the same time, the third transistor T3 also meets the turn-on condition. The data signal voltage Vdata is written to the first capacitor C1 through the fourth transistor T4, the third transistor T3, and the second transistor T2.

[0163] In one possible implementation, the pixel circuit in the embodiments of this application can be as follows: Figure 13a As shown, with Figure 8a Compared to the pixel circuit shown, the gate of the second transistor T2 is specifically connected to the first gate control signal terminal NGate; the gate of the fourth transistor T4 is specifically connected to the second gate control signal terminal PGate; and the gate of the seventh transistor T7 is specifically connected to the second gate control signal terminal PGate.

[0164] Figure 13a The timing diagrams for the pixel circuit initialization and signal writing stages are shown below. Figure 13b As shown, during the initialization phase, the first reset signal control terminal NReset is high, the first transistor T1 is turned on, and the N2 point of the pixel circuit is reset through the first reset signal input terminal Vinit1. At the same time, the second capacitor set at the first reset signal input terminal is charged, so that the potential can be maintained even after the first reset signal control terminal NReset is turned off, until the next frame is refreshed.

[0165] In one example, Figure 13aIn the pixel circuit shown, the first transistor T1 is an N-type transistor, the seventh transistor T7 is a P-type transistor, the second transistor T2 is an N-type transistor, and the fourth transistor T4 is a P-type transistor. During the signal writing stage, the second gate control signal terminal PGate is low, and the fourth transistor T4 is turned on; the first gate control signal terminal NGate is high, and the second transistor T2 is turned on. At the same time, the third transistor T3 also meets the turn-on condition. The data signal voltage Vdata is written to the first capacitor C1 through the fourth transistor T4, the third transistor T3, and the second transistor T2.

[0166] In one possible implementation, the pixel circuit in the embodiments of this application can be as follows: Figure 14a As shown, with Figure 9a Compared to the pixel circuit shown, the gate of the second transistor T2 is specifically connected to the first gate control signal terminal NGate; the gate of the fourth transistor T4 is specifically connected to the second gate control signal terminal PGate; and the gate of the seventh transistor T7 is specifically connected to the second gate control signal terminal PGate.

[0167] Figure 14a The timing diagrams for the pixel circuit initialization and signal writing stages shown can be as follows: Figure 14b As shown, during the signal writing phase, the second gate control signal terminal PGate is at a low level, the seventh transistor T7 is turned on, and the anode of the OLED is reset through the second reset signal input terminal Vinit2. Simultaneously, the third capacitor at the second reset signal input terminal is charged, ensuring that the voltage remains even after the second gate control signal terminal PGate is turned off until the next frame is refreshed.

[0168] In one example, Figure 14a In the pixel circuit shown, the first transistor T1 is an N-type transistor, the seventh transistor T7 is a P-type transistor, the second transistor T2 is an N-type transistor, and the fourth transistor T4 is a P-type transistor. During the signal writing stage, the second gate control signal terminal PGate is low, and the fourth transistor T4 is turned on; the first gate control signal terminal NGate is high, and the second transistor T2 is turned on. At the same time, the third transistor T3 also meets the turn-on condition. The data signal voltage Vdata is written to the first capacitor C1 through the fourth transistor T4, the third transistor T3, and the second transistor T2.

[0169] In one possible implementation, the pixel circuit in the embodiments of this application can be as follows: Figure 15a As shown, with Figure 10aCompared to the pixel circuit shown, the gate of the second transistor T2 is specifically connected to the first gate control signal terminal NGate; the gate of the fourth transistor T4 is specifically connected to the second gate control signal terminal PGate; and the gate of the seventh transistor T7 is specifically connected to the second gate control signal terminal PGate.

[0170] Figure 15a The timing diagrams for the pixel circuit initialization and signal writing stages shown can be as follows: Figure 15b As shown, during the initialization phase, the first reset signal control terminal NReset is high, the first transistor T1 is turned on, and the N2 point of the pixel circuit is reset through the first reset signal input terminal Vinit1. During the signal writing phase, the second gate control signal terminal PGate is low, the seventh transistor T7 is turned on, and the anode of the OLED light-emitting device is reset through the second reset signal input terminal Vinit2. Simultaneously, the two capacitors at the reset signal input terminals are charged, ensuring that the voltage remains constant even after the first reset signal control terminal NReset and the second gate control signal terminal PGate are turned off, until the next frame is refreshed.

[0171] In one example, Figure 15a In the pixel circuit shown, the first transistor T1 is an N-type transistor, the seventh transistor T7 is a P-type transistor, the second transistor T2 is an N-type transistor, and the fourth transistor T4 is a P-type transistor. During the signal writing stage, the second gate control signal terminal PGate is low, and the fourth transistor T4 is turned on; the first gate control signal terminal NGate is high, and the second transistor T2 is turned on. At the same time, the third transistor T3 also meets the turn-on condition. The data signal voltage Vdata is written to the first capacitor C1 through the fourth transistor T4, the third transistor T3, and the second transistor T2.

[0172] In one possible implementation, the data writing module further includes a tenth transistor, the gate of which is connected to a second reset signal control terminal, the first terminal of which is connected to a third reset signal input terminal, the second terminal of which is connected to the second terminal of a fourth transistor, and the gate of the first transistor is specifically connected to a first reset signal control terminal.

[0173] In one possible implementation, the pixel circuit in the embodiments of this application can be as follows: Figure 16 As shown, with Figure 11Compared to the pixel circuit shown, the data writing module 14 further includes a tenth transistor T10. The gate of the tenth transistor T10 is connected to the second reset signal control terminal PRESET, the second terminal of the tenth transistor T10 is connected to the third reset signal input terminal Vinit3, the first terminal of the tenth transistor T10 is connected to the second terminal of the fourth transistor T4, and the gate of the first transistor T1 is specifically connected to the first reset signal control terminal NReset.

[0174] In one possible implementation, the pixel circuit in the embodiments of this application can be as follows: Figure 17a As shown, with Figure 13a Compared to the pixel circuit shown, the data writing module 14 also includes a tenth transistor T10, and the specific connection relationship is as described above.

[0175] Figure 17a The timing diagrams for the pixel circuit initialization and signal writing stages shown can be as follows: Figure 17b As shown, before resetting point N2 of the pixel circuit, the second reset signal control terminal PREset is low, the tenth transistor T10 (P-type transistor) is turned on, and the second terminal of the fourth transistor T4 is reset through the third reset signal input terminal Vinit3.

[0176] In this embodiment, the second terminal of the fourth transistor is reset by controlling the tenth transistor to turn on.

[0177] In one possible implementation, the pixel circuit in the embodiments of this application can Figure 18a As shown, with Figure 14a Compared to the pixel circuit shown, the data writing module 14 also includes a tenth transistor T10, and the specific connection relationship is as described above.

[0178] Figure 18a The timing diagrams for the pixel circuit initialization and signal writing stages shown can be as follows: Figure 18b As shown, before resetting point N2 of the pixel circuit, the second reset signal control terminal PREset is low, the tenth transistor T10 (P-type transistor) is turned on, and the second terminal of the fourth transistor T4 is reset through the third reset signal input terminal Vinit3.

[0179] In this embodiment, the second terminal of the fourth transistor is reset by controlling the tenth transistor to turn on.

[0180] based on Figure 12a The analysis of the pixel circuit shown, including the tenth transistor T10, is the same as described above and will not be repeated here; based on Figure 15a The analysis of the pixel circuit shown, including the tenth transistor T10, is the same as described above, and will not be repeated here.

[0181] The above Figures 7a-18a In the embodiment of the pixel circuit shown, the second driver chip is connected to the first initialization signal line and the second initialization signal line, and the first driver chip is connected to the third initialization signal line. In the case where the display does not include the second driver chip, the initialization signal is provided by the first driver chip. The control of the first reset signal input and the second reset signal input can be realized through the following embodiments.

[0182] In one possible implementation, the pixel circuit in the embodiments of this application can Figure 19a As shown, with Figure 5 Compared to the pixel circuit shown, the reset module 11 includes a first transistor T1, an eighth transistor T8, and a first capacitor C1, and the anode potential control module 15 includes a seventh transistor T7.

[0183] The gate of the first transistor T1 is connected to the reset signal control terminal Reset, the first terminal of the first transistor T1 is connected to the second terminal of the first capacitor C1, and the second terminal of the first transistor T1 is connected to the first terminal of the eighth transistor T8.

[0184] The first terminal of the first capacitor C1 is connected to the power supply voltage terminal VDD;

[0185] The gate of the eighth transistor T8 is connected to the reset signal control terminal Reset, and the second terminal of the eighth transistor T8 is connected to the first reset signal input terminal Vinit1.

[0186] The gate of the seventh transistor T7 is connected to the gate control signal terminal Gate, the first terminal of the seventh transistor T7 is connected to the anode of the light-emitting device OLED, and the second terminal of the seventh transistor T7 is connected to the second reset signal input terminal Vinit2.

[0187] Figure 19a The timing diagrams for the pixel circuit initialization and signal writing stages shown can be as follows: Figure 19b As shown, during the initialization phase, the second reset signal control terminal PRESET is low, the first transistor T1 is turned on, the eighth transistor T8 is turned on, and the N2 point of the pixel circuit is reset through the first reset signal input terminal Vinit1. At the same time, the second capacitor set at the first reset signal input terminal is charged, so that it can maintain its potential even after the second reset signal control terminal PRESET is turned off, until the next frame is refreshed.

[0188] In one example, Figure 19aThe transistors in the pixel circuit shown are all P-type transistors, therefore the gate control signal terminal Gate is PGate, and the reset signal control terminal Reset is PReset. Figure 19a The transistors in the pixel circuit shown can also be N-type transistors, and the corresponding connection methods and timing will also change, which will not be elaborated here.

[0189] In this embodiment of the application, the input of the first reset signal input terminal Vinit1 can be controlled by controlling the turn-on and turn-off of the eighth transistor.

[0190] In one possible implementation, the pixel circuit in the embodiments of this application can Figure 20a ,and Figure 5 Compared to the pixel circuit shown, the anode potential control module 15 includes a seventh transistor T7 and a ninth transistor T9; the reset module 11 includes a first transistor T1 and a first capacitor C1.

[0191] The gate of the seventh transistor T7 is connected to the gate control signal terminal Gate, the first terminal of the seventh transistor T7 is connected to the anode of the light-emitting device OLED, and the second terminal of the seventh transistor T7 is connected to the first terminal of the ninth transistor T9;

[0192] The gate of the ninth transistor T9 is connected to the gate control signal terminal Gate, and the second terminal of the ninth transistor T9 is connected to the second reset signal input terminal Vinit2;

[0193] The gate of the first transistor T1 is connected to the reset signal control terminal Reset, the first terminal of the first transistor T1 is connected to the second terminal of the first capacitor C1, and the second terminal of the first transistor T1 is connected to the first reset signal input terminal Vinit1.

[0194] The first terminal of the first capacitor C1 is connected to the power supply voltage terminal VDD.

[0195] Figure 20a The timing diagrams for the pixel circuit initialization and signal writing stages shown can be as follows: Figure 20b As shown, during the signal writing phase, the second gate control signal terminal PGate is at a low level, the seventh transistor T7 is turned on, and the ninth transistor T9 is turned on. The anode of the OLED light-emitting device is reset through the second reset signal input terminal Vinit2. At the same time, the third capacitor set at the second reset signal input terminal is charged, so that the potential can be maintained even after the second gate control signal terminal PGate is turned off, until the next frame is refreshed.

[0196] In one example, Figure 20aThe transistors in the pixel circuit shown are all P-type transistors, therefore the gate control signal terminal Gate is PGate, and the reset signal control terminal Reset is PReset. Figure 20a The transistors in the pixel circuit shown can also be N-type transistors, and the corresponding connection methods and timing will also change, which will not be elaborated here.

[0197] In this embodiment, the input of the second reset signal input terminal Vinit2 can be controlled by controlling the turning on and off of the ninth transistor.

[0198] In one possible implementation, the reset module 11 includes a first transistor T1, an eighth transistor T8, and a first capacitor C1, while the anode potential control module 15 may include a seventh transistor T7 and a ninth transistor T9; a second capacitor may be provided at the first reset signal input terminal (controlling the first reset signal input through the eighth transistor), and a third capacitor may be provided at the second reset signal input terminal (controlling the second reset signal input through the ninth transistor); the first reset signal input terminal and the second reset signal input terminal may be connected to the same initialization signal line or to different initialization signal lines. For detailed analysis, please refer to the above embodiments, which will not be repeated here.

[0199] In one possible implementation, the pixel circuit in the embodiments of this application can Figure 21a ,and Figure 19a Compared to the pixel circuit shown, the gate of the second transistor T2 is specifically connected to the first gate control signal terminal NGate; the gate of the fourth transistor T4 is specifically connected to the second gate control signal terminal PGate; and the gate of the seventh transistor T7 is specifically connected to the second gate control signal terminal PGate.

[0200] Figure 21a The timing diagrams for the pixel circuit initialization and signal writing stages shown can be as follows: Figure 21b As shown, for detailed analysis, please refer to the above embodiments. Figure 13a The analysis of the pixel circuit shown will not be elaborated here.

[0201] In one possible implementation, the pixel circuit in the embodiments of this application can Figure 22a ,and Figure 20a Compared to the pixel circuit shown, the gate of the second transistor T2 is specifically connected to the first gate control signal terminal NGate; the gate of the fourth transistor T4 is specifically connected to the second gate control signal terminal PGate; and the gate of the seventh transistor T7 is specifically connected to the second gate control signal terminal PGate.

[0202] Figure 22aThe timing diagrams for the pixel circuit initialization and signal writing stages shown can be as follows: Figure 22b As shown, for detailed analysis, please refer to the above embodiments. Figure 14a The analysis of the pixel circuit shown will not be elaborated here.

[0203] In one possible implementation, the pixel circuit in the embodiments of this application can Figure 23a As shown, with Figure 21a Compared to the pixel circuit shown, the data writing module 14 further includes a tenth transistor T10. The gate of the tenth transistor T10 is connected to the second reset signal control terminal PRESET, the first terminal of the tenth transistor T10 is connected to the third reset signal input terminal Vinit3, the second terminal of the tenth transistor T10 is connected to the second terminal of the fourth transistor T4, and the gate of the first transistor T1 is specifically connected to the first reset signal control terminal NReset.

[0204] Figure 23a The timing diagrams for the pixel circuit initialization and signal writing stages shown can be as follows: Figure 23b As shown, for detailed analysis, please refer to the above embodiments. Figure 17a The analysis of the pixel circuit shown will not be elaborated here.

[0205] In one possible implementation, the pixel circuit in the embodiments of this application can Figure 24a As shown, with Figure 22a Compared to the pixel circuit shown, the data writing module 14 further includes a tenth transistor T10. The gate of the tenth transistor T10 is connected to the second reset signal control terminal PRESET, the first terminal of the tenth transistor T10 is connected to the third reset signal input terminal Vinit3, the second terminal of the tenth transistor T10 is connected to the second terminal of the fourth transistor T4, and the gate of the first transistor T1 is specifically connected to the first reset signal control terminal NReset.

[0206] Figure 24a The timing diagrams for the pixel circuit initialization and signal writing stages shown can be as follows: Figure 24b As shown, for detailed analysis, please refer to the above embodiments. Figure 18a The analysis of the pixel circuit shown will not be elaborated here.

[0207] This application also provides a pixel circuit 2, see [link to example]. Figure 25 The circuit includes:

[0208] The module includes a reset module 11', a compensation module 12', a drive module 13', a data writing module 14', an anode potential control module 15', and a light-emitting device 16'.

[0209] The reset module 11', the compensation module 12', the data writing module 14' and the anode potential control module 15' are respectively connected to the driving module 13', and the driving module 13' is connected to the light-emitting device 16';

[0210] The first reset signal input terminal of the reset module 11', the second reset signal input terminal of the anode potential control module 15', and the third reset signal input terminal of the data writing module 14' are used to connect the initialization signal line; the third reset signal input terminal is also connected to a capacitor.

[0211] In this embodiment, a capacitor is provided at the third reset signal input terminal of the data writing module to maintain the potential.

[0212] In one possible implementation, see Figure 26a The data writing module 14' includes a fourth transistor T4, a tenth transistor T10, and a fourth capacitor C4;

[0213] The gate of the fourth transistor T4 is connected to the second gate control signal terminal PGate, the first terminal of the fourth transistor T4 is connected to the data signal voltage terminal Vdata, and the second terminal of the fourth transistor T4 is connected to the driving module 13'.

[0214] The gate of the tenth transistor T10 is connected to the second reset signal control terminal PRESet, the first terminal of the tenth transistor T10 is connected to the third reset signal input terminal Vinit3, and the second terminal of the tenth transistor T10 is connected to the second terminal of the fourth transistor T4.

[0215] The first terminal of the fourth capacitor C4 is connected to the power supply voltage terminal VDD, and the second terminal of the fourth capacitor C4 is connected to the first terminal of the tenth transistor T10.

[0216] It should be noted that the reset module, compensation module, drive module, anode potential control module, and light-emitting device, including the components and their connection methods, are detailed in the following references. Figure 26a As shown, part of the same pixel circuit 1 will not be described in detail here.

[0217] Figure 26a The timing diagrams for the pixel circuit initialization and signal writing stages are shown below. Figure 26b As shown.

[0218] In this embodiment, before resetting point N2 of pixel circuit 2, the second reset signal control terminal PRESET is low, the tenth transistor T10 (P-type transistor) is turned on, and the second terminal of the fourth transistor T4 is reset through the third reset signal input terminal Vinit3. Simultaneously, the fourth capacitor located at the third reset signal input terminal is charged, ensuring that the voltage is maintained even after the second reset signal control terminal PRESET is turned off.

[0219] The above Figure 26a The display corresponding to the pixel circuit shown includes a second driver chip. In the case where the display does not include a second driver chip, the initialization signal is provided by the first driver chip. The control of the third reset signal input can be achieved through the following embodiments.

[0220] In one possible implementation, see Figure 27a The data writing module 14' further includes an eleventh transistor T11. The gate of the eleventh transistor T11 is connected to the first reset signal control terminal NReset. The first terminal of the eleventh transistor T11 is connected to the third reset signal input terminal Vinit3. The second terminal of the eleventh transistor T11 is connected to the second terminal of the fourth capacitor C4 and the first terminal of the tenth transistor T10, respectively.

[0221] Figure 27a The timing diagrams for the pixel circuit initialization and signal writing stages are shown below. Figure 27b As shown.

[0222] In this embodiment, the input of the third reset signal input terminal Vinit3 can be controlled by controlling the turn-on and turn-off of the eleventh transistor.

[0223] This application also provides a display 3, see [link to relevant documentation] Figure 28 It includes a first driving chip 22 and any of the pixel circuits described in the above embodiments, wherein the first driving chip 22 provides gate driving signals and scan control signals to the pixel circuit.

[0224] In this embodiment, a first driver chip provides gate drive signals and scan control signals to the pixel circuit.

[0225] In one possible implementation, see Figure 29 The display 2 further includes a second driving chip 21, which provides initialization signals to the pixel circuit partitions through an initialization signal line.

[0226] In this embodiment, the second driving chip provides initialization signals to the pixel circuit partitions through initialization signal lines, which can perform partition control of the OLED display screen to enhance the uniformity of the OLED display screen.

[0227] In one possible implementation, see Figure 30 This is a schematic diagram of a third structure of a display provided in an embodiment of this application. The pixel circuit can be as described in the above embodiments. Figure 7a / Figure 12a As shown, the second driver chip 21 is connected to multiple first initialization signal lines. Each first initialization signal line is connected to the first reset signal input terminal Vinit and the second reset signal input terminal Vinit of the pixel circuit in at least one row of pixels. The second driver chip 21 provides an initialization signal independently through each first initialization signal line.

[0228] The second driver chip connects to multiple first initialization signal lines. Each first initialization signal line of the second driver chip can be independently controlled by the Vinit signal. For each first initialization signal line, it is connected to at least one row of pixels. For example, Figure 30 As shown, each first initialization signal line connects to one row of pixels, providing a Vinit signal for that row. Therefore, the Vinit signal for each row of pixels can be controlled independently. In one example, each first initialization signal line connects to two adjacent rows of pixels, providing Vinit signals for both rows. Thus, the Vinit signals for two adjacent rows of pixels can be controlled independently. In other examples, each first initialization signal line connects to three or more rows of pixels, which will not be elaborated here.

[0229] By connecting a second capacitor to the first reset signal input terminal and a third capacitor to the second reset signal input terminal, the potential can be maintained even after the reset signal control terminal Reset and the gate control signal terminal Gate are turned off, until the next frame is refreshed. Based on this, the second driver chip provides an initialization signal independently through each first initialization signal line (the first reset signal input terminal and the second reset signal input terminal are connected to the same initialization signal line), so the OLED display screen can be zoned and controlled, enhancing the uniformity of the OLED display screen.

[0230] In this embodiment, the second driver chip independently provides an initialization signal through each first initialization signal line (the first reset signal input terminal and the second reset signal input terminal are connected to the same initialization signal line), which can perform zone control on the OLED display screen to enhance the uniformity of the OLED display screen.

[0231] In one possible implementation, see Figure 31 This is a schematic diagram of a fourth structure of a display provided in an embodiment of this application. The pixel circuit can be as described in the above embodiments. Figure 8a / Figure 13a As shown, the second driver chip 21 is connected to multiple first initialization signal lines. Each first initialization signal line is connected to the first reset signal input terminal Vinit1 of the pixel circuit in at least one row of pixels. The first driver chip 22 is connected to a third initialization signal line. The third initialization signal line is connected to the second reset signal input terminal Vinit2 of the pixel circuit in each row of pixels. The second driver chip 21 provides an initialization signal independently through each first initialization signal line.

[0232] The first reset signal input terminal is connected to the second capacitor, ensuring that the potential remains even after the reset signal control terminal (Reset) is turned off until the next frame is refreshed. Based on this, the second driver chip independently provides initialization signals through each of the first initialization signal lines (the first reset signal input terminal is connected to the first initialization signal line), thus enabling zoned control of the OLED display and enhancing the uniformity of the OLED display. The second reset signal input terminal does not have a capacitor, and its connection method (Vinit2) is the same as related technologies, connecting to the second reset signal input terminal of the pixel circuit in each pixel row through the third initialization signal line. Vinit2 is output from the first driver chip, enters from all sides, and is short-circuited to each pixel circuit in the OLED display.

[0233] In this embodiment, the second driver chip independently provides an initialization signal through each first initialization signal line (the first reset signal input is connected to the first initialization signal line), which can perform zoned control of the OLED display screen to enhance the uniformity of the OLED display screen.

[0234] In one possible implementation, see Figure 32 This is a schematic diagram of a fifth structure of a display provided in this application embodiment. The pixel circuit can be as described in the above embodiments. Figure 9a / Figure 14a As shown, the second driver chip 21 is connected to multiple second initialization signal lines, each of which is connected to the second reset signal input terminal Vinit2 of the pixel circuit in at least one row of pixels. The first driver chip 22 is connected to a third initialization signal line, which is connected to the first reset signal input terminal Vinit1 of the pixel circuit in each row of pixels. The second driver chip provides an initialization signal independently through each of the second initialization signal lines.

[0235] The second reset signal input is connected to the third capacitor, ensuring that the potential remains even after the gate control signal is turned off until the next frame is refreshed. Based on this, the second driver chip independently provides initialization signals through each second initialization signal line (the second reset signal input is connected to the second initialization signal line), thus enabling zoned control of the OLED display and enhancing the uniformity of the OLED display. The first reset signal input does not have a capacitor, and its connection method (Vinit1) is the same as related technologies, connecting to the first reset signal input of the pixel circuit in each pixel row through the third initialization signal line. Vinit1 is output from the first driver chip, enters from all sides, and is short-circuited to each pixel circuit in the OLED display.

[0236] In this embodiment, the second driver chip independently provides an initialization signal through each second initialization signal line (the second reset signal input is connected to the second initialization signal line), which can perform zoned control of the OLED display screen to enhance the uniformity of the OLED display screen.

[0237] In one possible implementation, see Figure 33 This is a schematic diagram of a sixth structure of a display provided in this application embodiment. The pixel circuit can be as described in the above embodiments. Figure 10a / Figure 15a As shown, the second driver chip 21 is connected to multiple first initialization signal lines and multiple second initialization signal lines. Each first initialization signal line is connected to the first reset signal input terminal Vinit1 of the pixel circuit in at least one row of pixels, and each second initialization signal line is connected to the second reset signal input terminal Vinit2 of the pixel circuit in at least one row of pixels. The second driver chip 21 provides an initialization signal independently through each of the first initialization signal lines and each of the second initialization signal lines.

[0238] By connecting a second capacitor to the first reset signal input terminal and a third capacitor to the second reset signal input terminal, the potential can be maintained even after the reset signal control terminal Reset and the gate control signal terminal Gate are turned off, until the next frame is refreshed. Based on this, the second driver chip provides initialization signals independently through each first initialization signal line and each second initialization signal line (the first reset signal input terminal is connected to the first initialization signal line, and the second reset signal input terminal is connected to the second initialization signal line). Therefore, the OLED display screen can be zoned and controlled, enhancing the uniformity of the OLED display screen.

[0239] In this embodiment, the second driver chip independently provides initialization signals through each first initialization signal line and each second initialization signal line (the first reset signal input terminal is connected to the first initialization signal line, and the second reset signal input terminal is connected to the second initialization signal line), which can perform zone control on the OLED display screen to enhance the uniformity of the OLED display screen.

[0240] In one possible implementation, in the above Figure 33 Based on this, the number of initialization signal lines can be reduced by introducing a Mux (Multiplexing) module design, such as... Figure 34a As shown, this reduces the size of the second driver chip and also reduces the layout space.

[0241] Figure 34a The pixel circuit design corresponding to the display shown can be as follows: Figure 10a / Figure 15a As shown, further details will not be elaborated upon here. Regarding... Figure 34a The timing diagrams for the initialization and signal writing phases in the design are as follows: Figure 34b As shown.

[0242] In one possible implementation, in the above Figure 33 Based on this, when the minimum number of control rows is n (n≥2), the Vinit signals of rows n can be short-circuited, such as... Figure 35a As shown, taking n=2 as an example, the connection method of the initialization signal line is illustrated, thereby reducing the size of the second driver chip and reducing the layout space.

[0243] Figure 35a The pixel circuit design corresponding to the display shown can be as follows: Figure 10a / Figure 15a As shown, further details will not be elaborated upon here. Regarding... Figure 35a The timing diagrams for the initialization and signal writing phases in the design are as follows: Figure 35b As shown.

[0244] In one possible implementation, see Figure 36 This is a schematic diagram of the ninth structure of a display provided in this application embodiment. The pixel circuit can be as described in the above embodiments. Figure 17aAs shown, the second driver chip 21 is connected to multiple first initialization signal lines and multiple fourth initialization signal lines. Each first initialization signal line is connected to the first reset signal input terminal Vinit1 of the pixel circuit in at least one row of pixels. Each fourth initialization signal line is connected to the third reset signal input terminal Vinit3 of the pixel circuit in at least one row of pixels. The first driver chip 22 is connected to a third initialization signal line, which is connected to the second reset signal input terminal Vinit2 of the pixel circuit in each row of pixels. The second driver chip 21 provides an initialization signal independently through each of the first initialization signal lines and each of the fourth initialization signal lines.

[0245] In one possible implementation, see Figure 37 This is a schematic diagram of the tenth structure of a display provided in this application embodiment. The pixel circuit can be as described in the above embodiments. Figure 18a As shown, the second driver chip 21 is connected to multiple second initialization signal lines and multiple fourth initialization lines. Each second initialization signal line is connected to the second reset signal input terminal Vinit2 of the pixel circuit in at least one row of pixels. Each fourth initialization signal line is connected to the third reset signal input terminal Vinit3 of the pixel circuit in at least one row of pixels. The first driver chip 22 is connected to a third initialization signal line, which is connected to the first reset signal input terminal Vinit1 of the pixel circuit in each row of pixels. The second driver chip 21 provides an initialization signal independently through each second initialization signal line and each fourth initialization signal line.

[0246] In one possible implementation, see Figure 38 This is an eleventh structural diagram of a display provided in an embodiment of this application. The pixel circuit can be as described in the above embodiments. Figure 26aAs shown, the second driver chip 21 is connected to multiple first initialization signal lines, multiple second initialization signal lines, and multiple fourth initialization signal lines. Each first initialization signal line is connected to the first reset signal input terminal Vinit1 of the pixel circuit in at least one row of pixels. Each second initialization signal line is connected to the second reset signal input terminal Vinit2 of the pixel circuit in at least one row of pixels. Each fourth initialization signal line is connected to the second reset signal input terminal Vinit3 of the pixel circuit in at least one row of pixels. The second driver chip 21 provides an initialization signal independently through each of the first initialization signal lines, each of the second initialization signal lines, and each of the fourth initialization signal lines.

[0247] In one possible implementation, see Figure 39 This is a schematic diagram of the twelfth structure of the display provided in the embodiments of this application. The pixel circuit can be as described in the above embodiments. Figure 19a / Figure 20a / Figure 21a / Figure 22a As shown, the first driver chip is connected to an initialization signal line. This initialization signal line connects to the first reset signal input terminal Vinit1 and the second reset signal input terminal Vinit2 of the pixel circuits in each pixel row. The first driver chip provides initialization signals to the pixel circuits through the initialization signal line, and also provides gate drive signals and scan control signals to the pixel circuits. Vinit1 and Vinit2 are output from the first driver chip, enter from all sides, and are short-circuited to each pixel circuit in the OLED display.

[0248] In one possible implementation, see Figure 40 This is a thirteenth structural diagram of a display provided in this application embodiment. The pixel circuit can be as described in the above embodiments. Figure 23a / Figure 24a / Figure 27a As shown, the first driver chip is connected to an initialization signal line. This initialization signal line connects to the first reset signal input terminal Vinit1, the second reset signal input terminal Vinit2, and the third reset signal input terminal Vinit3 of the pixel circuits in each pixel row. The first driver chip provides initialization signals to the pixel circuits through this initialization signal line, and also provides gate drive signals and scan control signals to the pixel circuits. Vinit1, Vinit2, and Vinit3 are output from the first driver chip, enter from all sides, and are short-circuited to each pixel circuit in the OLED display.

[0249] It should be noted that, in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0250] The various embodiments in this specification are described in a related manner. Similar or identical parts between embodiments can be referred to mutually. Each embodiment focuses on describing the differences from other embodiments. In particular, the system embodiments are basically similar to the method embodiments, so the description is relatively simple; relevant parts can be referred to the descriptions of the method embodiments.

[0251] The above description is merely a preferred embodiment of this application and is not intended to limit the scope of protection of this application. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application are included within the scope of protection of this application.

Claims

1. A pixel circuit, characterized by comprising: The circuit includes: Reset module, compensation module, drive module, data writing module, anode potential control module, and light-emitting device; The reset module, the compensation module, the data writing module, and the anode potential control module are respectively connected to the driving module, and the driving module is connected to the light-emitting device; The first reset signal input terminal of the reset module and the second reset signal input terminal of the anode potential control module are used to connect to the initialization signal line; The first reset signal input terminal is connected to the first terminal of the second capacitor, and the second terminal of the second capacitor is connected to the positive power supply signal line; and / or, the second reset signal input terminal is connected to the first terminal of the third capacitor, and the second terminal of the third capacitor is connected to the positive power supply signal line.

2. The circuit according to claim 1, characterized in that, The first reset signal input terminal and the second reset signal input terminal are used to connect to the same initialization signal line; the first reset signal input terminal is also connected to the first terminal of the second capacitor, and the second terminal of the second capacitor is connected to the positive power supply signal line; the second reset signal input terminal is also connected to the first terminal of the third capacitor, and the second terminal of the third capacitor is connected to the positive power supply signal line.

3. The circuit according to claim 1, characterized in that, The first reset signal input terminal is used to connect to the first initialization signal line, and the second reset signal input terminal is used to connect to the third initialization signal line; the first reset signal input terminal is also connected to the first end of the second capacitor, and the second end of the second capacitor is connected to the positive power supply signal line.

4. The circuit according to claim 1, characterized in that, The first reset signal input terminal is used to connect to the third initialization signal line, and the second reset signal input terminal is used to connect to the second initialization signal line; the second reset signal input terminal is also connected to the first terminal of the third capacitor, and the second terminal of the third capacitor is connected to the positive power supply signal line.

5. The circuit according to claim 1, characterized in that, The first reset signal input terminal is used to connect to the first initialization signal line, and the second reset signal input terminal is used to connect to the second initialization signal line; the first reset signal input terminal is also connected to the first end of the second capacitor, and the second end of the second capacitor is connected to the positive power supply signal line; the second reset signal input terminal is also connected to the first end of the third capacitor, and the second end of the third capacitor is connected to the positive power supply signal line.

6. The circuit according to claim 1, characterized in that, The data writing module includes a fourth transistor, the compensation module includes a second transistor, and the driving module includes a third transistor, a fifth transistor, and a sixth transistor. The gate of the second transistor is connected to the gate control signal terminal, the first terminal of the second transistor is connected to the second terminal of the third transistor and the first terminal of the sixth transistor, and the second terminal of the second transistor is connected to the reset module. The gate of the third transistor is connected to the reset module, and the first terminal of the third transistor is connected to the second terminal of the fourth transistor and the second terminal of the fifth transistor, respectively. The gate of the fourth transistor is connected to the gate control signal terminal, and the first terminal of the fourth transistor is connected to the data signal voltage terminal. The gate of the fifth transistor is connected to the scan control signal terminal, and the first terminal of the fifth transistor is connected to the power supply voltage terminal. The gate of the sixth transistor is connected to the scan control signal terminal, the second terminal of the sixth transistor is connected to the anode of the light-emitting device and the anode potential control module, and the cathode of the light-emitting device is connected to the negative terminal of the power supply.

7. The circuit according to claim 6, characterized in that, The reset module includes a first transistor and a first capacitor, and the anode potential control module includes a seventh transistor; The gate of the first transistor is connected to the reset signal control terminal, the first terminal of the first transistor is connected to the second terminal of the first capacitor, and the second terminal of the first transistor is connected to the first reset signal input terminal. The first terminal of the first capacitor is connected to the power supply voltage terminal; The gate of the seventh transistor is connected to the gate control signal terminal, the first terminal of the seventh transistor is connected to the anode of the light-emitting device, and the second terminal of the seventh transistor is connected to the second reset signal input terminal.

8. The circuit according to claim 6, characterized in that, The reset module includes a first transistor, an eighth transistor, and a first capacitor; the anode potential control module includes a seventh transistor. The gate of the first transistor is connected to the reset signal control terminal, the first terminal of the first transistor is connected to the second terminal of the first capacitor, and the second terminal of the first transistor is connected to the first terminal of the eighth transistor. The first terminal of the first capacitor is connected to the power supply voltage terminal; The gate of the eighth transistor is connected to the reset signal control terminal, and the second terminal of the eighth transistor is connected to the first reset signal input terminal. The gate of the seventh transistor is connected to the gate control signal terminal, the first terminal of the seventh transistor is connected to the anode of the light-emitting device, and the second terminal of the seventh transistor is connected to the second reset signal input terminal.

9. The circuit according to claim 6, characterized in that, The anode potential control module includes a seventh transistor and a ninth transistor; the reset module includes a first transistor and a first capacitor. The gate of the seventh transistor is connected to the gate control signal terminal, the first terminal of the seventh transistor is connected to the anode of the light-emitting device, and the second terminal of the seventh transistor is connected to the first terminal of the ninth transistor. The gate of the ninth transistor is connected to the gate control signal terminal, and the second terminal of the ninth transistor is connected to the second reset signal input terminal; The gate of the first transistor is connected to the reset signal control terminal, the first terminal of the first transistor is connected to the second terminal of the first capacitor, and the second terminal of the first transistor is connected to the first reset signal input terminal. The first terminal of the first capacitor is connected to the power supply voltage terminal.

10. The circuit according to any one of claims 7-9, characterized in that, The gate of the second transistor is specifically connected to the first gate control signal terminal; the gate of the fourth transistor is specifically connected to the second gate control signal terminal; and the gate of the seventh transistor is specifically connected to the second gate control signal terminal.

11. The circuit according to claim 10, characterized in that, The data writing module further includes a tenth transistor, the gate of which is connected to a second reset signal control terminal, the first terminal of which is connected to a third reset signal input terminal, the second terminal of which is connected to a second terminal of a fourth transistor, and the gate of the first transistor is specifically connected to a first reset signal control terminal.

12. A pixel circuit, characterized in that, The circuit includes: Reset module, compensation module, drive module, data writing module, anode potential control module, and light-emitting device; The reset module, the compensation module, the data writing module, and the anode potential control module are respectively connected to the driving module, and the driving module is connected to the light-emitting device; The first reset signal input terminal of the reset module, the second reset signal input terminal of the anode potential control module, and the third reset signal input terminal of the data writing module are used to connect to the initialization signal line; the third reset signal input terminal is connected to the second terminal of the fourth capacitor, and the first terminal of the fourth capacitor is connected to the power supply voltage terminal.

13. The circuit according to claim 12, characterized in that, The data writing module includes a fourth transistor, a tenth transistor, and a fourth capacitor; The gate of the fourth transistor is connected to the control signal terminal of the second gate, the first terminal of the fourth transistor is connected to the data signal voltage terminal, and the second terminal of the fourth transistor is connected to the driving module. The gate of the tenth transistor is connected to the second reset signal control terminal, the first terminal of the tenth transistor is connected to the third reset signal input terminal, and the second terminal of the tenth transistor is connected to the second terminal of the fourth transistor. The second terminal of the fourth capacitor is connected to the first terminal of the tenth transistor.

14. The circuit according to claim 13, characterized in that, The data writing module further includes an eleventh transistor, the gate of which is connected to the first reset signal control terminal, the first terminal of which is connected to the third reset signal input terminal, and the second terminal of which is connected to the second terminal of the fourth capacitor and the first terminal of the tenth transistor, respectively.

15. A display, characterized in that, It includes a first driving chip and a pixel circuit as described in any one of claims 1-14, wherein the first driving chip provides a gate driving signal and a scan control signal to the pixel circuit.

16. The display according to claim 15, characterized in that, The display also includes a second driver chip, which provides initialization signals to the pixel circuit partitions through initialization signal lines.

17. The display according to claim 16, characterized in that, As described in claim 2, the second driving chip is connected to multiple first initialization signal lines, and each initialization signal line is connected to a first reset signal input terminal and a second reset signal input terminal of the pixel circuit in at least one row of pixels, wherein the second driving chip independently provides an initialization signal through each of the first initialization signal lines.

18. The display according to claim 16, characterized in that, As described in claim 3, the second driving chip is connected to multiple first initialization signal lines, each of the first initialization signal lines being connected to a first reset signal input terminal of the pixel circuit in at least one row of pixels. The first driving chip is also connected to a third initialization signal line, which is connected to a second reset signal input terminal of the pixel circuit in each of the pixel rows. The second driving chip provides an initialization signal independently through each of the first initialization signal lines.

19. The display according to claim 16, characterized in that, As described in claim 4, the second driver chip is connected to multiple second initialization signal lines, each second initialization signal line is connected to a second reset signal input terminal of the pixel circuit in at least one row of pixels, and the first driver chip is connected to a third initialization signal line, the third initialization signal line being connected to a first reset signal input terminal of the pixel circuit in each row of pixels, wherein the second driver chip independently provides an initialization signal through each second initialization signal line.

20. The display according to claim 16, characterized in that, As described in claim 5, the second driver chip is connected to multiple first initialization signal lines and multiple second initialization signal lines. Each first initialization signal line is connected to a first reset signal input terminal of the pixel circuit in at least one row of pixels, and each second initialization signal line is connected to a second reset signal input terminal of the pixel circuit in at least one row of pixels. The second driver chip provides an initialization signal independently through each of the first initialization signal lines and each of the second initialization signal lines.

21. The display according to claim 15, characterized in that, The first driver chip provides an initialization signal to the pixel circuit through an initialization signal line.

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