Layout of semiconductor memory device

Abstract

A layout of a semiconductor memory device includes a substrate and a ternary content addressable memory. The ternary content addressable memory is disposed on the substrate and includes a plurality of ternary content addressable memory bit cells, and at least two of the ternary content addressable memory bit cells are mirror-symmetrical along a symmetry axis. Each ternary content addressable memory bit cell includes two memory cells electrically connected to two word lines, respectively, and a logic circuit electrically connected to the memory cells. The logic circuit includes two first read transistors and two second read transistors. Each second read transistor includes a gate and two source / drain regions. The source / drain regions of the second read transistor are electrically connected to two match lines and a first read transistor, respectively. The word lines are disposed parallel to the match lines.

Description

TECHNICAL FIELD

[0001] The present application relates to a layout of a semiconductor memory device, and more particularly, to a layout of a semiconductor memory device including a ternary content addressable memory (TCAM). BACKGROUND

[0002] In a conventional memory array structure, a six-transistor static-random access memory (6T-SRAM) cell is commonly used as a bit cell structure. As the performance of the memory is improved, two transistors can be further included in the memory bit cell structure. Therefore, a ternary content addressable memory (TCAM) is widely used to effectively accelerate the search speed of data so as to solve various search problems. However, the conventional TCAM has a non-charge sharing concern, a lower coupling effect, and a low impedance problem between match lines, which can cause the node voltage on the match line to be incorrectly reduced, resulting in a false judgment. Thus, the difficulty of layout setting of the related device is increased. SUMMARY

[0003] An object of the present application is to provide a layout of a semiconductor memory device, which is a modified layout structure of a TCAM to effectively reduce the match line coupling problem and avoid charge sharing.

[0004] To achieve the above object, the present application provides a layout of a semiconductor memory device, which includes a substrate and a ternary content addressable memory (TCAM). The TCAM is disposed on the substrate and includes a plurality of TCAM bit cells. At least two of the TCAM bit cells are mirror-symmetrical along a symmetry axis. Each of the TCAM bit cells includes two memory cells electrically connected to two word lines, respectively, and two logic circuits electrically connected to the memory cells. Each of the logic circuits includes two first read transistors and two second read transistors. Each of the second read transistors includes a gate and two source / drain regions. The source / drain regions of the second read transistors are electrically connected to two match lines and the first read transistors, respectively. The word lines are parallelly disposed between the match lines. BRIEF DESCRIPTION OF DRAWINGS

[0005] Figure 1Circuit diagram of ternary content addressable memory in semiconductor memory device according to an embodiment of the present application

[0006] Figures 2 to 6 Layout structure of ternary content addressable memory in semiconductor memory device according to an embodiment of the present application

[0007] Figures 7 to 9 Layout structure of ternary content addressable memory in semiconductor memory device according to another embodiment of the present application

[0008] Explanation of main element symbols

[0009] 10, 30 Semiconductor memory device

[0010] 100 Ternary content addressable memory

[0011] 102 Shallow trench isolation

[0012] 110 Ternary content addressable memory bit cell

[0013] 120 Memory cell

[0014] 121 First inverter

[0015] 121a First terminal

[0016] 121b Second terminal

[0017] 122 Second inverter

[0018] 122a First terminal

[0019] 122b Second terminal

[0020] 123 First pass transistor

[0021] 123a Gate

[0022] 124 Second pass transistor

[0023] 124a Gate

[0024] 140 Logic circuit

[0025] 141, 143 First read transistor

[0026] 142, 144 Second read transistor

[0027] 211 First gate line

[0028] 212 Second gate line

[0029] 213 Third gate line

[0030] 214 fourth gate line

[0031] 215 fifth gate line

[0032] 201 first active region

[0033] 202 second active region

[0034] 203 third active region

[0035] 204 fourth active region

[0036] 205 fifth active region

[0037] 220, 221, 222 plug

[0038] 230 metal layer

[0039] 231 first portion

[0040] 232 second portion

[0041] 240, 241, 242 plug

[0042] 250 metal layer

[0043] 251 first portion

[0044] 252 second portion

[0045] 253 third portion

[0046] 254 fourth portion

[0047] 255 fifth portion

[0048] 256 sixth portion

[0049] 257 seventh portion

[0050] 258 eighth portion

[0051] 260 plug

[0052] 270, 271 metal layer

[0053] 280 plug

[0054] 290, 291, 292 metal layer

[0055] 330 metal layer

[0056] 331 first portion

[0057] 332 second portion

[0058] 340, 341, 342, plug

[0059] 350 metal layer

[0060] 351 first portion

[0061] 352 second portion

[0062] 353 third portion

[0063] 354 fourth portion

[0064] 355 fifth portion

[0065] 356 sixth portion

[0066] 357 seventh portion

[0067] 358 eighth portion

[0068] 360, 361, 362, 363 plug

[0069] 370, 371, 372, 373 metal layer

[0070] A axis of symmetry

[0071] D1 first direction

[0072] D2 second direction

[0073] BL1, BL2 bit line

[0074] ML1, ML2 match line

[0075] SL1, SL2 search line

[0076] WL1, WL2 word line

[0077] P1 voltage source

[0078] PD1 first pull-down transistor

[0079] PD2 second pull-down transistor

[0080] PU1 first pull-up transistor

[0081] PU2 second pull-up transistor DETAILED DESCRIPTION

[0082] For those skilled in the art, the technical personnel familiar with the technical field of the present application can further understand the present application, below, several preferred embodiments of the present application are listed, and the accompanying drawings, detailed description of the present application, the composition and the desired effect. And, without departing from the spirit of the present application, the technical features of the different embodiments described below can be replaced, reorganized, mixed, to constitute other embodiments.

[0083] Please refer to Figures 1 to 6 The present application is illustrated in an embodiment of the semiconductor memory device 10, as shown in the schematic diagram, wherein, Figure 1 For the circuit schematic diagram of ternary content addressable memory (TCAM) 100 in semiconductor memory device 10, Figures 2 to 6 The layout schematic diagram of ternary content addressable memory 100 in semiconductor memory device 10 is shown. Please refer to Figure 1 As shown in the semiconductor memory device 10 includes a substrate (not shown) and disposed thereon ternary content addressable memory 100, the substrate, for example, including silicon substrate, silicon containing substrate or silicon on insulator substrate, etc. Among them, ternary content addressable memory 100 can include a plurality of ternary content addressable memory bit cell (TCAM bitcell, hereinafter referred to as TCAM bit cell) 110, a plurality of bit lines (bit lines) BL1, BL2, a plurality of word lines (word lines) WL1, WL2, a plurality of searching lines (searching lines) SL1, SL2 and a plurality of matching lines (matching lines) ML1, ML2, and each TCAM bit cell 110 can be electrically connected to the corresponding bit line BL1, BL2, word line WL1, WL2, search line SL1, SL2 and matching line ML1, ML2. For clarity, Figure 1 Only two adjacent TCAM bit cells 110 are shown, and the bit lines BL1, BL2, word lines WL1, WL2, search lines SL1, SL2 and matching lines ML1, ML2 corresponding to each TCAM bit cell 110, wherein the two adjacent TCAM bit cells 110 along the symmetry axis A of ternary content addressable memory 100 are mirror symmetric, but not limited to this. Those skilled in the art should understand that ternary content addressable memory 100 can include more than 2 TCAM bit cells 110, and each TCAM bit cell 110 can have the same electrical connection mode to form a memory array. Therefore, the present embodiment is described by taking a single TCAM bit cell 110 as an example, but not limited to this.

[0084] In detail, each TCAM bit unit 110 may include two memory units 120 and logic circuitry 140. Each memory unit 120 may include, for example, a static random access memory (6T-SRAM) unit composed of six transistors, but is not limited thereto. In this embodiment, each memory unit 120 may include a first inverter 121, a second inverter 122, and two transistors, such as a first pass-gate transistor 123 and a second pass-gate transistor 124. In each memory cell 120, the first inverter 121 and the second inverter 122 may each have a first terminal 121a, 122a and a second terminal 121b, 122b, for example, an input terminal and an output terminal, respectively. The first terminal 121a of the first inverter 121 may be electrically connected to the source / drain of the first gate transistor 123 and the second terminal 122b of the second inverter 122, and the first terminal 122a of the second inverter 122 may be electrically connected to the source / drain of the second gate transistor 124 and the second terminal 121b of the first inverter 121, such as... Figure 1 As shown. Furthermore, although Figure 1 The detailed components of the first inverter 121 and the second inverter 122 are not further shown in the figure, but those skilled in the art will understand that both the first inverter 121 and the second inverter 122 may include a pull-up (PU). Figure 1 (Not shown) Transistor and pull-down (PD) Figure 1 (Not shown) transistors, wherein in each inverter 121, 122, the gates (not shown) of the pull-up transistor and the pull-down transistor are electrically connected to each other and serve as first terminals 121a, 122a, and the source / drain (not shown) of the pull-up transistor and the pull-down transistor are electrically connected to each other and serve as second terminals 121b, 122b, and the source / drain of the pull-up transistor and the source / drain of the pull-down transistor can be electrically connected to different voltage sources (not shown).

[0085] It should be noted that in the TCAM bit cell 110, the source / drain of the first gate transistor 123 of each memory cell 120 can be electrically connected to the corresponding bit line BL1, and the source / drain of the second gate transistor 124 can be electrically connected to the corresponding bit line BL2. Furthermore, the gates 123a and 124a of the first gate transistor 123 and the second gate transistor 124 of one of the two memory cells 120, and the gates 123a and 124a of the first gate transistor 123 and the second gate transistor 124 of the other memory cell 120, are respectively electrically connected to different word lines WL1 and WL2. On the other hand, for example... Figure 1As shown, each logic circuit 140 may include two first read transistors (RPGs) 141 and 143 and two second read transistors (RPDs) 142 and 144. The gates of the second read transistors 142 and 144 may be electrically connected to the first terminal 122a of the second inverter 122, respectively. The gates of the first read transistors 141 and 143 may be electrically connected to different search lines SL1 and SL2, respectively. The sources / drains of the second read transistors 142 and 144 and the first read transistors 141 and 143 may be electrically connected to the voltage source P1 and the corresponding matching line ML1, respectively.

[0086] Please refer to Figure 2 This is a top view schematic diagram of the layout structure of the front-end-of-line (FEOL) fabrication process of the TCAM bit cell 110. The memory cell 120 may include a first active region 201, a second active region 202, a third active region 203, a fourth active region 204, a first gate line 211, a second gate line 212, a third gate line 213, and a fourth gate line 214. The first active region 201, the second active region 202, the third active region 203, and the fourth active region 204 may extend along a first direction D1, and are arranged sequentially from top to bottom along a second direction D2. While portions of the first active region 201 and the fourth active region 204 may not necessarily extend along the first direction D1, they can be considered as extending along the first direction D1 as a whole. In one embodiment, the first active region 201 and the fourth active region 204 have the same length in the first direction D1, but this is not a limitation. The first active region 201, the second active region 202, the third active region 203, and the fourth active region 204 may be surrounded by shallow trench isolation (STI) 102 and electrically isolated from each other.

[0087] The first active region 201, the second active region 202, the third active region 203, and the fourth active region 204 may each include a doped region (not shown) formed within the substrate. Thus, the first active region 201, the second active region 202, the third active region 203, and the fourth active region 204 can each be used to form a planar transistor, but are not limited thereto. In another embodiment, the first active region 201, the second active region 202, the third active region 203, and the fourth active region 204 may also optionally include a fin structure (not shown). Thus, the first active region 201, the second active region 202, the third active region 203, and the fourth active region 204 can each be used to form a fin field-effect transistor (FINFET). In this embodiment, the first active region 201 and the fourth active region 204 may have a first conductivity type, such as P-type, and the second active region 202 and the third active region 203 may have a second conductivity type different from the first conductivity type, such as N-type, but are not limited thereto.

[0088] For example Figure 2 As shown, the first gate line 211, the second gate line 212, the third gate line 213, and the fourth gate line 214 can extend along the second direction D2, wherein the fourth gate line 214 can cross the third active region 203 and the fourth active region 204, such that the fourth gate line 214 crossing the fourth active region 204 can form the gate of the first pull-down transistor PD1 of the first inverter 121, and the two sources / drains of the first pull-down transistor PD1 of the first inverter 121 are respectively disposed in the fourth active region 204 on both sides of the fourth gate line 214; the fourth gate line 214 crossing the third active region 203 can form the gate of the first pull-up transistor PU1 of the first inverter 121, and the two sources / drains of the first pull-up transistor PU1 are respectively disposed in the third active region 203 on both sides of the fourth gate line 214. The second gate line 212 can span the fourth active region 204, so that the second gate line 212 spanning the fourth active region 204 can form the gate of the first gate transistor 123, and the two sources / drains of the first gate transistor 123 are respectively disposed in the fourth active region 204 on both sides of the second gate line 212. Thus, the sources / drains of the first gate transistor 123 and the sources / drains of the first pull-down transistor PD1 of the first inverter 121 can be formed together by the same doped region disposed in the fourth active region 204, such as... Figure 2 As shown, but not limited to.

[0089] On the other hand, the third gate line 213 can cross the first active region 201, such that the third gate line 213 crossing the first active region 201 can form a gate of the second pass-gate transistor 124, and two source / drain regions of the second pass-gate transistor 124 are respectively disposed in the first active region 201 on two sides of the third gate line 213. The first gate line 211 can cross the first active region 201 and the second active region 202, such that the first gate line 211 crossing the first active region 201 can form a gate of the second pull-down transistor PD2 of the second inverter 122, and two source / drain regions of the second pull-down transistor PD2 of the second inverter 122 are respectively disposed in the first active region 201 on two sides of the first gate line 211; the first gate line 211 crossing the second active region 202 can form a gate of the second pull-up transistor PU2 of the second inverter 122, and two source / drain regions of the second pull-up transistor PU2 are respectively disposed in the second active region 202 on two sides of the first gate line 211. In the embodiment, the source / drain region of the second pass-gate transistor 124 and the source / drain region of the second pull-down transistor PD2 of the second inverter 122 can be formed by the same doped region disposed in the first active region 201, but are not limited thereto. In an embodiment, the first pull-up transistor PU1 and the second pull-up transistor PU2 are, for example, p-type field effect transistors (pFETs), and the first pull-down transistor PD1, the second pull-down transistor PD2, the first pass-gate transistor 123 and the second pass-gate transistor 124 can be n-type field effect transistors (nFETs). It should be noted that the first active region 201, the second active region 202, the third active region 203 and the fourth active region 204 are symmetrical to each other with the symmetry axis A of the ternary content addressable memory 100 as the center of symmetry, and the first gate line 211, the second gate line 212, the third gate line 213 and the fourth gate line 214 can also be symmetrical to each other with the symmetry axis A of the ternary content addressable memory 100 as the center of symmetry, so that the two memory cells 120 of the TCAM bit cell 110 can be mirror-symmetrical to each other, as shown in Figure 2

[0090] For example Figure 2 ​As shown, the logic circuit 140 can include a fifth active region 205, a fourth gate line 214, and a fifth gate line 215, wherein the fifth active region 205 can extend along the first direction Dl and be arranged below the fourth active region 204 in the second direction D2. In the embodiment, the fifth active region 205 has the same length as the first active region 201 and the fourth active region 204, and the fifth active region 205, the fourth gate line 214, and the fifth gate line 215 can also be symmetric with respect to the symmetry axis A of the ternary content addressable memory 100 as the center of symmetry, so that the two first read transistors 141, 143 and the two second read transistors 142, 144 of the logic circuit 140 can be mirror-symmetric to each other, as shown in FIG. 1C. Figure 2 As shown, but not limited thereto. The fifth gate line 215 can extend along the second direction D2 and across the fifth active region 205, so that the fifth gate line 215 across the fifth active region 205 can serve as the gate of the first read transistor 141, 143, and the two sources / drain of the first read transistor 141, 143 are arranged in the fifth active region 205 on both sides of the fifth gate line 215. In addition, the fourth gate line 214 can also extend along the second direction D2 and across the fifth active region 205, so that the fourth gate line 214 across the fifth active region 205 can serve as the gate of the second read transistor 142, 144, and the two sources / drain of the second read transistor 142, 144 are arranged in the fifth active region 205 on both sides of the fourth gate line 214. In this way, the sources / drain of the first read transistor 141, 143 and the sources / drain of the second read transistor 142, 144 can be arranged in the same fifth active region 205, for example, can be formed by the same doped region.

[0091] It should be noted that, Figure 2 The layout structure shown also includes a plurality of plugs 220 arranged in an insulating layer (not shown) in sequence on each active region and / or each gate line to be electrically connected to the first active region 201, the second active region 202, the third active region 203, the fourth active region 204, the fifth active region 205, the first gate line 211, the second gate line 212, the third gate line 213, the fourth gate line 214, and the fifth gate line 215. In an embodiment, the plug 220 includes a low-resistance conductive material, such as tungsten (W), aluminum (Al), copper (Cu), etc., but is not limited thereto.

[0092] In detail, the plug 220 includes a plurality of plugs 221 respectively disposed on and electrically connected to two source / drain electrodes of the second pull-down transistor PD2, a source / drain electrode of the second pull-up transistor PU2, two source / drain electrodes of the first pull-down transistor PD1, a source / drain electrode of the first pull-up transistor PU1, a source / drain electrode of the second pass transistor 124, two source / drain electrodes of the first pass transistor 123, source / drain electrodes of the first read transistors 141, 143, and source / drain electrodes of the second read transistors 142, 144. In addition, the plug 220 includes a plurality of plugs 222 respectively disposed on and electrically connected to a gate electrode of the first pass transistor 123, a gate electrode of the second pass transistor 124, and gate electrodes of the first read transistors 141, 143. The plug 220 further includes a plurality of plugs 223 disposed on and electrically connected to a gate electrode of the first pull-up transistor PU1 and a source / drain electrode of the second pull-up transistor PU2, and disposed on and electrically connected to a gate electrode of the second pull-up transistor PU2 and a source / drain electrode of the first pull-up transistor PU1.

[0093] Next, refer to Figure 3 , and refer to Figure 2 . Figure 3 FIG. 2A is a top view of a layout structure of a first metal layer (M1) and a first plug (V1) of a TCAM bit cell 110. For clarity, the layout structure of the first metal layer and the first plug is shown in a simplified manner. Figure 3 The labels of the corresponding gate lines and active regions are omitted. As shown in Figure 3 , the TCAM bit cell 110 further includes a metal layer 230 and a plug 240 disposed in another insulating layer (not shown). The metal layer 230 is disposed above the plug 220 to electrically connect the corresponding plug 220. The plug 240 is disposed above the metal layer 230 in sequence. In an embodiment, the metal layer 230 and the plug 240 include a low-resistance conductive material, such as tungsten, aluminum, copper, or the like, but are not limited thereto.

[0094] In detail, the metal layer 230 can be disposed above the plug 223 and the plug 221 to electrically connect the gate of the second pull-up transistor PU2, the source / drain of the first pull-up transistor PU1 and the source / drain shared by the second pull-down transistor PD2 and the second pass transistor 124, and to electrically connect the source / drain of the first pull-up transistor PU1, the gate of the second pull-up transistor PU2 and the source / drain shared by the first pull-down transistor PD1 and the first pass transistor 123. In addition, it is noted that the metal layer 230 disposed in the logic circuit 140 further includes a first portion 231 and a second portion 232, wherein the first portion 231 is electrically connected to the plug 222 (electrically connected to the gate of the first pass transistor 123) and further extends rightward or leftward above the plug 222 in the first direction D1 and finally falls on the shallow trench isolation 102 on the right side or the left side of the plug 222, and the plug 241 is disposed on the first portion 231; the second portion 232 is electrically connected to the plug 221 (electrically connected to the source / drain of the first read transistor 141, 143) and further extends leftward or rightward above the plug 221 in the first direction D1 and finally falls above the gate of the first read transistor 141, and the plug 242 is disposed on the second portion 232, as shown in Figure 3 .

[0095] Please refer to Figures 4 to 6 , and refer to Figure 2 and Figure 3 . Figure 4 FIG. 4 is a top view of a layout structure of a second metal layer (M2) and a second plug (V2) of a TCAM bit cell 110, Figure 5 FIG. 5 is a top view of a layout structure of a third metal layer (M3) and a third plug (V3) of the TCAM bit cell 110, Figure 6 FIG. 6 is a top view of a layout structure of a fourth metal layer (M4) and a third plug (V4) of the TCAM bit cell 110, wherein for clarity of illustration, Figure 4 , Figure 5 and Figure 6 the labels of the corresponding gate lines and active regions are omitted, and the labels of the aforementioned metal layers or the aforementioned plugs are generally omitted.

[0096] First, as Figure 4As shown, the TCAM bit unit 110 also includes a metal layer 250 and a plug 260 disposed within another insulating layer (not shown). The metal layer 250 is located above the plug 240 and includes multiple portions extending in the first direction D1, sequentially named a first portion 251, a second portion 252, a third portion 253, a fourth portion 254, a fifth portion 255, a sixth portion 256, a seventh portion 257, and an eighth portion 258, for electrically connecting to the corresponding plug 240. The plug 260 is sequentially disposed above the first portion 251, the fifth portion 255, the sixth portion 256, and the seventh portion 257 of the metal layer 250. In one embodiment, the metal layer 250 and the plug 260 may comprise, for example, a low-resistance conductive material, such as tungsten, aluminum, or copper, but are not limited thereto.

[0097] In detail, the first part 251 and the sixth part 256 can be disposed on the corresponding plug 240 to further connect the gate of the second gate transistor 124 and the gate of the first gate transistor 123 in each memory cell 120 through, for example... Figure 5 The metal layer 270 and plug 280 shown are electrically connected to the corresponding word lines (e.g., Figure 1 The word line WL1 or word line WL2 is shown. The second part 252 and the fourth part 254 are also disposed on the corresponding plug 240 to electrically connect the source / drain of the second gate transistor 124 to the corresponding bit line (e.g., Figure 1 The bit line BL2 is shown, and the source / drain of the first gate transistor 123 is electrically connected to the corresponding bit line (e.g., BL2). Figure 1 The bit line BL1 is shown. The third part 253, the fifth part 255, and the seventh part 257 are also disposed on the corresponding plug 240, so that the source / drain of the second pull-down transistor PD2 and the source / drain of the first pull-up transistor PU1 can be electrically connected to a voltage source respectively. Figure 1 (Not shown) The source / drain of the first read transistors 141 and 143 can be electrically connected to a voltage source (e.g., Figure 1 (Voltage source P1 shown). Furthermore, the eighth part 258 is also disposed on the corresponding plug 240, allowing the source / drain of the second read transistors 142 and 144 to pass through as shown in the figure. Figure 5 The metal layer 270 and plug 280 shown are Figure 6 The metal layer 290 shown is electrically connected to the corresponding matching line (e.g., Figure 1 (M1 or M2 shown).

[0098] Thus, the layout of the ternary content addressable memory 100 of the semiconductor storage device 10 of the present embodiment can be formed by at least four layers of metal wires, the ternary content addressable memory 100 includes at least two TCAM bit cells 110 and the layout structure thereof can be mirror-symmetrical with respect to the symmetry axis A of the ternary content addressable memory 100 as the center of symmetry. It is noted that the second layer of metal wires (i.e., the metal layer 250) of the ternary content addressable memory 100 includes bit lines (i.e., the second portion 252 and the fourth portion 254) and partial voltage source lines (i.e., the third portion 253, the fifth portion 255 and the seventh portion 257), the third layer of metal wires (i.e., the metal layer 270) includes word lines (i.e., the metal layer 271), and the fourth layer of metal wires (i.e., the metal layer 290) includes match lines (i.e., the metal layer 291) and another partial voltage source lines (i.e., the metal layer 292). Under this arrangement, one of the voltage source lines (i.e., the metal layer 292) of the ternary content addressable memory 100 can be sandwiched between two match lines (i.e., the metal layer 291), which can effectively reduce the lower ML coupling effect and avoid the non-charge sharing concern. Meanwhile, since the ternary content addressable memory 100 includes voltage source lines (i.e., the third portion 253, the fifth portion 255 and the seventh portion 257 of the metal layer 250) extending in the first direction D1 and voltage source lines (i.e., the metal layer 292) extending in the second direction D2, a mesh-shape voltage source line can be formed, which can effectively reduce the resistance of the voltage source. Thus, the semiconductor storage device 10 of the present embodiment can have good performance.

[0099] Those skilled in the art should understand that, in order to meet the actual product requirements, the semiconductor storage device of the present application can also have other forms, which are not limited to the above-mentioned embodiments. For example, the layout structure of the ternary content addressable memory 100 can also have other forms, which are not limited to the above-mentioned embodiments. Further embodiments or variations of the semiconductor storage device of the present application will be described below. For simplicity of description, the following description mainly focuses on the differences between the embodiments, and the same parts will not be repeated. In addition, the same elements in each embodiment of the present application are marked with the same reference numerals for mutual reference between the embodiments.

[0100] Please refer to Figures 7 to 9Fig. 3 shows a layout schematic diagram of a ternary content addressable memory 100 of a semiconductor memory device 30 in another embodiment of the present application. The layout structure of the ternary content addressable memory 100 in this embodiment is substantially the same as that of the ternary content addressable memory 100 in the aforementioned embodiment, and thus the same parts are not described again. The main difference between this embodiment and the aforementioned embodiment is the layout structure of the logic circuit 140.

[0101] First, refer to Fig. 1 Figure 7 , and refer to Fig. 2 Figure 2 together. Figure 7 Fig. 4 shows a top view schematic diagram of the layout structure of a first metal layer (Ml) and a first via (Vl) of a TCAM bit cell 110. In order to clearly show the layout structure of the first metal layer and the first via, Figure 7 the labels of the corresponding gate lines and active regions are omitted. As shown in Fig. 5 Figure 7 , the TCAM bit cell 110 further includes a metal layer 330 and a via 340 disposed in another insulating layer (not shown). The metal layer 330 is disposed above the via 220 to electrically connect the corresponding via 220, and the via 340 is disposed above the metal layer 330 in sequence. It should be noted that the layout structure of the metal layer 330 and the via 340 disposed in the memory cell 120 is substantially the same as that of the metal layer 230 and the via 240 in the aforementioned embodiment, and thus the same parts are not described again. The metal layer 330 disposed in the logic circuit 140 further includes a first portion 331 and a second portion 332. The first portion 331 of the metal layer 330 is electrically connected to the via 222 (electrically connected to the gate of the first pass transistor 123) and further extends above the via 222 to above the gates of the second read transistors 142, 144, and a via 341 is disposed on the first portion 331 of the metal layer 330. In detail, the first portion 331 first extends in the first direction Dl to the right or to the left, then extends downward along the second direction D2 to the shallow trench isolation 102 below the right or left of the via 222, and finally extends to the right or to the left along the first direction Dl until above the gates of the second read transistors 142, 144, as shown in Fig. 6 Figure 7 . On the other hand, the second portion 332 of the metal layer 330 is electrically connected to the via 221 (electrically connected to the source / drain of the first read transistors 141, 143) and further extends upward in the second direction D2, and finally falls on the shallow trench isolation 102 surrounding the source / drain of the first read transistors 141, as shown in Fig. 7 Figure 7 . A via 342 is disposed on the second portion 332 of the metal layer 330, and the via 342 does not overlap the source / drain region of the first read transistors 141, 143 below.

[0102] Please refer to Fig. 8 Figures 8 to 9and refer to them together. Figure 2 and Figure 7 . Figure 8 This is a top view schematic diagram of the layout structure of the second metal layer (M2) and the second plug (V2) of the TCAM bit unit 110 in this embodiment. Figure 9 This is a top view schematic diagram of the layout structure of the third metal layer (M3) and the third plug (V3) of the TCAM bit unit 110 in this embodiment. For clarity, Figure 8 and Figure 9 The labels for the corresponding gate lines and active regions are omitted, and the labels for the aforementioned metal layers or plugs are largely omitted as well. Firstly, as... Figure 8 As shown, the TCAM bit unit 110 also includes a metal layer 350 and a plug 360 disposed within another insulating layer (not shown). The metal layer 350 is located above the plug 340 and includes multiple portions extending in the first direction D1, which are, in sequence, a first portion 351, a second portion 352, a third portion 353, a fourth portion 354, a fifth portion 355, a sixth portion 356, a seventh portion 357, and an eighth portion 358, for electrically connecting the corresponding plug 340; while the plug 360 is sequentially disposed on the metal layer 350. In one embodiment, the metal layer 350 and the plug 360 include, for example, a low-resistance conductive material, such as tungsten, aluminum, copper, etc., but are not limited thereto.

[0103] It should be noted that the first portion 351, the second portion 352, the third portion 353, the fourth portion 354, and the fifth portion 355 of the metal layer 350 disposed within the memory cell 120 are substantially the same as the first portion 251, the second portion 252, the third portion 253, the fourth portion 254, and the fifth portion 255 of the metal layer 250 in the aforementioned embodiment, and will not be described again here; while the sixth portion 356 of the metal layer 350 is disposed on the corresponding plug 341, so as to further connect the gate of the second gate transistor 124 and the gate of the first gate transistor 123 in each memory cell 120 through the plug 361 and as shown in the figure. Figure 9 The metal layer 370 shown is electrically connected to the corresponding word line (e.g., Figure 1 The word line shown is either WL1 or WL2.

[0104] On the other hand, the seventh portion 357 and the eighth portion 358 of the metal layer 350 disposed within the logic circuit 140 are electrically connected to the corresponding voltage source and the corresponding matching line, respectively. Specifically, the seventh portion 357 is disposed on the corresponding plug 342 and extends upward along the second direction D2, directly contacting the fifth portion 355 of the metal layer 350. Thus, the seventh portion 357 and the fifth portion 355 of the metal layer 350 can directly contact and pass through the plug 362 and... Figure 9The metal layer 370 is electrically connected to the voltage source (such as the voltage source P1) as shown, thereby making the source / drain of the first read transistor 141, 143 electrically connected to the voltage source (such as the voltage source P1) as shown. Figure 1 The metal layer 370 is electrically connected to the voltage source (such as the voltage source P1) as shown, thereby making the source / drain of the first read transistor 141, 143 electrically connected to the voltage source (such as the voltage source P1) as shown. Figure 1 The metal layer 370 is electrically connected to the voltage source (such as the voltage source P1) as shown, thereby making the source / drain of the first read transistor 141, 143 electrically connected to the voltage source (such as the voltage source P1) as shown. Figure 9 The metal layer 370 is electrically connected to the voltage source (such as the voltage source P1) as shown, thereby making the source / drain of the first read transistor 141, 143 electrically connected to the voltage source (such as the voltage source P1) as shown. Figure 1 The metal layer 370 is electrically connected to the voltage source (such as the voltage source P1) as shown, thereby making the source / drain of the first read transistor 141, 143 electrically connected to the voltage source (such as the voltage source P1) as shown.

[0105] Thus, the layout of the ternary content addressable memory 100 of the semiconductor storage device 30 of the present embodiment can be formed by only three layers of metal wires. The second layer of metal wires (i.e. the metal layer 350) of the ternary content addressable memory 100 includes the bit lines (i.e. the second portion 352 and the fourth portion 354) and part of the voltage source lines (i.e. the third portion 353, the fifth portion 355 and the seventh portion 357), and the third layer of metal wires (i.e. the metal layer 370) includes the word lines (i.e. the metal layer 371), the match lines (i.e. the metal layer 372) and another part of the voltage source lines (i.e. the metal layer 373). With this arrangement, not only the layout structure of the ternary content addressable memory 100 can be simplified, but also the metal wire architecture of the logic circuit 104 can be completed in the third layer of metal wires (i.e. the metal layer 370) together with the metal wire architecture of the memory cells 120. Furthermore, in the third layer of metal wires (i.e. the metal layer 370), the two word lines (i.e. the metal layer 371) of the ternary content addressable memory 100 can be arranged in parallel between the two match lines (i.e. the metal layer 372), such that the two match lines are located on the opposite sides of the symmetry axis A and can pass through the center of the logic circuit 104 as shown. Figure 9When the first read transistor 141, 143 and the second read transistor 142, 144 of the logic circuit 104 are operated, the first inverter 121 (including the first pull-up transistor PU1 and the first pull-down transistor PD1), the second inverter 122 (including the second pull-up transistor PU2 and the second pull-down transistor PD2), the first pass transistor 123 and the second pass transistor 124 of the memory cell 120 are not operated at the same time, that is, when the first read transistor 141, 143 and the second read transistor 142, 144 of the logic circuit 104 are operated, the two word lines (i.e. the metal layer 371) are closed to the write function and can be used as a voltage source line (Vss potential). In this way, even if the voltage source line is not provided between the two matching lines (i.e. the metal layer 372) but the word line (i.e. the metal layer 371) is provided in the layout structure of the embodiment, the word line (i.e. the metal layer 371) between the two matching lines (i.e. the metal layer 372) can be used as a voltage source line (Vss potential) in actual operation, which can effectively reduce the matching line coupling problem and avoid charge sharing. In addition, the ternary content addressable memory 100 of the embodiment also includes the voltage source line (i.e. the third part 353 and the fifth part 355 of the metal layer 350) extending in the first direction D1 and the voltage source line (i.e. the seventh part 357 of the metal layer 350 and the metal layer 373) extending in the second direction D2, which can form a network of voltage source lines, thereby effectively reducing the resistance of the voltage source. Therefore, the semiconductor storage device 30 of the embodiment can further simplify the layout structure of the ternary content addressable memory 100 while still having good performance.

[0106] The above description is only the preferred embodiment of the present application, and any equivalent changes and modifications made according to the claims of the present application should be within the scope of the present application.

Claims

1. A layout for a semiconductor memory device, characterized in that, include: Base; A ternary content-addressable memory is disposed on the substrate. The ternary content-addressable memory includes a plurality of ternary content-addressable memory cells, at least two of which are mirror-symmetrical along an axis of symmetry. Each of the ternary content-addressable memory cells includes: Two memory cells, each electrically connected to one of two word lines, each memory cell comprising: The first inverter includes an input terminal and an output terminal; The second inverter includes an input terminal and an output terminal, and the output terminal of the second inverter is electrically connected to the input terminal of the first inverter. A first transistor includes a gate and two source / drain regions, the source / drain regions of the first transistor being electrically connected to the output terminal and the first bit line of the first inverter, respectively; and The second transistor includes a gate and two source / drain regions, the source / drain regions of the second transistor being electrically connected to the input terminal of the second inverter and the second bit line, and the gates of the second transistor and the first transistor being electrically connected to one of the word lines; Logic circuits, electrically connected to the memory cells, each logic circuit including: Two first read transistors; and Two second read transistors, each including a gate and two source / drain regions, the source / drain regions of the second read transistors being electrically connected to two matching lines and the first read transistors, wherein the word lines are arranged parallel between the matching lines. Each first read transistor includes a gate and two source / drain regions, the gate of each first read transistor being electrically connected to a search line, and the gate of each second read transistor being electrically connected to the input terminal of the first inverter; and Multiple first plugs are disposed on the source / drain regions and the gate of the first transistors, and on the source / drain regions of the first read transistors and the second read transistors; A first metal layer is disposed on the first plugs to electrically connect the first plugs, wherein a first portion of the first metal layer is disposed on the gate of the second transistor, the first portion of the first metal layer extends from above the gate of the first transistor to above the gate of one of the second read transistors, and a second portion of the first metal layer is disposed on the source / drain regions of the first read transistors. A plurality of second plugs are disposed on the first metal layer to be electrically connected to the second plugs; A second metal layer is disposed on the second plugs to electrically connect the second plugs; Multiple third plugs are disposed on the second metal layer to electrically connect to the second metal layer; and A third metal layer is disposed on the third plugs to electrically connect the third plugs, wherein the third metal layer includes the word lines and the mating lines.

2. The layout of the semiconductor memory device according to claim 1, characterized in that, These word lines pass through the center of the logic circuit.

3. The layout of the semiconductor memory device according to claim 1, characterized in that, Each of these storage units includes static random access memory.

4. The layout of the semiconductor memory device according to claim 1, characterized in that, The second portion of the first metal layer extends from above the source / drain regions of the first read transistors to above the shallow trench isolation surrounding the source / drain regions of the first read transistors.

5. The layout of the semiconductor memory device according to claim 4, characterized in that, The second plugs electrically connected to the second portion of the first metal layer do not overlap with the source / drain regions of the first read transistors.

6. The layout of the semiconductor memory device according to claim 1, characterized in that, The first and second portions of the second metal layer extend in two mutually perpendicular directions, and the first and second portions of the second metal layer are in direct contact with each other.

7. The layout of the semiconductor memory device according to claim 6, characterized in that, The second portion of the second metal layer is disposed above the source / drain regions of the first read transistors, and the first portion of the second metal layer spans over the first transistors and the first inverter.

8. The layout of the semiconductor memory device according to claim 6, characterized in that, The second metal layer includes voltage source lines.

9. The layout of the semiconductor memory device according to claim 6, characterized in that, The third portion of the second metal layer is disposed above the memory cells and includes the first bit line and the second bit line.

10. The layout of the semiconductor memory device according to claim 4, characterized in that, Also includes: Multiple doped regions are disposed within the substrate and isolated and surrounded by the shallow trench. The doped regions extend in a first direction and include a first doped region and a second doped region arranged sequentially in a second direction perpendicular to the first direction. as well as Multiple gate lines are disposed on the substrate to span the doped regions, wherein the gate lines extend in the second direction and include a first gate line that spans both the first and second doped regions to form the gates of the second readout transistors.

11. The layout of the semiconductor memory device according to claim 10, characterized in that, The gate lines also include a second gate line and a third gate line, the second gate line crossing the first doped region and the third gate line crossing both the second doped region and the first doped region to form the gates of the first transistor and the first readout transistors, respectively.

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