An ultra-low voltage SRAM cell with bit-interleaved structure that can eliminate half-select interference

Abstract

The technical solution of the present invention is to provide an ultra-low voltage SRAM cell with a bit-interleaved structure that can eliminate half-select interference. The cell is characterized by including a set of inverter rings, a read path consisting of two N-type write transistors NM1 and NM2, two P-type write transistors PM1 and PM2, and two N-type transistors NM3 and NM4. The present invention can be applied to applications with ultra-low voltage storage requirements, especially those that require certain SRAM access speed and reliability at low voltage. Compared with other different SRAM cells, the present invention can achieve higher read and write operating frequencies while maintaining similar energy consumption.

Description

Technical Field

[0001] The invention relates to an ultra-low voltage SRAM unit capable of eliminating semi-selective interference under a bit interleaving structure, and belongs to the technical field of electronic component design. Background Art

[0002] With the widespread adoption of wireless sensors, implantable biomedical devices, and small handheld devices, the demand for low power consumption is becoming increasingly significant. One of the most effective means of achieving this goal is to reduce the power supply voltage, leading to a growing demand for ultra-low voltage SRAM. However, the probability of soft errors occurring at low voltages also increases, making the use of a bit-interleaved structure crucial for effectively mitigating soft errors in ultra-low voltage SRAM. However, the occurrence of write-half-select interference in the bit-interleaved structure, which can lead to unstable operation, poses a key challenge to achieving fast write speeds at ultra-low voltages.

[0003] At present, many ultra-low voltage SRAM designs with different cell structures have been proposed to try to solve the half-select interference problem, such as DAWA12T[1], BLS9T[2], SPG11T[3], PG9T[4], SCM13T[5], etc. [1], [2], [4], etc. can completely eliminate the write half-select interference through the write word line structure with cross rows and columns, but this structure relies on two series NMOS for writing, so it will significantly deteriorate the write capability of SRAM under ultra-low voltage. [3] By improving the inverter feedback loop and introducing virtual ground, the half-select interference is effectively eliminated and a high write capability is obtained, but this structure has poor resistance to interference such as noise. Under ultra-low voltage, a small amplitude noise will cause the stored data to be rewritten. [5] A standardized SRAM cell with pure digital input and output that eliminates the half-select interference is proposed, but the read and write access speed of this cell is seriously reduced under low voltage. [6] The technology of separating ground lines is used to improve the noise margin against half-selective interference. However, this solution results in complex power supply control logic and cannot completely eliminate the problem of half-selective interference.

[0004] References:

[0005] [1]Y.-W.Chiu et al., "40nm Bit-Interleaving 12T Subthreshold SRAM WithData-Aware Write-Assist," IEEE Transactions on Circuits and Systems I: Regular Papers, vol.61, no.9, pp.2578-2585, Sept.2014.

[0006] [2]K.Shin,W.Choi and J.Park,"Half-Select Free and Bit-Line Sharing 9TSRAM for Reliable Supply Voltage Scaling,"IEEE Transactions on Circuits andSystems I:Regular Papers,vol.64,no.8,pp.2036-2048,Aug.2017.

[0007] [3]Y.He,J.Zhang,X.Wu,X.Si,S.Zhen and B.Zhang,"A Half-Select Disturb-Free 11T SRAM Cell With Built-In Write / Read-Assist Scheme for Ultralow-Voltage Operations,"IEEE Transactions on Very Large Scale Integration(VLSI)Systems,vol.27,no.10,pp.2344-2353,Oct.2019.

[0008] [4]T.W.Oh,H.Jeong,K.Kang,J.Park,Y.Yang and S.-O.Jung,"Power-Gated 9TSRAM Cell for Low-Energy Operation,"IEEE Transactions on Very Large ScaleIntegration(VLSI)Systems,vol.25,no.3,pp.1183-1187,March 2017.

[0009] [5]J.Sun,H.Guo,G.Li and H.Jiao,"An Ultra-Low-Voltage Bit-InterleavedSynthesizable 13T SRAM Circuit,"IEEE Journal of Solid-State Circuits,vol.57,no.11,pp.3477-3489,Nov.2022.

[0010] [6] MSMSiddiqui, ZCLee and TT-H.Kim, "A 16-kb 9T Ultralow-VoltageSRAM With Column-Based Split Cell-VSS, Data-Aware Write-Assist, and EnhancedRead Sensing Margin in 28-nm FDSOI," IEEE Transactions on Very Large ScaleIntegration(VLSI)Systems,vol.29,no.10,pp.1707-1719,Oct.2021. Summary of the Invention

[0011] The technical problem to be solved by the present invention is that the use of a bit-interleaved structure is crucial for effectively mitigating soft errors in ultra-low voltage SRAM. However, write half-select interference, which causes unstable operation, will occur in the bit-interleaved structure, posing a key challenge to achieving fast writing at ultra-low voltage.

[0012] In order to solve the above technical problems, the technical solution of the present invention is to provide an ultra-low voltage SRAM cell that can eliminate half-select interference under a bit-interleaved structure, characterized in that it includes a group of inverter rings, two N-type write transistors NM1 and NM2, two P-type write transistors PM1 and PM2, and a read path composed of two N-type transistors NM3 and NM4;

[0013] The two N-type write transistors NM1 and NM2 are controlled by the write word lines WWLNB and WWLN respectively, so that one of the two N-type write transistors NM1 and NM2 and a shared PMOS footer form a series PMOS pair;

[0014] The two P-type write transistors PM1 and PM2 are controlled by the write word lines WWLPB and WWLP respectively, so that one of the two P-type write transistors PM1 and PM2 forms a series NMOS pair with a shared NMOS header;

[0015] The NMOS Footer and PMOS Header are controlled by the row-share signals WLPC and WLNC, respectively, and connected to V_GND and V_VDD;

[0016] N-type write transistor NM1 and P-type write transistor PM1 are connected to one end of the inverter ring through terminal QB, and N-type write transistor NM2 and P-type write transistor PM2 are connected to the other end of the inverter ring through terminal Q; terminal Q and read word line RWL jointly determine the data of read port RBL led out of the read path;

[0017] In the write state: the digital 1 is directly written to the terminal Q through the series PMOS pair, and the digital 0 is written to the terminal QB through the series NMOS pair and the inverter ring; the digital 1 is directly written to the terminal QB through the series PMOS pair, and the digital 0 is written to the terminal Q through the series NMOS pair and the inverter ring;

[0018] In the read state, the data stored at the terminal Q is read out to the read port RBL via the read path using the read word line RWL.

[0019] Preferably, port 1 of the two N-type write transistors NM1 and NM2 is connected to the write word lines WWLNB and WWLN respectively, port 2 is connected to the port 2 of the two P-type write transistors PM1 and PM2 respectively, and port 3 is controlled by the write word lines WWLNB and WWLN and connected to V_GND through a shared PMOS Footer.

[0020] Preferably, ports 1 of the two P-type write transistors PM1 and PM2 are connected to the write word lines WWLPB and WWLP, respectively, and port 3 is controlled by the write word lines WWLPB and WWLP and connected to V_VDD through a shared NMOS header.

[0021] Preferably, one end of the inverter ring is connected to the port 2 of the P-type write transistor PM1 and the N-type write transistor NM1, defined as the terminal QB; the other end of the inverter ring is connected to the port 2 of the P-type write transistor PM2 and the N-type write transistor NM2, defined as the terminal Q.

[0022] Preferably, in the read path: port 1 of the N-type transistor NM3 is connected to the read word line RWL, port 2 is connected to port 2 of the N-type transistor NM3, and port 3 is connected to the read port RBL; port 1 of the N-type transistor NM4 is connected to the terminal Q, and port 3 is connected to V_GND.

[0023] Preferably, the bit interleaved structure includes N ultra-low voltage SRAM cells connected in series, and all the ultra-low voltage SRAM cells share the same NMOS Footer and PMOS Header.

[0024] Preferably, there are M rows of the bit-interleaved structures, and the bit-interleaved structures in different rows share different NMOS footers and PMOS headers, and the row-shared signals WLPC and WLNC of adjacent rows are opposite, wherein WLPC, WLNC, and the read word line RWL are row-shared signals, and the write word lines WWLPB, WWLP, WWLNB, WWLN, and the read word line RBL are column-shared signals:

[0025] For the row half-select unit, the shared PMOS Header and NMOS Footer are turned on, and the N-type write transistors NM1, NM2 and the P-type write transistors PM1, PM2 are turned off by the column-shared write word lines WWLPB, WWLP, WWLNB, and WWLN; for the column half-select unit, the corresponding write transistors are turned on by the corresponding column-shared write word lines, and the shared PMOS Header and NMOS Footer are turned off by the row-shared signals WLPC and WLNC.

[0026] Preferably, the SRAM array composed of M×N ultra-low voltage SRAM cells and its pre-charge module are powered by a relatively low voltage, and the peripheral circuits of the SRAM array are powered by a relatively high voltage.

[0027] Compared with the prior art, the present invention has the following advantages:

[0028] (1) The fully decoupled topology proposed in the present invention has dedicated read and write ports, which can achieve a high write margin during operation;

[0029] (2) The present invention proposes a differential data-aware write path, which opens different paths according to the different written data, which can effectively improve the write capability and reduce the write latency;

[0030] (3) The present invention proposes a speed-optimized dual-power supply method. Appropriately increasing the power supply voltage of the peripheral circuit can effectively reduce peripheral delays, while reducing the leakage energy consumption generated by a single operation, thereby maintaining the overall energy efficiency of the array.

[0031] The present invention can be applied to applications with ultra-low voltage storage requirements, especially some applications that have certain requirements for SRAM memory access speed and reliability under low voltage. Compared with other different SRAM units, the present invention can achieve higher read and write operating frequencies while maintaining similar energy consumption. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] Figure 1 The present invention demonstrates an ultra-low voltage 10T SRAM cell that can eliminate half-select interference under the bit-interleaved structure.

[0033] Figure 2 A set of 4-bit bit interleaving structures in an embodiment is shown;

[0034] Figure 3 The working state of the transistors of the SRAM cell of the present invention in different read and write states is demonstrated;

[0035] Figure 4 The principle of eliminating write half-select disturbance in the SRAM cell of the present invention is demonstrated (taking the write "0" operation as an example);

[0036] Figure 5 Demonstrates how the integrated SRAM array is powered. DETAILED DESCRIPTION

[0037] Below in conjunction with specific embodiment, further set forth the present invention.Should be understood that these embodiments are only used to illustrate the present invention and are not used in limiting the scope of the present invention.In addition, should be understood that after reading the content taught by the present invention, those skilled in the art can make various changes or modifications to the present invention, and these equivalent forms fall equally within the scope limited by the appended claims of the application.

[0038] like Figure 1 As shown, the ultra-low voltage 10TSRAM cell that can eliminate half-select interference under the bit-interleaved structure in this embodiment is composed of a readout path consisting of a group of inverter rings, two N-type write transistors, two P-type write transistors and two N-type transistors.

[0039] Port 1 of the two N-type write transistors NM1 and NM2 is connected to the write word lines WWLNB and WWLN respectively, and port 2 is connected to the port 2 of the two P-type write transistors PM1 and PM2 respectively. Port 3 is controlled by the write word lines WWLNB and WWLN and connected to V_GND through a shared PMOS footer.

[0040] Ports 1 of the two P-type write transistors PM1 and PM2 are connected to the write word lines WWLPB and WWLP, respectively. Port 3 is controlled by the write word lines WWLPB and WWLP and is connected to V_VDD through a shared NMOS header.

[0041] One end of the inverter ring is connected to the port 2 of the P-type write transistor PM1 and the N-type write transistor NM1, and is defined as the terminal QB; the other end of the inverter ring is connected to the port 2 of the P-type write transistor PM2 and the N-type write transistor NM2, and is defined as the terminal Q.

[0042] The read path consists of N-type transistors NM3 and NM4 connected in series. Port 1 of N-type transistor NM3 is connected to read word line RWL, port 2 is connected to port 2 of N-type transistor NM4, and port 3 is connected to read port RBL. Port 1 of N-type transistor NM4 is connected to terminal Q, and port 3 is connected to V_GND. Terminal Q and read word line RWL together determine the data on read port RBL.

[0043] The NMOS Footer and PMOS Header are controlled by row-share signals WLPC and WLNC, respectively.

[0044] The truth tables of the ports of the 10T SRAM cell described above in the read, write and hold states are shown in the following table.

[0045]

[0046] The corresponding row and column sharing relationships of each port signal are shown in the following table.

[0047]

[0048]

[0049] A 4-bit bit interleaving structure based on the above ultra-low voltage 10T SRAM cell is shown in FIG. Figure 2 As shown, four of the above ultra-low voltage 10T SRAM cells are connected in series, and the four ultra-low voltage 10T SRAM cells share the same NMOS Footer and PMOS Header to eliminate half-select interference. Figure 2 In the bit-interleaved structure, the differential write port is controlled by the column-shared word line signals WWLPB, WWLP, WWLNB, and WWLN.

[0050] like Figure 3 As shown, for the read operation of the selected ultra-low voltage 10T SRAM cell, the row-shared RWL is selected to open the read port. With the decoupling function, the read operation will not cause the problem of half-select interference. For the write operation, the row-shared signals WLPC and WLNC are in the enabled state to turn on the NMOS Footer and PMOS Header. When "1" is written, the P-type write transistor PM2 and the N-type write transistor NM1 are turned on by the column-shared signals WWLP and WWLNB. In this case, a series-connected PMOS pair (PMOS Header-P-type write transistor PM2) is used to transmit a lossless "1" to terminal Q. After the "1" is inverted by the inverter ring, a series-connected NMOS pair (NMOS Footer-N-type write transistor NM1) causes "0" to be transmitted to terminal QB, and "1" is stored at terminal Q. A similar analysis can be performed when "0" is written. In this case, a series PMOS pair (PMOS Header-P-type write transistor PM1) is used to transmit lossless "1" to terminal QB. After "1" is inverted by the inverter ring, "0" is transmitted to terminal Q through a series NMOS pair (NMOS Footer-N-type write transistor NM2), and "0" is stored at terminal Q.

[0051] like Figure 4As shown, the row-shared signals WLPC and WLNC of the NMOS footers and PMOS headers of the two rows are opposite. For the row half-select unit (upper left corner unit), although the shared PMOS header and NMOS footer are turned on, the four write access transistors are turned off by the column-shared write word lines WWLPB, WWLP, WWLNB, and WWLN, so no interference occurs. For the column half-select unit (lower right corner unit), although the two write access transistors are turned on by the column-shared signals WWLPB and WWLN, the shared PMOS header and NMOS footer are turned off by the row-shared signals WLPC and WLNC. Therefore, there is no write path that can cause interference.

[0052] like Figure 5 As shown in the figure, for the integrated SRAM array, the peripheral circuits, such as the driver module, wordline driver module, decoder module, select output module, sense amplifier SA, and output latch, use a higher power supply voltage, while the core circuits, such as the SRAM array and precharge module, use a lower voltage. This dual-power supply method increases the supply voltage of the peripheral circuits, effectively reducing operational delays and the leakage energy consumption generated by a single operation. As a result, the overall array operating speed is optimized while maintaining overall energy efficiency.

Claims

1. An ultra-low voltage SRAM cell capable of eliminating half-select interference in a bit-interleaved structure, characterized in that: A readout path comprising a set of inverter rings, two N-type write transistors NM1 and NM2, two P-type write transistors PM1 and PM2, and two N-type transistors NM3 and NM4; The two N-type write transistors NM1 and NM2 are controlled by the write word lines WWLNB and WWLN respectively, so that one of the two N-type write transistors NM1 and NM2 and a shared PMOS tail form a series PMOS pair; The two P-type write transistors PM1 and PM2 are controlled by write word lines WWLPB and WWLP, respectively, so that one of the two P-type write transistors PM1 and PM2 forms a series NMOS pair with a shared NMOS header; The NMOS tail and PMOS header are controlled by row-share signals WLPC and WLNC, respectively, and connected to V_GND and V_VDD; N-type write transistor NM1 and P-type write transistor PM1 are connected to one end of the inverter ring through terminal QB, and N-type write transistor NM2 and P-type write transistor PM2 are connected to the other end of the inverter ring through terminal Q; terminal Q and read word line RWL jointly determine the data of read port RBL led out of the read path; In the write state: the digital 1 is directly written to the terminal Q through the series PMOS pair, and the digital 0 is written to the terminal QB through the series NMOS pair and the inverter ring; the digital 1 is directly written to the terminal QB through the series PMOS pair, and the digital 0 is written to the terminal Q through the series NMOS pair and the inverter ring; In the read state, the data stored at the terminal Q is read out to the read port RBL via the read path using the read word line RWL.

2. The ultra-low voltage SRAM cell capable of eliminating half-select interference in a bit-interleaved structure according to claim 1, wherein: Port 1 of the two N-type write transistors NM1 and NM2 is connected to the write word lines WWLNB and WWLN respectively, and port 2 is connected to the port 2 of the two P-type write transistors PM1 and PM2 respectively. Port 3 is controlled by the write word lines WWLNB and WWLN and connected to V_GND through a shared PMOS tail.

3. The ultra-low voltage SRAM cell capable of eliminating half-select interference in a bit-interleaved structure according to claim 2, wherein: Ports 1 of the two P-type write transistors PM1 and PM2 are connected to the write word lines WWLPB and WWLP, respectively. Port 3 is controlled by the write word lines WWLPB and WWLP and is connected to V_VDD through a shared NMOS header.

4. The ultra-low voltage SRAM cell capable of eliminating half-select interference in a bit-interleaved structure according to claim 3, wherein: One end of the inverter ring is connected to the port 2 of the P-type write transistor PM1 and the N-type write transistor NM1, and is defined as the terminal QB; the other end of the inverter ring is connected to the port 2 of the P-type write transistor PM2 and the N-type write transistor NM2, and is defined as the terminal Q.

5. The ultra-low voltage SRAM cell capable of eliminating half-select interference in a bit-interleaved structure according to claim 4, wherein: In the read path: port 1 of N-type transistor NM3 is connected to read word line RWL, port 2 is connected to port 2 of N-type transistor NM3, and port 3 is connected to read port RBL; port 1 of N-type transistor NM4 is connected to terminal Q, and port 3 is connected to V_GND.

6. The ultra-low voltage SRAM cell capable of eliminating half-select interference in a bit-interleaved structure according to claim 1, wherein: The bit interleaved structure includes N ultra-low voltage SRAM cells connected in series, and all the ultra-low voltage SRAM cells share the same NMOS tail and PMOS header.

7. The ultra-low voltage SRAM cell capable of eliminating half-select interference in a bit-interleaved structure according to claim 6, wherein: There are M rows of the bit-interleaved structures. The bit-interleaved structures in different rows share different NMOS tails and PMOS headers, and the row-shared signals WLPC and WLNC of adjacent rows are opposite. WLPC, WLNC, and the read word line RWL are row-shared signals, and the write word lines WWLPB, WWLP, WWLNB, WWLN, and the read word line RBL are column-shared signals. For the row half-select unit, the shared PMOS header and NMOS tail are turned on, and the N-type write transistors NM1, NM2 and the P-type write transistors PM1, PM2 are turned off by the column-shared write word lines WWLPB, WWLP, WWLNB, and WWLN; for the column half-select unit, the corresponding write transistors are turned on by the corresponding column-shared write word lines, and the shared PMOS header and NMOS tail are turned off by the row-shared signals WLPC and WLNC.

8. The ultra-low voltage SRAM cell capable of eliminating half-select interference in a bit-interleaved structure according to claim 7, wherein: The SRAM array composed of M×N ultra-low voltage SRAM cells and its precharge module are powered by a relatively low voltage, and the peripheral circuits of the SRAM array are powered by a relatively high voltage.

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