Redundant storage of error correction code check bits for verifying proper memory operation.

Abstract

This disclosure relates to redundant storage of error correction code (ECC) check bits for verifying proper operation of memory. Application data and the associated error correction code (ECC) check bits are stored in a first memory. The ECC check bits, but not the application data, are stored in a second memory. In response to a request to read application data from the first memory, the ECC check bits are also read from the first memory and used to detect, and possibly correct, errors in the read application data. The ECC check bits are further output from both the first and second memories for bit-by-bit comparison. In response to a failure of the bit-by-bit comparison, a signal indicating a possible failure of one or both of the first and second memories is generated.

Description

[0001] Case Analysis

[0002] This application is a divisional application of Chinese Patent Application No. 201711172021.1, filed on November 22, 2017, entitled "Redundant storage of error correction code check bits for verifying proper operation of static random access memory". Technical Field

[0003] This disclosure generally relates to a storage circuit or system for storing data, and more specifically to verifying the proper operation of the memory circuit by testing redundantly stored error correction code (ECC) check bits. Background Technology

[0004] Many systems include memory circuitry for storing application data. The proper operation of the system depends on the accuracy of the stored application data. However, it is known that memory circuitry can store and / or retrieve application data that includes bit errors. For example, bit errors can be introduced with operations related to writing application data to memory. Bit errors can also be introduced with operations related to reading application data from memory. Bit errors can also be introduced during the period during which application data is stored in memory. To address the problem of bit errors in application data, the prior art knows to apply error correction codes (ECC), also known in the art as forward error correction (FEC), to the application data before storage. This encoding process adds redundant data (e.g., in the form of parity bits) to the application data, which, along with its associated redundant data, is stored in the memory circuitry. When needed later, the application data, along with its associated redundant data, is retrieved from the memory circuitry, and the redundant data is used to detect the presence of errors in the retrieved application data, and in some cases, to correct the detected errors.

[0005] However, the number and types of errors that a given ECC can correct are limited. Errors exceeding this limit can lead to unpredictable results. This could be due to operating conditions or fault conditions within the memory circuitry. These unreliable behaviors may be unacceptable in some applications. Furthermore, ECC may fail to detect faults in the memory circuitry.

[0006] Special attention should be paid to faults in the logic circuitry of the memory circuitry. Consider the following fault to be addressed: application data with ECC is written to a first memory address within the memory circuitry, but due to a fault in the logic circuitry within the memory circuitry, this application data is instead written to a second memory address. This fault causes three problems. First, data has been stored at the wrong address (i.e., the second memory address). Second, good data at the wrong address has been overwritten. Third, data that should have been overwritten still exists in the memory circuitry at the correct address (i.e., the first memory address). Detecting this fault during memory operations is important. However, ECC does not provide sufficient protection because when subsequent reads are made from the first memory address, the read data corresponding to the ECC may not reveal the data error. Similarly, subsequent reads from the second memory address may also fail to reveal the data error.

[0007] Consider the following failure regarding chip selection: The host requests application data to be written to a selected memory chip, but due to a malfunction in the logic circuitry within the memory circuitry that responds to the chip select (CS) signal, the write to the memory does not occur. Therefore, the application data that should be stored at the specified address in the memory circuitry is not present, and the data that should be overwritten remains in the memory circuitry at that address. Similarly, detecting this failure is crucial. However, ECC does not provide sufficient protection because subsequent reads from the memory address may not reveal the data error.

[0008] There is a need in this field to solve the problem of fault detection in memory circuit operation. Summary of the Invention

[0009] In one embodiment, a memory system includes: a first memory; a second memory; a memory controller configured to: apply memory addresses to the first and second memories, write error correction code (ECC) check bits to the memory addresses in the first and second memories, and read ECC check bits only from the first memory at the memory addresses; and a comparator circuit configured to: obtain ECC check bits from the memory addresses in the first and second memories, and perform a bit-by-bit comparison of the ECC check bits received from the first and second memories to generate a signal indicating that one or more of the first and second memories are faulty if the bit-by-bit comparison of the ECC check bits fails.

[0010] In one embodiment, a system includes: a host system configured to make a write request to write application data to memory; and a memory system that, in response to the write request, operates by: calculating an error correction code (ECC) check bit based on the application data; writing the application data and the calculated ECC check bit to a first memory; and writing the ECC check bit, but not the application data, to a second memory.

[0011] In one embodiment, a memory system includes: a first memory configured to store application data and error correction code (ECC) check bits associated with the application data; a second memory configured to store the ECC check bits associated with the application data, wherein the second memory does not store application data; memory controller circuitry configured to read the application data and the ECC check bits from the first memory, and to detect and correct errors in the retrieved application data using the retrieved ECC check bits; and comparator circuitry configured to receive the ECC check bits from the first memory and the second memory and perform a bit-by-bit comparison of the ECC check bits received from the first memory and the second memory to generate a signal indicating that one or more of the first memory and the second memory are faulty if the bit-by-bit comparison of the ECC check bits fails.

[0012] In one embodiment, a system includes: a host system configured to issue a read request to read application data from memory; and a memory system that, in response to the read request, operates by: reading application data and error correction code (ECC) check bits associated with the application data from a first memory; detecting and correcting errors in the retrieved application data using the retrieved ECC check bits; receiving ECC check bits associated with the application data from the first memory and from a second memory that does not store application data; and performing a bit-by-bit comparison of the received ECC check bits to generate a signal indicating that one or more of the first and second memories are faulty if the bit-by-bit comparison of the ECC check bits fails.

[0013] The foregoing and other features and advantages of this disclosure will become more apparent from the following detailed description of embodiments, which are read in conjunction with the accompanying drawings. The detailed description and drawings are merely illustrative of this disclosure and are not intended to limit the scope of the invention as defined by the appended claims and their equivalents. Attached Figure Description

[0014] The embodiments are illustrated by way of examples in the accompanying drawings, which are not drawn to scale, wherein the same numbers indicate similar parts, and wherein:

[0015] Figure 1 A block diagram of the memory system is shown. Detailed Implementation

[0016] Now referring to the block diagram of the memory system 10 shown Figure 1 Memory system 10 is coupled to host system 12 (e.g., in the form of a data processing system). Host system 12 has the need to store and retrieve application data. Memory system 10 operates in response to requests from host system 12 to store data, and further in response to requests from host system 12 to retrieve data from storage devices. Requests from host system 12, whether for data storage or retrieval, include a memory address (addr) sent via address bus 16, which specifies the location in memory system 10 where application data will be stored or retrieved. Bidirectional data bus 18 couples host system 12 to memory system 10, where data bus 18 carries application data (app_data). Read / write control lines (r / w) 20 specify whether the applied memory address (addr) is used for a read or write operation.

[0017] Memory system 10 includes a first memory 24 and a second memory 26. Each of the first and second memories 24 and 26 may, for example, include an array of static random access memory (SRAM). The first memory 24 includes a memory array 24a, however, its size is substantially larger than that of the memory array 26a of the second memory 26. For example, the first memory array 24a may have an n×(64+8) bit size, while the second memory array 26a may have an n×8 bit size (where n represents the number of different addresses in the memory array). Logic circuitry 24b (including circuitry for address decoding, enabling, multiplexing, etc.) provides an interface to memory array 24a. Logic circuitry 26b (including circuitry for address decoding, enabling, multiplexing, etc.) provides an interface to memory array 26a.

[0018] The operation of the first and second memories 24 and 26 is controlled by memory control circuitry 34. Memory control circuitry 34 is coupled to the first memory 24 and the second memory 26 via address bus 36. In response to a memory address (addr) sent by host system 12 via address bus 16, memory control circuitry 34 generates an address (SRAM_addr) specifically for the first memory 24 and the second memory 26 for use on address bus 36. In a preferred embodiment, the same address (SRAM_addr) is applied to the first memory 24 and the second memory 26 via address bus 36, and thus the first memory 24 and the second memory 26 are configured to cover the same memory address range. Logic 24b and 26b process the applied address to access locations in memory arrays 24a and 26a, respectively.

[0019] The memory controller circuit 34 further asserts a chip select (CS) signal to select the first memory 24 and the second memory 26 for operation (read and write). The CS signal is processed by logic 24b and 26b to enable memory arrays 24a and 26a for operation, respectively.

[0020] The memory controller circuit 34 is further coupled to the first memory 24 via a bidirectional data bus 40, which carries application data (app_data) to be stored in or retrieved from the first memory array 24a. The data bus 40 is not coupled to the second memory 26.

[0021] The memory controller circuitry 34 includes error correction code (ECC) circuitry 44, which operates in a manner widely known to those skilled in the art to process application data (app_data received from host system 12 during a requested write operation), and in some cases, memory addresses (addr) or SRAM_addr, and to calculate ECC check bits (ECC_write) for the first and second memories 24 and 26 to be written via the ECC bus 46 to the memory locations specified by the address (SRAM_addr) on the address bus 36. In an exemplary embodiment, 8-bit ECC check bits may be calculated for each 64-bit data slice in the application data (app_data).

[0022] The memory controller circuitry 34 is further coupled to the first memory 24 via a read ECC bus 52, which transmits an ECC check bit (ECC_read) read from the first memory 24 and transmitted to the ECC circuitry 44 in response to a read address on the address bus 36. In this context, it should be understood that the ECC check bit (ECC_read) should be identical to the fault-free ECC check bit (ECC_write) of the first memory 24. In a manner widely known to those skilled in the art, the ECC circuitry 44 processes the ECC check bit (ECC_read) to identify, and potentially correct, errors in the application data (app_data) read from the first memory 24.

[0023] although Figure 1 The write ECC bus 46 and read ECC bus 52 are shown as separate buses, but it should be understood that in the implementation these are logically distinct and the ECC check bits may instead be carried by a bidirectional bus.

[0024] Logic circuit 60 is coupled to read ECC bus 52 and further coupled to second memory 26 by redundant read ECC bus 62. Logic circuit 60 receives a redundant ECC check bit (red_ECC_read) accessed in second memory 26 in response to a read address on address bus 36. In this context, it should be understood that the redundant ECC check bit (red_ECC_read) should be identical to the non-faulty ECC check bit (ECC_write) of second memory 26. Logic circuit 60 acts as a data comparator circuit to compare individual bits of ECC check bit (ECC_read) with individual bits of redundant ECC check bit (red_ECC_read). If all bits match in this bit-by-bit comparison, logic circuit 60 establishes an SRAM_OK signal on line 70 coupled to host system 12. Host system 12 interprets the establishment of the SRAM_OK signal on line 70 as indicating that one or more of the first memory 24 and the second memory 26 are fault-free or faulty. Conversely, a bit mismatch in a bitwise comparison indicates the presence of a fault in one or both of the first memory 24 and the second memory 26, and is therefore deasserted by the logic circuit 60 to the SRAM_OK signal.

[0025] The memory system 10 operates as follows during application data writing: a) The host system 12 applies a memory address (addr) to the address bus 16, applies application data (app_data) to the data bus 18, and establishes a write control signal; b) The memory controller circuit 34 generates an address (SRAM_addr) for the first memory 24 and the second memory 26 from the memory address (addr) received from the host system 12, and applies the address (SRAM_addr) to the address bus 36; c) The memory controller circuit 34 further applies the application data (app_data) received from the host system 12 to the bidirectional data bus 40; d) The ECC circuit 44 processes the data received on the data bus 18. e) The memory controller circuit 34 further applies the ECC check bit (ECC_write) to the write-to-ECC bus 46; f) The logic circuit 24b of the first memory 24 stores the application data (app_data) and the ECC check bit (ECC_write) at a specified address (SRAM_addr) in the memory array 24a; and g) The logic circuit 26b of the second memory 26 stores the ECC check bit (ECC_write) at a specified address (SRAM_addr) in the memory array 26a (Note: The second memory 26 does not store the application data (app_data)).

[0026] The memory system 10 operates as follows during application data reading: a) The host system 12 applies a memory address (addr) to the address bus 16 and establishes a read control signal; b) The memory controller circuit 34 generates an address (SRAM_addr) for the first memory 24 and the second memory 26 from the memory address (addr) received from the host system 12 and applies the address (SRAM_addr) to the address bus 36; c) The logic circuit 24b of the first memory 24 retrieves the application data (app_data) and ECC check bit (ECC_read) stored at address (SRAM_addr) in the memory array 24a and applies them to the data bus 40 and the read ECC bus 52, respectively; d) The logic circuit 26b of the second memory 26 retrieves the application data (app_data) and ECC check bit (ECC_read) stored at address (SRAM_addr) in the memory array 26a. The redundant ECC check bit (red_ECC_read) at M_addr is used to apply to the redundant read ECC bus 62; e) the ECC circuit 44 processes the application data (app_data) received on the data bus 40 and the ECC check bit (ECC_read) received on the read ECC bus 52 to identify and correct errors, and applies the erroneously corrected application data (app_data) to the data bus 18 for delivery to the host system 12; and f) the logic circuit 60 performs a bit-by-bit comparison of the ECC check bit (ECC_read) and the redundant ECC check bit (red_ECC_read), and establishes the SRAM_OK signal if a complete bit match is found (and otherwise deasserts the SRAM_OK signal if any bit mismatch is detected).

[0027] The host system 12 can handle the de-established SRAM_OK signal (indicating a bitwise comparison failure and a possible memory fault) in many ways. For example, the host system 12 can raise a flag to query memory operations, but otherwise retrieve error-corrected application data (app_data) as normal use. Alternatively, the host system 12 can perform an operation to perform another read (at the same or a different memory location) in response to the de-establishment of the SRAM_OK signal for double checking or detection of a fault. Furthermore, the host system 12 can terminate further memory access operations caused by a detected fault and establish an error code.

[0028] Now, referring again to the previously stated content regarding faults in the logic circuitry of the memory, one fault of interest involves an addressing fault, where application data with ECC intended to be written to a first memory address is instead written to a second memory address. Using... Figure 1In this implementation, an erroneous write of application data with ECC to the second memory address may occur in memory array 24a due to a fault in logic 24b. However, it is unlikely that logic 26b of memory 26 will be similarly affected, so the ECC will be correctly written to the first memory address in memory array 26a. A subsequent read from the first memory address of memory array 24a, comparing the read data with the ECC, will likely reveal no data error. However, the ECC read from the first memory address in memory array 24a will not match the ECC read from the first memory address in memory array 26a. The de-established SRAM_OK signal will therefore indicate to host 12 that there is no error. Following the same path, a further read from the second memory address of memory array 24a, comparing the read data with the ECC, will likely reveal no data error, but the ECC read from the second memory address in memory array 24a will not match the ECC read from the second memory address in memory array 26a. The de-established SRAM_OK signal will therefore indicate to host 12 that there is an error.

[0029] Recall the previously described failure in the memory logic circuitry related to chip selection (CS): the application data requested by host 12 for writing to a selected memory chip did not occur. Figure 1 In this implementation, even if the application data with ECC is not written to the memory address in memory 24 due to a fault in logic 24b, it is unlikely that logic 26b in memory 26 will be similarly affected. Therefore, the ECC will be correctly written to that memory address in memory array 26a. Subsequent readings from that memory address in memory array 24a, comparing the read data with the ECC, will likely reveal no data errors. However, the ECC read from that memory address in memory array 24a will not match the ECC read from that memory address in memory array 26a. The de-established SRAM_OK signal will therefore indicate an error to host 12.

[0030] Figure 1 The advantage of this implementation is that a small memory 26 with relatively simple logic circuitry can be used to detect faults in the memory logic. Existing solutions for this memory logic fault detection / prevention would require specially designed memory (such as SRAM with feedback known in the art) or a complete copy of the memory.

[0031] The foregoing description has provided a comprehensive and rich description of one or more exemplary embodiments of the invention by way of exemplary and non-limiting examples. However, various modifications and alterations may become apparent to those skilled in the art when read in conjunction with the accompanying drawings and appended claims, taking into account the foregoing description. Nevertheless, all such teachings and similar modifications of the invention will still fall within the scope of the invention as defined in the appended claims.

Claims

1. A method for operating a memory system, the memory system comprising a memory controller, a first memory, and a second memory, the method comprising: When in write operation mode, the memory controller: Apply the memory address to both the first memory and the second memory; The application data with the corresponding error correction code (ECC) check bit is written to the memory address in the first memory. as well as Write the ECC check bit, instead of the corresponding application data, to the memory address in the second memory; When in read operation mode, the memory controller: Apply the memory address to both the first memory and the second memory; The ECC check bit and the corresponding application data are read only from the memory address in the first memory; The ECC check bit is obtained only from the memory address in the second memory; as well as A bit-by-bit comparison is performed between the ECC check bit read only from the first memory and the ECC check bit obtained from the second memory to generate a signal indicating that a fault exists in one or more of the first and second memories if the bit-by-bit comparison of the ECC check bit fails.

2. The method of claim 1, further comprising the memory controller performing ECC processing on the application data received from the host system to generate the ECC check bit.

3. The method according to claim 1, further comprising performing ECC processing on the application data and the ECC check bits read from the first memory by the memory controller to detect and correct data errors in the read application data.

4. The method of claim 1, wherein the first memory and the second memory each comprise an SRAM array.

5. The method according to claim 1, wherein the memory array of the first memory is larger than the memory array of the second memory.

6. A method comprising: Application data is written by the memory controller of the memory system: Calculate the error correction code (ECC) check bits from the application data; The application data and the calculated ECC check bits are written into the first memory of the memory system; as well as Write the ECC check bit, instead of the application data, into the second memory of the memory system.

7. The method of claim 6, wherein the writing includes the memory controller: A memory address is generated in response to a write request; The application data and the calculated ECC check bit are written to the memory address in the first memory of the memory system; as well as Write the ECC check bit, instead of the application data, to the same memory address in the second memory of the memory system.

8. The method of claim 7, wherein each of the first memory and the second memory comprises an SRAM array.

9. The method according to claim 7, wherein the memory array of the first memory is larger than the memory array of the second memory.

10. The method of claim 7, further comprising: Application data is read by the memory controller: Read the application data and ECC check bits from the first memory; Use the read ECC check bits to detect and correct errors in the read application data; Receive the ECC check bit from the first memory and the second memory; as well as A bit-by-bit comparison is performed on the ECC check bits received only from the first memory and from the second memory to generate a signal indicating that a fault exists in one or more of the first memory and the second memory if the bit-by-bit comparison of the ECC check bits fails.

11. The method of claim 10, wherein reading includes the memory controller: A memory address is generated in response to a read request; Read the application data and the ECC check bit from the memory address in the first memory; and The ECC check bit is received from the same memory address in the first memory and the second memory.

12. The method of claim 10, wherein each of the first memory and the second memory comprises an SRAM array.

13. The method of claim 10, wherein the memory array of the first memory is larger than the memory array of the second memory.

14. A method for operating a memory controller, comprising: The application data and the error correction code (ECC) check bits associated with the application data are stored in the first memory; The ECC check bit associated with the application data is stored in a second memory, wherein the second memory does not store the application data; Read the application data and the ECC check bit from the first memory; Use the retrieved ECC check bits to detect and correct errors in the retrieved application data; Receive ECC check bits from both the first memory and the second memory; as well as A bit-by-bit comparison is performed on the ECC check bits received only from the first memory and the second memory to generate a signal indicating that one or more of the first memory and the second memory are faulty if the bit-by-bit comparison of the ECC check bits fails.

15. The method of claim 14, further comprising applying the same memory address to both the first memory and the second memory to read the application data and the ECC check bit from the first memory, and causing the second memory to output the ECC check bit.

16. The method of claim 14, wherein the first memory and the second memory each comprise an SRAM array.

17. The method of claim 14, wherein the memory array of the first memory is larger than the memory array of the second memory.

18. A method for a memory controller to read application data, comprising: Read the application data and the error correction code (ECC) check bits associated with the application data from the first memory of the memory system: Use the retrieved ECC check bits to detect and correct errors in the retrieved application data; The ECC check bit associated with the application data is received from both the first memory and the second memory (which does not store the application data) of the memory system; and A bit-by-bit comparison is performed only on the received ECC check bits to generate a signal indicating that a fault exists in one or more of the first and second memories if the bit-by-bit comparison of the ECC check bits fails.

19. The method of claim 18, wherein each of the first memory and the second memory comprises an SRAM array.

20. The method of claim 18, wherein the memory array of the first memory is larger than the memory array of the second memory.

21. The method of claim 18, further comprising: Generate the memory address to be read; When the application data and the ECC check bit are read from the first memory, the memory address is applied to the first memory; as well as When the ECC check bit is received, the same memory address is applied to the second memory.

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