Semiconductor structure and method of forming the same

Abstract

The application provides a semiconductor structure and a forming method thereof, the semiconductor structure comprising: a substrate, the substrate comprising a semiconductor substrate and an epitaxial layer on the surface of the semiconductor substrate, the epitaxial layer comprising a gate region for forming a trench gate structure; a mask layer on the surface of the epitaxial layer covering the gate region, the material of the mask layer being a semiconductor material; a body contact structure in the epitaxial layer around the gate region, the body contact structure surrounding the length direction edge of the gate region and partially surrounding the width direction edge of the gate region, the proportion of the part of the body contact structure surrounding the width direction edge of the gate region to the width direction edge of the gate region being greater than or equal to 50% and less than 100%. The application can improve the electric field control ability of the bottom edge of the trench gate structure in the silicon carbide MOSFET with the trench gate structure and the process efficiency, and improve the device performance and the device reliability.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor, and in particular to a semiconductor structure and a forming method thereof. BACKGROUND

[0002] In a silicon carbide MOSFET with a trench gate structure, the electric field control of the bottom edge of the trench gate structure is one of the factors affecting the reliability of the gate insulating layer. In order to control the electric field, in some processes, a trench isolation structure is formed on both sides of the trench gate structure and ion implantation is performed at the bottom of the trench isolation structure to form a doped region. The doped region at the bottom of the trench isolation structure is deeper than the trench gate structure.

[0003] However, the formation of the trench isolation structure and the doped region requires additional trench etching and multiple ion implantations, which is low in process efficiency and cannot guarantee the electric field control capability, and the device reliability is low.

[0004] Therefore, it is necessary to provide a more effective and reliable technical solution to improve the process efficiency and the electric field control capability. SUMMARY

[0005] The present application provides a semiconductor structure and a forming method thereof, which can improve the electric field control capability of the bottom edge of the trench gate structure and the process efficiency in a silicon carbide MOSFET with a trench gate structure.

[0006] One aspect of the present application provides a forming method of a semiconductor structure, comprising: providing a substrate, the substrate comprising a semiconductor substrate and an epitaxial layer on the surface of the semiconductor substrate, the epitaxial layer comprising a gate region for forming a trench gate structure; forming a mask layer covering the gate region on the surface of the epitaxial layer, the material of the mask layer being a semiconductor material; forming a body contact structure in the epitaxial layer around the gate region by ion implantation process with the mask layer as a mask, the body contact structure surrounding the length direction edge of the gate region and partially surrounding the width direction edge of the gate region, the proportion of the part of the body contact structure surrounding the width direction edge of the gate region to the width direction edge of the gate region being greater than or equal to 50% and less than 100%.

[0007] In some embodiments of the present application, the semiconductor material comprises germanium-doped polysilicon, silicon carbide, amorphous silicon carbide or SiGeC.

[0008] In some embodiments of the present application, the method of forming the mask layer comprises a chemical vapor deposition process or a sputtering process.

[0009] In some embodiments of the present application, the thickness of the mask layer is 5 microns to 10 microns.

[0010] In some embodiments of the application, the material of the epitaxial layer is 4H-SiC, and the upper surface of the epitaxial layer is a silicon face, and the angle between the silicon face and the horizontal plane is 0-4 degrees.

[0011] In some embodiments of the application, the angle between the injection angle of the ion implantation process and the normal line of the silicon face is -0.5-5 degrees; the injection ions of the ion implantation process are aluminum ions; the injection energy of the ion implantation process is 500 keV-50 MeV; the injection depth of the ion implantation process is 2-15 microns; the injection concentration of the ion implantation process is 5E15 atom / cm 3 1E17 atom / cm 3 ; the temperature of the ion implantation process is 100-1200 degrees Celsius.

[0012] In some embodiments of the application, the method for forming the semiconductor structure further comprises: forming a trench gate structure in the epitaxial layer of the gate region, the depth of the body contact structure being greater than the depth of the trench gate structure, and the width of the body contact structure being less than the width of the trench gate structure.

[0013] In some embodiments of the application, the body contact structure penetrates the epitaxial layer.

[0014] Another aspect of the application also provides a semiconductor structure, comprising: a substrate comprising a semiconductor substrate and an epitaxial layer on the surface of the semiconductor substrate, the epitaxial layer comprising a gate region for forming a trench gate structure; a mask layer on the surface of the epitaxial layer covering the gate region, the material of the mask layer being a semiconductor material; a body contact structure in the epitaxial layer around the gate region, the body contact structure surrounding the length direction edge of the gate region and partially surrounding the width direction edge of the gate region, the proportion of the part of the body contact structure surrounding the width direction edge of the gate region to the width direction edge of the gate region being greater than or equal to 50% and less than 100%.

[0015] In some embodiments of the application, the semiconductor material comprises germanium-doped polysilicon, silicon carbide, amorphous silicon carbide, or SiGeC.

[0016] In some embodiments of the application, the thickness of the mask layer is 5-10 microns.

[0017] In some embodiments of the application, the material of the epitaxial layer is 4H-SiC, and the upper surface of the epitaxial layer is a silicon face, and the angle between the silicon face and the horizontal plane is 0-4 degrees.

[0018] In some embodiments of the present application, the body contact structure has implanted ions, the implanted ions are aluminum ions; 5E15 atom / cm 3 to 1E17 atom / cm 3 .

[0019] In some embodiments of the present application, the semiconductor structure further comprises: a trench gate structure in the epitaxial layer of the gate region, the depth of the body contact structure is greater than the depth of the trench gate structure, and the width of the body contact structure is less than the width of the trench gate structure.

[0020] In some embodiments of the present application, the body contact structure penetrates the epitaxial layer.

[0021] The present application provides a semiconductor structure and a forming method thereof, a body contact structure is formed on both sides of a trench gate structure, which can improve the electric field control ability of the edge at the bottom of the trench gate structure in a silicon carbide MOSFET with a trench gate structure and the process efficiency, in addition, using semiconductor material as a mask during ion implantation process can improve the ion implantation quality and the overall process efficiency, improve the quality of the body contact structure, improve the device performance and device reliability. BRIEF DESCRIPTION OF DRAWINGS

[0022] The following drawings in detail describe the exemplary embodiments disclosed in the present application. The same reference signs in the several views of the drawings represent similar structures. Those skilled in the art will understand that these embodiments are non-limiting, exemplary embodiments, the drawings are only for the purpose of illustration and description, and are not intended to limit the scope of the present application, other ways of embodiments can also achieve the same intention of the invention in the present application. It should be understood that the drawings are not drawn to scale.

[0023] wherein:

[0024] Figures 1 to 8 The structure schematic diagram of each step in the forming method of the semiconductor structure described in the embodiments of the present application. DETAILED DESCRIPTION

[0025] The following description provides specific application scenarios and requirements of the present application, which is to enable those skilled in the art to manufacture and use the content in the present application. Various local modifications of the disclosed embodiments are obvious to those skilled in the art, and the general principles defined herein can be applied to other embodiments and applications without departing from the spirit and scope of the present application. Therefore, the present application is not limited to the shown embodiments, but is consistent with the widest scope of the claims.

[0026] The technical solutions of the present application will be described in detail below in combination with embodiments and drawings.

[0027] The technical solutions of the present application will be described in detail below in combination with embodiments and drawings.Figures 1 to 8 The structure schematic diagram of each step in the forming method of the semiconductor structure is shown. The forming method of the semiconductor structure is described in detail below with reference to the accompanying drawings.

[0028] Reference is made to Figure 1 and Figure 2 , wherein, Figure 1 is a top view, Figure 2 is a longitudinal section view along the dotted line X-X in Figure 1 The substrate 100 is provided, which includes a semiconductor substrate 101 and an epitaxial layer 102 on the surface of the semiconductor substrate 101, and the epitaxial layer 102 includes a gate region 103 for forming a trench gate structure.

[0029] In some embodiments of the present application, the semiconductor structure described in the embodiments of the present application is, for example, a silicon carbide MOSFET with a trench gate structure.

[0030] In some embodiments of the present application, the semiconductor substrate 101 is a silicon carbide substrate, and the material of the semiconductor substrate 101 is silicon carbide. The material of the epitaxial layer 102 is also silicon carbide.

[0031] In some embodiments of the present application, the material of the epitaxial layer 102 is 4H-SiC, and the upper surface of the epitaxial layer 102 is a silicon face with an angle of 0 to 4 degrees with the horizontal plane. There are various polytypes of silicon carbide, the most common of which are, for example, 3C-SiC with cubic crystal structure, 4H-SiC and 6H-SiC with hexagonal crystal structure, etc. Single crystal SiC can be oriented and polished to present a main crystal face as its surface, for example, (0001) face, i.e. silicon face, with silicon as the surface. The silicon face can be miscut so that the angle of the silicon face with the horizontal plane is 0 to 4 degrees, for example, 1 degree, 2 degrees, or 3 degrees, etc.

[0032] Reference is made to Figure 3 and Figure 4 , wherein, Figure 3 is a top view, Figure 4 is a longitudinal section view along the dotted line X-X in Figure 3 The mask layer 110 is formed on the surface of the epitaxial layer 102, which covers the gate region 103, and the material of the mask layer 110 is a semiconductor material.

[0033] Reference is made to Figure 3 , the mask layer 110 also covers the positions above and below the gate region 103. The above and below refer to the orientation of the structure shown in Figure 3 .

[0034] In some embodiments of the present application, the semiconductor material includes polycrystalline silicon doped with germanium, silicon carbide, amorphous silicon carbide, or SiGeC, wherein the molar ratio of silicon atoms to germanium atoms in the polycrystalline silicon doped with germanium is (99-50):(1-50), i.e., the number of moles of silicon atoms accounts for 50% to 99% of the total number of moles of silicon atoms and germanium atoms; i.e., the number of moles of germanium atoms accounts for 1% to 50% of the total number of moles of silicon atoms and germanium atoms. In SiGeC, the molar ratio of silicon atoms, germanium atoms, and carbon atoms is (99-50):(1-48):(1-48), i.e., the number of moles of silicon atoms accounts for 50% to 99% of the total number of moles of silicon atoms, germanium atoms, and carbon atoms; i.e., the number of moles of germanium atoms accounts for 1% to 48% of the total number of moles of silicon atoms, germanium atoms, and carbon atoms; i.e., the number of moles of carbon atoms accounts for 1% to 48% of the total number of moles of silicon atoms, germanium atoms, and carbon atoms. The mask layer 110 serves to protect the gate region 103 from damage or doping in subsequent ion implantation processes. However, the mask layer materials currently used are generally silicon oxide or silicon nitride, which have insufficient protection effect in the case of large ion implantation energy and deep ion implantation depth. Moreover, the deposition rate of silicon oxide and silicon nitride is slow, and the deposition process conditions are high, for example, the temperature requirement is higher than 1000 degrees Celsius. The present application uses the above semiconductor material as the mask layer, which can improve the protection effect of the mask layer, increase the deposition rate of the mask layer, reduce the formation conditions of the mask layer, and improve the process efficiency.

[0035] Specifically, in the process of depositing SiGe, the gas source is SiH4 or SiH2Cl2, GeH4; the carrier gas is N2 or Ar or He; the pressure is 80 to 600 Torr; the temperature is 500 to 1000 degrees Celsius; and the deposition rate is 0.5 to 1 micrometer per minute.

[0036] In the process of depositing SiGeC, the gas source is SiH4 or SiH2Cl2, GeH4, C3H8; the carrier gas is N2 or Ar or He; the pressure is 80 to 600 Torr; the temperature is 500 to 1000 degrees Celsius; and the deposition rate is 0.5 to 1 micrometer per minute.

[0037] In some embodiments of the present application, the method of forming the mask layer 110 includes a chemical vapor deposition process or a sputtering process.

[0038] The chemical vapor deposition (CVD) process can still achieve rapid growth at low temperatures (below 1000 degrees Celsius). For example, taking germanium-doped polysilicon as the semiconductor material, the doping with germanium impurities is particularly beneficial for increasing the deposition rate. Germanium-doped polysilicon provides a localized effect of hydrogen diffusion from silicon to the germanium surface phase. Hydrogen is released from the GeH intermediate. Experiments show that doping with germanium in the polysilicon layer can significantly improve the deposition rate at low temperatures. More specifically, the hydrogen released from the germanium-covered surface, influenced by the presence of impurities, increases the CVD deposition rate. Adjusting the molar ratio of silicon to germanium atoms in the germanium-doped polysilicon can regulate the deposition rate. Polysilicon typically exhibits a columnar crystal structure with vertical boundaries. For ion-implanted hard masks, vertical boundaries are unfavorable because ions can be introduced along them; doping with additional Ge or C further reduces the number of vertical boundaries in the random structure of the polysilicon.

[0039] The sputtering process can be single-target sputtering of SiGe or dual-target sputtering of Si and Ge.

[0040] In some embodiments of this application, the thickness of the mask layer 110 is 5 micrometers to 10 micrometers. Increasing the thickness of the mask layer 110 can also increase its protective capability.

[0041] refer to Figure 5 and Figure 6 As shown, where, Figure 5 This is a top view. Figure 6 For along Figure 5 The longitudinal cross-sectional view is shown by the dashed line XX. Using the mask layer 110 as a mask, a bulk contact structure 120 is formed in the epitaxial layer 102 on both sides of the gate region 103 by ion implantation.

[0042] refer to Figure 5 As shown, the body contact structure 120 surrounds the length side of the gate region 103 and partially surrounds the width side of the gate region 103. Specifically, refer to... Figure 5 As shown, the body contact structure 120 located above and below the gate region 103 does not completely surround the gate region 103; the body contact structure 120 surrounds the side of the gate region 103 in the width direction (i.e., Figure 5 The portion of the upper and lower edges of the gate region 103 accounts for more than or equal to 50% but less than 100% of the width of the gate region 103, for example, 60%, 70%, 80%, 90%, or 95%. The length refers to... Figure 5 The dimension in the vertical direction, the width refers to Figure 5 The dimensions in the horizontal direction.

[0043] In some embodiments of this application, the body contact structure 120 extends through the epitaxial layer 102 to the surface of the semiconductor substrate 101.

[0044] In some embodiments of this application, the implantation angle of the ion implantation process is between -0.5 degrees and 5 degrees with the normal to the silicon surface; the implanted ions are p-type, such as aluminum ions; the implantation energy is between 500 keV and 50 MeV; the implantation depth is between 2 micrometers and 15 micrometers; and the implantation concentration is 5E15 atom / cm³. 3 Up to 1E17atom / cm 3 The temperature of the ion implantation process is between 100 degrees Celsius and 1200 degrees Celsius.

[0045] Due to the protection of the mask layer 110, even if the ion implantation process has a high implantation energy and a deep implantation depth, and even if ion implantation can be performed multiple times, the gate region 103 will not be damaged or doped by the ion implantation process.

[0046] refer to Figure 7 and Figure 8 As shown, where, Figure 7 This is a top view. Figure 8 For along Figure 7 The longitudinal cross-section is shown by the dashed line XX. A trench gate structure 130 is formed in the gate region 103, and the depth of the body contact structure 120 is greater than the depth of the trench gate structure 130. The gate region 103 can be entirely formed as the trench gate structure 130, allowing the trench gate structure 130 to directly contact the body contact structure 120. Alternatively, the gate region 103 can be partially formed as the trench gate structure 130, such as... Figure 7 As shown in the figure, the trench gate structure 130 and the body contact structure 120 are separated by the epitaxial layer 102 and do not make direct contact.

[0047] In some embodiments of this application, a P-type ion implantation region may be formed in the epitaxial layer 102 at the bottom of the trench gate structure 130, and a metal layer may be formed at the bottom and sidewalls of the trench gate structure 130. The metal layer contacts the P-type ion implantation region but does not contact the body contact structure 120.

[0048] In some embodiments of this application, the method of forming the semiconductor structure may further include: forming a contact structure electrically connected to the body contact structure 120 on the body contact structure 120, and connecting the voltage through the contact structure to enable the body contact structure 120 to be connected to the voltage, thereby improving its electric field control capability.

[0049] In some embodiments of this application, a Schottky barrier diode (SBD) may be formed in the gate region 103 instead of a trench gate structure. A P-type ion implantation region may also be formed in the epitaxial layer 102 at the bottom of the Schottky diode, and a metal layer may be formed on the bottom and sidewalls of the Schottky diode. The metal layer contacts the P-type ion implantation region but not the body contact structure 120.

[0050] In some embodiments of this application, the semiconductor structure described herein can also be a silicon carbide device with a planar MOSFET structure. In this case, the gate region is located above the epitaxial layer, and the body contact structure is located in the epitaxial layer surrounding the gate region.

[0051] This application provides a method for forming a semiconductor structure, which forms a body contact structure on both sides of a trench gate structure. This method can improve the electric field control capability and process efficiency of the bottom edge of the trench gate structure in a silicon carbide MOSFET with a trench gate structure. In addition, using a semiconductor material as a mask during the ion implantation process can improve the ion implantation quality and overall process efficiency, improve the quality of the body contact structure, and improve device performance and device reliability.

[0052] refer to Figure 5 and Figure 6 As shown, where, Figure 5 This is a top view. Figure 6 For along Figure 5 The longitudinal cross-section is shown by the dashed line XX. Embodiments of this application also provide a semiconductor structure, comprising: a substrate 100, the substrate 100 including a semiconductor substrate 101 and an epitaxial layer 102 located on the surface of the semiconductor substrate 101, the epitaxial layer 102 including a gate region 103 for forming a trench gate structure; a mask layer 110 located on the surface of the epitaxial layer 102 covering the gate region 103, the mask layer 110 being made of a semiconductor material; and a body contact structure 120 located in the epitaxial layer 102 surrounding the gate region 103, the body contact structure 120 surrounding the length side of the gate region 103 and partially surrounding the width side of the gate region 103, the portion of the body contact structure 120 surrounding the width side of the gate region 103 being greater than or equal to 50% and less than 100%, for example, 60%, 70%, 80%, 90%, or 95%, etc. Wherein, the length refers to... Figure 5 The dimension in the vertical direction, the width refers to Figure 5 The dimensions in the horizontal direction.

[0053] In some embodiments of the present application, the semiconductor structure described in the present application is, for example, a silicon carbide MOSFET with a trench gate structure.

[0054] In some embodiments of the present application, the semiconductor substrate 101 is a silicon carbide substrate, and the material of the semiconductor substrate 101 is silicon carbide. The material of the epitaxial layer 102 is also silicon carbide.

[0055] In some embodiments of the present application, the material of the epitaxial layer 102 is 4H-SiC, and the upper surface of the epitaxial layer 102 is a silicon face with an angle of 0-4 degrees with the horizontal plane. There are various polytypes of silicon carbide, the most common of which are, for example, 3C-SiC with a cubic crystal structure, 4H-SiC and 6H-SiC with a hexagonal crystal structure, etc. Single crystal SiC can be oriented and polished to present a major crystal face as its surface, for example, a (0001) face, i.e., a silicon face, with silicon as the surface. The silicon face can be miscut so that the silicon face has an angle of 0-4 degrees, for example, 1 degree, 2 degrees, or 3 degrees, etc., with the horizontal plane.

[0056] Reference Figure 3 As shown, the mask layer 110 also covers part of the positions above and below the gate region 103. The upper and lower refer to the orientation of the structure shown. Figure 3 As shown, the structure shown.

[0057] In some embodiments of the present application, the semiconductor material includes germanium-doped polysilicon, silicon carbide, amorphous silicon carbide, or SiGeC, wherein the molar ratio of silicon atoms and germanium atoms in the germanium-doped polysilicon is (99-50):(1-50), i.e., the number of moles of silicon atoms accounts for 50% to 99% of the total number of moles of silicon atoms and germanium atoms; i.e., the number of moles of germanium atoms accounts for 1% to 50% of the total number of moles of silicon atoms and germanium atoms. The molar ratio of silicon atoms, germanium atoms, and carbon atoms in SiGeC is (99-50):(1-48):(1-48), i.e., the number of moles of silicon atoms accounts for 50% to 99% of the total number of moles of silicon atoms, germanium atoms, and carbon atoms; i.e., the number of moles of germanium atoms accounts for 1% to 48% of the total number of moles of silicon atoms, germanium atoms, and carbon atoms; i.e., the number of moles of carbon atoms accounts for 1% to 48% of the total number of moles of silicon atoms, germanium atoms, and carbon atoms. The function of the mask layer 110 is to protect the gate region 103 from damage or doping in the subsequent ion implantation process. However, the mask layer material currently used is generally silicon oxide or silicon nitride, and such material has insufficient protection effect in the case of large ion implantation energy and deep ion implantation depth. Moreover, the deposition rate of silicon oxide and silicon nitride is slow, and the deposition process conditions are also high, for example, the temperature requirement is higher than 1000 degrees Celsius. The present application uses the above semiconductor material as the mask layer, which can improve the protection effect of the mask layer, increase the deposition rate of the mask layer, reduce the formation conditions of the mask layer, and improve the process efficiency.

[0058] In some embodiments of the present application, the thickness of the mask layer 110 is 5-10 microns. Increasing the thickness of the mask layer 110 can also increase the protection ability of the mask layer 110.

[0059] In some embodiments of the present application, the body contact structure 120 penetrates the epitaxial layer 102 to the surface of the semiconductor substrate 101.

[0060] In some embodiments of the present application, the body contact structure 120 has implanted ions therein, the implanted ions are P-type, such as aluminum ions; the concentration of the implanted ions is 5E15 atom / cm 3 to 1E17 atom / cm 3 .

[0061] Referring to Figure 7 and Figure 8 , wherein, Figure 7 is a top view, Figure 8 is a longitudinal cross-sectional view along the dotted line X-X in Figure 7 In some embodiments of the present application, the semiconductor structure further comprises: a trench gate structure 130 in the epitaxial layer 102 of the gate region 103, the depth of the body contact structure 120 is greater than the depth of the trench gate structure 130. Wherein, the gate region 103 can be entirely formed of the trench gate structure 130 so that the trench gate structure 130 directly contacts the body contact structure 120. The gate region 103 can also be partially formed of the trench gate structure 130, as shown in Figure 7 and Figure 8 , so that the trench gate structure 130 is separated from the body contact structure 120 by the epitaxial layer 102 and does not directly contact the body contact structure 120.

[0062] In some embodiments of the present application, the epitaxial layer 102 at the bottom of the trench gate structure 130 can also be formed with a P-type ion implantation region, the bottom and sidewall of the trench gate structure 130 are formed with a metal layer. The metal layer contacts the P-type ion implantation region, but does not contact the body contact structure 120.

[0063] In some embodiments of the present application, the semiconductor structure can further comprise: a contact structure on the body contact structure 120, the contact structure electrically connects the body contact structure 120, and the body contact structure 120 is connected to the voltage through the contact structure to improve the electric field control ability thereof.

[0064] In some embodiments of this application, the structure formed in the gate region 103 may not be a trench gate structure, but a Schottky barrier diode (SBD). A P-type ion implantation region may also be formed in the epitaxial layer 102 at the bottom of the Schottky diode, and a metal layer is formed on the bottom and sidewalls of the Schottky diode. The metal layer contacts the P-type ion implantation region but not the body contact structure 120.

[0065] In some embodiments of this application, the semiconductor structure described herein can also be a silicon carbide device with a planar MOSFET structure. In this case, the gate region is located above the epitaxial layer, and the body contact structure is located in the epitaxial layer surrounding the gate region.

[0066] This application provides a semiconductor structure and a method for forming the same. By forming a body contact structure on both sides of a trench gate structure, the electric field control capability and process efficiency of the bottom edge of the trench gate structure in a silicon carbide MOSFET with a trench gate structure can be improved. In addition, by using a semiconductor material as a mask during the ion implantation process, the ion implantation quality and overall process efficiency can be improved, the quality of the body contact structure can be improved, and the device performance and device reliability can be improved.

[0067] In summary, after reading this application, those skilled in the art will understand that the foregoing application content is presented by way of example only and is not restrictive. Although not explicitly stated herein, those skilled in the art will understand that this application is intended to encompass various reasonable changes, improvements, and modifications to the embodiments. These changes, improvements, and modifications are all within the spirit and scope of the exemplary embodiments of this application.

[0068] It should be understood that the term "and / or" as used in this embodiment includes any or all combinations of one or more of the associated listed items. It should be understood that when an element is referred to as "connected" or "coupled" to another element, it may be directly connected or coupled to the other element, or there may be an intermediate element.

[0069] Similarly, it should be understood that when an element such as a layer, region, or substrate is referred to as being "on" another element, it may be directly on that other element, or there may be intermediate elements present. Conversely, the term "directly" means without intermediate elements. It should also be understood that the terms "comprising," "including," "including," or "comprises," as used in this application, indicate the presence of the described features, integrals, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or groups thereof.

[0070] It will also be appreciated that, although terms such as first, second, third, etc. can be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. Thus, a first element in some embodiments could be called a second element in other embodiments without departing from the teachings of the present application. The same reference numerals or same reference designators denote the same elements throughout the specification.

[0071] Furthermore, the present application description describes exemplary embodiments by reference to idealized illustrative cross-sectional and / or plan and / or elevation views. Consequently, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and / or tolerances, are to be expected. Therefore, exemplary embodiments should not be construed as limited to the precise shapes and regions shown herein but are to include deviations in shapes that result, for example, from manufacturing. For example, an etched region illustrated as a rectangle will, typically, have rounded or curved features. Consequently, the regions illustrated in the figures are schematic and not drawn to scale. The same reference numerals or same reference designators denote the same elements throughout the specification.

Claims

1. A method of forming a semiconductor structure, comprising: The semiconductor structure is a silicon carbide MOSFET with a trench gate structure. The semiconductor material includes polycrystalline silicon doped with germanium, silicon carbide, amorphous silicon carbide, or SiGeC. The method for forming the mask layer includes a chemical vapor deposition process or a sputtering process. The thickness of the mask layer is 5 microns to 10 microns. The material of the epitaxial layer is 4H-SiC, the upper surface of the epitaxial layer is a silicon face, and the angle of the silicon face with the horizontal plane is 0 to 4 degrees.

2. The method of forming a semiconductor structure of claim 1, wherein, The semiconductor structure is a silicon carbide MOSFET with a trench gate structure.

3. The method of forming a semiconductor structure of claim 2, wherein, The semiconductor material includes polycrystalline silicon doped with germanium, silicon carbide, amorphous silicon carbide, or SiGeC.

4. The method of forming a semiconductor structure of claim 1, wherein, The method for forming the mask layer includes a chemical vapor deposition process or a sputtering process.

5. The method of forming a semiconductor structure of claim 1, wherein, The thickness of the mask layer is 5 microns to 10 microns.

6. The method of forming a semiconductor structure of claim 5, wherein, The ion implantation process has an implantation angle of -0.5 degrees to 5 degrees with respect to the normal of the silicon surface; the ion implantation process has an implantation energy of 500 keV to 50 MeV; the ion implantation process has an implantation depth of 2 microns to 15 microns; the ion implantation process has an implantation concentration of 5E15 atom / cm 3 to 1E17 atom / cm 3 ; and the ion implantation process has a temperature of 100 degrees Celsius to 1200 degrees Celsius.

7. The method of forming a semiconductor structure of claim 1, wherein The material of the epitaxial layer is 4H-SiC, the upper surface of the epitaxial layer is a silicon face, and the angle of the silicon face with the horizontal plane is 0 to 4 degrees. The semiconductor structure is a silicon carbide MOSFET with a trench gate structure.

8. The method of forming a semiconductor structure of claim 7, wherein, The semiconductor material includes polycrystalline silicon doped with germanium, silicon carbide, amorphous silicon carbide, or SiGeC.

9. A semiconductor structure, characterized by The method for forming the mask layer includes a chemical vapor deposition process or a sputtering process. The thickness of the mask layer is 5 microns to 10 microns. The material of the epitaxial layer is 4H-SiC, the upper surface of the epitaxial layer is a silicon face, and the angle of the silicon face with the horizontal plane is 0 to 4 degrees. The semiconductor structure is a silicon carbide MOSFET with a trench gate structure. The semiconductor material includes polycrystalline silicon doped with germanium, silicon carbide, amorphous silicon carbide, or SiGeC.

10. The semiconductor structure of claim 9, wherein, The method for forming the mask layer includes a chemical vapor deposition process or a sputtering process.

11. The semiconductor structure of claim 9, wherein, The thickness of the mask layer is 5 microns to 10 microns.

12. The semiconductor structure of claim 9, wherein, The material of the epitaxial layer is 4H-SiC, the upper surface of the epitaxial layer is a silicon face, and the angle of the silicon face with the horizontal plane is 0 to 4 degrees.

13. The semiconductor structure of claim 9, wherein, The body contact structure has implanted ions, the implanted ions are aluminum ions; the concentration of the implanted ions is 5E15 atom / cm 3 to 1E17 atom / cm 3 .

14. The semiconductor structure of claim 9, wherein, ​ ​ 15. The semiconductor structure of claim 14, wherein, ​

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