Semiconductor device and method for manufacturing the same

Abstract

The present invention provides a semiconductor device and a method for manufacturing the same. The method for manufacturing the semiconductor device includes: providing a substrate, the substrate including an NMOS device region and a PMOS device region, and gate structures are formed on the substrates of the NMOS device region and the PMOS device region; forming a buffer layer on the substrates of the NMOS device region and the PMOS device region, and the buffer layer covers the gate structure; removing the buffer layer on the NMOS device region; forming a stress layer on the buffer layer; when the stress layer is a tensile stress layer, the thickness of the buffer layer on the PMOS device region is greater than the thickness of the buffer layer on the NMOS device region; when the stress layer is a compressive stress layer, the thickness of the buffer layer on the NMOS device region is greater than the thickness of the buffer layer on the PMOS device region. The technical solution of the present invention can improve the performance of one of the NMOS device and the PMOS device and avoid reducing the performance of the other device while avoiding increasing the chip manufacturing cost.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor integrated circuit manufacturing, and in particular to a semiconductor device and a manufacturing method thereof. Background Art

[0002] At present, stress memory technology (SMT, Stress Memorization Technology) is usually used to improve the electron mobility of NMOS devices and the hole mobility of PMOS devices. Taking the improvement of the electron mobility of NMOS devices as an example, the steps include: after the sidewall and source and drain ion implantation processes are completed, a high tensile stress silicon nitride layer is deposited on the NMOS device area and the PMOS device area, and the tensile stress is transferred to the source, drain and gate of the NMOS device through a high temperature annealing process to improve the electron mobility of the NMOS device, and finally the silicon nitride layer is removed. However, the tensile stress in the silicon nitride layer will also be transferred to the source, drain and gate of the PMOS device, which will reduce the hole mobility of the PMOS device, thereby affecting the performance of the PMOS device.

[0003] In order to transfer more tensile stress to the NMOS device area and further improve the electron mobility of the NMOS device, a thicker silicon nitride layer will be deposited; but at the same time, the tensile stress in the thicker silicon nitride layer will be transferred to the PMOS device area, thereby affecting the performance of the PMOS device. Therefore, in order to improve the performance of the NMOS device while avoiding reducing the performance of the PMOS device, after depositing the thicker silicon nitride layer and before the high-temperature annealing process, an additional photolithography and etching process is added to remove the silicon nitride layer on the PMOS device area and only retain the silicon nitride layer on the NMOS device area. However, this method will add an additional photolithography and etching process, which will increase the chip manufacturing cost.

[0004] Therefore, how to improve the performance of one of the NMOS device and the PMOS device and avoid reducing the performance of the other device while avoiding increasing the chip manufacturing cost is an urgent problem to be solved. Summary of the invention

[0005] The object of the present invention is to provide a semiconductor device and a method for manufacturing the same, so as to improve the performance of one of the NMOS device and the PMOS device and avoid reducing the performance of the other device while avoiding increasing the chip manufacturing cost.

[0006] To achieve the above object, the present invention provides a method for manufacturing a semiconductor device, comprising:

[0007] Providing a substrate, the substrate comprising an NMOS device region and a PMOS device region, wherein gate structures are formed on the substrates of the NMOS device region and the PMOS device region;

[0008] Forming a buffer layer on the substrate of the NMOS device region and the PMOS device region, wherein the buffer layer covers the gate structure;

[0009] A stress layer is formed on the buffer layer; when the stress layer is a tensile stress layer, the thickness of the buffer layer on the PMOS device region is greater than the thickness of the buffer layer on the NMOS device region; when the stress layer is a compressive stress layer, the thickness of the buffer layer on the NMOS device region is greater than the thickness of the buffer layer on the PMOS device region.

[0010] Optionally, when the stress layer is a tensile stress layer, before forming the stress layer on the buffer layer, the method for manufacturing the semiconductor device further includes:

[0011] Forming a first source region and a first drain region in the substrate on both sides of the gate structure of the NMOS device region, wherein the first source region and the first drain region are formed using the same patterned photoresist layer as a mask as the buffer layer;

[0012] When the stress layer is a compressive stress layer, before forming the stress layer on the buffer layer, the method for manufacturing the semiconductor device further includes:

[0013] A second source region and a second drain region are formed in the substrate at both sides of the gate structure of the PMOS device region, and the second source region and the second drain region are formed using the same patterned photoresist layer as a mask as the buffer layer.

[0014] Optionally, when the stress layer is a tensile stress layer;

[0015] The step of forming the buffer layer on the substrate of the NMOS device region and the PMOS device region comprises:

[0016] Forming a first buffer layer on the substrate of the NMOS device region and the PMOS device region, wherein the first buffer layer covers the gate structure;

[0017] removing the first buffer layer on the NMOS device region;

[0018] forming a second buffer layer on the substrate and the gate structure in the NMOS device region and on the first buffer layer in the PMOS device region;

[0019] Alternatively, the step of forming the buffer layer on the substrate of the NMOS device region and the PMOS device region includes:

[0020] Forming a buffer layer on the substrate of the NMOS device region and the PMOS device region, wherein the buffer layer covers the gate structure;

[0021] A portion of the buffer layer on the NMOS device region is removed.

[0022] Optionally, before or after removing the first buffer layer on the NMOS device region, or before or after removing a portion of the buffer layer on the NMOS device region, the method for manufacturing the semiconductor device further includes:

[0023] A first source region and a first drain region are formed in the substrate on both sides of the gate structure of the NMOS device region, wherein the formation of the first source region and the first drain region and the removal of the first buffer layer on the NMOS device region or the removal of a portion of the thickness of the buffer layer on the NMOS device region use the same patterned photoresist layer as a mask.

[0024] Optionally, after removing the first buffer layer on the NMOS device region or after removing a portion of the buffer layer on the NMOS device region, the method for manufacturing the semiconductor device further includes:

[0025] A second source region and a second drain region are formed in the substrate at both sides of the gate structure of the PMOS device region.

[0026] Optionally, when the stress layer is a compressive stress layer;

[0027] The step of forming the buffer layer on the substrate of the NMOS device region and the PMOS device region comprises:

[0028] Forming a first buffer layer on the substrate of the NMOS device region and the PMOS device region, wherein the first buffer layer covers the gate structure;

[0029] removing the first buffer layer on the PMOS device region;

[0030] forming a second buffer layer on the substrate and the gate structure in the PMOS device region and on the first buffer layer in the NMOS device region;

[0031] Alternatively, the step of forming the buffer layer on the substrate of the NMOS device region and the PMOS device region includes:

[0032] Forming a buffer layer on the substrate of the NMOS device region and the PMOS device region, wherein the buffer layer covers the gate structure;

[0033] A portion of the buffer layer on the PMOS device region is removed.

[0034] Optionally, before or after removing the first buffer layer on the PMOS device region, or before or after removing a portion of the buffer layer on the PMOS device region, the method for manufacturing the semiconductor device further includes:

[0035] A second source region and a second drain region are formed in the substrate on both sides of the gate structure of the PMOS device region, wherein the second source region and the second drain region are formed and the first buffer layer on the PMOS device region or a portion of the buffer layer on the PMOS device region is removed using the same patterned photoresist layer as a mask.

[0036] Optionally, after removing the first buffer layer on the PMOS device region or after removing a portion of the buffer layer on the PMOS device region, the method for manufacturing the semiconductor device further includes:

[0037] A first source region and a first drain region are formed in the substrate on both sides of the gate structure of the NMOS device region.

[0038] Optionally, the method for manufacturing the semiconductor device further includes:

[0039] performing an annealing process;

[0040] The stress layer is removed.

[0041] The present invention also provides a semiconductor device, comprising:

[0042] A substrate, the substrate comprising an NMOS device region and a PMOS device region, and gate structures are formed on the substrates of the NMOS device region and the PMOS device region;

[0043] A buffer layer is formed on the substrate of the NMOS device region and the PMOS device region, and the buffer layer covers the gate structure;

[0044] A stress layer is formed on the buffer layer; when the stress layer is a tensile stress layer, the thickness of the buffer layer on the PMOS device region is greater than the thickness of the buffer layer on the NMOS device region; when the stress layer is a compressive stress layer, the thickness of the buffer layer on the NMOS device region is greater than the thickness of the buffer layer on the PMOS device region.

[0045] Optionally, a material of the stress layer includes silicon nitride, and a material of the buffer layer includes silicon oxide.

[0046] Optionally, the semiconductor device further includes:

[0047] A first source region and a first drain region are formed in the substrate on both sides of the gate structure of the NMOS device region;

[0048] A second source region and a second drain region are formed in the substrate at both sides of the gate structure of the PMOS device region.

[0049] Optionally, a P well is formed in the substrate of the NMOS device region, and the first source region and the first drain region are formed on the top of the P well; an N well is formed in the substrate of the PMOS device region, and the second source region and the second drain region are formed on the top of the N well.

[0050] Compared with the prior art, the technical solution of the present invention has the following beneficial effects:

[0051] 1. The method for manufacturing a semiconductor device of the present invention comprises the following steps: forming a buffer layer on a substrate in an NMOS device region and a PMOS device region, wherein the buffer layer covers a gate structure; removing the buffer layer on the NMOS device region; forming a stress layer on the buffer layer; when the stress layer is a tensile stress layer, the thickness of the buffer layer on the PMOS device region is greater than the thickness of the buffer layer on the NMOS device region; when the stress layer is a compressive stress layer, the thickness of the buffer layer on the NMOS device region is greater than the thickness of the buffer layer on the PMOS device region, so that the performance of one of the NMOS device and the PMOS device is improved and the performance of the other device is avoided from being reduced, while the chip manufacturing cost is avoided from being increased.

[0052] 2. The semiconductor device of the present invention comprises: a buffer layer formed on the substrate of the NMOS device region and the PMOS device region, and the buffer layer covers the gate structure; a stress layer formed on the buffer layer; when the stress layer is a tensile stress layer, the thickness of the buffer layer on the PMOS device region is greater than the thickness of the buffer layer on the NMOS device region; when the stress layer is a compressive stress layer, the thickness of the buffer layer on the NMOS device region is greater than the thickness of the buffer layer on the PMOS device region, so that the performance of one of the NMOS device and the PMOS device is improved and the performance of the other device is avoided from being reduced, while the chip manufacturing cost is avoided from being increased. BRIEF DESCRIPTION OF THE DRAWINGS

[0053] Figure 1 is a flow chart of a method for manufacturing a semiconductor device according to an embodiment of the present invention;

[0054] Figure 2a to Figure 2i yes Figure 1 A schematic diagram of a device in an embodiment of a method for manufacturing a semiconductor device is shown;

[0055] Figure 3a to Figure 3g yes Figure 1 A device schematic diagram of another embodiment of a method for manufacturing a semiconductor device is shown.

[0056] Among them, Figure 1 to Figure 3g The reference numerals are described as follows:

[0057] 11-substrate; 111-P well; 112-N well; 113-trench isolation structure; 114-lightly doped source region; 115-lightly doped drain region; 116-first source region; 117-first drain region; 118-second source region; 119-second drain region; 12-gate structure; 13-side wall; 14-buffer layer; 141-first buffer layer; 142-second buffer layer; 151-first patterned photoresist layer; 152-second patterned photoresist layer; 16-stress layer. DETAILED DESCRIPTION

[0058] In order to make the purpose, advantages and features of the present invention more clear, the semiconductor device and the manufacturing method thereof proposed by the present invention are further described in detail below. It should be noted that the drawings are all in a very simplified form and are not in precise proportions, which are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention.

[0059] An embodiment of the present invention provides a method for manufacturing a semiconductor device. Figure 1 ,from Figure 1 It can be seen that the method for manufacturing the semiconductor device includes:

[0060] Step S1, providing a substrate, wherein the substrate includes an NMOS device region and a PMOS device region, and gate structures are formed on the substrates of the NMOS device region and the PMOS device region;

[0061] Step S2, forming a buffer layer on the substrate of the NMOS device region and the PMOS device region, and the buffer layer covers the gate structure;

[0062] Step S3, forming a stress layer on the buffer layer; when the stress layer is a tensile stress layer, the thickness of the buffer layer on the PMOS device area is greater than the thickness of the buffer layer on the NMOS device area; when the stress layer is a compressive stress layer, the thickness of the buffer layer on the NMOS device area is greater than the thickness of the buffer layer on the PMOS device area.

[0063] See below Figure 2a to Figure 2i as well as Figure 3a to Figure 3g The method for manufacturing the semiconductor device provided in this embodiment is described in detail.

[0064] Follow step S1, refer to Figure 2a, providing a substrate 11, the substrate 11 includes an NMOS device area A1 and a PMOS device area A2, a gate structure 12 and a sidewall 13 are formed on the substrate 11 of the NMOS device area A1 and the PMOS device area A2, and the sidewall 13 is formed on the sidewall of the gate structure 12.

[0065] The gate structure 12 includes a gate oxide layer and a gate layer from bottom to top.

[0066] A trench isolation structure 113 may be formed in the substrate 11 between the NMOS device region A1 and the PMOS device region A2 to achieve mutual isolation between the NMOS device region A1 and the PMOS device region A2. The top surface of the trench isolation structure 113 is flush with the top surface of the substrate 11 or slightly higher than the top surface of the substrate 11.

[0067] A P well 111 is formed in the substrate 11 of the NMOS device region A1 , and an N well 112 is formed in the substrate 11 of the PMOS device region A2 . The bottom surfaces of the P well 111 and the N well 112 may be lower than the bottom surface of the trench isolation structure 113 .

[0068] Furthermore, in the NMOS device region A1, lightly doped source regions 114 and lightly doped drain regions 115 are formed on the top of the P well 111 on both sides of the gate structure 12; in the PMOS device region A2, lightly doped source regions 114 and lightly doped drain regions 115 are also formed on the top of the N well 112 on both sides of the gate structure 12. Furthermore, in the NMOS device region A1 and the PMOS device region A2, the lightly doped source regions 114 and the lightly doped drain regions 115 both extend to the bottom of the gate structure 12.

[0069] According to step S2, a buffer layer 14 is formed on the substrate 11 of the NMOS device area A1 and the PMOS device area A2, and the buffer layer 14 covers the gate structure 12 and the sidewall 13. The buffer layer 14 plays a role of buffering and protecting the device, and also plays a blocking role.

[0070] Preferably, the material of the buffer layer 14 includes silicon oxide. It should be noted that the material of the buffer layer 14 may also include silicon oxides such as silicon oxynitride, silicon fluoride glass, phosphosilicate glass, and borophosphosilicate glass.

[0071] According to step S3, Figure 2i and Figure 3gAs shown, a stress layer 16 is formed on the buffer layer 14. When the stress layer 16 is a tensile stress layer, the thickness of the buffer layer 14 on the PMOS device region A2 is greater than the thickness of the buffer layer 14 on the NMOS device region A1; when the stress layer 16 is a compressive stress layer, the thickness of the buffer layer 14 on the NMOS device region A1 is greater than the thickness of the buffer layer 14 on the PMOS device region A2.

[0072] When the stress layer 16 is a tensile stress layer, before forming the stress layer 16 on the buffer layer 14, the manufacturing method of the semiconductor device further includes: forming a first source region 116 and a first drain region 117 in the substrate 11 on both sides of the gate structure 12 of the NMOS device area A1, and forming the first source region 116 and the first drain region 117 and forming the buffer layer 14 using the same patterned photoresist layer as a mask; when the stress layer 16 is a compressive stress layer, before forming the stress layer 16 on the buffer layer 14, the manufacturing method of the semiconductor device further includes: forming a second source region 118 and a second drain region 119 in the substrate 11 on both sides of the gate structure 12 of the PMOS device area A2, and forming the second source region 118 and the second drain region 119 and forming the buffer layer 14 using the same patterned photoresist layer as a mask. Therefore, there is no need to add additional mask and photolithography steps, thereby reducing the cost of the stress memory process.

[0073] In one embodiment, when the stress layer 16 is a tensile stress layer, in step S2, the step of forming the buffer layer 14 on the substrate 11 of the NMOS device region A1 and the PMOS device region A2 may include: first, Figure 2b As shown, a first buffer layer 141 is formed on the substrate 11 of the NMOS device region A1 and the PMOS device region A2, and the first buffer layer 141 covers the gate structure 12 and the sidewall 13; then, as shown Figure 2d As shown, a first patterned photoresist layer 151 is formed, the first patterned photoresist layer 151 covers the first buffer layer 141 of the PMOS device region A2 and exposes the first buffer layer 141 of the NMOS device region A1, and an etching process is performed using the first patterned photoresist layer 151 as a mask to remove the first buffer layer 141 on the NMOS device region A1; then, as shown Figure 2e As shown, the first patterned photoresist layer 151 is removed; then, as shown Figure 2hAs shown, a second buffer layer 142 is formed on the substrate 11, the gate structure 12 and the sidewall 13 of the NMOS device area A1 and on the first buffer layer 141 of the PMOS device area A2. At this time, the second buffer layer 142 on the NMOS device area A1 serves as the buffer layer 14 on the NMOS device area A1, and the first buffer layer 141 and the second buffer layer 142 on the PMOS device area A2 jointly serve as the buffer layer 14 on the PMOS device area A2, so that the thickness of the buffer layer 14 on the PMOS device area A2 is greater than the thickness of the buffer layer 14 on the NMOS device area A1.

[0074] Furthermore, before removing the first buffer layer 141 on the NMOS device region A1 (eg Figure 2c As shown in or after, the method for manufacturing the semiconductor device may further include: performing an ion implantation process to form a first source region 116 and a first drain region 117 in the substrate 11 on the side of the sidewall 13 of the NMOS device region A1 away from the gate structure 12. Figure 2c and Figure 2d As shown, the same patterned photoresist layer (ie, the first patterned photoresist layer 151 ) is used as a mask to form the first source region 116 and the first drain region 117 and to remove the first buffer layer 141 on the NMOS device region A1 .

[0075] Alternatively, when the stress layer 16 is a tensile stress layer, in the step S2, the step of forming the buffer layer 14 on the substrate 11 of the NMOS device region A1 and the PMOS device region A2 may include: first, Figure 3a As shown, a buffer layer 14 is formed on the substrate 11 of the NMOS device region A1 and the PMOS device region A2, and the buffer layer 14 covers the gate structure 12 and the sidewall 13; then, as shown Figure 3c As shown, a first patterned photoresist layer 151 is formed, the first patterned photoresist layer 151 covers the buffer layer 14 of the PMOS device area A2 and exposes the buffer layer 14 of the NMOS device area A1, and an etching process is performed using the first patterned photoresist layer 151 as a mask to remove a portion of the buffer layer 14 on the NMOS device area A1, so that the thickness of the buffer layer 14 on the PMOS device area A2 is greater than the thickness of the buffer layer 14 on the NMOS device area A1; then, as shown Figure 3d As shown, the first patterned photoresist layer 151 is removed.

[0076] Furthermore, before removing a portion of the buffer layer on the NMOS device region (e.g. Figure 3bAs shown in or after, the method for manufacturing the semiconductor device further includes: performing an ion implantation process to form a first source region 116 and a first drain region 117 in the substrate 11 on the side of the sidewall 13 of the NMOS device region A1 away from the gate structure 12. Figure 3b and Figure 3c As shown, the same patterned photoresist layer (ie, the first patterned photoresist layer 151 ) is used as a mask to form the first source region 116 and the first drain region 117 and to remove a portion of the buffer layer 14 on the NMOS device region A1 .

[0077] It can be seen from the above steps that when the stress layer 16 is a tensile stress layer, since the steps of forming the first source region 116 and the first drain region 117 and removing the first buffer layer 141 on the NMOS device region A1 or removing a portion of the buffer layer 14 on the NMOS device region A1 both use the first patterned photoresist layer 151 as a mask, that is, the same mask is used, there is no need to add additional masks and photolithography steps, thereby reducing the cost of the stress memory process.

[0078] In addition, when the material of the buffer layer 14 is silicon oxide, hydrofluoric acid etching can be used to remove the first buffer layer 141 and a portion of the buffer layer 14 on the NMOS device region A1.

[0079] After removing the first buffer layer 141 on the NMOS device region A1 and before forming the second buffer layer 142, or after removing a portion of the buffer layer 14 on the NMOS device region A1, the method for manufacturing the semiconductor device may further include: first, Figure 2f and Figure 3e As shown, a second patterned photoresist layer 152 is formed, wherein the second patterned photoresist layer 152 covers the NMOS device region A1 and exposes the PMOS device region A2; then, as shown Figure 2f and Figure 3e As shown, an ion implantation process is performed using the second patterned photoresist layer 152 as a mask to form a second source region 118 and a second drain region 119 in the substrate 11 on the side of the sidewall 13 of the PMOS device region A2 away from the gate structure 12; then, as shown Figure 2g and Figure 3f As shown, the second patterned photoresist layer 152 is removed.

[0080] In another embodiment (not shown), when the stress layer 16 is a compressive stress layer, in the step S2, the step of forming the buffer layer 14 on the substrate 11 of the NMOS device area A1 and the PMOS device area A2 includes: first, forming a first buffer layer 141 on the substrate 11 of the NMOS device area A1 and the PMOS device area A2, and the first buffer layer 141 covers the gate structure 12 and the sidewall 13; then, forming a first patterned photoresist layer 151, the first patterned photoresist layer 151 covers the first buffer layer 141 of the NMOS device area A1 and exposes the first buffer layer 141 of the PMOS device area A2, and performing an etching process with the first patterned photoresist layer 151 as a mask to remove The first buffer layer 141 on the PMOS device area A2 is removed; then, the first patterned photoresist layer 151 is removed; then, a second buffer layer 142 is formed on the substrate 11, the gate structure 12 and the sidewall 13 of the PMOS device area A2 and on the first buffer layer 141 of the NMOS device area A1. At this time, the second buffer layer 142 on the PMOS device area A2 serves as the buffer layer 14 on the PMOS device area A2, and the first buffer layer 141 and the second buffer layer 142 on the NMOS device area A1 serve together as the buffer layer 14 on the NMOS device area A1, so that the thickness of the buffer layer 14 on the NMOS device area A1 is greater than the thickness of the buffer layer 14 on the PMOS device area A2.

[0081] Furthermore, before or after removing the first buffer layer 141 on the PMOS device region A2, the method for manufacturing the semiconductor device further includes: performing an ion implantation process to form a second source region 118 and a second drain region 119 in the substrate 11 on a side of the sidewall 13 of the PMOS device region A2 away from the gate structure 12. The formation of the second source region 118 and the second drain region 119 and the removal of the first buffer layer 141 on the PMOS device region A2 use the same patterned photoresist layer (i.e., the first patterned photoresist layer 151) as a mask.

[0082] Alternatively, when the stress layer 16 is a compressive stress layer, in the step S2, the step of forming the buffer layer 14 on the substrate 11 of the NMOS device area A1 and the PMOS device area A2 includes: first, forming a buffer layer 14 on the substrate 11 of the NMOS device area A1 and the PMOS device area A2, and the buffer layer 14 covers the gate structure 12 and the side wall 13; then, forming a first patterned photoresist layer 151, the first patterned photoresist layer 151 covers the buffer layer 14 of the NMOS device area A1 and exposes the buffer layer 14 of the PMOS device area A2, and performing an etching process with the first patterned photoresist layer 151 as a mask to remove a portion of the thickness of the buffer layer 14 on the PMOS device area A2, so that the thickness of the buffer layer 14 on the NMOS device area A1 is greater than the thickness of the buffer layer 14 on the PMOS device area A2; then, removing the first patterned photoresist layer 151.

[0083] Furthermore, before or after removing the partial thickness of the buffer layer 14 on the PMOS device area A2, the method for manufacturing the semiconductor device further includes: performing an ion implantation process to form a second source region 118 and a second drain region 119 in the substrate 11 on a side of the sidewall 13 of the PMOS device area A2 away from the gate structure 12. The formation of the second source region 118 and the second drain region 119 and the removal of the partial thickness of the buffer layer 14 on the PMOS device area A2 use the same patterned photoresist layer (i.e., the first patterned photoresist layer 151) as a mask.

[0084] It can be seen from the above steps that when the stress layer 16 is a compressive stress layer, since the steps of forming the second source region 118 and the second drain region 119 and removing the first buffer layer 141 on the PMOS device region A2 or removing a portion of the buffer layer 14 on the PMOS device region A2 both use the first patterned photoresist layer 151 as a mask, that is, the same mask is used, there is no need to add additional masks and photolithography steps, thereby reducing the cost of the stress memory process.

[0085] In addition, when the material of the buffer layer 14 is silicon oxide, hydrofluoric acid etching can be used to remove the first buffer layer 141 and a portion of the buffer layer 14 on the PMOS device region A2.

[0086] After removing the first buffer layer 141 on the PMOS device area A2 and before forming the second buffer layer 142, or after removing a portion of the thickness of the buffer layer 14 on the PMOS device area A2, the method for manufacturing the semiconductor device also includes: first, forming a second patterned photoresist layer 152, the second patterned photoresist layer 152 covering the PMOS device area A2 and exposing the NMOS device area A1; then, performing an ion implantation process using the second patterned photoresist layer 152 as a mask to form a first source region 116 and a first drain region 117 in the substrate 11 on the side of the sidewall 13 of the NMOS device area A1 away from the gate structure 12; then, removing the second patterned photoresist layer 152.

[0087] It should be noted that this embodiment does not illustrate the device schematic diagram corresponding to the steps S2 to S3 when the stress layer 16 is a compressive stress layer, and the device schematic diagram corresponding to the steps S2 to S3 when the stress layer 16 is a tensile stress layer (i.e. Figure 2b to Figure 2i as well as Figure 3a to Figure 3g ), the main difference between the device schematic diagram corresponding to the stress layer 16 when it is a compressive stress layer and the first patterned photoresist layer 151 and the second patterned photoresist layer 152 is that the exposed areas are different, so that the buffer layer 14 on the NMOS device area A1 and the PMOS device area A2 can meet different requirements under different tensile stress or compressive stress.

[0088] The first source region 116 and the first drain region 117 may extend to below the sidewall 13 , the first source region 116 and the first drain region 117 are formed at the top of the P-well 111 , and the bottom surfaces of the first source region 116 and the first drain region 117 are lower than the bottom surfaces of the lightly doped source region 114 and the lightly doped drain region 115 .

[0089] The second source region 118 and the second drain region 119 are formed at the top of the N-well 112 , and the second source region 118 and the second drain region 119 can extend to below the sidewall 13 , and the bottom surfaces of the second source region 118 and the second drain region 119 are lower than the bottom surfaces of the lightly doped source region 114 and the lightly doped drain region 115 .

[0090] In the NMOS device area A1, the ion doping types of the lightly doped source region 114, the lightly doped drain region 115, the first source region 116 and the first drain region 117 are all N-type; in the PMOS device area A2, the ion doping types of the lightly doped source region 114, the lightly doped drain region 115, the second source region 118 and the second drain region 119 are all P-type.

[0091] Preferably, the thickness of the first buffer layer 141 is

[0092] Preferably, the thickness of the second buffer layer 142 is

[0093] Preferably, the material of the stress layer 16 includes silicon nitride, and the stress layer 16 can have high tensile stress or high compressive stress by adjusting parameters when forming the stress layer 16 .

[0094] The manufacturing method of the semiconductor device may also include: first, performing an annealing process to introduce the tensile stress in the stress layer 16 into the gate structure 12 of the NMOS device area A1, the first source region 116, the first drain region 117 and the substrate 11, or introducing the compressive stress in the stress layer 16 into the gate structure 12 of the PMOS device area A2, the second source region 118, the second drain region 119 and the substrate 11; then, removing the stress layer 16.

[0095] In the method for manufacturing a semiconductor device of the present invention, when the stress layer 16 is a tensile stress layer, since a buffer layer 14 is formed between the NMOS device region A1 and the PMOS device region A2 and the stress layer 16, and the thickness of the buffer layer 14 on the PMOS device region A2 is greater than the thickness of the buffer layer 14 on the NMOS device region A1, after performing a high-temperature annealing process, more tensile stress in the stress layer 16 on the NMOS device region A1 can pass through the thinner buffer layer 14 and be smoothly transferred to the gate structure 12, the first source region 116, the first drain region 117 and the substrate 11 of the NMOS device region A1, and the PMOS device region A2 is formed between the NMOS device region A1 and the PMOS device region A2. The tensile stress in the stress layer 16 on the device area A2 is difficult to pass through the thicker buffer layer 14 and be transferred to the gate structure 12, the second source region 118, the second drain region 119 and the substrate 11 of the PMOS device area A2, so that more tensile stress can be transferred to the NMOS device area A1 without increasing the thickness of the stress layer 16, and the thickness of the stress layer 16 is not increased, which also makes the buffer layer 14 on the PMOS device area A2 have a sufficient blocking effect on tensile stress, thereby avoiding the influence of the tensile stress in the stress layer 16 on the PMOS device area A2, and the buffer layer 14 on the NMOS device area A1 can also play a role in protecting the device. Therefore, while further improving the electron mobility of the NMOS device, it can also avoid reducing the hole mobility of the PMOS device, so that while improving the performance of the NMOS device, it can also avoid reducing the performance of the PMOS device.

[0096] When the stress layer 16 is a compressive stress layer, since the thickness of the buffer layer 14 on the NMOS device region A1 is greater than the thickness of the buffer layer 14 on the PMOS device region A2, after the high temperature annealing process is performed, more compressive stress in the stress layer 16 on the PMOS device region A2 can pass through the thinner buffer layer 14 and be smoothly transferred to the gate structure 12, the second source region 118, the second drain region 119 and the substrate 11 of the PMOS device region A2, and the compressive stress in the stress layer 16 on the NMOS device region A1 is difficult to pass through the thicker buffer layer 14. The buffer layer 14 is transferred to the gate structure 12, the first source region 116, the first drain region 117 and the substrate 11 of the NMOS device region A1, so that more compressive stress can be transferred to the PMOS device region A2 without increasing the thickness of the stress layer 16, and the thickness of the stress layer 16 is not increased, so that the buffer layer 14 on the NMOS device region A1 has a sufficient blocking effect on the compressive stress, thereby avoiding the influence of the compressive stress in the stress layer 16 on the NMOS device region A1, and the buffer layer 14 on the PMOS device region A2 can also play a role in protecting the device. Therefore, while further improving the hole mobility of the PMOS device, it can also avoid reducing the electron mobility of the NMOS device, so that while improving the performance of the PMOS device, it can also avoid reducing the performance of the NMOS device.

[0097] Furthermore, when the stress layer 16 is a tensile stress layer, since the buffer layer 14 on the PMOS device area A2 has a sufficient blocking effect on the tensile stress, after the stress layer 16 is formed and before the annealing process is performed, there is no need to introduce additional photolithography and etching steps to remove the stress layer 16 on the PMOS device area A2, thereby avoiding an increase in chip manufacturing costs; when the stress layer 16 is a compressive stress layer, since the buffer layer 14 on the NMOS device area A1 has a sufficient blocking effect on the compressive stress, after the stress layer 16 is formed and before the annealing process is performed, there is no need to introduce additional photolithography and etching steps to remove the stress layer 16 on the NMOS device area A1, thereby avoiding an increase in chip manufacturing costs.

[0098] Furthermore, since the lattice constants of the materials of the stress layer 16 (e.g., silicon nitride), the buffer layer 14 (e.g., silicon oxide), the gate structure 12 and the substrate 11 (e.g., polysilicon and monocrystalline silicon, respectively) do not match each other, and the lattice spacing is greatly different, if the thickness of the stress layer 16 is increased so that more tensile stress is transferred to the NMOS device region A1 or more compressive stress is transferred to the PMOS device region A2, it is more likely to cause damage to the gate structure 12 and the substrate 11, and it is more likely to cause excessive leakage current of the device, or even the device cannot work. Therefore, the present invention does not increase the thickness of the stress layer 16 so that more tensile stress is transferred to the NMOS device region A1 or more compressive stress is transferred to the PMOS device region A2, so as to avoid causing excessive leakage current of the device.

[0099] In summary, the present invention provides a method for manufacturing a semiconductor device, comprising: providing a substrate, the substrate comprising an NMOS device region and a PMOS device region, and gate structures are formed on the substrates of the NMOS device region and the PMOS device region; forming a buffer layer on the substrates of the NMOS device region and the PMOS device region, and the buffer layer covers the gate structure; forming a stress layer on the buffer layer; when the stress layer is a tensile stress layer, the thickness of the buffer layer on the PMOS device region is greater than the thickness of the buffer layer on the NMOS device region; when the stress layer is a compressive stress layer, the thickness of the buffer layer on the NMOS device region is greater than the thickness of the buffer layer on the PMOS device region. The method for manufacturing a semiconductor device provided by the present invention can improve the performance of one of the NMOS device and the PMOS device and avoid reducing the performance of the other device, while also avoiding increasing chip manufacturing costs.

[0100] An embodiment of the present invention provides a semiconductor device, comprising: a substrate, the substrate comprising an NMOS device region and a PMOS device region, and gate structures are formed on the substrates of the NMOS device region and the PMOS device region; a buffer layer, formed on the substrates of the NMOS device region and the PMOS device region, and the buffer layer covers the gate structure; a stress layer, formed on the buffer layer; when the stress layer is a tensile stress layer, the thickness of the buffer layer on the PMOS device region is greater than the thickness of the buffer layer on the NMOS device region; when the stress layer is a compressive stress layer, the thickness of the buffer layer on the NMOS device region is greater than the thickness of the buffer layer on the PMOS device region.

[0101] See below Figure 2i and Figure 3g The semiconductor device provided by this embodiment is described in detail.

[0102] The substrate 11 includes an NMOS device region A1 and a PMOS device region A2 . A gate structure 12 and a sidewall spacer 13 are formed on the substrate 11 of the NMOS device region A1 and the PMOS device region A2 . The sidewall spacer 13 is formed on the sidewall of the gate structure 12 .

[0103] The gate structure 12 includes a gate oxide layer and a gate layer from bottom to top.

[0104] A trench isolation structure 113 may be formed in the substrate 11 between the NMOS device region A1 and the PMOS device region A2 to achieve mutual isolation between the NMOS device region A1 and the PMOS device region A2. The top surface of the trench isolation structure 113 is flush with the top surface of the substrate 11 or slightly higher than the top surface of the substrate 11.

[0105] A P well 111 is formed in the substrate 11 of the NMOS device region A1 , and an N well 112 is formed in the substrate 11 of the PMOS device region A2 . The bottom surfaces of the P well 111 and the N well 112 may be lower than the bottom surface of the trench isolation structure 113 .

[0106] Furthermore, in the NMOS device region A1, lightly doped source regions 114 and lightly doped drain regions 115 are formed on the top of the P well 111 on both sides of the gate structure 12; in the PMOS device region A2, lightly doped source regions 114 and lightly doped drain regions 115 are also formed on the top of the N well 112 on both sides of the gate structure 12. Furthermore, in the NMOS device region A1 and the PMOS device region A2, the lightly doped source regions 114 and the lightly doped drain regions 115 both extend to the bottom of the gate structure 12.

[0107] The semiconductor device further comprises:

[0108] A first source region 116 and a first drain region 117 are formed in the substrate 11 on a side of the sidewall 13 of the NMOS device region A1 away from the gate structure 12, and the first source region 116 and the first drain region 117 may extend to below the sidewall 13;

[0109] The second source region 118 and the second drain region 119 are formed in the substrate 11 on a side of the sidewall 13 of the PMOS device region A2 away from the gate structure 12 . The second source region 118 and the second drain region 119 may extend to below the sidewall 13 .

[0110] Among them, the first source region 116 and the first drain region 117 are formed at the top of the P-well 111, and the bottom surfaces of the first source region 116 and the first drain region 117 are lower than the bottom surfaces of the lightly doped source region 114 and the lightly doped drain region 115; the second source region 118 and the second drain region 119 are formed at the top of the N-well 112, and the bottom surfaces of the second source region 118 and the second drain region 119 are lower than the bottom surfaces of the lightly doped source region 114 and the lightly doped drain region 115.

[0111] In the NMOS device area A1, the ion doping types of the lightly doped source region 114, the lightly doped drain region 115, the first source region 116 and the first drain region 117 are all N-type; in the PMOS device area A2, the ion doping types of the lightly doped source region 114, the lightly doped drain region 115, the second source region 118 and the second drain region 119 are all P-type.

[0112] The buffer layer 14 is formed on the substrate 11 of the NMOS device region A1 and the PMOS device region A2, and the buffer layer 14 covers the gate structure 12 and the sidewall 13. The buffer layer 14 plays a role of buffering and protecting the device, and also plays a blocking role.

[0113] Preferably, the material of the buffer layer 14 includes silicon oxide. It should be noted that the material of the buffer layer 14 may also include silicon oxides such as silicon oxynitride, silicon fluoride glass, phosphosilicate glass, and borophosphosilicate glass.

[0114] The stress layer 16 is formed on the buffer layer 14 .

[0115] When the stress layer 16 is a tensile stress layer, the thickness of the buffer layer 14 on the PMOS device area A2 is greater than the thickness of the buffer layer 14 on the NMOS device area A1; when the stress layer 16 is a compressive stress layer, the thickness of the buffer layer 14 on the NMOS device area A1 is greater than the thickness of the buffer layer 14 on the PMOS device area A2.

[0116] When the stress layer 16 is a tensile stress layer, Figure 2i In the embodiment shown, the buffer layer 14 on the PMOS device region A2 includes a first buffer layer 141 and a second buffer layer 142, and the buffer layer 14 on the NMOS device region A1 includes only the second buffer layer 142, so that the thickness of the buffer layer 14 on the PMOS device region A2 is greater than the thickness of the buffer layer 14 on the NMOS device region A1; Figure 3gIn the illustrated embodiment, a portion of the buffer layer 14 on the NMOS device region A1 is removed, so that the thickness of the buffer layer 14 on the PMOS device region A2 is greater than the thickness of the buffer layer 14 on the NMOS device region A1.

[0117] When the stress layer 16 is a compressive stress layer, the buffer layer 14 on the NMOS device area A1 includes a first buffer layer 141 and a second buffer layer 142, and the buffer layer 14 on the PMOS device area A2 only includes the second buffer layer 142, so that the thickness of the buffer layer 14 on the NMOS device area A1 is greater than the thickness of the buffer layer 14 on the PMOS device area A2; or, a portion of the thickness of the buffer layer 14 on the PMOS device area A2 is removed, so that the thickness of the buffer layer 14 on the NMOS device area A1 is greater than the thickness of the buffer layer 14 on the PMOS device area A2.

[0118] Preferably, the thickness of the first buffer layer 141 is

[0119] Preferably, the thickness of the second buffer layer 142 is

[0120] Preferably, the material of the stress layer 16 includes silicon nitride, and the stress layer 16 can have high tensile stress or high compressive stress by adjusting parameters when forming the stress layer 16 .

[0121] It should be noted that the stress layer 16 is a stress layer after an annealing process is performed, so that the tensile stress in the stress layer 16 can be introduced into the gate structure 12 of the NMOS device area A1, the first source region 116, the first drain region 117 and the substrate 11, or the compressive stress in the stress layer 16 can be introduced into the gate structure 12 of the PMOS device area A2, the second source region 118, the second drain region 119 and the substrate 11; and, after the annealing process is performed, the stress layer 16 can be removed. In the semiconductor device of the present invention, when the stress layer 16 is a tensile stress layer, since a buffer layer 14 is formed between the NMOS device region A1 and the PMOS device region A2 and the stress layer 16, and the thickness of the buffer layer 14 on the PMOS device region A2 is greater than the thickness of the buffer layer 14 on the NMOS device region A1, after performing a high temperature annealing process, more tensile stress in the stress layer 16 on the NMOS device region A1 can pass through the thinner buffer layer 14 and be smoothly transferred to the gate structure 12, the first source region 116, the first drain region 117 and the substrate 11 of the NMOS device region A1, and the PMOS device region A2 can be further reduced in tensile stress. The tensile stress in the stress layer 16 on A2 is difficult to pass through the thicker buffer layer 14 and be transferred to the gate structure 12, the second source region 118, the second drain region 119 and the substrate 11 of the PMOS device region A2, so that more tensile stress can be transferred to the NMOS device region A1 without increasing the thickness of the stress layer 16, and the thickness of the stress layer 16 is not increased, which also makes the buffer layer 14 on the PMOS device region A2 have a sufficient blocking effect on tensile stress, thereby avoiding the influence of the tensile stress in the stress layer 16 on the PMOS device region A2, and the buffer layer 14 on the NMOS device region A1 can also play a role in protecting the device. Therefore, while further improving the electron mobility of the NMOS device, it can also avoid reducing the hole mobility of the PMOS device, so as to improve the performance of the NMOS device while avoiding reducing the performance of the PMOS device.

[0122] When the stress layer 16 is a compressive stress layer, since the thickness of the buffer layer 14 on the NMOS device region A1 is greater than the thickness of the buffer layer 14 on the PMOS device region A2, after the high temperature annealing process is performed, more compressive stress in the stress layer 16 on the PMOS device region A2 can pass through the thinner buffer layer 14 and be smoothly transferred to the gate structure 12, the second source region 118, the second drain region 119 and the substrate 11 of the PMOS device region A2, and the compressive stress in the stress layer 16 on the NMOS device region A1 is difficult to pass through the thicker buffer layer 14. The buffer layer 14 is transferred to the gate structure 12, the first source region 116, the first drain region 117 and the substrate 11 of the NMOS device region A1, so that more compressive stress can be transferred to the PMOS device region A2 without increasing the thickness of the stress layer 16, and the thickness of the stress layer 16 is not increased, so that the buffer layer 14 on the NMOS device region A1 has a sufficient blocking effect on the compressive stress, thereby avoiding the influence of the compressive stress in the stress layer 16 on the NMOS device region A1, and the buffer layer 14 on the PMOS device region A2 can also play a role in protecting the device. Therefore, while further improving the hole mobility of the PMOS device, it can also avoid reducing the electron mobility of the NMOS device, so that while improving the performance of the PMOS device, it can also avoid reducing the performance of the NMOS device.

[0123] Furthermore, when the stress layer 16 is a tensile stress layer, since the buffer layer 14 on the PMOS device area A2 has a sufficient blocking effect on the tensile stress, the stress layer 16 on the NMOS device area A1 and the PMOS device area A2 are both retained, indicating that before performing the annealing process, there is no need to introduce additional photolithography and etching steps to remove the stress layer 16 on the PMOS device area A2, thereby avoiding increasing the chip manufacturing cost; when the stress layer 16 is a compressive stress layer, since the buffer layer 14 on the NMOS device area A1 has a sufficient blocking effect on the compressive stress, the stress layer 16 on the NMOS device area A1 and the PMOS device area A2 are both retained, indicating that before performing the annealing process, there is no need to introduce additional photolithography and etching steps to remove the stress layer 16 on the NMOS device area A1, thereby avoiding increasing the chip manufacturing cost.

[0124] Furthermore, since the lattice constants of the materials of the stress layer 16 (e.g., silicon nitride), the buffer layer 14 (e.g., silicon oxide), the gate structure 12 and the substrate 11 (e.g., polysilicon and monocrystalline silicon, respectively) do not match each other, and the lattice spacing is greatly different, if the thickness of the stress layer 16 is increased so that more tensile stress is transferred to the NMOS device region A1 or more compressive stress is transferred to the PMOS device region A2, it is more likely to cause damage to the gate structure 12 and the substrate 11, and it is more likely to cause excessive leakage current of the device, or even the device cannot work. Therefore, the present invention does not increase the thickness of the stress layer 16 so that more tensile stress is transferred to the NMOS device region A1 or more compressive stress is transferred to the PMOS device region A2, so as to avoid causing excessive leakage current of the device.

[0125] In summary, the present invention provides a semiconductor device, comprising: a substrate, the substrate comprising an NMOS device region and a PMOS device region, and gate structures are formed on the substrates of the NMOS device region and the PMOS device region; a buffer layer formed on the substrates of the NMOS device region and the PMOS device region, and the buffer layer covers the gate structure; a stress layer formed on the buffer layer; when the stress layer is a tensile stress layer, the thickness of the buffer layer on the PMOS device region is greater than the thickness of the buffer layer on the NMOS device region; when the stress layer is a compressive stress layer, the thickness of the buffer layer on the NMOS device region is greater than the thickness of the buffer layer on the PMOS device region. The semiconductor device provided by the present invention can improve the performance of one of the NMOS device and the PMOS device and avoid reducing the performance of the other device, while also avoiding increasing chip manufacturing costs.

[0126] The above description is only a description of the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention. Any changes or modifications made by a person skilled in the art in the field of the present invention based on the above disclosure shall fall within the scope of protection of the claims.

Claims

1. A method for manufacturing a semiconductor device, characterized in that: include: Providing a substrate, the substrate comprising an NMOS device region and a PMOS device region, wherein gate structures are formed on the substrates of the NMOS device region and the PMOS device region; Forming a buffer layer on the substrate of the NMOS device region and the PMOS device region, wherein the buffer layer covers the gate structure; A stress layer is formed on the buffer layer in the NMOS device region and the PMOS device region; when the stress layer is a tensile stress layer, the thickness of the buffer layer in the PMOS device region is greater than the thickness of the buffer layer in the NMOS device region; when the stress layer is a compressive stress layer, the thickness of the buffer layer in the NMOS device region is greater than the thickness of the buffer layer in the PMOS device region.

2. The method for manufacturing a semiconductor device according to claim 1, wherein: When the stress layer is a tensile stress layer, before forming the stress layer on the buffer layer, the method for manufacturing the semiconductor device further includes: Forming a first source region and a first drain region in the substrate on both sides of the gate structure of the NMOS device region, wherein the first source region and the first drain region are formed using the same patterned photoresist layer as a mask as the buffer layer; When the stress layer is a compressive stress layer, before forming the stress layer on the buffer layer, the method for manufacturing the semiconductor device further includes: A second source region and a second drain region are formed in the substrate at both sides of the gate structure of the PMOS device region, and the second source region and the second drain region are formed using the same patterned photoresist layer as a mask as the buffer layer.

3. The method for manufacturing a semiconductor device according to claim 1, wherein: When the stress layer is a tensile stress layer; The step of forming the buffer layer on the substrate of the NMOS device region and the PMOS device region comprises: Forming a first buffer layer on the substrate of the NMOS device region and the PMOS device region, wherein the first buffer layer covers the gate structure; removing the first buffer layer on the NMOS device region; forming a second buffer layer on the substrate and the gate structure in the NMOS device region and on the first buffer layer in the PMOS device region; Alternatively, the step of forming the buffer layer on the substrate of the NMOS device region and the PMOS device region includes: Forming a buffer layer on the substrate of the NMOS device region and the PMOS device region, wherein the buffer layer covers the gate structure; A portion of the buffer layer on the NMOS device region is removed.

4. The method for manufacturing a semiconductor device according to claim 3, wherein: Before or after removing the first buffer layer on the NMOS device region, or before or after removing a portion of the buffer layer on the NMOS device region, the method for manufacturing the semiconductor device further includes: A first source region and a first drain region are formed in the substrate on both sides of the gate structure of the NMOS device region, wherein the formation of the first source region and the first drain region and the removal of the first buffer layer on the NMOS device region or the removal of a portion of the thickness of the buffer layer on the NMOS device region use the same patterned photoresist layer as a mask.

5. The method for manufacturing a semiconductor device according to claim 3, wherein: After removing the first buffer layer on the NMOS device region or after removing a portion of the buffer layer on the NMOS device region, the method for manufacturing the semiconductor device further includes: A second source region and a second drain region are formed in the substrate at both sides of the gate structure of the PMOS device region.

6. The method for manufacturing a semiconductor device according to claim 1, wherein: When the stress layer is a compressive stress layer; The step of forming the buffer layer on the substrate of the NMOS device region and the PMOS device region comprises: Forming a first buffer layer on the substrate of the NMOS device region and the PMOS device region, wherein the first buffer layer covers the gate structure; removing the first buffer layer on the PMOS device region; forming a second buffer layer on the substrate and the gate structure in the PMOS device region and on the first buffer layer in the NMOS device region; Alternatively, the step of forming the buffer layer on the substrate of the NMOS device region and the PMOS device region includes: Forming a buffer layer on the substrate of the NMOS device region and the PMOS device region, wherein the buffer layer covers the gate structure; A portion of the buffer layer on the PMOS device region is removed.

7. The method for manufacturing a semiconductor device according to claim 6, wherein: Before or after removing the first buffer layer on the PMOS device region, or before or after removing a portion of the buffer layer on the PMOS device region, the method for manufacturing the semiconductor device further includes: A second source region and a second drain region are formed in the substrate on both sides of the gate structure of the PMOS device region, wherein the second source region and the second drain region are formed and the first buffer layer on the PMOS device region or a portion of the buffer layer on the PMOS device region is removed using the same patterned photoresist layer as a mask.

8. The method for manufacturing a semiconductor device according to claim 6, wherein: After removing the first buffer layer on the PMOS device region or after removing a portion of the buffer layer on the PMOS device region, the method for manufacturing the semiconductor device further includes: A first source region and a first drain region are formed in the substrate on both sides of the gate structure of the NMOS device region.

9. The method for manufacturing a semiconductor device according to claim 1, wherein: The method for manufacturing the semiconductor device further includes: performing an annealing process; The stress layer is removed.

10. A semiconductor device, characterized in that: include: A substrate, the substrate comprising an NMOS device region and a PMOS device region, and gate structures are formed on the substrates of the NMOS device region and the PMOS device region; A buffer layer is formed on the substrate of the NMOS device region and the PMOS device region, and the buffer layer covers the gate structure; A stress layer is formed on the buffer layer in the NMOS device region and the PMOS device region; when the stress layer is a tensile stress layer, the thickness of the buffer layer in the PMOS device region is greater than the thickness of the buffer layer in the NMOS device region; when the stress layer is a compressive stress layer, the thickness of the buffer layer in the NMOS device region is greater than the thickness of the buffer layer in the PMOS device region.

11. The semiconductor device according to claim 10, wherein: The material of the stress layer includes silicon nitride, and the material of the buffer layer includes silicon oxide.

12. The semiconductor device according to claim 10, wherein: The semiconductor device further comprises: A first source region and a first drain region are formed in the substrate on both sides of the gate structure of the NMOS device region; A second source region and a second drain region are formed in the substrate at both sides of the gate structure of the PMOS device region.

13. The semiconductor device according to claim 12, wherein: A P well is formed in the substrate of the NMOS device region, and the first source region and the first drain region are formed on the top of the P well; an N well is formed in the substrate of the PMOS device region, and the second source region and the second drain region are formed on the top of the N well.

Images