Semiconductor structure and method for forming the same

Abstract

The present application provides a semiconductor structure and a method for forming the same. The semiconductor structure comprises: an SOI substrate comprising a bottom silicon layer, an insulating layer, and a top silicon layer; the SOI substrate comprising a grating region, a first waveguide region, a second waveguide region, and a third waveguide region; a first ridge waveguide located in the top silicon layer of the first waveguide region; and a grating structure comprising a first portion located in the top silicon layer of the grating region and a second portion located above the first portion, the second portion and the first portion being formed by simultaneous etching. The present application provides a semiconductor structure and a method for forming the same, which can reduce the processing difficulty of silicon-based optoelectronic passive devices.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a semiconductor structure and a method for forming the same. Background Art

[0002] The silicon-based optoelectronic passive device integration process can realize the preparation of silicon photonic passive devices including strip waveguides, ridge waveguides, edge couplers, vertically coupled gratings, directional couplers, microring resonators, star couplers, arrayed waveguide gratings, polarization beam splitters, etc.

[0003] However, the current silicon-based optoelectronic passive device formation process still has defects, so it is necessary to provide a more effective and reliable technical solution. Summary of the Invention

[0004] The present application provides a semiconductor structure and a method for forming the same, which can reduce the process difficulty of silicon-based optoelectronic passive devices and improve device reliability.

[0005] One aspect of the present application provides a method for forming a semiconductor structure, comprising: providing an SOI substrate, the SOI substrate comprising a bottom silicon layer, an insulating layer, and a top silicon layer, the SOI substrate comprising a grating region, a first waveguide region, a second waveguide region, and a third waveguide region; sequentially forming an oxide layer, a polysilicon layer, and a hard mask layer on a surface of the SOI substrate; performing a first etching process to etch the hard mask layer, the polysilicon layer, the oxide layer, and the top silicon layer in the first and second waveguide regions, thereby forming a preliminary first ridge waveguide in the top silicon layer of the first and second waveguide regions; performing a second etching process to etch the hard mask layer, the polysilicon layer, the oxide layer, and the top silicon layer in the grating region, thereby forming a grating structure, and converting the preliminary first ridge waveguide into a first ridge waveguide, wherein the grating structure comprises a first portion located in the top silicon layer and a second portion located in the polysilicon layer.

[0006] In some embodiments of the present application, the first etching process includes: forming a patterned first photoresist layer on the surface of the hard mask layer, the patterned first photoresist layer defining the position of the first ridge waveguide; etching the hard mask layer, the polysilicon layer, the oxide layer and the top silicon layer using the patterned first photoresist layer as a mask to form the preliminary first ridge waveguide; and removing the patterned first photoresist layer.

[0007] In some embodiments of the present application, in the second etching process, the prepared first ridge waveguide in the second waveguide region is also etched to convert the prepared first ridge waveguide into a strip waveguide, and the hard mask layer, polysilicon layer, oxide layer and top silicon layer in the third waveguide region are etched to form a second ridge waveguide in the top silicon layer of the third waveguide region.

[0008] In some embodiments of the present application, the second etching process includes: forming an anti-reflection layer covering the SOI substrate on the SOI substrate and forming a patterned second photoresist layer on the surface of the anti-reflection layer, the patterned second photoresist layer defining the positions of the grating structure, the second ridge waveguide and the strip waveguide; etching the anti-reflection layer, the hard mask layer, the polysilicon layer, the oxide layer and the top silicon layer using the patterned second photoresist layer as a mask to form the grating structure, the second ridge waveguide and the strip waveguide; and removing the patterned second photoresist layer and the anti-reflection layer.

[0009] In some embodiments of the present application, the prepared first ridge waveguide includes a main body portion and an extension portion extending from the bottom end of the main body portion to both sides. The second etching process etches away the extension portion of the prepared first ridge waveguide in the second waveguide area to convert the prepared first ridge waveguide into a strip waveguide.

[0010] In some embodiments of the present application, the second ridge waveguide includes a main body and an extension portion extending from a bottom end of the main body to both sides, and a thickness of the extension portion of the second ridge waveguide is greater than a thickness of the extension portion of the first ridge waveguide.

[0011] In some embodiments of the present application, the method for forming the semiconductor structure further includes: forming a first dielectric layer covering the SOI substrate on the SOI substrate, the top surface of the first dielectric layer being coplanar with the top surface of the hard mask layer; removing the hard mask layer and the first dielectric layer above the top surface of the polysilicon layer; performing a third etching process to remove the polysilicon layer and the first dielectric layer above the top surface of the oxide layer in the first waveguide region, the second waveguide region, and the third waveguide region; and forming a second dielectric layer covering the SOI substrate on the SOI substrate.

[0012] In some embodiments of the present application, the third etching process includes: forming a patterned third photoresist layer on the surface of the polysilicon layer and the first dielectric layer, the patterned third photoresist layer exposing the polysilicon layer and the first dielectric layer in the first waveguide region, the second waveguide region, and the third waveguide region; etching the polysilicon layer and the first dielectric layer to the surface of the oxide layer using the patterned third photoresist layer as a mask to remove the polysilicon layer and the first dielectric layer in the first waveguide region, the second waveguide region, and the third waveguide region that are higher than the top surface of the oxide layer; and removing the patterned third photoresist layer.

[0013] Another aspect of the present application provides a semiconductor structure, comprising: an SOI substrate, the SOI substrate comprising a bottom silicon layer, an insulating layer, and a top silicon layer, the SOI substrate comprising a grating region, a first waveguide region, a second waveguide region, and a third waveguide region; a first ridge waveguide located in the top silicon layer of the first waveguide region; and a grating structure, the grating structure comprising a first portion located in the top silicon layer of the grating region and a second portion located above the first portion, the second portion and the first portion being formed by synchronous etching.

[0014] In some embodiments of the present application, the semiconductor structure further includes: a strip waveguide and a second ridge waveguide, the strip waveguide being located in the top silicon layer of the second waveguide region, the second ridge waveguide being located in the top silicon layer of the third waveguide region, and the strip waveguide and the second ridge waveguide being formed by synchronous etching.

[0015] In some embodiments of the present application, the first ridge waveguide includes a main body and an extension portion extending from the bottom end of the main body to both sides, the second ridge waveguide includes a main body and an extension portion extending from the bottom end of the main body to both sides, and the thickness of the extension portion of the second ridge waveguide is greater than the thickness of the extension portion of the first ridge waveguide.

[0016] In some embodiments of the present application, the semiconductor structure further includes: an oxide layer, located on the top surface of the first portion of the grating structure, the top surface of the first ridge waveguide, the top surface of the strip waveguide, and the top surface of the second ridge waveguide; a first dielectric layer, covering the SOI substrate, the top surface of the first dielectric layer being coplanar with the top surface of the oxide layer; and a second dielectric layer, covering the SOI substrate.

[0017] The present application provides a semiconductor structure and a method for forming the same. The first and second parts of the grating structure are formed by synchronous etching, so the alignment accuracy of the first and second parts of the grating structure is high, which can improve the grating coupling efficiency and thus improve the device performance; the second ridge waveguide and the strip waveguide are formed by synchronous etching, which reduces the use of a high-precision mask and can reduce the process difficulty of silicon-based optoelectronic passive devices. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] The following figures describe in detail exemplary embodiments disclosed in this application. Like reference numerals denote similar structures throughout the several views of the drawings. Those skilled in the art will appreciate that these embodiments are non-limiting, exemplary embodiments, and that the drawings are provided for illustration and description purposes only and are not intended to limit the scope of this application. Other embodiments may also achieve the inventive intent of this application. It should be understood that the drawings are not drawn to scale.

[0019] in:

[0020] Figures 1 to 14 Schematic diagram of each step in the method for forming a semiconductor structure described in an embodiment of the present application. DETAILED DESCRIPTION

[0021] The following description provides specific application scenarios and requirements of the present application, with the purpose of enabling those skilled in the art to make and use the content of this application. Various local modifications to the disclosed embodiments will be apparent to those skilled in the art, and the general principles defined herein may be applied to other embodiments and applications without departing from the spirit and scope of this application. Therefore, this application is not limited to the embodiments shown, but is intended to be of the widest scope consistent with the claims.

[0022] The technical solution of the present invention is described in detail below with reference to the embodiments and drawings.

[0023] Based on the Silicon On Insulator (SOI) substrate, the preparation of silicon-based optoelectronic passive devices is mainly achieved by three depth waveguide forming processes and a polysilicon grating forming process, including: 1) strip waveguide process, with an etching depth of generally 150 nanometers to 220 nanometers, and the top silicon layer of the SOI is fully etched; 2) deep ridge waveguide process, with an etching depth of generally 70 nanometers to 150 nanometers, partially etching the top silicon, which can also be used for modulator preparation; 3) shallow ridge waveguide process, with an etching depth of generally 0 to 70 nanometers, and silicon grating etching is generally performed simultaneously for vertical coupling testing; 4) polysilicon grating process, which has the effect of improving the silicon grating coupling efficiency.

[0024] However, the above preparation process still has the following defects: 1) Silicon gratings and polysilicon gratings are formed in two steps, and silicon gratings and polysilicon gratings are prone to size mismatch or insufficient overlay accuracy in the vertical direction, affecting the grating coupling efficiency; 2) Considering the accuracy problem, the above four-step process requires four layers of high-precision masks to implement, which increases the difficulty of the process.

[0025] In response to the above problems, the present application provides a semiconductor structure and a method for forming the same. The first part and the second part of the grating structure are formed by synchronous etching, so the alignment accuracy of the first part and the second part of the grating structure is high, which can improve the grating coupling efficiency, thereby improving the device performance and reliability; the second ridge waveguide and the strip waveguide are formed by synchronous etching, which reduces the use of a high-precision mask and can reduce the process difficulty of silicon-based optoelectronic passive devices.

[0026] Figures 1 to 14 The following is a structural diagram of each step in the method for forming a semiconductor structure according to an embodiment of the present application. The method for forming a semiconductor structure according to an embodiment of the present application is described in detail with reference to the accompanying drawings.

[0027] refer to Figure 1 As shown, an SOI substrate 100 is provided, comprising a bottom silicon layer 101, an insulating layer 102, and a top silicon layer 103. The SOI substrate 100 includes a grating region 111, a first waveguide region 112, a second waveguide region 113, and a third waveguide region 114. Specifically, the SOI (silicon on insulator) substrate 100 comprises a bottom silicon layer 101, an insulating layer 102 located on a surface of the bottom silicon layer 101, and a top silicon layer 103 located on a surface of the insulating layer 102.

[0028] In some embodiments of the present application, the semiconductor structure of the present application is, for example, a silicon-based optoelectronic passive device based on an SOI substrate.

[0029] In some embodiments of the present application, the material of the bottom silicon layer 101 is silicon, the material of the insulating layer 102 is silicon dioxide, and the material of the top silicon layer 103 is silicon. A silicon-on-insulator substrate (SOI substrate) is a common substrate structure in semiconductor structures, so the formation process and detailed structure of the silicon-on-insulator substrate 100 are not described here.

[0030] In some embodiments of the present application, the grating region 111 is used to form a grating structure, the first waveguide region 112 is used to form a first ridge waveguide (deep ridge waveguide), the second waveguide region 113 is used to form a stripe waveguide, and the third waveguide region 114 is used to form a second ridge waveguide (shallow ridge waveguide). The grating region 111, the first waveguide region 112, the second waveguide region 113, and the third waveguide region 114 may be adjacent or non-adjacent.

[0031] refer to Figure 2 As shown, an oxide layer 120 , a polysilicon layer 130 and a hard mask layer 140 are sequentially formed on the surface of the SOI substrate 100 .

[0032] In some embodiments of the present application, the material of the oxide layer 120 is, for example, silicon. Methods for forming the oxide layer 120 include thermal oxidation process or chemical vapor deposition process.

[0033] In some embodiments of the present application, the polysilicon layer 130 is made of polycrystalline silicon. The polysilicon layer 130 is used to form a grating structure, and thus the polysilicon layer 130 may also be made of other materials suitable for forming a grating structure. The polysilicon layer 130 may be formed by a chemical vapor deposition process or a physical vapor deposition process.

[0034] In some embodiments of the present application, the material of the hard mask layer 140 is, for example, silicon nitride, silicon oxide, silicon oxynitride, silicon carbon nitride, titanium nitride, etc. The hard mask layer 140 is formed by a chemical vapor deposition process or a physical vapor deposition process.

[0035] refer to Figures 3 to 5 As shown, a first etching process is performed to etch the hard mask layer 140, the polysilicon layer 130, the oxide layer 120 and the top silicon layer 103 in the first waveguide region 112 and the second waveguide region 113, and form a preliminary first ridge waveguide 150a in the top silicon layer 103 of the first waveguide region 112 and the second waveguide region 113.

[0036] In some embodiments of the present application, the first etching process includes: Figure 3 As shown, a patterned first photoresist layer 151 is formed on the surface of the hard mask layer 140, and the patterned first photoresist layer 151 defines the position of the first ridge waveguide 150; Figure 4 As shown, the hard mask layer 140, the polysilicon layer 130, the oxide layer 120 and the top silicon layer 103 are etched using the patterned first photoresist layer 151 as a mask to form the preliminary first ridge waveguide 150a; Figure 5 As shown, the patterned first photoresist layer 151 is removed.

[0037] The prepared first ridge waveguide 150a means that the structure of the first ridge waveguide 150 has been formed, but the first ridge waveguide 150 is still connected to other structures and is not independent. Subsequently, the prepared first ridge waveguide 150a needs to be separated from other structures and converted into a real first ridge waveguide 150.

[0038] In some embodiments of the present application, the preliminary first ridge waveguide 150 includes a main body and extensions extending from the bottom of the main body to both sides. The preliminary first ridge waveguide 150 is shaped like a "convex" character, with the main body forming the center portion and the extensions forming the edges of the character. The extensions of the preliminary first ridge waveguide 150 have a thickness ranging from 1 to 220 nanometers.

[0039] refer to Figures 6 to 8 As shown, a second etching process is performed to etch the hard mask layer 140, the polysilicon layer 130, the oxide layer 120, and the top silicon layer 103 in the grating region 111 to form a grating structure 180. The preliminary first ridge waveguide 150a is separated from other structures and transformed into a true first ridge waveguide 150. The grating structure 180 includes a first portion 181 located in the top silicon layer 103 and a second portion 182 located in the polysilicon layer 130.

[0040] In some embodiments of the present application, in the second etching process, the prepared first ridge waveguide 150a in the second waveguide region 113 is further etched to convert the prepared first ridge waveguide 150a into a strip waveguide 160, and the hard mask layer 140, the polysilicon layer 130, the oxide layer 120 and the top silicon layer 103 in the third waveguide region 114 are etched to form a second ridge waveguide 170 in the top silicon layer 103 of the third waveguide region 114.

[0041] In some embodiments of the present application, the second etching process includes: Figure 6 As shown, an anti-reflection layer 190 covering the SOI substrate 100 is formed on the SOI substrate 100 and a patterned second photoresist layer 152 is formed on the surface of the anti-reflection layer 190. The patterned second photoresist layer 152 defines the positions of the grating structure 180, the second ridge waveguide 170 and the strip waveguide 160; Figure 7 As shown, the anti-reflection layer 190, the hard mask layer 140, the polysilicon layer 130, the oxide layer 120 and the top silicon layer 103 are etched using the patterned second photoresist layer 152 as a mask to form the grating structure 180, the second ridge waveguide 170 and the strip waveguide 160; Figure 8 As shown, the patterned second photoresist layer 152 and the anti-reflection layer 190 are removed.

[0042] In some embodiments of the present application, the second ridge waveguide 170 includes a main body and extensions extending from the bottom end of the main body to both sides. The thickness of the extensions of the second ridge waveguide 170 is greater than the thickness of the extensions of the first ridge waveguide 150. The thickness of the extensions of the second ridge waveguide 170 is 1 to 220 nanometers.

[0043] In some embodiments of the present application, the second etching process etches away the extended portion of the prepared first ridge waveguide 150 a in the second waveguide region 113 to transform the prepared first ridge waveguide 150 a into a strip waveguide 160 .

[0044] In the technical solution of the present application, the first part 181 and the second part 182 of the grating structure 180 are formed by synchronous etching, so the alignment accuracy of the first part 181 and the second part 182 in the vertical direction is guaranteed, and the sizes are consistent, which can improve the grating coupling efficiency of the grating structure 180 and improve the device performance.

[0045] In the technical solution of the present application, the second ridge waveguide 170 and the strip waveguide 160 are formed synchronously, which saves a high-precision light, reduces the process difficulty, and improves the process efficiency.

[0046] In some embodiments of the present application, the SOI substrate 100 further includes other structures, such as a germanium photodiode, a modulator, a CMOS transistor, and the like. The formation of the germanium photodiode, modulator, and CMOS transistor can be integrated with the formation process of the first ridge waveguide, the second ridge waveguide, and the strip waveguide. That is, the germanium photodiode, modulator, CMOS transistor, and other structures are formed simultaneously with the formation of the first ridge waveguide, the second ridge waveguide, and the strip waveguide. It is only necessary to change the mask structure for forming the first ridge waveguide, the second ridge waveguide, and the strip waveguide, and then etch the corresponding structures of the germanium photodiode, modulator, and CMOS transistor in other areas.

[0047] refer to Figure 9 As shown, a first dielectric layer 191 covering the SOI substrate 100 is formed on the SOI substrate 100 , and a top surface of the first dielectric layer 191 is coplanar with a top surface of the hard mask layer 140 .

[0048] In some embodiments of the present application, the material of the first dielectric layer 191 is, for example, silicon oxide or silicon nitride, etc. The method of forming the first dielectric layer 191 includes a chemical vapor deposition process or a physical vapor deposition process, etc.

[0049] refer to Figure 10 As shown, the hard mask layer 140 and the first dielectric layer 191 above the top surface of the polysilicon layer 130 are removed.

[0050] In some embodiments of the present application, a method for removing the hard mask layer 140 and the first dielectric layer 191 above the top surface of the polysilicon layer 130 is, for example, a chemical mechanical polishing process.

[0051] refer to Figures 11 to 13 As shown, a third etching process is performed to remove the polysilicon layer 130 and the first dielectric layer 191 above the top surface of the oxide layer 120 in the first waveguide region 112 , the second waveguide region 113 , and the third waveguide region 114 .

[0052] In some embodiments of the present application, the third etching process includes: referring to Figure 11 As shown, a patterned third photoresist layer 153 is formed on the surface of the polysilicon layer 130 and the first dielectric layer 191, and the patterned third photoresist layer 153 exposes the polysilicon layer 130 and the first dielectric layer 191 of the first waveguide region 112, the second waveguide region 113 and the third waveguide region 114; Figure 12As shown, the polysilicon layer 130 and the first dielectric layer 191 are etched to the surface of the oxide layer 120 using the patterned third photoresist layer 153 as a mask to remove the polysilicon layer 13 and the first dielectric layer 191 above the top surface of the oxide layer 120 in the first waveguide region 112, the second waveguide region 113 and the third waveguide region 114; Figure 13 As shown, the patterned third photoresist layer 153 is removed.

[0053] refer to Figure 14 As shown, a second dielectric layer 192 covering the SOI substrate 100 is formed on the SOI substrate 100 .

[0054] In some embodiments of the present application, the material of the second dielectric layer 192 is, for example, silicon oxide or silicon nitride, etc. The method of forming the second dielectric layer 192 includes a chemical vapor deposition process or a physical vapor deposition process, etc.

[0055] In some processes, at least four high-precision photomasks are required to fabricate silicon-based optoelectronic passive devices. However, the technical solution of the present application only requires three photomasks (a patterned first photoresist layer 151, a patterned second photoresist layer 152, and a patterned third photoresist layer 153), and the patterned third photoresist layer 153 is not a high-precision photomask. Therefore, the technical solution of the present application reduces process difficulty and improves process efficiency.

[0056] The present application provides a method for forming a semiconductor structure, wherein the first and second parts of the grating structure are formed by synchronous etching, so that the alignment accuracy of the first and second parts of the grating structure is high, which can improve the grating coupling efficiency, thereby improving the performance and reliability of the device; the second ridge waveguide and the strip waveguide are formed by synchronous etching, which reduces the use of a high-precision mask and can reduce the process difficulty of silicon-based optoelectronic passive devices.

[0057] The embodiment of the present application further provides a semiconductor structure, referring to Figure 14 As shown, it includes: an SOI substrate 100, the SOI substrate 100 includes a bottom silicon layer 101, an insulating layer 102 and a top silicon layer 103, the SOI substrate 100 includes a grating region 111, a first waveguide region 112, a second waveguide region 113 and a third waveguide region 114; a first ridge waveguide 150, located in the top silicon layer 103 of the first waveguide region 112; a grating structure 180, the grating structure 180 includes a first portion 181 located in the top silicon layer 103 of the grating region 111 and a second portion 182 located above the first portion 181, and the second portion 182 and the first portion 181 are formed by synchronous etching.

[0058] refer to Figure 14As shown, the SOI (Silicon On Insulator) substrate 100 includes a bottom silicon layer 101 , an insulating layer 102 located on a surface of the bottom silicon layer 101 , and a top silicon layer 103 located on a surface of the insulating layer 102 .

[0059] In some embodiments of the present application, the semiconductor structure of the present application is, for example, a silicon-based optoelectronic passive device based on an SOI substrate.

[0060] In some embodiments of the present application, the material of the bottom silicon layer 101 is silicon, the material of the insulating layer 102 is silicon dioxide, and the material of the top silicon layer 103 is silicon. A silicon-on-insulator substrate (SOI substrate) is a common substrate structure in semiconductor structures, so the formation process and detailed structure of the silicon-on-insulator substrate 100 are not described here.

[0061] In some embodiments of the present application, the grating region 111 is used to form a grating structure, the first waveguide region 112 is used to form a first ridge waveguide (deep ridge waveguide), the second waveguide region 113 is used to form a stripe waveguide, and the third waveguide region 114 is used to form a second ridge waveguide (shallow ridge waveguide). The grating region 111, the first waveguide region 112, the second waveguide region 113, and the third waveguide region 114 may be adjacent or non-adjacent.

[0062] In some embodiments of the present application, the first ridge waveguide 150 includes a main body and extensions extending from the bottom of the main body to both sides. The first ridge waveguide 150 is shaped like a "convex" character, with the main body forming the center portion and the extensions forming the edges of the character. The thickness of the extensions of the first ridge waveguide 150 ranges from 1 to 220 nanometers.

[0063] In some embodiments of the present application, the semiconductor structure further includes: a strip waveguide 160 and a second ridge waveguide 170, wherein the strip waveguide 160 is located in the top silicon layer 103 of the second waveguide region 113, and the second ridge waveguide 170 is located in the top silicon layer 103 of the third waveguide region 114, and the strip waveguide 160 and the second ridge waveguide 170 are formed by synchronous etching.

[0064] In some embodiments of the present application, the second ridge waveguide 170 includes a main body and extensions extending from the bottom end of the main body to both sides. The thickness of the extensions of the second ridge waveguide 170 is greater than the thickness of the extensions of the first ridge waveguide 150. The thickness of the extensions of the second ridge waveguide 170 is 1 to 220 nanometers.

[0065] In some semiconductor structures, the strip waveguide and the second ridge waveguide are formed separately, requiring two high-precision masks. However, in the technical solution of the present application, the strip waveguide 160 and the second ridge waveguide 170 are formed by simultaneous etching, requiring only a single mask. Therefore, the technical solution of the present application reduces process difficulty and improves process efficiency.

[0066] In some embodiments of the present application, the SOI substrate 100 further includes other structures, such as a germanium photodiode, a modulator, a CMOS transistor, etc.

[0067] In some embodiments of the present application, the semiconductor structure further includes: an oxide layer 120, located on the top surface of the first portion 181 of the grating structure 180, the top surface of the first ridge waveguide 150, the top surface of the strip waveguide 160, and the top surface of the second ridge waveguide 170; a first dielectric layer 191, covering the SOI substrate 100, the top surface of the first dielectric layer 191 being coplanar with the top surface of the oxide layer 120; and a second dielectric layer 192, covering the SOI substrate 100.

[0068] In some embodiments of the present application, the material of the oxide layer 120 is, for example, silicon.

[0069] In some embodiments of the present application, the material of the first dielectric layer 191 is, for example, silicon oxide or silicon nitride.

[0070] In some embodiments of the present application, the material of the second dielectric layer 192 is, for example, silicon oxide or silicon nitride.

[0071] In the technical solution of the present application, the first part 181 and the second part 182 of the grating structure 180 are formed by synchronous etching, so the alignment accuracy of the first part 181 and the second part 182 in the vertical direction is guaranteed, and the sizes are consistent, which can improve the grating coupling efficiency of the grating structure 180 and improve the device performance.

[0072] In some embodiments of the present application, the first portion 181 of the grating structure 180 is a silicon grating, and the second portion 182 of the grating structure 180 is a polysilicon grating.

[0073] The present application provides a semiconductor structure and a method for forming the same. The first and second parts of the grating structure are formed by synchronous etching, so the alignment accuracy of the first and second parts of the grating structure is high, which can improve the grating coupling efficiency, thereby improving the performance and reliability of the device; the second ridge waveguide and the strip waveguide are formed by synchronous etching, which reduces the use of a high-precision mask and can reduce the process difficulty of silicon-based optoelectronic passive devices.

[0074] In summary, after reading the contents of this application, those skilled in the art will understand that the foregoing contents are presented by way of example only and are not intended to be limiting. Although not expressly stated herein, those skilled in the art will understand that this application is intended to encompass various reasonable changes, improvements, and modifications to the embodiments. Such changes, improvements, and modifications are within the spirit and scope of the exemplary embodiments of this application.

[0075] It should be understood that the term "and / or" used in this embodiment includes any or all combinations of one or more of the associated listed items. It should be understood that when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element, or intervening elements may also be present.

[0076] Similarly, it should be understood that when an element such as a layer, region, or substrate is referred to as being "on" another element, it can be directly on the other element or intervening elements may be present. In contrast, the term "directly" indicates that there are no intervening elements. It should also be understood that the terms "comprising," "including," "include," or "comprising," when used in this specification, indicate the presence of recited features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0077] It should also be understood that although the terms first, second, third, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. Therefore, without departing from the teachings of the present application, the first element in some embodiments may be referred to as the second element in other embodiments. The same reference numerals or the same reference designators represent the same elements throughout the specification.

[0078] In addition, this specification describes exemplary embodiments by reference to idealized exemplary cross-sectional views and / or plan views and / or stereograms. Therefore, differences from the illustrated shapes due to, for example, manufacturing techniques and / or tolerances are foreseeable. Therefore, the exemplary embodiments should not be interpreted as being limited to the shapes of the regions shown herein, but should include deviations in shapes due to, for example, manufacturing. For example, an etched region shown as a rectangle will typically have rounded or curved features. Therefore, the regions shown in the figures are schematic in nature, and their shapes are not intended to illustrate the actual shape of the region of the device nor to limit the scope of the exemplary embodiments.

Claims

1. A method for forming a semiconductor structure, characterized in that: include: Providing an SOI substrate, the SOI substrate comprising a bottom silicon layer, an insulating layer, and a top silicon layer, the SOI substrate comprising a grating region, a first waveguide region, a second waveguide region, and a third waveguide region; forming an oxide layer, a polysilicon layer and a hard mask layer in sequence on the surface of the SOI substrate; Performing a first etching process to etch the hard mask layer, the polysilicon layer, the oxide layer, and the top silicon layer in the first waveguide region and the second waveguide region, thereby forming a preliminary first ridge waveguide in the top silicon layer in the first waveguide region and the second waveguide region; A second etching process is performed to etch the hard mask layer, the polysilicon layer, the oxide layer and the top silicon layer in the grating region to form a grating structure, and to transform the prepared first ridge waveguide in the first waveguide region into a first ridge waveguide, wherein the grating structure includes a first portion located in the top silicon layer and a second portion located in the polysilicon layer.

2. The method for forming a semiconductor structure according to claim 1, wherein: The first etching process includes: forming a patterned first photoresist layer on a surface of the hard mask layer, wherein the patterned first photoresist layer defines a position of the first ridge waveguide; Using the patterned first photoresist layer as a mask, etching the hard mask layer, the polysilicon layer, the oxide layer, and the top silicon layer to form the preliminary first ridge waveguide; The patterned first photoresist layer is removed.

3. The method for forming a semiconductor structure according to claim 1, wherein: In the second etching process, the prepared first ridge waveguide in the second waveguide region is also etched to convert the prepared first ridge waveguide into a strip waveguide, and the hard mask layer, polysilicon layer, oxide layer and top silicon layer in the third waveguide region are etched to form a second ridge waveguide in the top silicon layer of the third waveguide region.

4. The method for forming a semiconductor structure according to claim 3, wherein: The second etching process includes: forming an anti-reflection layer covering the SOI substrate on the SOI substrate and forming a patterned second photoresist layer on the surface of the anti-reflection layer, wherein the patterned second photoresist layer defines positions of the grating structure, the second ridge waveguide, and the strip waveguide; Using the patterned second photoresist layer as a mask, etching the anti-reflection layer, the hard mask layer, the polysilicon layer, the oxide layer and the top silicon layer to form the grating structure, the second ridge waveguide and the strip waveguide; The patterned second photoresist layer and the anti-reflection layer are removed.

5. The method for forming a semiconductor structure according to claim 4, wherein: The prepared first ridge waveguide includes a main body and extensions extending from the bottom end of the main body to both sides. The second etching process etches away the extensions of the prepared first ridge waveguide in the second waveguide region to transform the prepared first ridge waveguide into a strip waveguide.

6. The method for forming a semiconductor structure according to claim 5, wherein: The second ridge waveguide includes a main body and extensions extending from a bottom end of the main body to both sides. The thickness of the extension of the second ridge waveguide is greater than that of the extension of the first ridge waveguide.

7. The method for forming a semiconductor structure according to claim 1, wherein: Also includes: forming a first dielectric layer covering the SOI substrate on the SOI substrate, wherein a top surface of the first dielectric layer is coplanar with a top surface of the hard mask layer; removing the hard mask layer and the first dielectric layer above the top surface of the polysilicon layer; Performing a third etching process to remove the polysilicon layer and the first dielectric layer above the top surface of the oxide layer in the first waveguide region, the second waveguide region, and the third waveguide region; A second dielectric layer covering the SOI substrate is formed on the SOI substrate.

8. The method for forming a semiconductor structure according to claim 7, wherein: The third etching process includes: forming a patterned third photoresist layer on the surface of the polysilicon layer and the first dielectric layer, wherein the patterned third photoresist layer exposes the polysilicon layer and the first dielectric layer in the first waveguide region, the second waveguide region, and the third waveguide region; Using the patterned third photoresist layer as a mask, the polysilicon layer and the first dielectric layer are etched to the surface of the oxide layer to remove the polysilicon layer and the first dielectric layer above the top surface of the oxide layer in the first waveguide region, the second waveguide region, and the third waveguide region; The patterned third photoresist layer is removed.

9. A semiconductor structure formed by the method for forming a semiconductor structure according to any one of claims 1 to 8, characterized in that: include: An SOI substrate, the SOI substrate comprising a bottom silicon layer, an insulating layer, and a top silicon layer, the SOI substrate comprising a grating region, a first waveguide region, a second waveguide region, and a third waveguide region; a first ridge waveguide located in the top silicon layer of the first waveguide region; The grating structure includes a first portion located in the top silicon layer of the grating region and a second portion located above the first portion, wherein the second portion and the first portion are formed by synchronous etching.

10. The semiconductor structure according to claim 9, wherein: Also includes: A strip waveguide and a second ridge waveguide, wherein the strip waveguide is located in the top silicon layer of the second waveguide region, and the second ridge waveguide is located in the top silicon layer of the third waveguide region, and the strip waveguide and the second ridge waveguide are formed by synchronous etching.

11. The semiconductor structure according to claim 10, wherein: The first ridge waveguide includes a main body and extensions extending from the bottom end of the main body to both sides. The second ridge waveguide includes a main body and extensions extending from the bottom end of the main body to both sides. The thickness of the extension of the second ridge waveguide is greater than the thickness of the extension of the first ridge waveguide.

12. The semiconductor structure according to claim 10, wherein: Also includes: an oxide layer, located on a top surface of the first portion of the grating structure, a top surface of the first ridge waveguide, a top surface of the stripe waveguide, and a top surface of the second ridge waveguide; a first dielectric layer covering the SOI substrate, wherein a top surface of the first dielectric layer is coplanar with a top surface of the oxide layer; The second dielectric layer covers the SOI substrate.

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