A flexible display integrated device and its fabrication method

Abstract

This invention discloses a flexible display integrated device and its fabrication method, relating to the field of power semiconductors. The device includes, from bottom to top, a substrate, a buffer layer, an n-type GaN layer, a multiple quantum well layer, and a p-type GaN layer; both the buffer layer and the n-type GaN layer have convex structures; a first passivation layer covers the entire assembly from bottom to top, a thin-film channel layer covers the top of the first passivation layer, and a second passivation layer covers the entire assembly formed by the first passivation layer and the thin-film channel layer; the top of the cathode is covered by the second passivation layer, and the bottom is connected to the n-type GaN layer; the top of the source / anode is covered by the thin-film channel layer, and the bottom is connected to the p-type GaN layer; the top of the drain is covered by the thin-film channel layer, and the bottom is connected to the upper surface of the first passivation layer; the gate is located between the source / anode and the drain, and the gate is located on the upper surface of the second passivation layer. This invention reduces the difficulty of the manufacturing process.

Description

Technical Field

[0001] This invention relates to the field of power semiconductor technology, and in particular to a flexible display integrated device and its fabrication method. Background Technology

[0002] The traditional approach to manufacturing active matrix micro-LED displays involves connecting the Micro-LED chips and Field Programmable Gate Array (FPGA) circuits with leads. However, this approach is mainly suitable for low-resolution displays.

[0003] Using a silicon-based complementary metal-oxide-semiconductor (CMOS) backplane to drive Micro-LEDs is suitable for high-resolution displays. However, this approach requires aligning and bonding the silicon-based CMOS driving backplane and the Micro-LED chip, which presents a high-precision alignment and bonding challenge and cannot be applied to the field of flexible displays. Summary of the Invention

[0004] The purpose of this invention is to provide a flexible display integrated device and its fabrication method, which reduces the difficulty of the manufacturing process.

[0005] To achieve the above objectives, the present invention provides the following solution:

[0006] A flexible display integrated device includes a substrate, a buffer layer, an n-type GaN layer, a multiple quantum well layer and a p-type GaN layer arranged sequentially from bottom to top. The flexible display integrated device also includes a first passivation layer, a thin film channel layer, a second passivation layer, a source / anode, a gate, a drain and a cathode.

[0007] The buffer layer has a convex structure with a raised upper surface. The lower surface of the n-type GaN layer coincides with the upper surface of the buffer layer. The n-type GaN layer has a convex structure with a raised upper surface. The lower surface of the multi-quantum well layer coincides with the upper surface of the n-type GaN layer. The lower surface of the p-type GaN layer coincides with the upper surface of the multi-quantum well layer.

[0008] The first passivation layer covers the entirety of the buffer layer, the n-type GaN layer, the multiple quantum well layer, and the p-type GaN layer. The thin-film channel layer covers the top of the first passivation layer. The second passivation layer covers the entirety of the first passivation layer and the thin-film channel layer. The cathode is located on a recessed side of the upper surface of the n-type GaN layer, penetrates the first passivation layer, has its top covered by the second passivation layer, and its bottom connected to the n-type GaN layer. The source / anode is located above the p-type GaN layer, penetrates the first passivation layer, has its top covered by the thin-film channel layer, and its bottom connected to the p-type GaN layer. The drain is located above the first passivation layer, has its top covered by the thin-film channel layer, and its bottom connected to the upper surface of the first passivation layer. The gate is located between the source / anode and the drain, and is located on the upper surface of the second passivation layer.

[0009] Optionally, the substrate is a silicon substrate, a sapphire substrate, a silicon carbide substrate, a self-supporting gallium nitride substrate, or a flexible substrate.

[0010] Optionally, the buffer layer is a gallium nitride layer doped with iron or carbon, an AlN layer, an AlN / GaN superlattice structure, or an AlGaN / GaN superlattice structure.

[0011] Optionally, the materials of the first passivation layer and the second passivation layer are aluminum oxide or silicon oxide.

[0012] Optionally, the material of the thin film channel layer is MoS2, ZnO or IGZO.

[0013] This invention also discloses a method for fabricating a flexible display integrated device, the method being used to fabricate the aforementioned flexible display integrated device, the method comprising:

[0014] Obtain an epitaxial wafer, the epitaxial wafer comprising, from bottom to top, a substrate, a buffer layer, an n-type GaN layer, a multiple quantum well layer and a p-type GaN layer;

[0015] The buffer layer, the n-type GaN layer, the multiple quantum well layer, and the p-type GaN layer are etched to obtain the buffer layer with a protrusion on its upper surface, the n-type GaN layer with a protrusion on its upper surface, the multiple quantum well layer with its lower surface overlapping the upper surface of the n-type GaN layer, and the p-type GaN layer with its lower surface overlapping the upper surface of the multiple quantum well layer.

[0016] A first passivation layer is deposited on top of the entire structure consisting of the buffer layer, the n-type GaN layer, the multiple quantum well layer, and the p-type GaN layer;

[0017] The first passivation layer under the cathode region is removed to form a cathode region window; the cathode region is located on the recessed side of the upper surface of the n-type GaN layer;

[0018] An ohmic contact metal is evaporated on the cathode region window and then annealed at high temperature to form a cathode;

[0019] The first passivation layer under the source / anode region is removed to form a source / anode region window; the source / anode region is located above the p-type GaN layer.

[0020] A drain region window is obtained on top of the first passivation layer using a photolithography process;

[0021] Ohmic contact metal is evaporated on the source / anode region window and the drain region window, and then annealed at high temperature to form the source / anode and drain.

[0022] A thin film channel layer is deposited above the top of the first passivation layer;

[0023] A second passivation layer is deposited over the entirety formed by the first passivation layer and the thin film channel layer;

[0024] A gate region window is obtained at the top of the second passivation layer using a photolithography process; the gate region window is located between the source / anode and the drain.

[0025] A Schottky contact metal is evaporated on the gate region window to form a gate.

[0026] Optionally, the etching of the buffer layer, the n-type GaN layer, the multiple quantum well layer, and the p-type GaN layer to obtain the buffer layer with a raised upper surface, the n-type GaN layer with a raised upper surface, the multiple quantum well layer with a lower surface overlapping the upper surface of the n-type GaN layer, and the p-type GaN layer with a lower surface overlapping the upper surface of the multiple quantum well layer, further includes:

[0027] The etched buffer layer, n-type GaN layer, multi-quantum-well layer, and p-type GaN layer are subjected to surface acid treatment.

[0028] Optionally, the ohmic contact metal is Ti / Al / Ni / Au or Ti / Al / Mo / Au, and the Schottky contact metal includes Ti and Al.

[0029] According to specific embodiments provided by the present invention, the present invention discloses the following technical effects:

[0030] This invention, based on the growth of GaN-based multi-quantum-well LEDs (multi-quantum-well layers) on a substrate, integrates the source of a thin-film transistor (TFT) and the anode of the Micro-LED on top of the Micro-LED (multi-quantum-well layer). This enables the TFT to drive and control the Micro-LED. The TFT source and the Micro-LED anode can minimize parasitic capacitance, inductance, and resistance caused by metal interconnects. This invention directly sets the channel layer of the TFT on the top layer of the Micro-LED chip, making the manufacturing process easier to implement and more suitable for the field of flexible displays. It reduces the difficulty of the manufacturing process and improves the yield. Attached Figure Description

[0031] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0032] Figure 1 This is a schematic diagram of a flexible display integrated device structure according to the present invention;

[0033] Figure 2 This is a schematic diagram of the fabrication process of a flexible display integrated device according to the present invention. Figure 1 ;

[0034] Figure 3 This is a schematic diagram of the fabrication process of a flexible display integrated device according to the present invention. Figure 2 ;

[0035] Symbol explanation:

[0036] Substrate—1, Buffer layer—2, n-type GaN layer—3, Multiple quantum well layer—4, p-type GaN layer—5, First passivation layer—6, Thin film channel layer—7, Second passivation layer—8, Source / anode—9, Gate—10, Drain—11, Cathode—12. Detailed Implementation

[0037] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0038] The purpose of this invention is to provide a flexible display integrated device and its fabrication method, which reduces the difficulty of the manufacturing process.

[0039] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0040] Example 1

[0041] This embodiment uses a molybdenum disulfide-based transistor as an example of a thin-film transistor to illustrate the present invention. In this embodiment, "thin-film transistor" includes, but is not limited to, various transistors based on two-dimensional materials, as well as thin-film oxide transistors.

[0042] Integrated device structure for driving gallium nitride (GaN)-based micro-LEDs using molybdenum disulfide transistors, such as... Figure 1 As shown.

[0043] like Figure 1 As shown, the present invention provides a flexible display integrated device, comprising, from bottom to top, a substrate 1, a buffer layer 2, an n-type GaN layer 3, a multiple quantum well layer 4, and a p-type GaN layer 5. The flexible display integrated device further comprises a first passivation layer 6, a thin film channel layer 7, a second passivation layer 8, a source / anode 9, a gate 10, a drain 11, and a cathode 12.

[0044] Source / Anode 9 integrates the source of the thin-film transistor and the anode of the Micro-LED device.

[0045] The buffer layer 2 has a convex structure with raised upper surface. The lower surface of the n-type GaN layer 3 coincides with the upper surface of the buffer layer 2. The n-type GaN layer 3 has a convex structure with raised upper surface. The lower surface of the multi-quantum well layer 4 coincides with the upper surface of the n-type GaN layer 3. The lower surface of the p-type GaN layer 5 coincides with the upper surface of the multi-quantum well layer 4.

[0046] The first passivation layer 6 covers the entire structure formed by the buffer layer 2, the n-type GaN layer 3, the multiple quantum well layer 4, and the p-type GaN layer 5. The thin-film channel layer 7 covers the top of the first passivation layer 6. The second passivation layer 8 covers the entire structure formed by the first passivation layer 6 and the thin-film channel layer 7. The cathode 12 is located on a recessed side of the upper surface of the n-type GaN layer 3. The cathode 12 penetrates the first passivation layer 6. The top of the cathode 12 is covered by the second passivation layer 8, and the bottom of the cathode 12 is connected to the n-type GaN layer 3. The source / anode 9 is located above the p-type GaN layer 5, penetrates the first passivation layer 6, is covered by the thin film channel layer 7 at its top, and is connected to the p-type GaN layer 5 at its bottom. The drain 11 is located above the first passivation layer 6, is covered by the thin film channel layer 7 at its top, and is connected to the upper surface of the first passivation layer 6 at its bottom. The gate 10 is located between the source / anode 9 and the drain 11, and is located on the upper surface of the second passivation layer 8.

[0047] The substrate 1 is a silicon substrate, a sapphire substrate, a silicon carbide substrate, a self-supporting gallium nitride substrate, or a flexible substrate.

[0048] The buffer layer 2 is a gallium nitride layer doped with iron or carbon, an AlN layer, an AlN / GaN superlattice structure, or an AlGaN / GaN superlattice structure.

[0049] The materials of the first passivation layer 6 and the second passivation layer 8 are aluminum oxide or silicon oxide.

[0050] The material of the thin film channel layer 7 is MoS2, ZnO or IGZO.

[0051] Substrate 1 is located at the bottom of the entire flexible display integrated device structure, serving a supporting function. It may be, but is not limited to, a silicon substrate, a sapphire substrate, a silicon carbide (SiC) substrate, a self-supporting gallium nitride substrate, or a flexible substrate. Buffer layer 2 is located above substrate 1. Introduced as buffer layer 2, it achieves stress relief and dislocation filtering to obtain better crystal quality. It may be, but is not limited to, a gallium nitride layer doped with iron (Fe) or carbon (C) or an Al(Ga)N / GaN superlattice structure. n-type GaN layer 3 is located above buffer layer 2. Multiple quantum well layer 4 is located above n-type GaN layer 3 and generates a two-dimensional electron gas (2DEG) near n-type GaN layer 3 at its interface through piezoelectric polarization and spontaneous polarization effects. First passivation layer 6 and second passivation layer 8 are located above p-type GaN layer 5 to reduce surface traps. They may be, but are not limited to, aluminum oxide (Al2O3) or silicon oxide (SiO2) as passivation layer materials.

[0052] Example 2

[0053] Figure 2 This is a schematic diagram of the fabrication process of a flexible display integrated device according to the present invention. Figure 1 , Figure 3 This is a schematic diagram of the fabrication process of a flexible display integrated device according to the present invention. Figure 2 The present invention provides a method for fabricating a flexible display integrated device, used to fabricate the flexible display integrated device described in Example 1, such as... Figures 2-3 As shown, a method for fabricating a flexible display integrated device includes the following steps:

[0054] Step 101: Obtain an epitaxial wafer, which includes a substrate, a buffer layer, an n-type GaN layer, a multiple quantum well layer and a p-type GaN layer arranged sequentially from bottom to top.

[0055] After step 101, the countertop is isolated.

[0056] Step 102: Etch the buffer layer, the n-type GaN layer, the multiple quantum well layer, and the p-type GaN layer to obtain the buffer layer with a raised upper surface, the n-type GaN layer with a raised upper surface, the multiple quantum well layer with a lower surface overlapping the upper surface of the n-type GaN layer, and the p-type GaN layer with a lower surface overlapping the upper surface of the multiple quantum well layer.

[0057] Step 102 is followed by:

[0058] The etched buffer layer, n-type GaN layer, multiple quantum well layer, and p-type GaN layer are subjected to surface acid treatment (for devices with mesa isolation).

[0059] Acid treatment is performed using HCl, H2SO4+H2O2, or buffered oxide etching solution (BOE).

[0060] Step 103: Deposit a first passivation layer on top of the entire structure consisting of the buffer layer, the n-type GaN layer, the multiple quantum well layer, and the p-type GaN layer.

[0061] Step 104: Remove the first passivation layer under the cathode region to form a cathode region window; the cathode region is located on the recessed side of the upper surface of the n-type GaN layer.

[0062] Specifically, step 104 includes: removing the first passivation layer under the cathode region by a wet etching process to form a cathode region window.

[0063] Step 105: Evaporate ohmic contact metal on the cathode region window and anneal at high temperature to form a cathode.

[0064] Specifically, step 105 includes: using an electron beam evaporation process to evaporate ohmic contact metal on the cathode region window, and then annealing it at high temperature to form a cathode.

[0065] Step 106: Remove the first passivation layer under the source / anode region to form a source / anode region window; the source / anode region is located above the p-type GaN layer.

[0066] Specifically, step 106 includes: removing the first passivation layer under the source / anode region by wet etching process to form a source / anode region window.

[0067] Step 107: Drain region window obtained on top of the first passivation layer by photolithography.

[0068] Specifically, step 107 includes: removing the first passivation layer under the drain region by a wet etching process to form a drain region window.

[0069] Step 108: Evaporate ohmic contact metal on the source / anode region window and the drain region window, and anneal at high temperature to form the source / anode and drain.

[0070] Specifically, step 108 includes: using an electron beam evaporation process to evaporate ohmic contact metal on the source / anode region window and the drain region window, and then annealing at high temperature to form the source / anode and drain.

[0071] Step 109: Deposit a thin film channel layer above the top of the first passivation layer.

[0072] The thin film channel layer is a MoS2 layer.

[0073] Step 109 also includes etching the MoS2 layer.

[0074] Step 110: Deposit a second passivation layer over the entirety formed by the first passivation layer and the thin film channel layer.

[0075] Step 111: A gate region window is obtained at the top of the second passivation layer by photolithography; the gate region window is located between the source / anode and the drain.

[0076] Step 112: Evaporate the Schottky contact metal on the gate region window to form the gate.

[0077] The ohmic contact metal is Ti / Al / Ni / Au or Ti / Al / Mo / Au, and the Schottky contact metal includes Ti and Al.

[0078] This invention uses a thin-film transistor to drive an integrated device structure for Micro-LEDs. Compared with the traditional silicon-based CMOS driving circuit and the heterogeneous integration structure of Micro-LEDs, it can directly grow the channel layer of thin-film transistors on the top layer of the Micro-LED chip through chemical vapor deposition. This is easier to achieve in terms of manufacturing process and is more suitable for flexible displays.

[0079] This invention integrates the source of a thin-film transistor and the anode of a Micro-LED device, reducing the length of the metal interconnect and thus reducing the parasitic capacitance, inductance, and resistance introduced by the metal interconnect. It enables monolithic integration of the top-layer MoS2 transistor array and the bottom-layer Micro-LED array, avoiding the steps of connecting, aligning, and bonding the Micro-LED chip and driving circuit, providing a new solution for ultra-high resolution and flexible displays. Furthermore, the transistors disclosed in this invention employ a back-gate structure, which results in a higher yield rate compared to the conventional top-gate structure.

[0080] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. The same or similar parts between the various embodiments can be referred to each other.

[0081] This document uses specific examples to illustrate the principles and implementation methods of the present invention. The descriptions of the above embodiments are only for the purpose of helping to understand the method and core ideas of the present invention. Furthermore, those skilled in the art will recognize that, based on the ideas of the present invention, there will be changes in the specific implementation methods and application scope. Therefore, the content of this specification should not be construed as a limitation of the present invention.

Claims

1. A flexible display integrated device, characterized in that, The flexible display integrated device includes, from bottom to top, a substrate, a buffer layer, an n-type GaN layer, a multiple quantum well layer, and a p-type GaN layer. The flexible display integrated device also includes a first passivation layer, a thin film channel layer, a second passivation layer, a source / anode, a gate, a drain, and a cathode. The buffer layer has a convex structure with a raised upper surface. The lower surface of the n-type GaN layer coincides with the upper surface of the buffer layer. The n-type GaN layer has a convex structure with a raised upper surface. The lower surface of the multi-quantum well layer coincides with the upper surface of the n-type GaN layer. The lower surface of the p-type GaN layer coincides with the upper surface of the multi-quantum well layer. The first passivation layer is used to cover the entirety consisting of the buffer layer, the n-type GaN layer, the multiple quantum well layer and the p-type GaN layer, the thin film channel layer is covered above the top of the first passivation layer, and the second passivation layer is used to cover the entirety consisting of the first passivation layer and the thin film channel layer. The cathode is located on a recessed side of the upper surface of the n-type GaN layer. The cathode penetrates the first passivation layer. The top of the cathode is covered by the second passivation layer, and the bottom of the cathode is connected to the n-type GaN layer. The source / anode is located above the p-type GaN layer, the source / anode penetrates the first passivation layer, the top of the source / anode is covered by the thin film channel layer, and the bottom of the source / anode is connected to the p-type GaN layer. The drain is located above the first passivation layer, the top of the drain is covered by the thin film channel layer, and the bottom of the drain is connected to the upper surface of the first passivation layer. The gate is located between the source / anode and the drain, and the gate is located on the upper surface of the second passivation layer.

2. The flexible display integrated device according to claim 1, characterized in that, The substrate is a silicon substrate, a sapphire substrate, a silicon carbide substrate, a self-supporting gallium nitride substrate, or a flexible substrate.

3. The flexible display integrated device according to claim 1, characterized in that, The buffer layer is a gallium nitride layer doped with iron or carbon, an AlN layer, an AlN / GaN superlattice structure, or an AlGaN / GaN superlattice structure.

4. The flexible display integrated device according to claim 1, characterized in that, The materials of the first passivation layer and the second passivation layer are aluminum oxide or silicon oxide.

5. The flexible display integrated device according to claim 1, characterized in that, The material of the thin film channel layer is MoS2, ZnO or IGZO.

6. A method for fabricating a flexible display integrated device, wherein the method is used to fabricate the flexible display integrated device according to any one of claims 1-5, characterized in that, The method for fabricating the flexible display integrated device includes: Obtain an epitaxial wafer, the epitaxial wafer comprising, from bottom to top, a substrate, a buffer layer, an n-type GaN layer, a multiple quantum well layer and a p-type GaN layer; The buffer layer, the n-type GaN layer, the multiple quantum well layer, and the p-type GaN layer are etched to obtain the buffer layer with a protrusion on its upper surface, the n-type GaN layer with a protrusion on its upper surface, the multiple quantum well layer with its lower surface overlapping the upper surface of the n-type GaN layer, and the p-type GaN layer with its lower surface overlapping the upper surface of the multiple quantum well layer. A first passivation layer is deposited on top of the entire structure consisting of the buffer layer, the n-type GaN layer, the multiple quantum well layer, and the p-type GaN layer; The first passivation layer under the cathode region is removed to form a cathode region window; the cathode region is located on the recessed side of the upper surface of the n-type GaN layer; An ohmic contact metal is evaporated on the cathode region window and then annealed at high temperature to form a cathode; The first passivation layer under the source / anode region is removed to form a source / anode region window; the source / anode region is located above the p-type GaN layer. A drain region window is obtained on top of the first passivation layer using a photolithography process; Ohmic contact metal is evaporated on the source / anode region window and the drain region window, and then annealed at high temperature to form the source / anode and drain. A thin film channel layer is deposited above the top of the first passivation layer; A second passivation layer is deposited over the entirety formed by the first passivation layer and the thin film channel layer; A gate region window is obtained at the top of the second passivation layer using a photolithography process; the gate region window is located between the source / anode and the drain. A Schottky contact metal is evaporated on the gate region window to form a gate.

7. The method for fabricating a flexible display integrated device according to claim 6, characterized in that, The process involves etching the buffer layer, the n-type GaN layer, the multiple quantum well layer, and the p-type GaN layer to obtain the buffer layer with a raised upper surface, the n-type GaN layer with a raised upper surface, the multiple quantum well layer with a lower surface overlapping the upper surface of the n-type GaN layer, and the p-type GaN layer with a lower surface overlapping the upper surface of the multiple quantum well layer. The process further includes: The etched buffer layer, the n-type GaN layer, the multiple quantum well layer, and the p-type GaN layer are subjected to surface acid treatment.

8. The method for fabricating a flexible display integrated device according to claim 6, characterized in that, The ohmic contact metal is Ti / Al / Ni / Au or Ti / Al / Mo / Au, and the Schottky contact metal includes Ti and Al.

Images