LED chip and preparation method thereof

Abstract

The application provides an LED chip and a preparation method thereof. The LED chip is prepared by the following steps: providing an epitaxial wafer, depositing a charge balance (CB) layer on the surface of the epitaxial wafer to obtain a patterned CB pattern and a bare P-GaN layer; preparing a mirror on the bare P-GaN layer; forming a barrier layer; preparing a bonding layer on the barrier layer and a provided bonding substrate; bonding the epitaxial wafer with the prepared bonding layer and the bonding substrate, and removing a sapphire substrate; etching the epitaxial wafer with the removed sapphire substrate to form an epitaxial layer structure meeting a light distribution requirement, and the edge of the epitaxial layer structure is a sidewall with a preset inclination angle; depositing an insulating PV layer, and patterning the PV layer to expose part of an N-GaN layer; and preparing an N electrode on the PV layer and the exposed part of the N-GaN layer. The LED chip is prepared to adjust the light emitting angle.

Description

Technical Field

[0001] This invention relates to the field of LED manufacturing technology, and in particular to an LED chip and its preparation method. Background Technology

[0002] For LED chips, especially vertically oriented LED chips, the light emission angle of the LED chip is usually adjusted during the packaging process to obtain the LED chip with the required light emission angle.

[0003] However, for some specific application areas, the light distribution of the small-angle LED chips required during the packaging process not only increases the workload and difficulty of packaging, but may also result in LED chips with unreliable light emission angles. Summary of the Invention

[0004] In view of this, embodiments of the present invention provide an LED chip and a method for manufacturing the same, in order to solve the problem of adjusting the light emission angle of the LED chip.

[0005] To address the above problems, embodiments of the present invention provide the following technical solutions:

[0006] The first aspect of this invention discloses a method for fabricating an LED chip, the method comprising:

[0007] An epitaxial wafer is provided, the epitaxial wafer comprising a sapphire substrate, an N-GaN layer, an MQWs layer, and a P-GaN layer;

[0008] A charge-balanced CB layer is deposited on the surface of the epitaxial wafer and patterned to obtain a patterned CB pattern and a partially exposed P-GaN layer.

[0009] A mirror is fabricated on the exposed portion of the P-GaN layer;

[0010] A barrier layer is formed to cover the patterned CB pattern and the reflector;

[0011] A bonding layer is prepared on the barrier layer and the provided bonding substrate;

[0012] The epitaxial wafer with the bonding layer prepared is bonded to the bonding substrate, and then the sapphire substrate is removed.

[0013] The epitaxial wafer of the sapphire substrate is etched away to form an epitaxial layer structure that meets the light distribution requirements. The edge of the epitaxial layer structure is a sidewall with a preset tilt angle.

[0014] An insulating PV layer is deposited to cover the surface of the epitaxial layer structure, and the PV layer is patterned to expose part of the N-GaN layer.

[0015] N electrodes are fabricated on the PV layer and the exposed portion of the N-GaN layer.

[0016] Optionally, a charge-balanced CB layer is deposited on the surface of the epitaxial wafer, comprising:

[0017] At a preset power of 20W to 120W, a charge-balanced CB layer with a thickness of 1000A to 8000A is deposited on the surface of the epitaxial wafer using N2O with a gas ratio of 400 to 1400 and 5% SiH4 / N2 with a gas ratio of 200 to 1800.

[0018] Optionally, a mirror is fabricated on the exposed portion of the P-GaN layer, including:

[0019] A reflector is formed on the exposed P-GaN layer by sputtering or evaporation. The reflector comprises one or more metal structures of ITO, Ni, Ag, Rh, Au, Ti, Cr, Pt, Mg, and Al with high reflectivity.

[0020] The patterned CB pattern is located at both ends of the epitaxial wafer, and the exposed P-GaN layer is located between the patterned CB pattern.

[0021] Optionally, a barrier layer is formed, including:

[0022] A barrier layer is formed on the patterned CB pattern and the mirror by sputtering or vapor deposition. The barrier layer includes one or more metals such as Ti, Ni, Pt, TiW, and Au.

[0023] Accordingly, a bonding layer is prepared on the barrier layer and the provided bonding substrate, including:

[0024] A bonding layer is formed by simultaneously depositing a bonding metal on the barrier layer and the provided bonding substrate. The bonding metal includes Au, In, or Ni, or Sn or Sn and Au.

[0025] Optionally, etching removes the epitaxial wafer from the sapphire substrate to form an epitaxial layer structure that meets light distribution requirements, including:

[0026] On the epitaxial wafer with the sapphire substrate removed, DE etching is performed with the N-GaN layer as the upper layer. Sidewalls are formed on both sides of the epitaxial wafer with the sapphire substrate removed, and part of the CB pattern is exposed along the edge of the sidewalls. A preset tilt angle is formed between the sidewalls and the CB pattern, and a preset length difference is formed between the N-GaN layer constituting the sidewalls and the P-GaN layer, forming an epitaxial layer structure with a preset tilt angle and a preset length difference.

[0027] Optionally, an insulating PV layer is deposited to cover the surface of the epitaxial layer structure, and the PV layer is patterned to expose a portion of the N-GaN layer, including:

[0028] An insulating material, such as SiO2, SiN, ZnO, Al2O3, TiO2, or ZrO2, is deposited on the surface of the epitaxial layer structure to form a PV layer covering the surface of the epitaxial layer structure.

[0029] The PV layer is patterned using wet etching or dry etching to expose part of the N-GaN layer.

[0030] Optionally, an N-electrode is fabricated on the PV layer and the exposed portion of the N-GaN layer, including:

[0031] A highly reflective metal electrode is fabricated on the exposed N-GaN layer to form an N electrode, and the fabricated N electrode is completely or partially covered on the PV layer located on the entire sidewall of the epitaxial layer structure.

[0032] Optionally, it also includes: connecting or disconnecting the N electrode covering the sidewall by exposure to adjust the light emission angle of the LED chip.

[0033] The second aspect of the present invention discloses an LED chip, which is prepared by the LED chip preparation method disclosed in the first aspect of the present invention, wherein the LED chip forms an epitaxial layer structure that meets the light distribution requirements during the preparation process.

[0034] Optionally, the LED chip is a vertically structured LED chip.

[0035] An LED chip and its fabrication method based on the above embodiments of the present invention are provided. The fabrication method includes: providing an epitaxial wafer, the epitaxial wafer including a sapphire substrate, an N-GaN layer, an MQWs layer, and a P-GaN layer; depositing a charge-balanced CB layer on the surface of the epitaxial wafer and patterning it to obtain a patterned CB pattern and a bare portion of the P-GaN layer; fabricating a reflector on the bare portion of the P-GaN layer; forming a barrier layer to cover the patterned CB pattern and the reflector; fabricating a bonding layer on the barrier layer and a provided bonding substrate; bonding the epitaxial wafer with the bonding layer fabricated to the bonding substrate and removing the sapphire substrate; etching the epitaxial wafer with the sapphire substrate removed to form an epitaxial layer structure that meets the light distribution requirements, the edges of the epitaxial layer structure being sidewalls with a preset tilt angle; depositing an insulating PV layer to cover the surface of the epitaxial layer structure and patterning the PV layer to expose a portion of the N-GaN layer; and fabricating an N-electrode on the PV layer and the exposed portion of the N-GaN layer. In this embodiment of the invention, during the fabrication process, by setting the edge of the epitaxial layer structure as a sidewall with a preset tilt angle, the desired light emission angle can be obtained, thereby achieving adjustment of the light emission angle of the LED chip during the fabrication process; at the same time, the N electrode completely or partially covers the PV layer located on the entire sidewall of the epitaxial layer structure, making the sidewall have an additional layer of metal, enhancing the protection and heat conduction capabilities of the LED chip, thereby improving the reliability of the LED chip. Attached Figure Description

[0036] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on the provided drawings without creative effort.

[0037] Figure 1 A flowchart illustrating a method for fabricating an LED chip according to an embodiment of the present invention;

[0038] Figure 2 This is a schematic diagram of the structure of an epitaxial wafer provided in an embodiment of the present invention;

[0039] Figure 3 This is a schematic diagram of the structure after forming a patterned CB pattern and an exposed portion of the P-GaN layer, provided by an embodiment of the present invention;

[0040] Figure 4 This is a schematic diagram of the structure after forming a reflector, provided by an embodiment of the present invention;

[0041] Figure 5This is a schematic diagram of the structure after the barrier layer is formed, provided by an embodiment of the present invention;

[0042] Figure 6 This is a schematic diagram of the structure after forming a bonding layer on the barrier layer, provided by an embodiment of the present invention;

[0043] Figure 7 This is a schematic diagram of the structure after forming a bonding layer on a bonding substrate, provided by an embodiment of the present invention;

[0044] Figure 8 This is a schematic diagram of the structure of an epitaxial wafer with a bonding layer prepared and a bonding substrate bonded according to an embodiment of the present invention;

[0045] Figure 9 This is a schematic diagram of the structure after removing the sapphire substrate, provided in an embodiment of the present invention;

[0046] Figure 10 This is a schematic diagram of the structure of an epitaxial layer after forming a preset tilt angle and a preset length difference, provided by an embodiment of the present invention;

[0047] Figure 11 This is a schematic diagram of the structure after depositing a PV layer according to an embodiment of the present invention;

[0048] Figure 12 This is a schematic diagram of the structure after forming a patterned PV layer, provided by an embodiment of the present invention;

[0049] Figure 13 A schematic diagram of a structure in which an N-electrode completely covers a PV layer located on the entire sidewall of an epitaxial layer structure, as provided in an embodiment of the present invention;

[0050] Figure 14 A schematic diagram of a structure in which an N-electrode portion covers a PV layer located on the entire sidewall of an epitaxial layer structure, provided for an embodiment of the present invention;

[0051] Figure 15 This is a schematic diagram of the structure of an LED chip provided in an embodiment of the present invention.

[0052] Among them, sapphire substrate 1, N-GaN layer 2, MQWs layer 3, P-GaN layer 4, CB pattern 5, mirror 6, barrier layer 7, bonding layer 8, bonding substrate 9, PV layer 10, and N electrode 11. Detailed Implementation

[0053] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0054] In this application, the terms "comprising," "including," or any other variations thereof are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0055] For LED chips, especially vertical structure chips, the light emission angle is generally determined by light distribution during the packaging process to obtain the required LED chip emission angle. However, the light distribution curve of vertical structure LED chips conforms to the Lambertian distribution, and the light emission angle is generally between 110° and 140°, which is difficult to meet the small-angle LED chips required by some specific application areas. At the same time, performing light distribution during the packaging process increases the workload and difficulty of packaging.

[0056] To address the aforementioned problems, this invention provides an LED chip and its fabrication method, which adjusts the light emission angle of the LED chip during the LED chip manufacturing process to obtain the desired light emission angle.

[0057] like Figure 1 The diagram shows a flowchart of a method for fabricating an LED chip according to an embodiment of the present invention. The method includes:

[0058] S11: Provide an epitaxial wafer.

[0059] In S11, the epitaxial wafer includes a substrate, an N-type functional layer, a light-emitting layer, and a P-type functional layer. The N-type functional layer may include an N-GaN layer, the light-emitting layer may include an MQWs layer, and the P-type functional layer may include a P-GaN layer.

[0060] like Figure 2 The diagram shown is a schematic diagram of an epitaxial wafer provided in an embodiment of the present invention. The epitaxial wafer includes, from bottom to top, a sapphire substrate 1, an N-GaN layer 2, an MQWs layer 3, and a P-GaN layer 4.

[0061] S12: A charge-balanced CB layer is deposited on the surface of the epitaxial wafer and patterned to obtain a patterned CB pattern and a partially exposed P-GaN layer.

[0062] In the specific execution of S12, a charge-balanced CB layer is first deposited on the surface of the epitaxial wafer. Then, after performing processes such as uniform negative coating, exposure and development, the charge-balanced CB layer is patterned using BOE solution to obtain a patterned CB pattern and a bare P-GaN layer.

[0063] In one embodiment of the present invention, forming a charge balance CB layer on the surface of an epitaxial wafer specifically includes: depositing a charge balance CB layer with a thickness of 1000Å to 8000Å on the surface of the epitaxial wafer using N2O with a gas ratio of 400 to 1400 and 5% SiH4 / N2 with a gas ratio of 200 to 1800 at a preset power of 20W to 120W.

[0064] like Figure 3 The diagram shown is a schematic representation of the structure after forming a patterned CB pattern and an exposed portion of the P-GaN layer, according to an embodiment of the present invention. Figure 3 It can be seen that the patterned CB pattern 5 is located at both ends of the epitaxial wafer. Specifically, the patterned CB pattern 5 is located on the P-GaN layer 4 and at both ends of the P-GaN layer 4, and the exposed part of the P-GaN layer 4 is located between the patterned CB patterns 5.

[0065] It should be noted that the specific shape of the graphical CB pattern 5 and its specific location on the P-GaN layer 4 are not limited to... Figure 3 As shown, those skilled in the art can make corresponding adjustments according to actual needs.

[0066] S13: Fabricate a mirror on the exposed P-GaN layer.

[0067] In the specific execution of S13, a highly reflective metal structure is fabricated on the exposed P-GaN layer to form a reflector.

[0068] In one embodiment of the present invention, forming a reflector specifically includes forming a reflector on a bare portion of the P-GaN layer by means of sputtering or evaporation.

[0069] The mirror comprises one or more layers of metal structures with high reflectivity, such as ITO, Ni, Ag, Rh, Au, Ti, Cr, Pt, Mg, and Al.

[0070] That is, the reflector comprises a metal structure consisting of one or more of the following materials with high reflectivity: ITO, Ni, Ag, Rh, Au, Ti, Cr, Pt, Mg, and Al. The metal structure may be one or more layers.

[0071] like Figure 4 The diagram shown is a schematic representation of the structure after forming a reflector according to an embodiment of the present invention. Figure 4 It is known that the reflector 6 covers the exposed portion of the P-GaN layer 4, and the thickness of the reflector 6 can be the same as the thickness of the patterned CB pattern 5.

[0072] S14: Form a barrier layer, which covers the graphic CB pattern and the reflector.

[0073] During the specific execution of S14, a blocking layer is formed on both the graphic CB pattern and the reflector, so that the blocking layer covers the graphic CB pattern and the reflector.

[0074] In one embodiment of the present invention, forming the barrier layer specifically includes forming the barrier layer on the patterned CB pattern and the reflector by means of sputtering or vapor deposition.

[0075] The barrier layer includes, but is not limited to, one or more metals selected from Ti, Ni, Pt, TiW, and Au.

[0076] like Figure 5 The diagram shown is a schematic representation of the structure after forming a barrier layer according to an embodiment of the present invention. Figure 5 It can be seen that the blocking layer 7 covers the reflector 6 and the graphic CB pattern 5.

[0077] S15: Prepare a bonding layer on the barrier layer and the provided bonding substrate.

[0078] In the specific execution of S15, bonding metals are prepared on the barrier layer and the provided bonding substrate respectively to form a bonding layer.

[0079] In one embodiment of the present invention, the preparation of the bonding layer specifically includes: simultaneously depositing bonding metals on the barrier layer and the provided bonding substrate to form the bonding layer.

[0080] The bonding metals include, but are not limited to, Au, In, or Ni, Sn, or Sn and Au.

[0081] like Figure 6 The diagram shown is a schematic representation of a structure formed on a barrier layer according to an embodiment of the present invention. The bonding layer 8 covers the barrier layer 7. The thickness of the bonding layer 8 can be selected according to actual bonding requirements.

[0082] like Figure 7 The diagram shown is a schematic representation of a structure formed on a bonding substrate according to an embodiment of the present invention. The bonding layer 8 covers the bonding substrate 9. Figure 7 The thickness of the intermediate bonding layer 8 can be the same as Figure 6The bonding layers 8 in the middle can have the same thickness, or they can have different thicknesses.

[0083] S16: Bond the epitaxial wafer with the bonding layer prepared to the bonding substrate, and remove the sapphire substrate.

[0084] In the specific execution of S16, the epitaxial wafer with the bonding layer prepared is first bonded to the bonding substrate.

[0085] like Figure 8 The diagram shown is a schematic representation of the structure of an epitaxial wafer with a bonding layer fabricated and a bonding substrate according to an embodiment of the present invention. Bonding is performed between the bonding layer 8 on the epitaxial wafer and the bonding layer 8 on the bonding substrate 9. After bonding, the sapphire substrate 1 is removed using methods such as laser lift-off or chemical etching to expose the N-GaN layer 2.

[0086] like Figure 9 The diagram shown is a schematic representation of the structure after removing the sapphire substrate according to an embodiment of the present invention. After removing the sapphire substrate, the N-GaN layer 2 is exposed and used as the upper layer.

[0087] S17: Etching removes the epitaxial wafer from the sapphire substrate to form an epitaxial layer structure that meets the light distribution requirements.

[0088] In the specific execution of S17, the epitaxial wafer with the sapphire substrate removed is deeply etched (DE etching) through processes such as spin coating, exposure and development to form an epitaxial layer structure that meets the light distribution requirements.

[0089] The edge of the epitaxial layer structure is a sidewall with a preset tilt angle.

[0090] In one embodiment of the present invention, forming an epitaxial layer structure that meets the light distribution requirements specifically includes: performing DE etching on an epitaxial wafer with the sapphire substrate removed, with an N-GaN layer as the upper layer, forming sidewalls on both sides of the epitaxial wafer with the sapphire substrate removed, and exposing a portion of the CB pattern along the sidewall edges, so that a preset tilt angle is formed between the sidewall and the CB pattern, and a preset length difference is formed between the N-GaN layer constituting the sidewall and the P-GaN layer, thereby forming an epitaxial layer structure with a preset tilt angle and a preset length difference.

[0091] The preset tilt angle between the sidewall of the epitaxial layer structure and the CB pattern, as well as the preset length difference between the N-GaN layer and the P-GaN layer, can be selected according to the required emission angle, thereby obtaining an LED chip with a specific emission angle.

[0092] In other words, the tilt angle between the sidewalls of the epitaxial layer structure and the CB pattern, as well as the length difference between the N-GaN layer and the P-GaN layer that make up the sidewalls, can be adjusted according to the required light emission angle, so that the LED chip with the epitaxial layer structure having a specific tilt angle and a specific length difference has the required light emission angle.

[0093] like Figure 10 The diagram shown is a schematic representation of an epitaxial layer structure with a preset tilt angle and a preset length difference, according to an embodiment of the present invention. Figure 10 It can be seen that the sidewalls of the epitaxial layer structure are composed of the sidewalls of N-GaN layer 2, MQWs layer 3 and P-GaN layer 4. The angle α formed between the sidewalls of the epitaxial layer structure and the CB pattern 5 is a preset tilt angle, and the length difference L formed between the N-GaN layer 2 and the P-GaN layer 4 that constitute the sidewalls is a preset length difference.

[0094] S18: Deposit an insulating PV layer to cover the surface of the epitaxial layer structure, and pattern the PV layer to expose part of the N-GaN layer.

[0095] In the specific execution of S18, an insulating PV layer is first deposited on the sidewalls of the epitaxial layer structure, the upper surface of the epitaxial layer structure, and the exposed CB pattern, so that the PV layer covers the surface of the epitaxial layer structure.

[0096] like Figure 11 This is a schematic diagram of the structure after depositing a PV layer, provided in an embodiment of the present invention. Figure 11 It can be seen that the PV layer 10 is deposited on the sidewall of the epitaxial layer structure with a preset tilt angle, which is composed of the sidewalls of the N-GaN layer 2, the MQWs layer 3 and the P-GaN layer 4. It is also deposited on the upper surface of the N-GaN layer 2 and the exposed CB pattern 5.

[0097] After the PV layer 10 is deposited, wet etching or dry etching is performed on the PV layer 10 through processes such as spin coating, exposure and development to pattern the PV layer 10 and expose part of the N-GaN layer 2.

[0098] like Figure 12 The diagram shown is a schematic representation of the structure after forming a patterned PV layer according to an embodiment of the present invention. Figure 12 It can be seen that after the PV layer 10 is patterned, part of the N-GaN layer 2 is exposed.

[0099] In practical applications, N-GaN layers at different locations and / or with different areas can be exposed as needed.

[0100] In one embodiment of the present invention, depositing an insulating PV layer 10 and patterning the PV layer 10 to expose a portion of the N-GaN layer 2 includes: first, depositing an insulating material such as SiO2, SiN, ZnO, Al2O3, TiO2, or ZrO2 on the surface of the epitaxial layer structure to form a PV layer 10 covering the surface of the epitaxial layer structure; then, patterning the PV layer 10 using wet etching or dry etching to expose a portion of the N-GaN layer 2.

[0101] The PV layer 10 formed on the surface of the epitaxial layer structure can be used to protect the sidewalls of the LED chip.

[0102] S19: Fabricate N electrodes on the PV layer and the exposed portion of the N-GaN layer.

[0103] In S19, the N electrode includes, but is not limited to, a stacked structure composed of one or more metals selected from Ni, Al, Ti, Pt, Au, Sn, Ag, Mg, Zn, and Cr.

[0104] In the specific execution of S19, N electrodes are prepared on the PV layer and the exposed part of the N-GaN layer through processes such as spin coating, exposure and development, and the N electrodes are completely or partially covered on the PV layer located on the entire sidewall of the epitaxial layer structure.

[0105] It should be noted that since the N electrode is completely or partially covered on the PV layer that is located on the entire sidewall of the epitaxial layer structure, an additional layer of metal is added to protect the LED chip, thereby improving the LED chip's resistance to moisture and external conditions. At the same time, the complete or partial coverage of the N electrode on the PV layer that is located on the entire sidewall of the epitaxial layer structure gives the LED chip a larger metal area, which can achieve faster heat conduction, thereby improving the reliability of the LED chip.

[0106] In other words, completely or partially covering the N electrode on the PV layer, which is located on the entire sidewall of the epitaxial layer structure, can increase the protection and thermal conductivity of the LED chip and prevent problems such as salt spray and water vapor erosion during the aging test and the reverse pressure process.

[0107] In one embodiment of the present invention, the preparation of an N electrode on the PV layer and the exposed portion of the N-GaN layer specifically includes: preparing a highly reflective metal electrode on the exposed portion of the N-GaN layer to form an N electrode, and ensuring that the prepared N electrode completely or partially covers the PV layer located on the entire sidewall of the epitaxial layer structure.

[0108] like Figure 13The diagram shows a structure provided by an embodiment of the present invention in which an N-electrode completely covers a PV layer located on the entire sidewall of an epitaxial layer structure. The N-electrode 11 covers the exposed portion of the N-GaN layer 2 and also completely covers the PV layer 10 located on the entire sidewall of the epitaxial layer structure.

[0109] like Figure 14 The diagram illustrates a structure provided by an embodiment of the present invention, in which an N-electrode partially covers a PV layer located on the entire sidewall of an epitaxial layer structure. The N-electrode 11 covers a portion of the exposed N-GaN layer 2 and also partially covers the PV layer 10 located on the entire sidewall of the epitaxial layer structure, thus exposing a portion of the PV layer 10 on the sidewall of the epitaxial layer structure.

[0110] Specifically, in Figure 14 In the middle, the N electrode 11 is not covered on the corresponding PV layer 10 with a length of D in a specific direction.

[0111] That is, combination Figure 13 and Figure 14 It can be seen that the N electrode 11 can completely cover the PV layer 10 located on the entire sidewall of the epitaxial layer structure, or it can partially cover any area of ​​the PV layer 10 located on the entire sidewall of the epitaxial layer structure. The specific covered area is different, and the emission angle is different.

[0112] Specifically, when the N electrode 11 completely covers the PV layer 10 located on the entire sidewall of the epitaxial layer structure, an LED chip with a small emission angle can be fabricated. When the N electrode 11 partially covers different areas of the PV layer 10 located on the entire sidewall of the epitaxial layer structure, an LED chip with an adjustable emission angle can be fabricated.

[0113] In this embodiment of the invention, during the fabrication process, by setting the edge of the epitaxial layer structure as a sidewall with a preset tilt angle, the desired light emission angle can be obtained, thereby achieving adjustment of the light emission angle during the manufacturing process; at the same time, the N electrode completely or partially covers the PV layer located on the entire sidewall of the epitaxial layer structure, making the sidewall have an additional layer of metal, enhancing the protection and heat conduction capabilities of the LED chip, thereby improving the reliability of the LED chip.

[0114] Based on the LED chip fabrication method provided in the above embodiments of the present invention, in addition to setting the edge of the epitaxial layer structure as a sidewall with a preset tilt angle to achieve adjustment of the light emission angle during the manufacturing process, in one embodiment of the present invention, the N electrode covering the sidewall can also be connected or disconnected by exposure to adjust the light emission angle of the LED chip.

[0115] Specifically, when the N electrode covering the sidewall is connected, the light emission angle of the LED chip is relatively small; when the N electrode covering the sidewall is disconnected, the light emission angle of the LED chip can be adjusted.

[0116] In this embodiment of the invention, the connection or disconnection of the N electrode is controlled by exposure, thereby adjusting the light emission angle of the LED chip. At the same time, extending the N electrode to the sidewall provides secondary protection for the LED chip, enhancing its heat dissipation and corrosion resistance.

[0117] Based on the LED chip fabrication method provided in the above embodiments of the present invention, the present invention also provides an LED chip, such as... Figure 15 As shown, the LED chip is fabricated according to the LED chip fabrication method provided in the above embodiments of the present invention. During the fabrication process, an epitaxial layer structure that meets the light distribution requirements is formed in the LED chip. The edges of the epitaxial layer structure are sidewalls with a predetermined tilt angle.

[0118] The epitaxial layer structure includes an N-GaN layer 2, an MQWs layer 3, a P-GaN layer 4, a patterned CB pattern 5, a mirror 6, a barrier layer 7, a bonding layer 8, and a bonding substrate 9.

[0119] The bonding layer 8 is located on the bonding substrate 9. The bonding layer 8 is formed of a bonding metal, which includes Au, In or Ni, Sn or Sn and Au.

[0120] The barrier layer 7 is located on the bonding layer 8, and the barrier layer 7 includes one or more metals such as Ti, Ni, Pt, TiW, and Au.

[0121] The patterned CB pattern 5 is located at both ends of the barrier layer 7 and is formed by N2O and SiH4 / N2 gas.

[0122] The reflector 6 is located on the barrier layer 7 and between the patterned CB patterns 5. The reflector 6 includes one or more metal structures with high reflectivity, such as ITO, Ni, Ag, Rh, Au, Ti, Cr, Pt, Mg, and Al.

[0123] P-GaN layer 4 is located on mirror 6 and patterned partial CB pattern 5.

[0124] MQWs layer 3 is located on P-GaN layer 4.

[0125] The N-GaN layer 2 is located on the MQWs layer 3.

[0126] Furthermore, the surface of the epitaxial layer structure that meets the light distribution requirements has a patterned PV layer 10, which exposes a portion of the N-GaN layer 2.

[0127] The patterned PV layer 10 is composed of insulating materials such as SiO2, SiN, ZnO, Al2O3, TiO2, or ZrO2.

[0128] Furthermore, the patterned PV layer 10 and the exposed portion of the N-GaN layer 2 have N electrodes 11, which are made of a highly reflective metallic material.

[0129] It should be noted that the N electrode 11 can completely cover the PV layer 10 located on the entire sidewall of the epitaxial layer structure, or it can partially cover any region of the PV layer 10 located on the entire sidewall of the epitaxial layer structure.

[0130] Figure 15 Only one configuration is shown, where the N-electrode 11 partially covers the PV layer 10 located on the entire sidewall of the epitaxial layer structure. Specifically, in Figure 15 In the middle, the N electrode 11 is not covered on the corresponding PV layer 10 with lengths D1 and D2 in a specific direction.

[0131] In practical applications, the area of ​​the N electrode 11 covering the PV layer 10 can be adjusted according to the required emission angle, and is not limited to... Figure 15 As shown in the diagram.

[0132] In one embodiment of the present invention, during the fabrication process, the N electrode covering the sidewall can be connected or disconnected by exposure to adjust the light emission angle of the LED chip.

[0133] In one embodiment of the present invention, the LED chip is a vertically structured LED chip.

[0134] In this embodiment of the invention, during the manufacturing process, by setting the edge of the epitaxial layer structure as a sidewall with a preset tilt angle, the required light emission angle can be obtained, thereby realizing the adjustment of the light emission angle during the manufacturing process; at the same time, the N electrode completely or partially covers the PV layer located on the entire sidewall of the epitaxial layer structure, so that the sidewall has an additional layer of metal, which enhances the protection and heat conduction capabilities of the LED chip, thereby improving the reliability of the LED chip.

[0135] It should be noted that, in the description of this application, the terms "upper," "lower," "top," "bottom," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, and are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this application. When a component is considered to be "connected" to another component, it can be directly connected to the other component or there may be a component centrally located at the same time.

[0136] It should also be noted that, in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that an article or apparatus comprising a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such an article or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the article or apparatus that includes the aforementioned element.

[0137] The above description of the disclosed embodiments enables those skilled in the art to make or use this application. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of this application. Therefore, this application is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A method for fabricating an LED chip, characterized in that, The preparation method includes: An epitaxial wafer is provided, the epitaxial wafer comprising a sapphire substrate, an N-GaN layer, an MQWs layer, and a P-GaN layer; A charge-balanced CB layer is deposited on the surface of the epitaxial wafer and patterned to obtain a patterned CB pattern and a partially exposed P-GaN layer. A mirror is fabricated on the exposed portion of the P-GaN layer; A barrier layer is formed to cover the patterned CB pattern and the reflector; A bonding layer is prepared on the barrier layer and the provided bonding substrate; The epitaxial wafer with the bonding layer prepared is bonded to the bonding substrate, and then the sapphire substrate is removed. The epitaxial wafer of the sapphire substrate is etched away to form an epitaxial layer structure that meets the light distribution requirements. The edge of the epitaxial layer structure is a sidewall with a preset tilt angle. An insulating PV layer is deposited to cover the surface of the epitaxial layer structure, and the PV layer is patterned to expose part of the N-GaN layer. N electrodes are fabricated on the PV layer and the exposed portion of the N-GaN layer.

2. The method according to claim 1, characterized in that, A charge-balanced CB layer is deposited on the surface of the epitaxial wafer, comprising: At a preset power of 20W to 120W, a charge-balanced CB layer with a thickness of 1000A to 8000A is deposited on the surface of the epitaxial wafer using N2O with a gas ratio of 400 to 1400 and 5% SiH4 / N2 with a gas ratio of 200 to 1800.

3. The method according to claim 1, characterized in that, Fabricating a mirror on the exposed portion of the P-GaN layer includes: A reflector is formed on the exposed P-GaN layer by sputtering or evaporation. The reflector comprises one or more metal structures of ITO, Ni, Ag, Rh, Au, Ti, Cr, Pt, Mg, and Al with high reflectivity. The patterned CB pattern is located at both ends of the epitaxial wafer, and the exposed P-GaN layer is located between the patterned CB pattern.

4. The method according to claim 1, characterized in that, Forming a barrier layer, including: A barrier layer is formed on the patterned CB pattern and the mirror by sputtering or vapor deposition. The barrier layer includes one or more metals such as Ti, Ni, Pt, TiW, and Au. Accordingly, a bonding layer is prepared on the barrier layer and the provided bonding substrate, including: A bonding layer is formed by simultaneously depositing a bonding metal on the barrier layer and the provided bonding substrate. The bonding metal includes Au, In, or Ni, or Sn or Sn and Au.

5. The method according to any one of claims 1 to 4, characterized in that, Etching removes the epitaxial wafer from the sapphire substrate to form an epitaxial layer structure that meets light distribution requirements, including: On the epitaxial wafer with the sapphire substrate removed, DE etching is performed with the N-GaN layer as the upper layer. Sidewalls are formed on both sides of the epitaxial wafer with the sapphire substrate removed, and part of the CB pattern is exposed along the edge of the sidewalls. A preset tilt angle is formed between the sidewalls and the CB pattern, and a preset length difference is formed between the N-GaN layer constituting the sidewalls and the P-GaN layer, forming an epitaxial layer structure with a preset tilt angle and a preset length difference.

6. The method according to any one of claims 1 to 4, characterized in that, Depositing an insulating PV layer to cover the surface of the epitaxial layer structure, and patterning the PV layer to expose a portion of the N-GaN layer, including: An insulating material, such as SiO2, SiN, ZnO, Al2O3, TiO2, or ZrO2, is deposited on the surface of the epitaxial layer structure to form a PV layer covering the surface of the epitaxial layer structure. The PV layer is patterned using wet etching or dry etching to expose part of the N-GaN layer.

7. The method according to any one of claims 1 to 4, characterized in that, Fabricating an N-electrode on the PV layer and the exposed portion of the N-GaN layer includes: A highly reflective metal electrode is fabricated on the exposed N-GaN layer to form an N electrode, and the fabricated N electrode is completely or partially covered on the PV layer located on the entire sidewall of the epitaxial layer structure.

8. The method according to any one of claims 1 to 4, characterized in that, Also includes: The light emission angle of the LED chip is adjusted by connecting or disconnecting the N electrode covering the sidewall through exposure.

9. An LED chip, characterized in that, The LED chip is prepared according to the method of LED chip preparation according to any one of claims 1 to 8, wherein the LED chip forms an epitaxial layer structure that meets the light distribution requirements during the preparation process.

10. The LED chip according to claim 9, characterized in that, The LED chip is a vertically structured LED chip.

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