An integrated half-bridge drive module

Abstract

The application discloses an integrated half-bridge driving module, which comprises a driving circuit, two output ends of the driving circuit are connected to the gate of a high-side power tube and the gate of a low-side power tube respectively, and the gate of the high-side power tube and the gate of the low-side power tube are charged and discharged to realize the opening and closing functions of the gate of the high-side power tube and the gate of the low-side power tube. The application omits a high-voltage level shifting circuit, integrates two circuit modules of high-side and low-side driving circuits into one circuit module, so that the driving circuit can generate two kinds of gate signals meeting the requirements of the high-side and low-side power tubes, and the high-side control signal does not need to be level shifted and the driving circuit with a multi-stage inverter structure is omitted.

Description

Technical Field

[0001] The present invention belongs to the technical field of power integration and motor drive circuits, and particularly relates to an integrated half-bridge drive module. Background Art

[0002] Intelligent power integrated circuit is a new type of integrated circuit that integrates power device, control circuit, drive circuit, protection circuit, sensor and other modules. Power driver is a typical intelligent power integrated circuit.

[0003] Existing Full-NMOS circuit structure (such as Figure 1 As shown), in this circuit, the conduction of the high and low side power tubes depends on the gate signal. When the gate-source voltage V GS >Threshold voltage V THN , the power tube is turned on. For this circuit, the low-side power tube M N2 The gate signal V GL Need to meet V GL >V THN In this circuit structure, the V GL The voltage level requirement is around 0-5V; the high-side power tube M N1 The gate signal V GH Need to meet V GH >V THN , because the VDD level of this circuit is high, V GH The voltage level must be between VDD and (VDD+5V). Therefore, the signal output by the high-side driver circuit needs to be processed before it can drive the M N1 Tube.

[0004] Existing multi-stage inverter cascade push-pull drive circuit (such as Figure 2 As shown in the figure, due to the large size of high-side and low-side power tubes, multiple inverter cascades are required to improve the output current driving capability.

[0005] The existing multi-stage inverter cascade push-pull structure driving circuit structure. Figure 3 As shown in the figure, the high-side and low-side drive circuits are both multi-stage inverter cascade push-pull drive circuits. The oscillator circuit provides a fixed-frequency waveform for the charge pump circuit to ensure the normal operation of the charge pump circuit. VSW~VBOOT corresponds to VDD~(VDD+5V), V GH Input high-side gate control signal to the outside world, V GL Input low-side gate control signal to the outside world. N1 A high-voltage level shift circuit is designed on the front side of the drive circuit to convert the 0-5V voltage signal generated by the inverter into a voltage signal of VDD~(VDD+5V) and input it into the high-side power tube M. N1 Gate, to ensure the high side power tube MN1 normal operation. The problem of high voltage required for the gate of the high-side power transistor M N1 is effectively solved, but because the size of the power transistor of the H-bridge is large, a large charging and discharging current is required for the gate of the power transistor, which requires a large current driving capability of the high-side and low-side driving circuits, resulting in an increase in the size and number of inverters of the driving circuit, and in order to meet the signal output of VDD~(VDD+5V) of the high-side driving circuit, a high-voltage level shifting circuit needs to be added in the high-side driving circuit. SUMMARY

[0006] In order to overcome the problems existing in the prior art, the purpose of the present application is to provide an integrated half-bridge driving module, which eliminates the high-voltage level shifting circuit, integrates the high-side and low-side driving circuits into one circuit module, so that the driving circuit can generate two kinds of gate signals required by the high-side and low-side power transistors, without the need for level shifting of the high-side control signal and the driving circuit of the multi-stage inverter structure.

[0007] In order to achieve the above purpose, the technical scheme adopted by the present application is:

[0008] An integrated half-bridge driving module, comprising a driving circuit, two output ends of the driving circuit being connected to the gates of the high-side power transistor M N1 and the low-side power transistor M N2 respectively, the gates of the high-side power transistor M N1 and the low-side power transistor M N2 being charged and discharged to realize the on and off functions of the gates of the high-side power transistor M N1 and the low-side power transistor M N2 ;

[0009] The high-side power transistor M N1 and the low-side power transistor M N2 form a half-bridge structure and are integrated together with the driving circuit to form an integrated half-bridge driving circuit;

[0010] The driving circuit comprises a high-side power transistor driving module and a low-side power transistor driving module, wherein the output of the high-side driving module is connected to the gate of the high-side power transistor M N1 , and the output of the low-side driving module is connected to the gate of the low-side power transistor M N2 . The input end of the driving circuit is connected to a charge pump circuit, which is responsible for providing a power voltage to the entire driving circuit;

[0011] The normal operation of the charge pump circuit requires a fixed frequency square wave signal, so an oscillator circuit is required to generate a square wave signal, which is responsible for providing the working frequency of the charge pump.

[0012] The front-end circuit of the driving circuit, i.e. other circuits except the driving module, i.e. the output ends of which need to be connected to the input ends of the driving module, is called front-end because it needs to be connected to the input ends of the driving module, and the front-end circuit provides the prerequisite for the normal operation of the driving module. The front-end circuit in the application includes a charge

[0013] The front-end of the driving circuit (i.e. the input end of the driving circuit) is connected with a 5V input and a current bias IBIAS. The 5V input is responsible for providing a power input for the low-side driving circuit, and the current bias IBIAS is responsible for providing a stable bias current for the high-side driving module to ensure the normal operation of the high-side driving circuit. The 5V input is VREF, the power input is VBB, and the current bias IBIAS is responsible for providing a certain current input for the driving circuit to meet the prerequisite for the normal operation of the driving circuit.

[0014] The driving circuit includes an inverter INV1 and an inverter INV2, which generate two clock signals with a phase difference of 180 degrees. The inverter INV1 is connected to the gate of NLD2, and the inverter INV2 is connected to the gate of NLD1. NLD1 is connected to the pull-down resistor R1, and NLD2 is connected to the pull-down resistor R2. The control of the opening and closing of the pull-down resistor branch is realized through the control of the clock signal.

[0015] The high-side power tube M N1 The charging circuit is composed of PLD4 and SPLD. The drain end of PLD4 is connected to the source end of SPLD, and the source end of SPLD is connected to the gate end of the high-side power tube. There are two groups of discharge channels. The first group is composed of PLD5, PLD6 and NLD5. The drain end of PLD5 is connected to the source end of PLD6, and the drain end of PLD6 is connected to the gate end of NLD5. The second group is composed of NLD4. The gate end of NLD4 is connected to the drain end, and is also connected to the gate end of the low-side power tube M N2

[0016] The lower end of the pull-down resistor R1 is connected to the gate of SPLD, and the lower end of the pull-down resistor R2 is connected to the gate of PLD6. Whether the charging circuit and the discharge channel are turned on or not is determined by the pull-down resistor branch.

[0017] The charging and discharging circuit of the low-side power tube M N2 includes an inverter INV3 and a Class AB amplifier. The Class AB amplifier includes a large-size transistor MP1 and a large-size transistor MN4. The inverter INV3 is in front, and the Class AB amplifier is behind. The inverter INV3 and the Class AB amplifier are connected in series, and the output position is connected to the gate end of the low-side power tube M N2

[0018] ​​The gate end of the large-size transistor MP1 is connected with the gate end of the large-size transistor MN4, the drain end is connected, the source end of the large-size transistor MP1 is connected with VREF, the source end of the large-size transistor MN4 is connected with the ground, the output of the inverter INV3 is connected with the gate end of the large-size transistor MP1 and the large-size transistor MN4, and the drain end of the large-size transistor MP1 and the large-size transistor MN4 is used as the output position of the structure connected with the inverter INV3 and the Class AB amplifier.

[0019] The bottom layer of the driving circuit is provided with a current mirror structure for providing a determined working current for the upper power device and the pull-down resistance branch, so as to ensure the normal working state of the driving circuit; the current mirror structure comprises current mirror structures MN1, MN2, MN3 and MN5; the gate end and the drain end of the current mirror structure MN1 are connected, the gate ends of the current mirror structures MN2, MN3 and MN5 are connected with the gate end of the current mirror structure MN1, and the source ends of the current mirror structures MN1, MN2, MN3 and MN5 are connected with the ground; the current mirror structure MN1 is used as the input of the current mirror at the front end of the current mirror structure, and the current mirror structures MN2, MN3 and MN5 are used as the load of the current mirror and are located behind the current mirror structure MN1.

[0020] The opening and closing function of the PLD5 is controlled by the current mirror structure composed of the PLD3 and the PLD4, and the PLD3 mirrors the current of the current mirror structure MN5 to the branch where the PLD4 is located.

[0021] The beneficial effects of the present application are as follows:

[0022] The present application uses the principle of current mirror, and uses low-voltage devices to provide fixed current bias for high-voltage devices. The power tube gate charging and discharging circuit is designed in the form of transistor switch, and the pull-down resistance is used as the judgment condition of the opening and closing of the switch, so that the high-side and low-side driving are integrated together and the gate discharging channel is formed.

[0023] The present application integrates the high-side and low-side driving, eliminates the design of high-voltage level shift module, applies the design of BCD process, and reduces the load of charge pump. BRIEF DESCRIPTION OF DRAWINGS

[0024] Figure 1 It is a schematic diagram of the prior art Full-NMOS circuit structure.

[0025] Figure 2 It is a schematic diagram of the prior art multi-stage inverter cascade push-pull driving circuit.

[0026] Figure 3The application discloses a driving circuit structure topology of a multi-stage inverter cascade push-pull type structure.

[0027] Figure 4 The application discloses a driving circuit structure topology.

[0028] Figure 5 The application discloses a specific circuit diagram of the driving circuit.

[0029] Figure 6 The application discloses a driving circuit structure topology. DETAILED DESCRIPTION

[0030] The application will be further described in detail below with reference to the drawings and embodiments.

[0031] The application adopts a BCD process and further improves the circuit by using the characteristics of an LDMOS device. The BCD process is a kind of existing monolithic integrated process technology. The technology can manufacture Bipolar, CMOS and DMOS devices on the same chip. The application is based on an existing BCD manufacturing process library and uses the circuit designed by the devices in the process library.

[0032] The application integrates the high-side driving circuit and the low-side driving circuit, so that the control signals can be simultaneously input into the same circuit, without the need of level shifting processing, thereby saving Figure 3 a middle-high voltage level shifting circuit and simplifying the design process.

[0033] Figure 4 The application discloses a half-bridge structure topology, wherein two output ends of the driving circuit are connected to the gate of the high-side power tube and the low-side power tube respectively, the on and off functions of the power tube are realized by charging and discharging of the gate of the power tube; the oscillator circuit is connected to the front end of the charge pump and is responsible for providing the working frequency for the charge pump, so that the charge pump can normally generate a (VDD+5V) signal; the charge pump circuit is connected to the front end of the driving circuit and is responsible for providing the power supply voltage for the whole driving circuit; and the 5V input and the current bias are connected to the front end of the driving circuit, the 5V input is responsible for providing the low-voltage power supply input for the low-voltage module in the driving circuit, and the current bias is responsible for providing the determined current input for the driving circuit, so as to meet the prerequisite for the normal working of the driving circuit.

[0034] Figure 5 The application discloses a specific circuit design diagram of the middle driving circuit. Figure 4 Figure 5 ​In the figure, VBB is a power input, VCP is a (VDD+5V) signal output by a charge pump, VREF is a 5V signal output by a reference voltage, IBIAS is a fixed current bias, which can be understood as a current source, IN1 and IN2 are external control signal inputs, PLD1, PLD2, PLD3, PLD4, PLD5 and PLD6 are LPDMOS devices, NLD1, NLD2, NLD3 and NLD4 are LNDMOS devices, MN1, MN2 and MN3 are NMOS devices, SPLD is a P-type switch tube, R1 and R2 are pull-down resistors, INV1, INV2 and INV3 are single-stage inverters, MP1 and MN4 are large-size transistors, which together form a Class AB amplifier structure, the purpose of which is to increase current driving capability, and MN1, MN2, MN3 and MN5 form a current mirror structure. N1 N2 M N1 is a high-side power tube, and M N2 is a low-side power tube.

[0035] Figure 5 The connection relationship in the figure is shown as follows: INV1 and INV2 are two inverters, which generate two clock signals with a phase difference of 180 degrees, the two-phase clock signals are connected to the gates of NLD1 and NLD2 respectively, NLD1 is connected to pull-down resistor R1, NLD2 is connected to pull-down resistor R2, and the opening and closing of the pull-down resistor branch is controlled by the clock signals. The charging circuit of the high-side power tube is composed of PLD4 and SPLD, and the discharging channel has two groups, the first group is composed of PLD5, PLD6 and NLD5, and the second group is composed of NLD4, since the lower end of pull-down resistor R1 is connected to the gate of SPLD, and the lower end of pull-down resistor R2 is connected to the gate of PLD6, whether they are turned on or not is determined by the pull-down resistor branch. The charging and discharging circuit of the low-side power tube is composed of a Class AB amplifier structure composed of INV3, large-size transistor MP1 and large-size transistor MN4. MN1, MN2, MN3 and MN5 form a current mirror structure, which provides a certain working current for the upper power device and the pull-down resistor branch at the bottom layer of the circuit, and ensures the normal working state of the driving circuit; at the same time, PLD3 and PLD4 form a current mirror structure, PLD3 mirrors the current of MN5 to MN1 again to the branch where PLD4 is located, and realizes the function of controlling the opening and closing of PLD5.

[0036] The application uses the pull-down resistor mode to make a 5V voltage difference between the two ends of the resistor in the branch of the fixed current bias IBIAS, so as to open the charging circuit of the gate of the driving power tube; the switching of the charging and discharging process of the control power tube is controlled by using the transistor switch idea, and the complexity of the system design is reduced.

[0037] ​As Figure 6 shown, the driving circuit includes a high-side power tube driving module and a low-side power tube driving module, wherein the output of the high-side driving module is connected to the gate of the high-side power tube M N1 , and the output of the low-side driving module is connected to the gate of the low-side power tube M N2 .

[0038] Working principle of the present application:

[0039] When the high-side on signal arrives, the low-side on signal does not arrive, the pull-down resistor R1 pulls down the voltage of about 5V, and the PLD1 and PLD2 ensure that the potential difference between the two ends of the pull-down resistor R2 is 0. At this time, the SPLD switch tube is opened, the NLD4 is closed, the PLD4 and PLD3 are current mirror structures, the PLD3, PLD4 and SPLD together constitute a high-side power tube charging branch, and only the high-side power tube gate is charged. At this time, since the gate charging and discharging current is small and the duration is short, it can be ensured that the gate of the high-side power tube is 5V higher than the power supply voltage;

[0040] When the low-side on signal arrives, the high-side on signal is closed, the pull-down resistor R2 pulls down the voltage of about 5V, and the low-side power tube M N2 is opened. The PLD1 and PLD2 ensure that the potential difference between the two ends of the pull-down resistor R1 is 0. At this time, the PLD6 and NLD4 are opened, and the opening of the PLD6 makes the NLD5 opened. The NLD5 and NLD4 constitute a discharge channel, quickly discharge the charge of the high-side power tube gate, and ensure the working stability of the half-bridge structure. The inverter directly connected with the low-side power tube M N2 needs to be appropriately increased in size to ensure its driving capacity since it needs to drive the gate of the power tube.

Claims

1. An integrated half-bridge drive module, characterized by The drive circuit includes two outputs connected to the gates of high-side power transistor M N1 and low-side power transistor M N2 , and the gates of high-side power transistor M N1 and low-side power transistor M N2 are charged and discharged to realize the on-off function of high-side power transistor M N1 and low-side power transistor M N2 . The high-side power transistor M N1 The low-side power transistor M N2 The high-side power transistor M and the low-side power transistor M constitute a half-bridge structure, and are integrated together with the driving circuit to form an integrated half-bridge driving circuit. The driving circuit comprises a high-side power transistor driving module and a low-side power transistor driving module, wherein the output of the high-side driving module is connected to the gate of the high-side power transistor M N1 , and the output of the low-side driving module is connected to the gate of the low-side power transistor M N2 . The driving circuit comprises inverters INV1 and INV2, which generate two clock signals with a phase difference of 180 degrees, the inverter INV1 is connected to the gate of NLD2, the inverter INV2 is connected to the gate of NLD1, NLD1 is connected to the pull-down resistor R1, NLD2 is connected to the pull-down resistor R2, and the control of the pull-down resistor branch is realized through the control of the clock signal.

2. An integrated half bridge driver module according to claim 1, wherein, The input end of the driving circuit is connected to a charge pump circuit, which is responsible for providing power supply voltage for the entire driving circuit; the input end of the charge pump is connected to an oscillator circuit, which is responsible for providing the working frequency for the charge pump.

3. An integrated half bridge driver module according to claim 1, wherein, The input end of the driving circuit is connected to a 5V input and a current bias IBIAS, the 5V input is responsible for providing power input for the low-side driving circuit, the current bias IBIAS is responsible for providing a stable bias current for the high-side driving module to ensure the normal operation of the high-side driving circuit, the 5V input is VREF, the power input is VBB, and the current bias IBIAS is responsible for providing a certain current input for the driving circuit to meet the prerequisite for normal operation of the driving circuit.

4. An integrated half bridge driver module according to claim 1, wherein, The high-side power transistor M N1 The charging circuit is composed of PLD4 and SPLD, the drain of PLD4 is connected with the source of SPLD, and the source of SPLD is connected with the gate of the high-side power transistor; the discharging channel has two groups, the first group is composed of PLD5, PLD6 and NLD5, the drain of PLD5 is connected with the source of PLD6, and the drain of PLD6 is connected with the gate of NLD5; the second group is composed of NLD4; the gate of NLD4 is connected with the drain, and is connected with the gate of the low-side power transistor M N2 ​ The lower end of the pull-down resistor R1 is connected to the gate of SPLD, and the lower end of the pull-down resistor R2 is connected to the gate of PLD6, and the charging circuit and the discharging channel determine whether to conduct through the pull-down resistor branch.

5. An integrated half bridge drive module according to claim 4, wherein, The opening and closing function of the PLD5 is controlled by the current mirror structure composed of PLD3 and PLD4, and the current mirror structure MN5 mirrors the current of the current mirror structure MN1, and then mirrors the current to the branch where the PLD4 is located.

6. An integrated half bridge driver module according to claim 1, wherein, The low-side power transistor M N2 The charge-discharge circuit comprises an inverter INV3 and a Class AB amplifier, the Class AB amplifier comprising a large-size transistor MP1 and a large-size transistor MN4; the inverter INV3 is in front, the Class AB amplifier is in back, the inverter INV3 and the Class AB amplifier are connected in series, and the output position is connected with the gate end of the low-side power transistor M N2 . The gate end of the larger size transistor MP1 is connected to the gate end of the larger size transistor MN4, and the drain end is connected, the source end of the larger size transistor MP1 is connected to VREF, the source end of the larger size transistor MN4 is connected to ground, the output of the inverter INV3 is connected to the gate end of the larger size transistor MP1 and the larger size transistor MN4, and the drain end of the larger size transistor MP1 and the larger size transistor MN4 is the output position of the structure composed of the inverter INV3 and the Class AB amplifier in series.

7. An integrated half bridge driver module according to claim 1, wherein, The current mirror structure is arranged at the bottom of the driving circuit, which is used to provide a certain working current for the upper power device and the pull-down resistor branch to ensure the normal working state of the driving circuit; the current mirror structure comprises current mirror structures MN1, MN2, MN3 and MN5; the gate end of the current mirror structure MN1 is connected to the drain end, and the gate end of the current mirror structures MN2, MN3 and MN5 is connected to the gate end of the current mirror structure MN1; the source end of the current mirror structures MN1, MN2, MN3 and MN5 is connected to ground; the current mirror structure MN1 is the input of the current mirror at the front end of the current mirror structure, and the current mirror structures MN2, MN3 and MN5 are the load of the current mirror, which are located behind the current mirror structure MN1.

Images