A control method of a switching converter

Abstract

The application discloses a control method of a switching converter, which sequentially enters a bootstrap capacitor pre-charging stage, a narrow pulse mode low-frequency starting stage, a narrow pulse mode volt-second balance frequency increasing stage and a complementary mode volt-second balance frequency increasing stage before entering a stable working state of a clamped asymmetric half-bridge flyback topology; on the one hand, the main power tube and the secondary rectifier tube can realize full-range zero-voltage switching and zero-current switching in the starting process, greatly improving the problems of large primary voltage and current stress and large secondary voltage stress of the existing clamped asymmetric half-bridge flyback topology during power-on starting; on the other hand, the starting speed of the switching converter can be effectively improved, and the smooth switching of the switching converter from soft-start voltage to loop feedback voltage for controlling the working of the switching converter can be ensured, and the current stress peak of the main power tube and the secondary rectifier tube caused by switching can be reduced; therefore, the safety and reliability of the switching converter can be improved.

Description

Technical Field

[0001] This invention relates to the field of switching power supplies, and more specifically to a control method for a switching converter. Background Technology

[0002] When a switching power supply converter is working, the subsequent stage often has a large output capacitor or capacitive load. The former is to filter the output current, and the latter is to increase the load-carrying capacity of the switching power supply system. This structure often makes it easy for the output voltage to overshoot during the build-up process, or for the excessive current during startup to damage the switching transistor. The common solution is to gradually increase the duty cycle of the switching transistor drive signal during startup, so that the output voltage builds up slowly from low voltage to rated output voltage over a longer period of time, thus achieving soft start.

[0003] For an asymmetric half-bridge flyback converter (AHBF) system, when using a conventional high-frequency soft-start scheme, the demagnetizing current decreases slowly before the output voltage is established, preventing the main power transistor from achieving zero-voltage switching (ZVS) and the secondary rectifier diode from achieving zero-switching (ZCS). A reverse recovery process occurs, generating a large dv / dt at the moment the main power transistor turns on. This current resonates across the parasitic inductance and the parasitic capacitance Coss of the auxiliary power transistor, increasing the voltage at the midpoint of the bridge arm. This results in increased voltage stress on the lower main switch transistor Q2, which is then coupled to the secondary side via the transformer, increasing the stress spike of the secondary rectifier diode.

[0004] In summary, under conventional soft-start schemes, asymmetric half-bridge flyback converter systems are prone to current spikes, as well as high primary-side voltage and current stress and high secondary-side voltage stress. The root cause lies in whether the soft-start level can be smoothly switched, whether the secondary-side rectifier can achieve zero-current switching (ZCS) when the main power transistor is turned on, and whether the main power transistor can achieve ZVS.

[0005] To mitigate the aforementioned startup stress issue, existing researchers have proposed a "variable gate drive" scheme to reduce the turn-on speed of the main power transistor, thereby decreasing its dv / dt and di / dt during turn-on. However, different types of MOSFETs or MOSFETs at different temperatures exhibit varying turn-on voltages, complicating control. This scheme causes the main power MOSFET to operate in a variable resistance region for a period, and frequent startup processes can lead to overheating risks for the main power transistor. The invention patent CN202210308825, "Startup Control Method, Device, and Switching Power Supply for Boost DC-DC Converters," proposes a segmented startup control strategy. This strategy first involves a pre-charging process, followed by an output voltage compensation stage where the auxiliary power transistor remains off while the gate voltage of the upper power transistor gradually increases. In the third stage, the main power transistor and the lower transistor are alternately switched, with the duty cycle of the upper main power transistor increasing gradually until the output voltage reaches a preset value. This scheme can reduce inductor current to some extent and prevent current overshoot, but it still cannot solve the voltage stress problem of the switching devices during startup. Summary of the Invention

[0006] The technical problem to be solved by the present invention is to provide a control method for a switching converter to solve the problems of current spikes, high primary-side voltage and current stress, and high secondary-side voltage stress in existing asymmetric half-bridge flyback converter systems during power-on.

[0007] To solve the above-mentioned technical problems, the technical solution adopted by the present invention is as follows:

[0008] A control method for a switching converter, wherein the switching converter adopts a clamped asymmetric half-bridge flyback topology including a main power transistor, an auxiliary power transistor, a resonant capacitor, a unidirectional diode, a clamping switch transistor, a transformer, and a secondary rectifier transistor;

[0009] Specifically: the drain of the main power transistor is connected to the input voltage of the switching converter; the source of the main power transistor is connected to the drain of the auxiliary power transistor, and their connection point is connected to the same-name terminal of the primary winding of the transformer through a resonant capacitor; a unidirectional diode and a clamping switch form a unidirectional clamping network; the anode of the unidirectional diode is connected to the same-name terminal of the primary winding of the transformer, and the cathode of the unidirectional diode is connected to the drain of the clamping switch; the source of the auxiliary power transistor, the source of the clamping switch, and the opposite-name terminal of the primary winding of the transformer are all connected to the primary ground; the opposite-name terminal of the secondary winding of the transformer is connected to the anode of the secondary rectifier, and the same-name terminal of the secondary winding of the transformer is connected to the secondary ground; the cathode of the secondary rectifier and the same-name terminal of the secondary winding of the transformer serve as the positive and negative output terminals of the switching converter, respectively; an input capacitor can also be connected in series between the input terminal of the input voltage and the primary ground, and an output capacitor can also be connected in series between the positive and negative output terminals of the switching converter; the secondary rectifier can be a diode or a MOSFET.

[0010] The clamped asymmetric half-bridge flyback topology operates under pulse width modulation (PWM) signal control, including: main power transistor drive signal, auxiliary power transistor drive signal, and clamping transistor drive signal, which are respectively input to the gate of the main power transistor, the gate of the auxiliary power transistor, and the gate of the clamping switching transistor.

[0011] Its features are:

[0012] The switching converter is also provided with a bootstrap capacitor and a charging circuit, wherein the bootstrap capacitor is connected between the gate and source of the main power transistor.

[0013] The control method includes, in sequence:

[0014] Step S1: When the switching converter is powered on, control the clamped asymmetric half-bridge flyback topology to enter the bootstrap capacitor pre-charging stage, that is: control the main power transistor to turn off, the auxiliary power transistor to turn on, and the clamping switch transistor to turn off, so as to provide a circuit for charging the bootstrap capacitor, and control the charging circuit to charge the bootstrap capacitor.

[0015] Step S2: When the voltage of the bootstrap capacitor reaches the charging voltage that enables the main power transistor to conduct, after a first fixed dead time interval, control the clamped asymmetric half-bridge flyback topology to enter the narrow pulse mode low-frequency start-up stage.

[0016] Step S3, at the volt-second equilibrium frequency f vs Higher than the minimum clock frequency f smin At that time, the clamped asymmetric half-bridge flyback topology is controlled to enter the narrow pulse mode volt-second balanced up-frequency stage;

[0017] Step S4, the output voltage V of the switching converter o Increase to the preset reference voltage V X When the current cycle of the narrow pulse mode volt-second balanced up-frequency phase ends, and after a first fixed dead time interval, the clamped asymmetric half-bridge flyback topology is controlled to enter the complementary mode volt-second balanced up-frequency phase; wherein, the set reference voltage V X The value of V is set according to the required rate of increase of the operating frequency of the switching converter. The faster the required rate of increase of the operating frequency, the higher the reference voltage V should be. X The smaller the setting value, the better.

[0018] Step S5, in the loop feedback voltage V FB Reduce to the second soft-start voltage V comp2 At this point, the startup process from steps S1 to S4 ends, and the clamped asymmetric half-bridge flyback topology is controlled to enter a stable operating state, that is, by the loop feedback voltage V FB The control switch converter operates; wherein, the loop feedback voltage V FBThe voltage output by the loop compensator, which consists of a comparator and an error amplifier, is given by the two inputs of the comparator being the output voltage V of the switching converter. o and the preset reference voltage V ref The input terminal of the error amplifier is connected to the output terminal of the comparator; the second soft-start voltage V comp2 The voltage value is obtained by converting the steady-state peak current, which is K2 times the voltage value, according to a preset ratio.

[0019] Among them, see Figure 3a In step S2, during the narrow pulse mode low-frequency startup phase, the clamped asymmetric half-bridge flyback topology operates at a fixed minimum clock frequency f. smin It operates periodically in the order of the first to the sixth period of the low-frequency phase:

[0020] In the first period of the low-frequency phase (i.e.) Figure 3a t 0a Time to t 1a At any given moment, the main power transistor is turned off, the auxiliary power transistor is turned on, and the clamping switch is turned off in the first time period of the first low-frequency phase. Furthermore, the duration of the first time period of the low-frequency phase is 1 / 2 of the resonant period to ensure that the secondary rectifier transistor achieves zero-current switching (ZCS). The resonant period is the resonant period of the resonant circuit composed of the resonant capacitor and the leakage inductance of the transformer.

[0021] During the second period of the low-frequency phase (i.e.) Figure 3a t 1a Time to t 2a At any given moment, the main power transistor, auxiliary power transistor, and clamping switch transistor are all turned off; and the duration of the second period in the low-frequency phase is a preset first fixed dead time, which is a fixed value preset according to the switching converter system parameters.

[0022] In the third period of the low-frequency phase (i.e.) Figure 3a t 2a Time to t 3a At a certain moment, the main power transistor is turned on, while the auxiliary power transistor and clamping switch are both turned off; and the third period of the low-frequency phase ends when the excitation current of the transformer reaches K1 times the steady-state peak current (i.e., Figure 3a t 3a (At any given time), K1 is a preset overcurrent multiple, which can be adjusted according to different start-up time requirements of the switching converter. The steady-state peak current is the peak value of the transformer's excitation current when the switching converter is in a stable operating state under the nominal input voltage and rated output load. In the specific implementation of the switching converter, the steady-state peak current, which is K1 times the voltage, is generally converted into a corresponding voltage value according to a preset ratio and used as the first soft-start voltage V. comp1The excitation current is converted into a voltage value by the same preset ratio as the first soft-start voltage V. comp1 Comparisons were made to determine the end time of the third period in the low-frequency phase.

[0023] In the fourth period of the low-frequency phase (i.e.) Figure 3a t 3a Time to t 4a At any given moment, the main power transistor, auxiliary power transistor, and clamping switch transistor are all turned off; and the duration of the fourth period in the low-frequency phase is a preset second fixed dead time, which is a fixed value preset according to the switching converter system parameters.

[0024] In the fifth period of the low-frequency phase (i.e.) Figure 3a t 4a Time to t 5a At a certain moment, the auxiliary power transistor and the clamping switch are both turned on, and the main power transistor is turned off; and, the duration of the fifth period of the low-frequency stage is 3 / 4 of the resonant cycle, then within one resonant cycle after the auxiliary power transistor is turned on, the resonant capacitor and the primary winding of the transformer jointly transfer energy to the secondary winding of the transformer. After the resonant cycle ends, the primary winding of the transformer transfers energy to the secondary winding of the transformer alone.

[0025] During the sixth period of the low-frequency phase (i.e.) Figure 3a t 5a Time to t 7a At a certain time, both the main power transistor and the auxiliary power transistor are turned off, and the clamping switch is kept on until the end of the first period of the low-frequency phase of the next cycle (i.e., Figure 3a t 8a (at time t), so that the excitation current of the transformer is at t 6a Time to t 7a When the clock crosses zero, the demagnetizing current is clamped near zero by a clamping switch to reduce current oscillation; furthermore, the duration of the sixth period in the low-frequency phase is determined by the lowest clock frequency f. smin The decision is made, and the calculation formula is as follows:

[0026]

[0027] In the formula, n represents the turns ratio of the transformer, V D I represents the tube voltage drop of the secondary rectifier tube. peak Lm represents the peak value of the excitation current of the transformer, and Lm represents the excitation inductance value of the transformer.

[0028] Among them, see Figure 3b In step S3, during the narrow pulse mode volt-second balance up-frequency stage, the clamped asymmetric half-bridge flyback topology operates at a dynamically changing volt-second balance frequency f. vsIt operates periodically in the order of the first to the sixth phase of the frequency upsampling stage:

[0029] During the first period of the frequency upsampling phase (i.e.) Figure 3b t 0b Time to t 1b At any given moment, the main power transistor is turned off, the auxiliary power transistor is turned on, and the clamping switch is turned off during the first time period of the first frequency boosting phase; and the duration of the first time period of the frequency boosting phase is a delay time. Furthermore, during the startup phase of the switching converter, the output voltage V o The setup is slow, therefore the calculated t d The delay time t is relatively large. To avoid resonance between the magnetizing inductance, leakage inductance Lr, and resonant capacitor Cr when the auxiliary power transistor is turned on, which would be detrimental to the generation of negative current, the delay time t is... d The maximum value is limited to 1 / 2 of the resonant period; where Lm represents the magnetizing inductance of the transformer, n represents the turns ratio of the transformer, and V o I represents the output voltage of the switching converter. nset I represents the magnitude of the negative current required for the main power transistor to achieve zero-voltage switching (ZVS). nset It is proportional to the input voltage of the switching converter;

[0030] During the second phase of the frequency upsampling phase (i.e.) Figure 3b t 1b Time to t 2b At any given moment, the main power transistor, auxiliary power transistor, and clamping switch transistor are all turned off; and the duration of the second period of the frequency boosting phase is the same as the first fixed dead time.

[0031] During the third phase of the frequency upsampling phase (i.e.) Figure 3b t 2b Time to t 3b At a certain moment, the main power transistor is turned on, while the auxiliary power transistor and clamping switch are both turned off; and the third period of the frequency ramp-up phase ends when the excitation current of the transformer reaches K1 times the steady-state peak current (i.e., Figure 3b t 3b (At any given time), K1 is a preset overcurrent multiple, which can be adjusted according to different start-up time requirements of the switching converter. The steady-state peak current is: the peak value of the transformer's excitation current when the switching converter is operating stably under the nominal input voltage and rated output load. In the specific implementation of the switching converter, the steady-state peak current of K1 times is generally converted into a corresponding voltage value according to a preset ratio as the first soft-start voltage V. comp1 The excitation current is converted into a voltage value by the same preset ratio as the first soft-start voltage V. comp1 The comparison is used to determine the end time of the third period of the frequency upsampling phase.

[0032] During the fourth period of the up-frequency phase (i.e.) Figure 3b t 3b Time to t 4b At any given moment, the main power transistor, auxiliary power transistor, and clamping switch transistor are all turned off; and the duration of the fourth period of the frequency ramping phase is the second fixed dead time.

[0033] During the fifth phase of the frequency upsampling phase (i.e.) Figure 3b t 4b Time to t 5b At a certain moment, the auxiliary power transistor and the clamping switch transistor are both turned on, and the main power transistor is turned off; and the duration of the fifth period of the frequency boosting phase is 3 / 4 of the resonant period;

[0034] During the sixth period of the frequency upsampling phase (i.e.) Figure 3b t 5b Time to t 6b At the specified time, both the main power transistor and the auxiliary power transistor are turned off, and the clamping switch is kept on until the end of the first time period of the frequency ramping phase of the next cycle (i.e., ...). Figure 3b t 7b At the moment when the transformer's excitation current crosses zero, the demagnetizing current is clamped near zero by a clamping switch to reduce current oscillation; and the sixth period of the frequency ramp-up phase ends at the moment the demagnetizing current crosses zero (i.e., Figure 3b t 6b (at a certain time), such that the clamped asymmetric half-bridge flyback topology operates at the volt-second equilibrium frequency f. vs Works, in accordance with the output voltage V o The establishment of this mechanism advances the zero-crossing moment of the demagnetizing current, thereby achieving frequency upscaling; wherein, the zero-crossing moment of the demagnetizing current is the moment when the excitation current of the transformer drops to zero, and the volt-second balance frequency f... vs That is, the reciprocal of the time interval between two consecutive zero-crossing moments of the demagnetizing current (e.g. Figure 3b t 0b Time to t 6b time).

[0035] In step S3, the zero-crossing time of the demagnetizing current is calculated based on the volt-second balance theory.

[0036] The volt-second balance theory states that the excitation volt-second product of the excitation winding within one cycle is equal to the demagnetization volt-second product, i.e. To obtain the zero-crossing point of the excitation current, the excitation starting point is set at the positive zero-crossing point of the excitation current. Then, the zero-crossing point of the demagnetizing current can be calculated using the volt-second balance theory. That is: sample the excitation current to obtain the zero-crossing signal of the excitation current, which serves as the starting point for the volt-second balance calculation. Also, sample the voltage of the excitation winding to calculate the volt-second product. Based on the volt-second balance, the zero-crossing time of the demagnetizing current can be calculated.

[0037] Among them, see Figure 3c In step S4, during the complementary mode volt-second balance up-frequency stage, the clamped asymmetric half-bridge flyback topology operates at a dynamically changing volt-second balance frequency f. vs It operates periodically in the order of the first to the fourth phase of the complementary phase:

[0038] In the first phase of the complementary phase (i.e.) Figure 3c t 0c Time to t 1c At any given moment, both the main power transistor and the auxiliary power transistor are turned off; and the duration of the first period of the complementary phase is the first fixed dead time.

[0039] In the second phase of the complementary phase (i.e.) Figure 3c t 1c Time to t 2c At a certain moment, the main power transistor is turned on and the auxiliary power transistor is turned off; and the second period of the complementary phase ends when the excitation current of the transformer reaches K2 times the steady-state peak current (i.e., Figure 3c t 2c At any given time, K2 is a preset overcurrent multiple, and K2 < K1; where, in the specific implementation of the switching converter, the steady-state peak current, which is K2 times the current, is generally converted into a corresponding voltage value according to a preset ratio as the second soft-start voltage V. comp2 The excitation current is converted into a voltage value by the same preset ratio as the second soft-start voltage V. comp2 A comparison is made to determine the end time of the second phase of the complementary phase.

[0040] In the third phase of the complementary phase (i.e.) Figure 3c t 2c Time to t 3c At any given moment, both the main power transistor and the auxiliary power transistor are turned off; and the duration of the third period of the complementary phase is the second fixed dead time.

[0041] In the fourth phase of the complementary phase (i.e.) Figure 3c t 3c Time to t 5c At a certain moment, the main power transistor is turned off and the auxiliary power transistor is turned on; and, in the fourth period of the complementary phase...

[0042] At the zero-crossing time of the demagnetizing current (i.e. Figure 3c t 4c (Time) Delayed by the aforementioned delay time End (i.e.) Figure 3c t 5c (time), and t d The maximum value is limited to 1 / 2 of the resonant period; and the clamping switch remains off during the complementary mode volt-second balance up-frequency phase.

[0043] Preferably, the values ​​of the overcurrent factor K1 and the overcurrent factor K2 are 1.4 and 1.2, respectively.

[0044] Thus, the present invention enables the startup process to sequentially enter the bootstrap capacitor pre-charging stage, the narrow pulse mode low-frequency startup stage, the narrow pulse mode volt-second balance frequency up-up stage, and the complementary mode volt-second balance frequency up-up stage before the clamped asymmetric half-bridge flyback topology enters the stable working state.

[0045] On the one hand, it can achieve zero-voltage switching (ZVS) and zero-current switching (ZCS) of the main power transistor and the secondary rectifier transistor during the entire startup process, which greatly improves the problem of large primary-side voltage and current stress and large secondary-side voltage stress in the existing clamped asymmetric half-bridge flyback topology during power-on startup.

[0046] On the other hand, since the startup process employs a soft-start voltage adapted to different modes, specifically, a steady-state peak current of K1 times is used as the first soft-start voltage V during the narrow-pulse mode low-frequency startup phase and the narrow-pulse mode volt-second balance frequency up-amplitude phase. comp1 In the complementary mode volt-second balance up-frequency phase, K2 times the steady-state peak current is used as the second soft-start voltage V. comp2 This can effectively improve the startup speed of the switching converter, and utilize the loop feedback voltage V FB With the first soft-start voltage V comp1 Second soft-start voltage V comp2 The competitive mechanism ensures a smooth switching from the soft-start voltage to the loop feedback voltage to control the operation of the switching converter, reducing the current stress spikes in the main power transistor and secondary rectifier transistor caused by the switching.

[0047] Therefore, the present invention can improve the safety and reliability of switching converters employing clamped asymmetric half-bridge flyback topology.

[0048] Among them, the above-mentioned loop feedback voltage V FB With the first soft-start voltage V comp1 Second soft-start voltage V comp2 The competition mechanism is as follows: during the startup process, the loop feedback voltage V... FB With the first soft-start voltage V comp1 Second soft-start voltage V comp2A comparison was made throughout the process. Since the output voltage Vo was not established at the initial startup, the loop feedback voltage V... FB It remains at its highest value, higher than the first soft-start voltage V. comp1 Second soft-start voltage V comp2 Therefore, the first soft-start voltage V during this stage comp1 Second soft-start voltage V comp2 Enter peak current closed-loop control. Until the output voltage Vo is established, the loop feedback voltage V... FB Below the first soft-start voltage V comp1 Second soft-start voltage V comp2 Loop feedback voltage V FB The switch takes over the operation of the control switch converter, thereby achieving a smooth switching between the soft-start voltage and the loop feedback voltage through a competition mechanism of "whoever has the lower voltage enters the loop".

[0049] Preferably: the output terminal of the charging circuit is connected to the anode of the charging diode, and the cathode of the charging diode is connected to the connection point between the main power transistor and the bootstrap capacitor; in the pre-charging stage of the bootstrap capacitor in step S1, the charging circuit outputs a signal with a duration of T. pre =(R pre +R dson C pre And a pre-charge pulse with a voltage equal to the charging voltage charges the bootstrap capacitor to the charging voltage; where T pre R represents the duration of the pre-charge pulse. pre R represents the resistance value of the current-limiting resistor connected in series with the charging diode in the charging circuit. dson C represents the on-resistance of the auxiliary power transistor. pre This indicates the capacitance value of the bootstrap capacitor.

[0050] Compared with the prior art, the present invention has the following beneficial effects:

[0051] This invention introduces a startup process that sequentially enters the bootstrap capacitor pre-charging stage, the narrow pulse mode low-frequency startup stage, the narrow pulse mode volt-second balance frequency up-up stage, and the complementary mode volt-second balance frequency up-up stage before the clamped asymmetric half-bridge flyback topology enters a stable working state.

[0052] On the one hand, it can achieve zero-voltage switching (ZVS) and zero-current switching (ZCS) of the main power transistor and the secondary rectifier transistor during the entire startup process, which greatly improves the problem of large primary-side voltage and current stress and large secondary-side voltage stress in the existing clamped asymmetric half-bridge flyback topology during power-on startup.

[0053] On the other hand, since the startup process employs a soft-start voltage adapted to different modes, specifically, a steady-state peak current of K1 times is used as the first soft-start voltage V during the narrow-pulse mode low-frequency startup phase and the narrow-pulse mode volt-second balance frequency up-amplitude phase. comp1 In the complementary mode volt-second balance up-frequency phase, K2 times the steady-state peak current is used as the second soft-start voltage V. comp2 This can effectively improve the startup speed of the switching converter, and utilize the loop feedback voltage V FB With the first soft-start voltage V comp1 Second soft-start voltage V comp2 The competitive mechanism ensures a smooth switching from the soft-start voltage to the loop feedback voltage to control the operation of the switching converter, reducing the current stress spikes in the main power transistor and secondary rectifier transistor caused by the switching.

[0054] Therefore, the present invention can improve the safety and reliability of switching converters employing clamped asymmetric half-bridge flyback topology. Attached Figure Description

[0055] The present invention will now be described in further detail with reference to the accompanying drawings and specific embodiments:

[0056] Figure 1 This is a circuit diagram of the switching converter of the present invention. In the diagram, Lr and Lm represent the leakage inductance and magnetizing inductance of transformer T, respectively. Lm i represents the magnetizing current through the magnetizing inductor Lm. Lr i represents the leakage inductance current through the leakage inductance Lr. d This represents the secondary current flowing through the secondary rectifier diode Q4;

[0057] Figure 2 This is a flowchart of the control method for the switching converter of the present invention;

[0058] Figure 3a This is a timing and waveform diagram of the low-frequency start-up phase in the narrow pulse mode of this invention;

[0059] Figure 3b The timing and waveform diagrams for the narrow pulse mode volt-second balanced up-frequency stage in this invention are shown.

[0060] Figure 3c The timing and waveform diagrams for the complementary mode volt-second balance up-frequency stage in this invention are shown.

[0061] Figure 4 This is a diagram showing the drive signal waveform and output voltage waveform during the startup process of this invention. Detailed Implementation

[0062] The present invention will now be described in detail with reference to the embodiments and accompanying drawings to help those skilled in the art better understand the inventive concept of the present invention. However, the scope of protection of the claims of the present invention is not limited to the following embodiments. For those skilled in the art, all other embodiments obtained without creative effort without departing from the inventive concept of the present invention are within the scope of protection of the present invention.

[0063] like Figures 1 to 4 As shown, the present invention discloses a control method for a switching converter, applicable to: the switching converter adopting a clamped asymmetric half-bridge flyback topology including a main power transistor Q1, an auxiliary power transistor Q2, a resonant capacitor Cr, a unidirectional diode D2, a clamping switch transistor Q3, a transformer T, and a secondary rectifier transistor D4;

[0064] Specifically: the drain of the main power transistor Q1 is connected to the input voltage Vin of the switching converter; the source of the main power transistor Q1 is connected to the drain of the auxiliary power transistor Q2, and their connection point Vsw is connected to the same-name terminal of the primary winding Lp of the transformer T through the resonant capacitor Cr; the unidirectional diode D2 and the clamping switch Q3 form a unidirectional clamping network; the anode of the unidirectional diode D2 is connected to the same-name terminal of the primary winding Lp of the transformer T; the cathode of the unidirectional diode D2 is connected to the drain of the clamping switch Q3; the source of the auxiliary power transistor Q2, the source of the clamping switch Q3, and the opposite-name terminal of the primary winding Lp of the transformer T are all connected to the primary ground terminal; The opposite-named terminal of the secondary winding Ls of transformer T is connected to the anode of the secondary rectifier diode D4, and the same-named terminal of the secondary winding Ls of transformer T is connected to the secondary ground. The cathode of the secondary rectifier diode D4 and the same-named terminal of the secondary winding Ls of transformer T serve as the positive output terminal Vout+ and the negative output terminal Vout- of the switching converter, respectively. An input capacitor Cin can also be connected in series between the input terminal of the input voltage Vin and the primary ground terminal, and an output capacitor Cout can also be connected in series between the positive output terminal Vout+ and the negative output terminal Vout- of the switching converter. The secondary rectifier diode D4 can be a diode or a MOSFET.

[0065] The clamped asymmetric half-bridge flyback topology operates under pulse width modulation (PWM) signal control, including: main power transistor drive signal VG_Q1, auxiliary power transistor drive signal VG_Q2, and clamping transistor drive signal VG_Q3, which are respectively input to the gate of the main power transistor Q1, the gate of the auxiliary power transistor Q2, and the gate of the clamping switching transistor Q3.

[0066] The switching converter is also equipped with a bootstrap capacitor C. B And the charging circuit, the bootstrap capacitor C B It is connected between the gate and source of the main power transistor Q1;

[0067] The control method includes, in sequence:

[0068] Step S1: When the switching converter is powered on, control the clamped asymmetric half-bridge flyback topology to enter the bootstrap capacitor pre-charging stage, that is: control the main power transistor Q1 to turn off, the auxiliary power transistor Q2 to turn on, and the clamping switch transistor Q3 to turn off, so as to charge the bootstrap capacitor C. B A charging circuit is provided, and the charging circuit is controlled to supply power to the bootstrap capacitor C. B Charge;

[0069] Preferably, the output terminal of the charging circuit is connected to the anode of the charging diode D1, and the cathode of the charging diode D1 is connected to the main power transistor Q1 and the bootstrap capacitor C. B The connection point; in the bootstrap capacitor pre-charging stage described in step S1, the charging circuit outputs a duration of T. pre =(R pre +R dson C pre And the pre-charge pulse with voltage equal to the charging voltage Vcc causes the bootstrap capacitor C to... B Charge to the charging voltage Vcc; where T pre R represents the duration of the pre-charge pulse. pre R represents the resistance value of the current-limiting resistor connected in series with the charging diode D1 in the charging circuit. dson C represents the on-resistance of the auxiliary power transistor Q2. pre This indicates that the bootstrap capacitor C B The capacitance value.

[0070] Step S2, in the bootstrap capacitor C B When the voltage reaches the charging voltage Vcc that enables the main power transistor Q1 to conduct, the interval is the first fixed dead time T. dead1 Then, the clamped asymmetric half-bridge flyback topology is controlled to enter the narrow pulse mode low-frequency start-up stage;

[0071] Among them, see Figure 3a In step S2, during the narrow pulse mode low-frequency startup phase, the clamped asymmetric half-bridge flyback topology operates at a fixed minimum clock frequency f. smin It operates periodically in the order of the first to the sixth period of the low-frequency phase:

[0072] In the first period of the low-frequency phase (i.e.) Figure 3a t 0a Time to t 1aAt any given moment, the main power transistor Q1 is turned off, the auxiliary power transistor Q2 is turned on, and the clamping switch Q3 is turned off in the first time period of the first low-frequency phase. The duration of the first time period of the low-frequency phase is 1 / 2 of the resonant period to ensure that the secondary rectifier transistor D4 achieves zero-current switching (ZCS). The resonant period is the resonant period of the resonant circuit composed of the resonant capacitor Cr and the leakage inductance Lr of the transformer T.

[0073] During the second period of the low-frequency phase (i.e.) Figure 3a t 1a Time to t 2a At a certain time, the main power transistor Q1, auxiliary power transistor Q2, and clamping switch Q3 are all turned off; and the duration of the second period in the low-frequency phase is a preset first fixed dead time T. dead1 The first fixed dead time T dead1 These are fixed values ​​preset based on the switching converter system parameters;

[0074] In the third period of the low-frequency phase (i.e.) Figure 3a t 2a Time to t 3a At a certain time, the main power transistor Q1 is turned on, while the auxiliary power transistor Q2 and the clamping switch Q3 are both turned off; and, during the third time period of the low-frequency phase, the excitation current i of the transformer T is... Lm The process ends when the steady-state peak current reaches K1 times (i.e., Figure 3a t 3a (Time), K1 is a preset overcurrent multiple, which can be adjusted according to different start-up time requirements of the switching converter. The steady-state peak current is: when the switching converter is in a stable operating state under the nominal input voltage and rated output load, the excitation current i of the transformer T. Lm The peak value; where, in the specific implementation of the switching converter, the steady-state peak current of K1 times is generally converted into a corresponding voltage value according to a preset ratio as the first soft-start voltage V. comp1 and the excitation current i Lm The same preset ratio is converted into a voltage value and compared with the first soft-start voltage V. comp1 Comparisons were made to determine the end time of the third period in the low-frequency phase.

[0075] In the fourth period of the low-frequency phase (i.e.) Figure 3a t 3a Time to t 4a At a certain time, the main power transistor Q1, auxiliary power transistor Q2, and clamping switch Q3 are all turned off; and the duration of the fourth period in the low-frequency phase is the preset second fixed dead time T. dead2 The second fixed dead time T dead2 These are fixed values ​​preset based on the switching converter system parameters;

[0076] In the fifth period of the low-frequency phase (i.e.) Figure 3a t 4a Time to t 5a At a certain moment, the auxiliary power transistor Q2 and the clamping switch Q3 are both turned on, while the main power transistor Q1 is turned off. Furthermore, the duration of the fifth period in the low-frequency phase is 3 / 4 of the resonant cycle. In one resonant cycle after the auxiliary power transistor Q2 is turned on, the resonant capacitor Cr and the primary winding Lp of the transformer T jointly transfer energy to the secondary winding Ls of the transformer T. After the resonant cycle ends, the primary winding Lp of the transformer T transfers energy to the secondary winding Ls of the transformer T alone.

[0077] During the sixth period of the low-frequency phase (i.e.) Figure 3a t 5a Time to t 7a At the specified time, both the main power transistor Q1 and the auxiliary power transistor Q2 are turned off, and the clamping switch Q3 is kept on until the end of the first period of the low-frequency phase of the next cycle (i.e., Figure 3a t 8a At time), with the excitation current i at transformer T Lm In t 6a Time to t 7a When the clock crosses zero, the demagnetizing current is clamped near zero by the clamping switch Q3 to reduce current oscillation; and the duration of the sixth period in the low-frequency phase is determined by the lowest clock frequency f. smin The decision is made, and the calculation formula is as follows:

[0078]

[0079] In the formula, n represents the turns ratio of the transformer T, and V D I represents the tube voltage drop of the secondary rectifier tube D4. peak The excitation current i of the transformer T is represented by Lm The peak value is Lm, which represents the magnetizing inductance of the transformer T.

[0080] Step S3, at the volt-second equilibrium frequency f vs Higher than the minimum clock frequency f smin At that time, the clamped asymmetric half-bridge flyback topology is controlled to enter the narrow pulse mode volt-second balanced up-frequency stage;

[0081] Among them, see Figure 3b In step S3, during the narrow pulse mode volt-second balance up-frequency stage, the clamped asymmetric half-bridge flyback topology operates at a dynamically changing volt-second balance frequency f. vs It operates periodically in the order of the first to the sixth phase of the frequency upsampling stage:

[0082] During the first period of the frequency upsampling phase (i.e.) Figure 3b t 0b Time to t 1b At a certain moment, the main power transistor Q1 is turned off, the auxiliary power transistor Q2 is turned on, and the clamping switch Q3 is turned off during the first time period of the first frequency boosting phase; and the duration of the first time period of the frequency boosting phase is the delay time. Furthermore, during the startup phase of the switching converter, the output voltage V o The setup is slow, therefore the calculated t d The delay time t is relatively large. To avoid resonance between the magnetizing inductance Lm, leakage inductance Lr, and resonant capacitor Cr when the auxiliary power transistor Q2 is turned on, which would be detrimental to the generation of negative current, the delay time t is... d The maximum value is limited to 1 / 2 of the resonant period; where Lm represents the magnetizing inductance of the transformer T, n represents the turns ratio of the transformer T, and V o I represents the output voltage of the switching converter. nset I represents the magnitude of the negative current required for the main power transistor Q1 to achieve zero-voltage switching (ZVS). nset It is proportional to the input voltage of the switching converter;

[0083] During the second phase of the frequency upsampling phase (i.e.) Figure 3b t 1b Time to t 2b At a certain time, the main power transistor Q1, auxiliary power transistor Q2, and clamping switch Q3 are all turned off; and the duration of the second time period of the frequency upsampling phase is the first fixed dead time T. dead1 ;

[0084] During the third phase of the frequency upsampling phase (i.e.) Figure 3b t 2b Time to t 3b At a certain moment, the main power transistor Q1 is turned on, while the auxiliary power transistor Q2 and the clamping switch Q3 are both turned off; and, during the third time period of the frequency ramping phase, the excitation current i of the transformer T is... Lm The process ends when the steady-state peak current reaches K1 times (i.e., Figure 3b t 3b (Time), K1 is a preset overcurrent multiple, which can be adjusted according to different start-up time requirements of the switching converter. The steady-state peak current is: when the switching converter is operating stably under the nominal input voltage and rated output load, the excitation current i of the transformer T. Lm The peak value; where, in the specific implementation of the switching converter, the steady-state peak current of K1 times is generally converted into a corresponding voltage value according to a preset ratio as the first soft-start voltage V. comp1 and the excitation current i Lm The same preset ratio is converted into a voltage value and compared with the first soft-start voltage V. comp1The comparison is used to determine the end time of the third period of the frequency upsampling phase.

[0085] During the fourth period of the up-frequency phase (i.e.) Figure 3b t 3b Time to t 4b At a certain time, the main power transistor Q1, auxiliary power transistor Q2, and clamping switch Q3 are all turned off; and the duration of the fourth period of the frequency upsampling phase is the second fixed dead time T. dead2 ;

[0086] During the fifth phase of the frequency upsampling phase (i.e.) Figure 3b t 4b Time to t 5b At a certain moment, the auxiliary power transistor Q2 and the clamping switch transistor Q3 are both turned on, while the main power transistor Q1 is turned off; and the duration of the fifth period of the frequency boosting phase is 3 / 4 of the resonant period.

[0087] During the sixth period of the frequency upsampling phase (i.e.) Figure 3b t 5b Time to t 6b At the specified time, both the main power transistor Q1 and the auxiliary power transistor Q2 are turned off, and the clamping switch Q3 is kept on until the end of the first time period of the next cycle's frequency rise phase (i.e., ...). Figure 3b t 7b At time), with the excitation current i at transformer T Lm At the zero-crossing point, the demagnetizing current is clamped near zero by the clamping switch Q3, reducing current oscillation; and the sixth period of the frequency ramp-up phase ends at the zero-crossing point of the demagnetizing current (i.e., Figure 3b t 6b (at a certain time), such that the clamped asymmetric half-bridge flyback topology operates at the volt-second equilibrium frequency f. vs Works, in accordance with the output voltage V o The establishment of this mechanism advances the zero-crossing time of the demagnetizing current, thereby achieving frequency upscaling; wherein, the zero-crossing time of the demagnetizing current is the excitation current i of the transformer T. Lm At the moment it drops to zero, the volt-second equilibrium frequency f vs That is, the reciprocal of the time interval between two consecutive zero-crossing moments of the demagnetizing current (e.g. Figure 3b t 0b Time to t 6b time).

[0088] In step S3, the zero-crossing time of the demagnetizing current is calculated based on the volt-second balance theory.

[0089] The volt-second balance theory states that the excitation volt-second product of the excitation winding within one cycle is equal to the demagnetization volt-second product, i.e. To obtain the zero-crossing point of the excitation current, the excitation starting point is set at the positive zero-crossing point of the excitation current. Then, the zero-crossing point of the demagnetizing current can be calculated using the volt-second balance theory. That is: sample the excitation current to obtain the zero-crossing signal of the excitation current, which serves as the starting point for the volt-second balance calculation. Also, sample the voltage of the excitation winding to calculate the volt-second product. Based on the volt-second balance, the zero-crossing time of the demagnetizing current can be calculated.

[0090] Step S4, the output voltage V of the switching converter o Increase to the preset reference voltage V X When the current cycle of the narrow pulse mode volt-second balanced up-frequency phase ends, and after a first fixed dead time T... dead1 Then, the clamped asymmetric half-bridge flyback topology is controlled to enter the complementary mode volt-second balanced up-frequency stage; wherein, the set reference voltage V X The value of V is set according to the required rate of increase of the operating frequency of the switching converter. The faster the required rate of increase of the operating frequency, the higher the reference voltage V should be. X The smaller the setting value, the better.

[0091] Among them, see Figure 3c In step S4, during the complementary mode volt-second balance up-frequency stage, the clamped asymmetric half-bridge flyback topology operates at a dynamically changing volt-second balance frequency f. vs It operates periodically in the order of the first to the fourth phase of the complementary phase:

[0092] In the first phase of the complementary phase (i.e.) Figure 3c t 0c Time to t 1c At a certain time, both the main power transistor Q1 and the auxiliary power transistor Q2 are turned off; and the duration of the first period of the complementary phase is the first fixed dead time T. dead1 ;

[0093] In the second phase of the complementary phase (i.e.) Figure 3c t 1c Time to t 2c At a certain moment, the main power transistor Q1 is turned on and the auxiliary power transistor Q2 is turned off; and, during the second time period of the complementary phase, the excitation current i of the transformer T is... Lm The process ends when the steady-state peak current reaches K2 times (i.e., Figure 3c t 2c At any given time, K2 is a preset overcurrent multiple, and K2 < K1; where, in the specific implementation of the switching converter, the steady-state peak current, which is K2 times the current, is generally converted into a corresponding voltage value according to a preset ratio as the second soft-start voltage V. comp2 and the excitation current i Lm The same preset ratio is converted into a voltage value and the second soft-start voltage V. comp2A comparison is made to determine the end time of the second phase of the complementary phase.

[0094] Preferably, the values ​​of the overcurrent factor K1 and the overcurrent factor K2 are 1.4 and 1.2, respectively.

[0095] In the third phase of the complementary phase (i.e.) Figure 3c t 2c Time to t 3c At a certain time, both the main power transistor Q1 and the auxiliary power transistor Q2 are turned off; and the duration of the third period of the complementary phase is the second fixed dead time T. dead2 ;

[0096] In the fourth phase of the complementary phase (i.e.) Figure 3c t 3c Time to t 5c At the moment when the main power transistor Q1 is turned off and the auxiliary power transistor Q2 is turned on, the fourth period of the complementary phase is at the moment when the demagnetizing current crosses zero (i.e., Figure 3c t 4c (Time) Delayed by the aforementioned delay time End (i.e.) Figure 3c t 5c (time), and t d The maximum value is limited to 1 / 2 of the resonant period; and the clamping switch Q3 remains off during the complementary mode volt-second balance up-frequency phase.

[0097] Step S5, in the loop feedback voltage V FB Reduce to the second soft-start voltage V comp2 At this point, the startup process from steps S1 to S4 ends, and the clamped asymmetric half-bridge flyback topology is controlled to enter a stable operating state, that is, by the loop feedback voltage V FB The control switch converter operates; wherein, the loop feedback voltage V FB The voltage output by the loop compensator, which consists of a comparator and an error amplifier, is given by the two inputs of the comparator being the output voltage V of the switching converter. o and the preset reference voltage V ref The input terminal of the error amplifier is connected to the output terminal of the comparator; the second soft-start voltage V comp2 The voltage value is obtained by converting the steady-state peak current, which is K2 times the voltage value, according to a preset ratio.

[0098] Thus, the present invention enables the startup process to sequentially enter the bootstrap capacitor pre-charging stage, the narrow pulse mode low-frequency startup stage, the narrow pulse mode volt-second balance frequency up-up stage, and the complementary mode volt-second balance frequency up-up stage before the clamped asymmetric half-bridge flyback topology enters the stable working state.

[0099] On the one hand, it can achieve zero-voltage switching (ZVS) and zero-current switching (ZCS) of the main power transistor Q1 and the secondary rectifier transistor D4 during the entire startup process, which greatly improves the problem of large primary-side voltage and current stress and large secondary-side voltage stress in the existing clamped asymmetric half-bridge flyback topology during power-on startup.

[0100] On the other hand, since the startup process employs a soft-start voltage adapted to different modes, specifically, a steady-state peak current of K1 times is used as the first soft-start voltage V during the narrow-pulse mode low-frequency startup phase and the narrow-pulse mode volt-second balance frequency up-amplitude phase. comp1 In the complementary mode volt-second balance up-frequency phase, K2 times the steady-state peak current is used as the second soft-start voltage V. comp2 This can effectively improve the startup speed of the switching converter, and utilize the loop feedback voltage V FB With the first soft-start voltage V comp1 Second soft-start voltage V comp2 The competition mechanism ensures a smooth switching from the soft-start voltage to the loop feedback voltage to control the operation of the switching converter, reducing the current stress spikes of the main power transistor Q1 and the secondary rectifier transistor D4 caused by the switching.

[0101] Therefore, the present invention can improve the safety and reliability of switching converters employing clamped asymmetric half-bridge flyback topology.

[0102] Among them, the above-mentioned loop feedback voltage V FB With the first soft-start voltage V comp1 Second soft-start voltage V comp2 The competition mechanism is as follows: during the startup process, the loop feedback voltage V... FB With the first soft-start voltage V comp1 Second soft-start voltage V comp2 A comparison was made throughout the process. Since the output voltage Vo was not established at the initial startup, the loop feedback voltage V... FB It remains at its highest value, higher than the first soft-start voltage V. comp1 Second soft-start voltage V comp2 Therefore, the first soft-start voltage V during this stage comp1 Second soft-start voltage V comp2 Enter peak current closed-loop control. Until the output voltage Vo is established, the loop feedback voltage V... FB Below the first soft-start voltage V comp1 Second soft-start voltage V comp2 Loop feedback voltage V FB The switch takes over the operation of the control switch converter, thereby achieving a smooth switching between the soft-start voltage and the loop feedback voltage through a competition mechanism of "whoever has the lower voltage enters the loop".

[0103] Additionally: The control method of this invention can be achieved through... Figure 1 The control circuit shown includes: primary current detection, excitation winding voltage detection, volt-second balance calculation, peak current control module, operating frequency comparison module, PWM logic processing and drive waveform generation module.

[0104] The primary current detection circuit samples the excitation current i. Lm On one hand, the primary current signal enters the volt-second balance calculation module, where it is compared with zero to obtain the primary current zero-crossing signal, which serves as the starting point for the volt-second balance calculation. On the other hand, the primary current signal enters the peak current control module; the excitation winding voltage detection circuit samples the primary excitation winding voltage information V. Lm This data is input into the volt-second balance calculation module to calculate the zero-crossing time of the demagnetizing current and the volt-second balance frequency f. vs The volt-second balance module will calculate the volt-second balance frequency f. vs The input is fed into the frequency comparison module and compared with the given minimum clock frequency f. smin The current operating frequency f is obtained by comparison. s The output voltage detection circuit samples the output voltage Vo and the reference voltage V. ref The voltage compensation signal is obtained by comparing and amplifying the signal, and then input to the peak current control module. This voltage compensation signal is compared with the given first soft-start voltage V. comp1 Second soft-start voltage V comp2 Competition leads to peak current closed-loop control, from which the turn-off signal for the main power transistor Q1 is derived; the operating frequency f of the volt-second balance module... s The turn-off control signal of the main power transistor Q1 of the peak current module is processed by the PWM module logic to output the main power transistor Q1, auxiliary power transistor Q2 and clamping switch transistor Q3 driving signals VG_Q1, VG_Q2 and VG_Q3 driving signals, which are used to control the conduction and turn-off of the main power transistor Q1, auxiliary power transistor Q2 and clamping switch transistor Q3.

[0105] This invention is not limited to the specific embodiments described above. Based on the above content and in accordance with common technical knowledge and conventional methods in the field, without departing from the basic technical concept of this invention, this invention can also make other equivalent modifications, substitutions or alterations, all of which fall within the protection scope of this invention.

Claims

1. A control method of a switching converter, the switching converter adopting a clamped asymmetric half-bridge flyback topology comprising a main power tube (Q1), an auxiliary power tube (Q2), a resonant capacitor (Cr), a unidirectional diode (D2), a clamping switch tube (Q3), a transformer (T) and a secondary rectifier tube (D4); characterized in that: The switching converter is further provided with a bootstrap capacitor (C B ) and a charging circuit, the bootstrap capacitor (C B ) is connected between the gate and the source of the main power tube (Q1). the control method comprises sequentially: Step S1, when the switching converter is powered on, control the clamping asymmetric half-bridge flyback topology to enter the pre-charge phase of the bootstrap capacitor, that is, control the main power tube (Q1) to be turned off, the auxiliary power tube (Q2) to be turned on, the clamping switch tube (Q3) to be turned off, and control the charging circuit to charge the bootstrap capacitor (C B ) Step S2, when the voltage of the bootstrap capacitor (C B ) reaches the charging voltage (Vcc) capable of turning on the main power tube (Q1), after a first fixed dead time (T dead1 ) interval, control the clamping asymmetric half-bridge flyback topology to enter the narrow pulse mode low-frequency starting stage. In the narrow pulse mode low frequency start-up phase of step S2, the clamped asymmetric half-bridge flyback topology works periodically in the order of the first low frequency phase to the sixth low frequency phase with a fixed lowest clock frequency f smin , the first low frequency phase to the sixth low frequency phase in sequence periodically. in a first period of a low-frequency stage, controlling the main power tube (Q1) to be off, the auxiliary power tube (Q2) to be on, and the clamping switch tube (Q3) to be off in a first period of a first low-frequency stage; and the length of the first period of the low-frequency stage is 1 / 2 of a resonant period of a resonant circuit composed of the resonant capacitor (Cr) and a leakage inductance (Lr) of the transformer (T); In the low-frequency stage second period, the main power tube (Q1), the auxiliary power tube (Q2) and the clamping switch tube (Q3) are all controlled to be turned off; and the length of the low-frequency stage second period is a preset first fixed dead time (T dead1 ). In the third period of the low frequency stage, the main power tube (Q1) is controlled to be turned on, the auxiliary power tube (Q2) and the clamping switch tube (Q3) are both turned off; and the third period of the low frequency stage ends when the excitation current (i Lm ) of the transformer (T) reaches K1 times of the steady state peak current, K1 is a preset overcurrent multiple, and the steady state peak current is a peak value of the excitation current (i Lm ) of the transformer (T) when the switching converter is in a steady working state under a nominal input voltage and a rated output load. In the fourth period of the low-frequency stage, the main power tube (Q1), the auxiliary power tube (Q2) and the clamping switch tube (Q3) are all turned off; and the length of the fourth period of the low-frequency stage is a preset second fixed dead time (T dead2 ). in a fifth period of the low-frequency stage, controlling the auxiliary power tube (Q2) and the clamping switch tube (Q3) to be on, and the main power tube (Q1) to be off; and the length of the fifth period of the low-frequency stage is 3 / 4 of the resonant period; In the sixth period of the low-frequency stage, the main power tube (Q1) and the auxiliary power tube (Q2) are controlled to be turned off, and the clamping switch tube (Q3) is controlled to be kept on to the end time of the first period of the low-frequency stage of the next period; and the duration of the sixth period of the low-frequency stage is determined by the lowest clock frequency f smin The decision is calculated as follows: where n represents the turns ratio of the transformer (T), V D represents the voltage drop of the secondary rectifier diode (D4), I peak represents the peak value of the excitation current (i Lm ) of the transformer (T), and Lm represents the excitation inductance value of the transformer (T). Step S3, at the voltage-second balance frequency f vs above the minimum clock frequency f smin when, control the clamped asymmetric half-bridge flyback topology to enter the narrow pulse mode voltage-second balance frequency increasing phase; In the narrow pulse mode volt-second balance frequency boost phase of step S3, the clamped asymmetric half-bridge flyback topology works periodically in the order of the first period of the frequency boost phase to the sixth period of the frequency boost phase with a dynamically changed volt-second balance frequency f vs , the first period of the frequency boost phase to the sixth period of the frequency boost phase in sequence: In the first period of the frequency raising stage, the main power tube (Q1) is controlled to be turned off, the auxiliary power tube (Q2) is turned on, and the clamping switch tube (Q3) is turned off in the first period of the first frequency raising stage; and the duration of the first period of the frequency raising stage is the delay time and the maximum value of the delay time t d is limited to 1 / 2 of the resonance period; in the formula, Lm represents the excitation inductance value of the transformer (T), n represents the turn ratio of the transformer (T), V o represents the output voltage of the switching converter, I nset represents the negative current required for the main power tube (Q1) to realize zero voltage switching. In the second period of the frequency raising stage, the main power tube (Q1), the auxiliary power tube (Q2) and the clamping switch tube (Q3) are all turned off; and the length of the second period of the frequency raising stage is the first fixed dead time (T dead1 ). In the third period of the frequency raising stage, the main power tube (Q1) is controlled to be turned on, the auxiliary power tube (Q2) and the clamping switch tube (Q3) are both turned off; and the third period of the frequency raising stage ends when the excitation current (i Lm ) of the transformer (T) reaches K1 times of the steady-state peak current, K1 is a preset overcurrent multiple, and the steady-state peak current is a peak value of the excitation current (i Lm ) of the transformer (T) when the switching converter is in a steady working state under a nominal input voltage and a rated output load. In the fourth period of the frequency raising stage, the main power tube (Q1), the auxiliary power tube (Q2) and the clamping switch tube (Q3) are all turned off; and the length of the fourth period of the frequency raising stage is the second fixed dead time (T dead2 ). in a fifth period of a frequency-increasing stage, controlling the auxiliary power tube (Q2) and the clamping switch tube (Q3) to be on, and the main power tube (Q1) to be off; and the length of the fifth period of the frequency-increasing stage is 3 / 4 of the resonant period; In the sixth period of the frequency increasing stage, the main power tube (Q1) and the auxiliary power tube (Q2) are controlled to be turned off, and the clamping switch tube (Q3) is controlled to be kept on to the end time of the first period of the frequency increasing stage in the next period; and the sixth period of the frequency increasing stage ends at the demagnetizing current zero-crossing time, so that the clamping asymmetric half-bridge flyback topology operates at the volt-second balance frequency f vs . Working; wherein the demagnetizing current zero-crossing time is the time when the magnetizing current (i Lm ) of the transformer (T) drops to zero, the volt-second balance frequency f vs is the reciprocal of the time interval between adjacent two demagnetizing current zero-crossing times. Step S4, when the output voltage V o of the switching converter is raised to a preset set reference voltage V X , the current period of the narrow pulse mode volt-second balance step-up phase is ended, and after a first fixed dead time (T dead1 ), the control of the clamped asymmetric half-bridge flyback topology enters the complementary mode volt-second balance step-up phase. In the complementary mode volt-second balance step-up phase of step S4, the clamped asymmetric half-bridge flyback topology operates at a dynamically varying volt-second balance frequency f vs periodically in the order of a first complementary phase period to a fourth complementary phase period: In the first period of the complementary phase, the main power tube (Q1) and the auxiliary power tube (Q2) are both controlled to be turned off; and the length of the first period of the complementary phase is the first fixed dead time (T dead1 ). In the second period of the complementary phase, the main power tube (Q1) is controlled to be turned on, and the auxiliary power tube (Q2) is controlled to be turned off; and the second period of the complementary phase ends when the excitation current (i Lm ) of the transformer (T) reaches K2 times of the steady-state peak current, K2 is a preset overcurrent multiple, and K2 < K1. In the complementary phase third period, the main power tube (Q1) and auxiliary power tube (Q2) are controlled to be turned off; and the length of the complementary phase third period is the second fixed dead time (T dead2 ). in a fourth period of a complementary stage, controlling the main power tube (Q1) to be off, and the auxiliary power tube (Q2) to be on; and the length of the fourth period of the complementary stage delaying the delay time at the de-excitation current zero-crossing post-end, and t d the maximum value of the resonance period is limited to 1 / 2; and the clamping switch tube (Q3) remains off during the complementary mode volt-second balance up-conversion phase; Step S5, when the loop feedback voltage V FB is reduced to the second soft start voltage V comp2 , the control of the clamped asymmetric half-bridge flyback topology enters a stable working state; wherein the loop feedback voltage V FB is a voltage output by a loop compensator composed of a comparator and an error amplifier, two inputs of the comparator are respectively an output voltage V o of the switching converter and a preset reference voltage V ref , an input end of the error amplifier is connected to an output end of the comparator; the second soft start voltage V comp2 is a voltage value converted from a steady-state peak current by K2 times at a preset ratio.

2. The control method of the switching converter according to claim 1, characterized in that: in the step S3, the zero-crossing time of the demagnetizing current is calculated according to the volt-second balance theory.

3. The control method of the switching converter according to claim 1, characterized in that: The overcurrent multiples K1 and K2 are respectively 1.4 and 1.

2.

4. The control method of the switching converter according to any one of claims 1 to 3, characterized in that: The output end of the charging circuit is connected to the anode of a charging diode (D1), and the cathode of the charging diode (D1) is connected to the connection point of the main power tube (Q1) and a bootstrap capacitor (C B ); in the bootstrap capacitor pre-charging phase of step S1, the charging circuit charges the bootstrap capacitor (C pre ) to the charging voltage (Vcc) through a pre-charging pulse with a duration of T pre =(R dson +R pre )C B and a voltage of the charging voltage (Vcc); wherein T pre represents the duration of the pre-charging pulse, R pre represents the resistance value of the current-limiting resistor in series with the charging diode (D1) in the charging circuit, R dson represents the on-resistance of the auxiliary power tube (Q2), and C pre represents the capacitance of the bootstrap capacitor (C B ).

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