A half-bridge synchronous rectification integrated circuit and its control method

Abstract

The present invention provides a half-bridge synchronous rectification integrated circuit and a control method thereof, including a filtering circuit and a synchronous rectification circuit. The filtering circuit is connected to the power supply to be rectified and is connected to the synchronous rectification circuit. The synchronous rectification circuit includes a first synchronous rectification tube, a first hysteresis comparison circuit, a first logic control circuit, a second synchronous rectification tube, a second hysteresis comparison circuit, a second logic control circuit, and a driving circuit. The first logic control circuit is connected to the first hysteresis comparison circuit to control the switching of different working gears of the first hysteresis comparison circuit. The second logic control circuit is connected to the second hysteresis comparison circuit to control the switching of different working gears of the second hysteresis comparison circuit. The first logic control circuit and the second logic control circuit respectively control the conduction or cut-off of the first synchronous rectification tube and the second synchronous rectification tube through the driving circuit. The present invention integrates half-bridge rectification and synchronous rectification, and has a simple circuit structure, achieving the effects of improving the reliability of the circuit and reducing costs.

Description

Technical Field

[0001] The present invention relates to the field of power electronics technology, and particularly relates to a half-bridge synchronous rectification integrated circuit and a control method thereof. Background Art

[0002] With the development of power electronics technology and the increasing requirements of the market for the size and cost of rectification circuits, half-bridge rectification is increasingly widely used in medium and low power applications. Traditional half-bridge rectification circuits are generally composed of diodes connected to achieve the rectification function by using the unidirectional conductivity of diodes. However, due to the large forward voltage drop of diodes, the rectification efficiency is not high after rectification. Therefore, synchronous rectification is more widely used at present. Synchronous rectification uses transistors to replace diodes, turning on the transistors when the current flows forward and turning off the transistors when the current flows backward, so that the current is equivalent to the unidirectional flow of diodes, thereby achieving the rectification function. Since the on-resistance of transistors can be made very small, the efficiency of synchronous rectification will be improved. However, due to the switch control, a control circuit is required to generate the turn-on and turn-off timing of the transistors to ensure that there is no mis-triggering, so the design is relatively complex.

[0003] Disadvantages of the prior art:

[0004] 1: The traditional half-bridge circuit has a large size and high cost, and cannot adapt to the market development;

[0005] 1: The forward voltage drop of the diodes in the traditional half-bridge circuit is large, and the rectification efficiency is low;

[0006] 2: The synchronous rectification circuit needs to prevent the transistors from being mis-triggered, resulting in a complex control circuit.

[0007] Therefore, it is necessary to design a half-bridge synchronous rectification integrated circuit with high integration, high rectification efficiency, a simplified control circuit structure, low cost and high reliability. Summary of the Invention

[0008] A half-bridge synchronous rectification integrated circuit and a control method thereof provided by the present invention are mainly used to solve the problems of large size, high cost, low rectification efficiency of the traditional half-bridge rectification circuit, and complex synchronous rectification control circuit, so as to achieve the effects of integrating half-bridge rectification and synchronous rectification, improving rectification efficiency, simplifying the control circuit to reduce costs, and improving reliability.

[0009] The present invention achieves the above object through the following technical solutions:

[0010] A half-bridge synchronous rectification integrated circuit, comprising: a filtering circuit and a synchronous rectification circuit. The input end of the filtering circuit is connected to a power supply to be rectified, and its output end is connected to the synchronous rectification circuit. The synchronous rectification circuit includes a first synchronous rectification tube, a first hysteresis comparison circuit, a first logic control circuit, a second synchronous rectification tube, a second hysteresis comparison circuit, a second logic control circuit, and a driving circuit.

[0011] The first input end of the first synchronous rectification tube and the first input end of the first hysteresis comparison circuit are both connected to the first output end of the filtering circuit. The second input end of the first synchronous rectification tube and the second input end of the first hysteresis comparison circuit are both connected to a reference voltage signal. The first hysteresis comparison circuit outputs a first comparison level signal to the first logic control circuit. The first logic control circuit outputs a first turn-on hysteresis control signal and a first reset hysteresis control signal back to the first hysteresis comparison circuit to control the switching of different working gears of the first hysteresis comparison circuit. The first logic control circuit outputs a first rectification tube control signal to the driving circuit. The driving circuit amplifies the first rectification tube control signal and drives the first synchronous rectification tube to conduct or cut off.

[0012] The second input end of the second synchronous rectification tube and the second input end of the second hysteresis comparison circuit are both connected to the first output end of the filtering circuit. The first input end of the second synchronous rectification tube and the first input end of the second hysteresis comparison circuit are both grounded. The second hysteresis comparison circuit outputs a second comparison level signal to the second logic control circuit. The second logic control circuit outputs a second turn-on hysteresis control signal and a second reset hysteresis control signal back to the second hysteresis comparison circuit to control the switching of different working gears of the second hysteresis comparison circuit. The second logic control circuit outputs a second rectification tube control signal to the driving circuit. The driving circuit amplifies the second rectification tube control signal and drives the second synchronous rectification tube to conduct or cut off.

[0013] A further solution is that both the first logic control circuit and the second logic control circuit are timing control circuits.

[0014] A further solution is that the circuit structures of the first logic control circuit and the second logic control circuit are the same, including a turn-on control signal generation circuit, a reset control signal generation circuit, a turn-off control signal generation circuit, and a rectification tube control signal generation circuit.

[0015] A further solution is that the turn-on control signal generation circuit, the reset control signal generation circuit, and the turn-off control signal generation circuit are all connected to a comparison level signal. The output ends of the turn-on control signal generation circuit and the reset control signal generation circuit are both connected to the input ends of a 4th SR flip-flop for outputting a turn-on hysteresis control signal. The output ends of the reset control signal generation circuit and the turn-off control signal generation circuit are both connected to the input ends of a 5th SR flip-flop for outputting a reset hysteresis control signal.

[0016] A further solution is that the input end of the rectifier tube control signal generation circuit is respectively connected to the output ends of the turn-on control signal generation circuit, the reset control signal generation circuit, and the turn-off control signal generation circuit. The rectifier tube control signal generation circuit outputs a rectifier tube control signal to the drive circuit, and the rectifier tube control signal returns to the input ends of the turn-on control signal generation circuit, the reset control signal generation circuit, and the turn-off control signal generation circuit.

[0017] A further solution is that both the first logic control circuit and the second logic control circuit are provided with logic shielding to shield the situation where both the turn-on hysteresis control signal and the reset hysteresis control signal are at high level.

[0018] A further solution is that both the first hysteresis comparison circuit and the second hysteresis comparison circuit are provided with a turn-off gear, a reset gear, and a turn-on gear.

[0019] A control method for a half-bridge synchronous rectification integrated circuit, applied to the described half-bridge synchronous rectification integrated circuit, includes:

[0020] S1: When the circuit is powered on, the output voltage of the filter circuit is at a low level. At this time, both the first hysteresis comparison circuit and the second hysteresis comparison circuit are in the reset gear, and both the first synchronous rectifier tube and the second synchronous rectifier tube are turned off.

[0021] S2: When the voltage difference between the two input ends of the first hysteresis comparison circuit is less than the threshold of its reset gear, the output level of the first hysteresis comparison circuit changes from low to high. The first logic control circuit releases the turn-off lock and controls the first hysteresis comparison circuit to switch to the turn-on gear, and the output voltage of the first logic control circuit remains at a low level.

[0022] S3: The output voltage of the filter circuit gradually rises. When the voltage difference between the two input ends of the first hysteresis comparison circuit is greater than the threshold of its turn-on gear, the output level of the first hysteresis comparison circuit changes from high to low. At this time, the output level of the first logic control circuit changes from low to high, causing the drive circuit to drive the first synchronous rectifier tube to turn on, and the first hysteresis comparison circuit switches to the turn-off gear.

[0023] S4: The output voltage of the filtering circuit gradually decreases. When the voltage difference between the two input terminals of the first hysteresis comparator circuit is less than the threshold of its turn-off gear, the output level of the first hysteresis comparator circuit changes from low to high. At this time, the output level of the first logic control circuit changes from high to low, causing the drive circuit to drive the first synchronous rectifier tube to turn off. The first hysteresis comparator circuit switches to the reset gear. At this time, the output level of the first hysteresis comparator circuit changes from high to low, and the first logic control circuit is turned off and locked.

[0024] S5: When the voltage difference between the two input terminals of the second hysteresis comparator circuit is greater than the threshold of its reset gear, the output level of the second hysteresis comparator circuit changes from low to high. The second logic control circuit releases the turn-off lock and controls the second hysteresis comparator circuit to switch to the on gear. The output voltage of the second logic control circuit remains low.

[0025] S6: The output voltage of the filtering circuit gradually decreases, causing the voltage difference between the two input terminals of the second hysteresis comparator circuit to be less than the threshold of its on gear. The output level of the second hysteresis comparator circuit changes from high to low. At this time, the output level of the second logic control circuit changes from low to high, causing the drive circuit to drive the second synchronous rectifier tube to turn on. The second hysteresis comparator circuit switches to the off gear.

[0026] S7: The output voltage of the filtering circuit gradually increases. When the voltage difference between the two input terminals of the second hysteresis comparator circuit is greater than the threshold of its off gear, the output level of the second hysteresis comparator circuit changes from low to high. At this time, the output level of the second logic control circuit changes from high to low, causing the drive circuit to drive the second synchronous rectifier tube to turn off. The second hysteresis comparator circuit switches to the reset gear. At this time, the output level of the second hysteresis comparator circuit changes from high to low, and the second logic control circuit is turned off and locked.

[0027] S8: When the output current of the filtering circuit flows into the synchronous rectifier circuit in the positive direction, the process of S2 - S4 is repeated.

[0028] S9: When the output current of the filtering circuit flows out of the synchronous rectifier circuit in the reverse direction, the process of S5 - S7 is repeated.

[0029] A further solution is that when the output current of the filtering circuit flows into the synchronous rectifier circuit in the positive direction, since the voltage of the second input terminal of the second hysteresis comparator circuit is much higher than the voltage of its first input terminal, the on gear of the second hysteresis comparator circuit will not be triggered, and the second synchronous rectifier tube remains in the off state.

[0030] A further solution is that when the current of the filtering circuit flows out of the synchronous rectification circuit in the reverse direction, since the voltage difference between the two input terminals of the first hysteresis comparison circuit is always smaller than the threshold value of its turn-on gear, the turn-on gear of the first hysteresis comparison circuit will not be triggered, and the first synchronous rectification tube remains in the off state.

[0031] Therefore, the present invention has the following beneficial effects:

[0032] 1. The logic control circuit of the present invention has a simple structure and a turn-off locking function, thus ensuring that the transistor will not be mis-triggered;

[0033] 2. The present invention integrates half-bridge rectification and synchronous rectification, with a simple circuit structure and high integration;

[0034] 3. The half-bridge synchronous rectification integrated circuit of the present invention has high reliability and low cost.

[0035] Therefore, a half-bridge synchronous rectification integrated circuit and a control method thereof provided by the present invention integrate half-bridge rectification and synchronous rectification, achieving the effects of simple circuit structure, high reliability, high integration and low cost.

[0036] The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. Description of the Drawings

[0037] Figure 1 is a schematic diagram of a half-bridge synchronous rectification integrated circuit of the present invention;

[0038] Figure 2 is a schematic diagram of the logic control circuit of the present invention;

[0039] Figure 3 is a schematic diagram of the SR flip-flop of the present invention;

[0040] Figure 4 is a waveform diagram of the half-bridge synchronous rectification integrated circuit of the present invention. Specific Embodiments

[0041] To make the objectives, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are some, but not all, of the embodiments of the present invention. All other embodiments obtained by those of ordinary skill in the art based on the described embodiments of the present invention without creative efforts shall fall within the protection scope of the present invention.

[0042] An embodiment of a half-bridge synchronous rectification integrated circuit

[0043] See Figures 1-4, a half-bridge synchronous rectification integrated circuit according to the present invention includes: a filtering circuit 101 and a synchronous rectification circuit 100. The input end of the filtering circuit 101 is connected to the power supply to be rectified, and its output end is connected to the synchronous rectification circuit 100. The synchronous rectification circuit 100 includes a first synchronous rectification tube HS, a first hysteresis comparison circuit 10, a first logic control circuit 20, a second synchronous rectification tube LS, a second hysteresis comparison circuit 30, a second logic control circuit 40, and a driving circuit 50.

[0044] The first input end of the first synchronous rectification tube HS and the first input end of the first hysteresis comparison circuit 10 are both connected to the first output end of the filtering circuit 101. The second input end of the first synchronous rectification tube HS and the second input end of the first hysteresis comparison circuit 10 are both connected to the reference voltage signal VO. The first hysteresis comparison circuit 10 outputs a first comparison level signal VOUTH to the first logic control circuit 20. The first logic control circuit 20 outputs a first turn-on hysteresis control signal HSY_HA and a first reset hysteresis control signal HSY_HB back to the first hysteresis comparison circuit 10 to control the switching of different working gears of the first hysteresis comparison circuit 10. The first logic control circuit 20 outputs a first rectification tube control signal HS_ON to the driving circuit 50. The driving circuit 50 amplifies the first rectification tube control signal HS_ON and drives the first synchronous rectification tube HS to conduct or cut off.

[0045] The second input end of the second synchronous rectification tube LS and the second input end of the second hysteresis comparison circuit 30 are both connected to the first output end of the filtering circuit 101. The first input end of the second synchronous rectification tube LS and the first input end of the second hysteresis comparison circuit 30 are both grounded to VSS. The second hysteresis comparison circuit 30 outputs a second comparison level signal VOUTL to the second logic control circuit 40. The second logic control circuit 40 outputs a second turn-on hysteresis control signal HSY_LA and a second reset hysteresis control signal HSY_LB back to the second hysteresis comparison circuit 30 to control the switching of different working gears of the second hysteresis comparison circuit 30. The second logic control circuit 40 outputs a second rectification tube control signal LS_ON to the driving circuit 50. The driving circuit 50 amplifies the second rectification tube control signal LS_ON and drives the second synchronous rectification tube LS to conduct or cut off.

[0046] Specifically, the second output end of the filtering circuit 101 in this embodiment is grounded to VSS through a capacitor C1.

[0047] Specifically, the output end of the synchronous rectification circuit 100 in this embodiment is connected in parallel with an output filtering capacitor C0.

[0048] Wherein, one end of the filtering capacitor C0 is connected to the second input end of the first synchronous rectification tube HS, and the other end is grounded to VSS.

[0049] Specifically, the synchronous rectification circuit 100 of this embodiment further includes an internal power supply circuit 60 and a charge pump boost circuit 70. The internal power supply circuit 60 is used to supply power to the first hysteresis comparison circuit 10, the first logic control circuit 20, the second hysteresis comparison circuit 30, the second logic control circuit 40, and the charge pump boost circuit 70. The charge pump boost circuit 70 outputs a pumped-up power supply BST to supply power to the drive circuit 50.

[0050] In this embodiment, both the first logic control circuit 20 and the second logic control circuit 40 are timing control circuits.

[0051] In this embodiment, the circuit structures of the first logic control circuit 20 and the second logic control circuit 40 are the same, including a turn-on control signal generation circuit 21, a reset control signal generation circuit 22, a turn-off control signal generation circuit 23, and a rectifier control signal generation circuit 24.

[0052] In this embodiment, the turn-on control signal generation circuit 21, the reset control signal generation circuit 22, and the turn-off control signal generation circuit 23 are all connected to the comparison level signal VOUT. The output ends of the turn-on control signal generation circuit 21 and the reset control signal generation circuit 22 are both connected to the input ends of the 4th SR flip-flop SR4 for outputting the turn-on hysteresis control signal HSY_A. The output ends of the reset control signal generation circuit 22 and the turn-off control signal generation circuit 23 are both connected to the input ends of the 5th SR flip-flop SR5 for outputting the reset hysteresis control signal HSY_B.

[0053] Specifically, the comparison level signal VOUT of this embodiment is the first comparison level signal VOUTH or the second comparison level signal VOUTL.

[0054] Specifically, the turn-on hysteresis control signal HSY_A of this embodiment is the first turn-on hysteresis control signal HSY_HA or the second turn-on hysteresis control signal HSY_LA.

[0055] Specifically, the reset hysteresis control signal HSY_B of this embodiment is the first reset hysteresis control signal HSY_HB or the second reset hysteresis control signal HSY_LB.

[0056] Specifically, the turn-on control signal generation circuit 21 of this embodiment includes a first inverter I1, a third AND gate AN3, and a first SR flip-flop SR1. The first inverter I1 is connected to the comparison level signal VOUT. The output end of the first inverter I1 is connected to the first input end of the third AND gate AN3. The second input end of the third AND gate AN3 is connected to the turn-on hysteresis control signal HSY_A. The output end of the third AND gate AN3 is connected to the second input end S of the first SR flip-flop SR1.

[0057] Specifically, the reset control signal generating circuit 22 of this embodiment includes a second inverter I2, a fifth inverter I5, a second AND gate AN2, a first D flip-flop D1, and a second SR flip-flop SR2. The clock control terminal CLK of the first D flip-flop D1 is connected to the comparison level signal VOUT through the second inverter I2. Its reset terminal Reset is connected to the reset hysteresis control signal HSY_B through the fifth inverter I5. Its data terminal D is grounded. The output terminal Q of the first D flip-flop D1 is connected to the second input terminal of the second AND gate AN2. The first input terminal of the second AND gate AN2 is connected to the comparison level signal VOUT. Its output terminal is connected to the second input terminal S of the second SR flip-flop SR2.

[0058] Specifically, the turn-off control signal generating circuit 23 of this embodiment includes a third NOR gate NR3, a first AND gate AN1, a third inverter I3, and a third SR flip-flop SR3. The input terminals of the third NOR gate NR3 are respectively connected to the turn-on hysteresis control signal HSY_A and the reset hysteresis control signal HSY_B. Its output terminal is connected to the second input terminal of the first AND gate AN1. The first input terminal of the first AND gate AN1 is connected to the comparison level signal VOUT. Its output terminal is connected to the second input terminal S of the third SR flip-flop SR3.

[0059] In this embodiment, the input terminals of the rectifier control signal generating circuit 24 are respectively connected to the output terminals of the turn-on control signal generating circuit 21, the reset control signal generating circuit 22, and the turn-off control signal generating circuit 23. The rectifier control signal generating circuit 24 outputs a rectifier control signal S_ON to the drive circuit 50. The rectifier control signal S_ON is returned to the input terminals of the turn-on control signal generating circuit 21, the reset control signal generating circuit 22, and the turn-off control signal generating circuit 23.

[0060] Specifically, the rectifier control signal S_ON of this embodiment is a first rectifier control signal HS_ON or a second rectifier control signal LS_ON.

[0061] Specifically, the first input terminal R of the first SR flip-flop SR1 and the first input terminal R of the second SR flip-flop SR2 of this embodiment are both connected to the rectifier control signal S_ON. The third SR flip-flop SR3 is connected to the rectifier control signal S_ON through the third inverter I3.

[0062] Specifically, the rectifier control signal generating circuit 24 of this embodiment includes a fourth inverter I4, a fourth AND gate AN4, a second D flip-flop D2, and a sixth SR flip-flop SR6. The clock control terminal CLK of the second D flip-flop D2 is connected to the rectifier control signal S_ON through the fourth inverter I4. Its reset terminal Reset is connected to the output terminal Q of the second SR flip-flop SR2. Its data terminal D is grounded. The output terminal of the second D flip-flop D2 It is connected to the second input terminal of the fourth AND gate AN4. The first input terminal of the fourth AND gate AN4 is connected to the output terminal Q of the second SR flip-flop SR2. Its output terminal is connected to the second input terminal S of the sixth SR flip-flop SR6. The first input terminal R of the sixth SR flip-flop SR6 is connected to the output terminal Q of the third SR flip-flop SR3. The sixth SR flip-flop SR6 outputs a second rectifier control signal LS_ON to the drive circuit 50.

[0063] Among them, the first SR flip-flop, the second SR flip-flop, the third SR flip-flop, the fourth SR flip-flop, the fifth SR flip-flop, and the sixth SR flip-flop are all SR flip-flops with the same circuit structure, including a first NOR gate NR0, a second NOR gate NR1, and an inverter I0. The first input terminal of the first NOR gate NR0 is the input terminal R of the SR flip-flop. The first input terminal of the second NOR gate NR1 is the input terminal S of the SR flip-flop. The second input terminal of the first NOR gate NR0 is interlocked with the second input terminal of the second NOR gate NR1. The output terminal of the first NOR gate NR0 is connected to the input terminal of the inverter I0. The output terminal of the inverter I0 is the output terminal Q of the SR flip-flop. The output terminal of the second NOR gate NR1 is the output terminal of the SR flip-flop

[0064] Among them, the truth table of the SR flip-flop is as follows in Table (1):

[0065] S R Q 0 0 Remain unchanged 0 1 0 1 0 1 1 1 1

[0066] Table (1)

[0067] In this embodiment, both the first logic control circuit 20 and the second logic control circuit 40 are provided with logic shielding to shield the case where both the turn-on hysteresis control signal HSY_A and the reset hysteresis control signal HSY_B are at high level.

[0068] Specifically, the logic shielding of the first logic control circuit 20 in this embodiment is to prevent the first hysteresis comparison circuit 10 from having a new flip threshold.

[0069] Specifically, the logic shielding of the second logic control circuit 40 in this embodiment is to prevent the second hysteresis comparison circuit 40 from having a new flip threshold.

[0070] In this embodiment, both the first hysteresis comparison circuit 10 and the second hysteresis comparison circuit 30 are provided with an off gear, a reset gear, and an on gear.

[0071] Specifically, when the first hysteresis comparison circuit 10 or the second hysteresis comparison circuit 30 is in the off gear in this embodiment, both the turn-on hysteresis control signal HSY_A and the reset hysteresis control signal HSY_B are at low level, and the threshold of the off gear is 0 at this time.

[0072] Among them, when the voltage at the first input terminal of the first hysteresis comparison circuit 10 or the second hysteresis comparison circuit 30 is greater than the voltage at its second input terminal, the comparison level signal VOUT output therefrom is at a low level; when the voltage at the first input terminal of the first hysteresis comparison circuit 10 or the second hysteresis comparison circuit 30 is less than the voltage at its second input terminal, the comparison level signal VOUT output therefrom is at a high level.

[0073] Specifically, in this embodiment, when the first hysteresis comparison circuit 10 or the second hysteresis comparison circuit 30 is in the reset gear, the turn-on hysteresis control signal HSY_A is at a low level, and the reset hysteresis control signal HSY_B is at a high level. At this time, the threshold value of the reset gear is not 0.

[0074] Among them, when the voltage difference between the two input terminals of the first hysteresis comparison circuit 10 or the second hysteresis comparison circuit 30 is greater than the threshold value of the reset gear, the comparison level signal VOUT output therefrom is at a high level; when the voltage difference between the two input terminals of the first hysteresis comparison circuit 10 or the second hysteresis comparison circuit 30 is less than the threshold value of the reset gear, the comparison level signal VOUT output therefrom is at a low level.

[0075] Specifically, in this embodiment, when the first hysteresis comparison circuit 10 or the second hysteresis comparison circuit 30 is in the turn-on gear, the turn-on hysteresis control signal HSY_A is at a high level, and the reset hysteresis control signal HSY_B is at a low level. At this time, the threshold value of the turn-on gear is not 0. When the voltage difference between the two input terminals of the first hysteresis comparison circuit 10 or the second hysteresis comparison circuit 30 is greater than the threshold value of the turn-on gear, the comparison level signal VOUT output therefrom is at a low level; when the voltage difference between the two input terminals of the first hysteresis comparison circuit 10 or the second hysteresis comparison circuit 30 is less than the threshold value of the turn-on gear, the comparison level signal VOUT output therefrom is at a high level.

[0076] An embodiment of a control method for a half-bridge synchronous rectification integrated circuit

[0077] A control method for a half-bridge synchronous rectification integrated circuit according to the present invention is applied to the half-bridge synchronous rectification integrated circuit, and includes:

[0078] S1: When the circuit is powered on, the output voltage AC of the filter circuit 101 is at a low level. At this time, both the first hysteresis comparison circuit 10 and the second hysteresis comparison circuit 30 are in the reset gear, and both the first synchronous rectifier tube HS and the second synchronous rectifier tube LS are turned off.

[0079] Specifically, in this embodiment, the output level HS_ON of the first logic control circuit 20 is at a low level.

[0080] Specifically, in this embodiment, the output level LS_ON of the second logic control circuit 40 is at a low level.

[0081] Specifically, the third AND gate AN3 in this embodiment outputs a low level to the second input terminal S of the first SR flip-flop SR1, causing the output ON of the first SR flip-flop SR1 to remain at the initial low level unchanged. The second AND gate AN2 outputs a low level, causing the output RST of the second SR flip-flop SR2 to remain at the initial low level unchanged. Therefore, the output HYS_A of the fourth SR flip-flop SR4 also remains at a low level unchanged. The output of the third inverter I3 is high, and the output of the first AND gate AN1 is low, causing the output OFF of the third SR flip-flop SR3 to be low. Therefore, the output HYS_B of the fifth SR flip-flop SR5 remains at a low level unchanged. The output of the fourth AND gate AN4 is low. Therefore, the output S_ON of the sixth SR flip-flop SR6 remains at the initial low level unchanged. At this time, both the first hysteresis comparison circuit 10 and the second hysteresis comparison circuit 30 are in the off gear.

[0082] Among them, when both the first hysteresis comparison circuit 10 and the second hysteresis comparison circuit 30 are in the off gear, the output VOUT_H of the first hysteresis comparison circuit 10 and the output VOUT_L of the second hysteresis comparison circuit 30 are high. The output of the first inverter I1 is low, and the output of the third AND gate AN3 is low. Also, since the output level HS_ON of the first logic control circuit 20 and the output level LS_ON of the second logic control circuit 40 are both low at this time, the output ON of the first SR flip-flop SR1 remains at a low level unchanged. The output of the fifth inverter I5 is high, the output of the first D flip-flop D1 is low, and the output of the second AND gate AN2 is low. Therefore, the output RST of the second SR flip-flop SR2 remains at a low level unchanged. So, the output HYS_A of the fourth SR flip-flop SR4 remains at a low level unchanged. The output of the third AND gate NR3 is high, and the output of the first AND gate AN1 is high. Therefore, the output OFF of the third SR flip-flop SR3 becomes high, and the output HYS_B of the fifth SR flip-flop SR5 becomes high. The output of the fourth AND gate AN4 remains low. So, the output S_ON of the sixth SR flip-flop SR6 remains at a low level. At this time, both the first hysteresis comparison circuit 10 and the second hysteresis comparison circuit 30 are in the reset gear.

[0083] Among them, after the first hysteresis comparison circuit 10 and the second hysteresis comparison circuit 30 are in the reset gear, since the threshold value of the reset gear is larger than the threshold value of the off gear (about 0), the output VOUT_H of the first hysteresis comparison circuit 10 and the output VOUT_L of the second hysteresis comparison circuit 30 will change back to low level again. The output of the second inverter I2 changes from low level to high level, and the output of the first D flip-flop D1 becomes high.

[0084] S2: When the voltage difference between the two input terminals of the first hysteresis comparator circuit 10 is less than the threshold value of its reset gear, the output level VOUTH of the first hysteresis comparator circuit 10 changes from low to high, the first logic control circuit 20 releases the turn-off lock, and controls the first hysteresis comparator circuit 10 to switch to the on gear, and the output voltage HS_ON of the first logic control circuit 20 remains low.

[0085] Specifically, the output of the third AND gate AN3 in this embodiment is low, so the output ON of the first SR flip-flop SR1 remains low. The output of the second AND gate AN2 becomes high, so the output RST of the second SR flip-flop SR2 becomes high, and thus the output HSY_HA of the fourth SR flip-flop SR4 becomes high. The output of the third NAND gate NR3 is low, and the output of the first AND gate AN1 is low, so the output OFF of the third SR flip-flop SR3 remains low, and thus the output HYS_HB of the fifth SR flip-flop SR5 becomes low. The output of the fourth AND gate AN4 remains low, so the output HS_ON of the sixth SR flip-flop SR6 remains low. At this time, the first hysteresis comparator circuit 10 switches to the on gear.

[0086] S3: The output voltage AC of the filter circuit 101 gradually rises. When the voltage difference between the two input terminals of the first hysteresis comparator circuit 10 is greater than the threshold value of its on gear, the output level VOUTH of the first hysteresis comparator circuit 10 changes from high to low. At this time, the output level HS_ON of the first logic control circuit 20 changes from low to high, enabling the drive circuit 50 to drive the first synchronous rectifier HS to turn on, and the first hysteresis comparator circuit 10 switches to the off gear.

[0087] Specifically, the output of the first inverter I1 in this embodiment becomes low, and the output of the third AND gate AN3 becomes high, so the output ON of the first SR flip-flop SR1 becomes high. The output level of the second inverter I2 changes from low to high, and the output of the fifth inverter I5 is high, so the output of the first D flip-flop D1 becomes high. The output of the second AND gate AN2 is low, and at this time the output RST of the second SR flip-flop SR2 remains high, so the output HYS_HA of the fourth SR flip-flop SR4 remains high. The output of the first AND gate AN1 is low, and at this time the output OFF of the third SR flip-flop SR3 remains low, so the output HSY_HB of the fifth SR flip-flop SR5 remains low. The output of the second D flip-flop D2 is high, and the output of the fourth AND gate AN4 becomes high, so the output HS_ON of the sixth SR flip-flop SR6 becomes high. At this time, the drive circuit 50 drives the first synchronous rectifier HS to turn on.

[0088] Among them, after the output HS_ON of the 6th SR flip-flop SR6 becomes high level, the output RST of the 2nd SR flip-flop SR2 becomes low level, and the output OFF of the 3rd SR flip-flop SR3 remains low level. Since the output ON of the 1st SR flip-flop SR1 is high level, the output HSY_HA of the 4th SR flip-flop SR4 becomes low level, and the output HSY_HB of the 5th SR flip-flop SR5 remains low level. At this time, the first hysteresis comparison circuit 10 switches to the off gear.

[0089] S4: The output voltage AC of the filter circuit 101 gradually decreases. When the voltage difference between the two input terminals of the first hysteresis comparison circuit 10 is less than the threshold value of its off gear, the output level VOUTH of the first hysteresis comparison circuit 10 changes from low to high. At this time, the output level HS_ON of the first logic control circuit 20 changes from high to low, so that the drive circuit 50 drives the first synchronous rectifier tube HS to turn off, and the first hysteresis comparison circuit 10 switches to the reset gear. At this time, the output level VOUTH of the first hysteresis comparison circuit 10 changes from high to low, and the first logic control circuit 20 is turned off and locked.

[0090] Specifically, the output of the 1st inverter I1 in this embodiment becomes low level, and the output of the 3rd AND gate AN3 becomes low level. Therefore, the output ON of the 1st SR flip-flop SR1 becomes low level. The output of the 1st D flip-flop D1 remains low level, and the output of the 2nd AND gate AN2 is low level. Therefore, the output RST of the 2nd SR flip-flop SR2 remains low level, so the output HYS_HA of the 4th SR flip-flop SR4 remains low level; the output of the 3rd NOR gate NR3 is high level, and the output of the 1st AND gate AN1 becomes high level. Therefore, the output OFF of the 3rd SR flip-flop SR3 becomes high level, so the output HYS_HB of the SR flip-flop SR5 becomes high level. The output of the 4th AND gate AN4 becomes low level, and the output HS_ON of the 6th SR flip-flop SR6 becomes low level. At this time, the first hysteresis comparison circuit 10 switches to the reset gear.

[0091] Among them, after the output HS_ON of the 6th SR flip-flop SR6 becomes low level, the output level of the 4th inverter I4 changes from low to high. Therefore, the output of the 2nd D flip-flop D2 becomes low level, and the output of the 4th AND gate AN4 becomes low level. At this time, the first logic control circuit 20 is turned off and locked.

[0092] S5: When the voltage difference between the two input terminals of the second hysteresis comparison circuit 30 is greater than the threshold value of its reset gear, the output level VOUTL of the second hysteresis comparison circuit 30 changes from low to high. The second logic control circuit 40 releases the off lock and controls the second hysteresis comparison circuit 30 to switch to the on gear. The output voltage LS_ON of the second logic control circuit 40 remains low level.

[0093] Specifically, the output of the third AND gate AN3 in this embodiment is at a low level. Therefore, the output ON of the first SR flip-flop SR1 remains at a low level. The output of the second AND gate AN2 becomes high. Therefore, the output RST of the second SR flip-flop SR2 becomes high, so the output HSY_LA of the fourth SR flip-flop SR4 becomes high. The output of the third AND gate NR3 is low, and the output of the first AND gate AN1 is low. Therefore, the output OFF of the third SR flip-flop SR3 remains at a low level, so the output HYS_LB of the fifth SR flip-flop SR5 becomes low. The output of the fourth AND gate AN4 remains low, so the output LS_ON of the sixth SR flip-flop SR6 remains low. At this time, the first hysteresis comparator circuit 30 switches to the on state.

[0094] S6: As the output voltage AC of the filter circuit 101 gradually decreases, when the voltage difference between the two input terminals of the second hysteresis comparator circuit 30 is less than the threshold value of its on state, the output level VOUTL of the second hysteresis comparator circuit 30 changes from high to low. At this time, the output level LS_ON of the second logic control circuit 40 changes from low to high, causing the drive circuit 50 to drive the second synchronous rectifier LS to turn on, and the second hysteresis comparator circuit 30 switches to the off state.

[0095] Specifically, the output of the first inverter I1 in this embodiment becomes low, and the output of the third AND gate AN3 becomes high. Therefore, the output ON of the first SR flip-flop SR1 becomes high. The output level of the second inverter I2 changes from low to high, and the output of the fifth inverter I5 is high. Therefore, the output of the first D flip-flop D1 becomes high, and the output of the second AND gate AN2 is low. At this time, the output RST of the second SR flip-flop SR2 remains high, so the output HYS_LA of the fourth SR flip-flop SR4 remains high. The output of the first AND gate AN1 is low, and at this time, the output OFF of the third SR flip-flop SR3 remains low, so the output HSY_LB of the fifth SR flip-flop SR5 remains low. The output of the second D flip-flop D2 is high, and the output of the fourth AND gate AN4 becomes high. Therefore, the output LS_ON of the sixth SR flip-flop SR6 becomes high, and at this time, the drive circuit 50 drives the second synchronous rectifier LS to turn on.

[0096] Among them, after the output LS_ON of the sixth SR flip-flop SR6 becomes high, the output RST of the second SR flip-flop SR2 becomes low, and the output OFF of the third SR flip-flop SR3 remains low. Since the output ON of the first SR flip-flop SR1 is high, the output HYS_LA of the fourth SR flip-flop SR4 becomes low, and the output HSY_LB of the fifth SR flip-flop SR5 remains low. At this time, the second hysteresis comparator circuit 30 switches to the off state.

[0097] S7: The output voltage AC of the filter circuit 101 gradually rises. When the voltage difference between the two input terminals of the second hysteresis comparator circuit 30 is greater than the threshold value of its turn-off gear, the output level VOUTL of the second hysteresis comparator circuit 30 changes from low to high. At this time, the output level LS_ON of the second logic control circuit 40 changes from high to low, causing the drive circuit 50 to drive the second synchronous rectifier tube LS to turn off. The second hysteresis comparator circuit 30 switches to the reset gear. At this time, the output level VOUTL of the second hysteresis comparator circuit 30 changes from high to low, and the second logic control circuit 40 shuts off and locks.

[0098] Specifically, in this embodiment, the output of the first inverter I1 becomes low level, and the output of the third AND gate AN3 becomes low level. Therefore, the output ON of the first SR flip-flop SR1 becomes low level. The output of the first D flip-flop D1 remains low level, and the output of the second AND gate AN2 is low level. Therefore, the output RST of the second SR flip-flop SR2 remains low level. So, the output HYS_LA of the fourth SR flip-flop SR4 remains low level; the output of the third NOR gate NR3 is high level, and the output of the first AND gate AN1 becomes high level. Therefore, the output OFF of the third SR flip-flop SR3 becomes high level. So, the output HYS_HB of the SR flip-flop SR5 becomes high level. The output of the fourth AND gate AN4 becomes low level, and the output LS_ON of the sixth SR flip-flop SR6 becomes low level. At this time, the second hysteresis comparator circuit 40 switches to the reset gear.

[0099] Among them, after the output LS_ON of the sixth SR flip-flop SR6 becomes low level, the output level of the fourth inverter I4 changes from low to high. Therefore, the output of the second D flip-flop D2 becomes low level, and the output of the fourth AND gate AN4 becomes low level. At this time, the second logic control circuit 40 shuts off and locks.

[0100] S8: When the output current of the filter circuit 101 flows into the synchronous rectifier circuit 100 in the positive direction, the processes of S2 - S4 are repeated;

[0101] Specifically, in this embodiment, when the reset gear of the first hysteresis comparator circuit 10 is triggered again, after the output RST of the second SR flip-flop SR2 of the first logic control circuit 20 becomes high level, the first logic control circuit 20 releases the shut-off lock.

[0102] S9: When the output current of the filter circuit 101 flows out of the synchronous rectifier circuit 100 in the reverse direction, the processes of S5 - S7 are repeated.

[0103] Specifically, in this embodiment, when the reset gear of the second hysteresis comparator circuit 30 is triggered again, after the output RST of the second SR flip-flop SR2 of the second logic control circuit 40 becomes high level, the second logic control circuit 40 releases the shut-off lock.

[0104] In this embodiment, when the output current of the filter circuit 101 flows into the synchronous rectification circuit 100 in the positive direction, since the voltage AC at the second input terminal of the second hysteresis comparison circuit 30 is much higher than the voltage VSS at its first input terminal, the on state of the second hysteresis comparison circuit 30 will not be triggered, and the second synchronous rectification diode LS remains in the off state.

[0105] In this embodiment, when the current of the filter circuit 101 flows out of the synchronous rectification circuit 100 in the reverse direction, since the voltage difference between the two input terminals of the first hysteresis comparison circuit 10 is always less than the threshold value of its on state, the on state of the first hysteresis comparison circuit 10 will not be triggered, and the first synchronous rectification diode HS remains in the off state.

[0106] The above embodiments are only the preferred embodiments of the present invention, and the scope of protection of the present invention cannot be limited thereby. Any non-substantial changes and substitutions made by those skilled in the art based on the present invention belong to the scope of protection required by the present invention.

Claims

1. A half-bridge synchronous rectification integrated circuit, comprising a filtering circuit and a synchronous rectification circuit. The input end of the filtering circuit is connected to a power supply to be rectified, and its output end is connected to the synchronous rectification circuit. It is characterized in that, The synchronous rectification circuit includes: a first synchronous rectifier tube, a first hysteresis comparison circuit, a first logic control circuit, a second synchronous rectifier tube, a second hysteresis comparison circuit, a second logic control circuit, and a drive circuit; A first input end of the first synchronous rectifier tube and a first input end of the first hysteresis comparison circuit are both connected to a first output end of the filter circuit. A second input end of the first synchronous rectifier tube and a second input end of the first hysteresis comparison circuit are both connected to a reference voltage signal. The first hysteresis comparison circuit outputs a first comparison level signal to the first logic control circuit. The first logic control circuit outputs a first turn-on hysteresis control signal and a first reset hysteresis control signal back to the first hysteresis comparison circuit to control the switching of different operating gears of the first hysteresis comparison circuit. The first logic control circuit outputs a first rectifier tube control signal to the drive circuit, and the drive circuit amplifies the first rectifier tube control signal and drives the first synchronous rectifier tube to conduct or cut off; A second input end of the second synchronous rectifier tube and a second input end of the second hysteresis comparison circuit are both connected to a first output end of the filter circuit. A first input end of the second synchronous rectifier tube and a first input end of the second hysteresis comparison circuit are both grounded. The second hysteresis comparison circuit outputs a second comparison level signal to the second logic control circuit. The second logic control circuit outputs a second turn-on hysteresis control signal and a second reset hysteresis control signal back to the second hysteresis comparison circuit to control the switching of different operating gears of the second hysteresis comparison circuit. The second logic control circuit outputs a second rectifier tube control signal to the drive circuit, and the drive circuit amplifies the second rectifier tube control signal and drives the second synchronous rectifier tube to conduct or cut off.

2. The half-bridge synchronous rectification integrated circuit according to claim 1, wherein: Both the first logic control circuit and the second logic control circuit are timing control circuits.

3. The half-bridge synchronous rectification integrated circuit according to claim 2, wherein: The circuit structures of the first logic control circuit and the second logic control circuit are the same, and include a turn-on control signal generation circuit, a reset control signal generation circuit, a turn-off control signal generation circuit, and a rectifier tube control signal generation circuit.

4. The half-bridge synchronous rectification integrated circuit according to claim 3, wherein: The turn-on control signal generation circuit, the reset control signal generation circuit, and the turn-off control signal generation circuit are all connected to a comparison level signal. Output ends of the turn-on control signal generation circuit and the reset control signal generation circuit are both connected to input ends of a 4th SR flip-flop for outputting a turn-on hysteresis control signal. Output ends of the reset control signal generation circuit and the turn-off control signal generation circuit are both connected to input ends of a 5th SR flip-flop for outputting a reset hysteresis control signal.

5. The half-bridge synchronous rectification integrated circuit according to claim 4, wherein: The input end of the rectifier tube control signal generation circuit is respectively connected to the output ends of the turn-on control signal generation circuit, the reset control signal generation circuit, and the turn-off control signal generation circuit. The rectifier tube control signal generation circuit outputs a rectifier tube control signal to the drive circuit, and the rectifier tube control signal returns to the input ends of the turn-on control signal generation circuit, the reset control signal generation circuit, and the turn-off control signal generation circuit.

6. The half-bridge synchronous rectification integrated circuit according to claim 5, characterized in that: Both the first logic control circuit and the second logic control circuit are provided with logic shielding to shield the situation where both the turn-on hysteresis control signal and the reset hysteresis control signal are at high level.

7. The half-bridge synchronous rectification integrated circuit according to claim 1, characterized in that: Both the first hysteresis comparison circuit and the second hysteresis comparison circuit are provided with a turn-off gear, a reset gear, and a turn-on gear.

8. A control method for a half-bridge synchronous rectification integrated circuit, characterized in that, Applied to a half-bridge synchronous rectification integrated circuit according to any one of claims 1 to 7, including: S1: When the circuit is powered on, the output voltage of the filter circuit is at a low level. At this time, both the first hysteresis comparison circuit and the second hysteresis comparison circuit are in the reset gear, and both the first synchronous rectifier tube and the second synchronous rectifier tube are turned off; S2: When the voltage difference between the two input ends of the first hysteresis comparison circuit is less than the threshold value of its reset gear, the output level of the first hysteresis comparison circuit changes from low to high. The first logic control circuit releases the turn-off lock and controls the first hysteresis comparison circuit to switch to the turn-on gear, and the output voltage of the first logic control circuit remains at a low level; S3: The output voltage of the filter circuit gradually rises. When the voltage difference between the two input ends of the first hysteresis comparison circuit is greater than the threshold value of its turn-on gear, the output level of the first hysteresis comparison circuit changes from high to low. At this time, the output level of the first logic control circuit changes from low to high, so that the drive circuit drives the first synchronous rectifier tube to turn on, and the first hysteresis comparison circuit switches to the turn-off gear; S4: The output voltage of the filter circuit gradually decreases. When the voltage difference between the two input ends of the first hysteresis comparison circuit is less than the threshold value of its turn-off gear, the output level of the first hysteresis comparison circuit changes from low to high. At this time, the output level of the first logic control circuit changes from high to low, so that the drive circuit drives the first synchronous rectifier tube to turn off, and the first hysteresis comparison circuit switches to the reset gear. At this time, the output level of the first hysteresis comparison circuit changes from high to low, and the first logic control circuit turns off the lock; S5: When the voltage difference between the two input ends of the second hysteresis comparison circuit is greater than the threshold value of its reset gear, the output level of the second hysteresis comparison circuit changes from low to high. The second logic control circuit releases the turn-off lock and controls the second hysteresis comparison circuit to switch to the turn-on gear, and the output voltage of the second logic control circuit remains at a low level; S6: When the output voltage of the filtering circuit gradually decreases and the voltage difference between the two input terminals of the second hysteresis comparator circuit is less than the threshold value of its on state, the output level of the second hysteresis comparator circuit changes from high to low. At this time, the output level of the second logic control circuit changes from low to high, enabling the driving circuit to drive the second synchronous rectifier to turn on, and the second hysteresis comparator circuit switches to the off state; S7: When the output voltage of the filtering circuit gradually increases and the voltage difference between the two input terminals of the second hysteresis comparator circuit is greater than the threshold value of its off state, the output level of the second hysteresis comparator circuit changes from low to high. At this time, the output level of the second logic control circuit changes from high to low, enabling the driving circuit to drive the second synchronous rectifier to turn off, and the second hysteresis comparator circuit switches to the reset state. At this time, the output level of the second hysteresis comparator circuit changes from high to low, and the second logic control circuit is turned off and locked; S8: When the output current of the filtering circuit flows into the synchronous rectification circuit in the forward direction, the process of S2 - S4 is repeated; S9: When the output current of the filtering circuit flows out of the synchronous rectification circuit in the reverse direction, the process of S5 - S7 is repeated.

9. The control method of the half - bridge synchronous rectification integrated circuit according to claim 8, wherein: When the current of the filtering circuit flows out of the synchronous rectification circuit in the reverse direction, since the voltage difference between the two input terminals of the first hysteresis comparator circuit is always less than the threshold value of its on state, the on state of the first hysteresis comparator circuit will not be triggered, and the first synchronous rectifier remains in the off state.

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