A high precision self-zeroing comparator

Abstract

The application belongs to the technical field of semiconductor and integrated circuit, and particularly relates to a high-precision self-zeroing comparator. The comparator comprises a first-stage preamplifier and a second-stage latch, wherein the first-stage preamplifier comprises an amplifier circuit and a self-zeroing circuit; the amplifier circuit amplifies signals and improves signal-to-noise ratio; and the self-zeroing circuit reduces comparator offset voltage and reduces comparator flicker noise; the second-stage latch comprises a latch formed by two inverters and serves as an output stage to output digital code words. The comparator provided by the application can significantly improve noise and precision performance of the comparator by using the self-zeroing technology, and does not need an additional amplifier circuit, thereby saving area and power consumption consumed by the self-zeroing technology.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor and integrated circuit technology, and specifically relates to a high-precision self-zero comparator. Background Technology

[0002] With the development of Internet of Things (IoT) technology, the performance of Successive Approximation Register (SAR) analog-to-digital converters (ADCs) has been continuously improved due to the advancement of process nodes, attracting widespread attention and research. As the core circuit of SAR ADC circuits, the performance of the comparator often limits the upper limit of the entire system's performance. Therefore, designing a low-noise, high-precision comparator has become a challenge in circuit design.

[0003] Traditional comparators such as Figure 1 As shown, it consists of a preamplifier and a latch. The preamplifier mainly amplifies the input signal to a detectable range, while the latch mainly determines whether the amplified signal outputs a high or low level. However, due to manufacturing limitations, a mismatch may occur between the transistors receiving the input signal during manufacturing, resulting in an offset voltage V at the input. os Furthermore, due to the inherent current noise of the transistor, a noise voltage V also exists at the input. n . Summary of the Invention

[0004] To address the above technical problems, this invention proposes a high-precision comparator that employs self-zeroing technology to reduce input offset voltage and input voltage noise.

[0005] The technical solution of this invention is:

[0006] A high-precision self-zero comparator is characterized by comprising a cascaded first-stage preamplifier, a bridge switch, and a second-stage latch.

[0007] The first-stage preamplifier comprises a first input amplifier, a first self-zeroing circuit and a second self-zeroing circuit; the first input amplifier comprises a current source, a first PMOS transistor MP1, a second PMOS transistor MP2, a third PMOS transistor MP3, a fourth PMOS transistor MP4, a reset switch, a second NMOS transistor MN2, a third NMOS transistor MN3, a fourth NMOS transistor MN4 and a fifth NMOS transistor MN5; the source of the first PMOS transistor MP1 is connected to the current source, the gate thereof is connected to the positive input terminal of a comparator, and the drain thereof is connected to the source of the third PMOS transistor MP3; the source of the second PMOS transistor MP2 is connected to the current source, the gate thereof is connected to the negative input terminal of the comparator, and the drain thereof is connected to the source of the fourth PMOS transistor MP4; the gates of the third PMOS transistor MP3 and the fourth PMOS transistor MP4 are connected to a bias voltage, the drain of the third PMOS transistor MP3 is connected to one end of the reset switch, the drain and the gate of the second NMOS transistor MN2 and the gate of the fourth NMOS transistor MN4; the drain of the fourth PMOS transistor MP4 is connected to the other end of the reset switch, the drain and the gate of the fifth NMOS transistor MN5 and the gate of the third NMOS transistor MN3; the sources of the second NMOS transistor MN2, the third NMOS transistor MN3, the fourth NMOS transistor MN4 and the fifth NMOS transistor MN5 are connected to ground;

[0008] The first self-zeroing circuit comprises a first switch, a first sampling capacitor and a first NMOS transistor MN1; one end of the first switch is connected to the drain of the first NMOS transistor MN1 and the drain of the third PMOS transistor MP3, the other end of the first switch is connected to the gate of the first NMOS transistor MN1 and one end of the first sampling capacitor; the other end of the first sampling capacitor and the source of the first NMOS transistor MN1 are connected to ground;

[0009] The second self-zeroing circuit comprises a second switch, a second sampling capacitor and a sixth NMOS transistor MN6; one end of the second switch is connected to the drain of the sixth NMOS transistor MN6 and the drain of the fourth PMOS transistor MP4, the other end of the second switch is connected to the gate of the sixth NMOS transistor MN6 and one end of the second sampling capacitor; the other end of the second sampling capacitor and the source of the sixth NMOS transistor MN1 are connected to ground;

[0010] The bridge switch comprises a third switch and a fourth switch; one end of the third switch is connected to the drain of the third PMOS transistor MP3, and one end of the fourth switch is connected to the drain of the fourth PMOS transistor MP4;

[0011] The second-stage latch comprises a first inverter and a second inverter; the input terminal of the first inverter is connected to the other end of the third switch and the output terminal of the second inverter, which is defined as a first connection point; the input terminal of the second inverter is connected to the output terminal of the first inverter and the other end of the fourth switch, which is defined as a second connection point; the first connection point and the second connection point are respectively the differential output terminals of the comparator;

[0012] The control signals for the third and fourth switches are the inverted signals of the reset switch control signal.

[0013] The beneficial effects of this invention are as follows: This invention proposes a high-precision self-zero comparator. Addressing the problems of offset voltage and voltage noise that cannot be solved in traditional comparators, this invention employs self-zero technology. By introducing a self-zero phase during idle periods, it collects the comparator's own offset voltage and low-frequency voltage noise and stores them on the sampling capacitor. During normal comparator operation, the offset voltage caused by manufacturing processes and the noise of the device itself will cancel out the error collected on the sampling capacitor, thereby reducing offset voltage and low-frequency noise. Furthermore, compared to traditional comparators, the second stage of this invention also adopts a latch structure, introducing positive feedback, which can greatly reduce comparison time and improve circuit operating speed. Attached Figure Description

[0014] Figure 1 This is a block diagram of a traditional comparator.

[0015] Figure 2 This is a comparator circuit.

[0016] Figure 3 This is the timing diagram of the comparator state. Detailed Implementation

[0017] The invention will now be further described with reference to the accompanying drawings.

[0018] like Figure 2 As shown, the comparator of this invention includes a first preamplifier, a bridge switch, a latch, and a reset signal generation module. The reset circuit of the first preamplifier is controlled by the reset signal RST, and the bridge switch is controlled by the inverse RST_N of the reset signal. The first preamplifier includes a first-stage two-input two-output small-signal amplifier, a self-zeroing circuit, and a reset circuit. The reset circuit is placed between the output ports of the first-stage preamplifier, ensuring that the voltage difference at the output nodes is zero during the reset phase, thus reducing the charging time during the next comparison. The self-zeroing circuit is placed at the output port of the first-stage preamplifier and can detect offset voltage and low-frequency noise stored in capacitor C during the self-zeroing period. az This allows for the cancellation of offset voltage and low-frequency noise during the comparison process.

[0019] The first-stage two-input two-output small-signal amplifier includes an input differential pair transistor, a tail current source, and a load circuit. Figure 2As shown, the source and tail current source IDC output port of the input differential pair tube MP1 and MP2 are connected, the drain of the input differential pair tube MP1 and MP2 are connected with the source of the third PMOS and the fourth PMOS respectively to form a common source and common gate structure, and the output gain is improved. The load circuit includes the second to fifth NMOS, and the cross-coupled circuit structure can improve the output resistance. The drain of the third PMOS and the fourth PMOS is connected with the drain of the second to fifth NMOS. The effect can amplify the input voltage and improve the signal-to-noise ratio.

[0020] The self-zeroing circuit includes a switch AZ1, a switch AZ2, a sampling capacitor C az1 , a sampling capacitor C az2 , a first NMOS and a fifth NMOS. One end of the switch AZ1 is connected with the P port of the first two-input two-output small signal amplifier, and the other end is connected with one end of the sampling capacitor C az1 and the gate of the first NMOS. One end of the switch AZ2 is connected with the P port of the first two-input two-output small signal amplifier, and the other end is connected with one end of the sampling capacitor C az2 and the gate of the fifth NMOS. The beneficial effect is that the differential offset voltage and differential voltage noise can be stored in the sampling capacitor during the self-zeroing period

[0021] The bridge switch is arranged between the first preamplifier and the latch, one end of the bridge switch is connected with the differential output port of the first preamplifier, and the other end is connected with the differential input port of the latch. The beneficial effect is that the self-zeroing and reset states isolate the first preamplifier and the latch, and prevent the noise of the latch from being coupled to the input port.

[0022] The latch is a positive feedback circuit composed of two back-to-back inverters, and the beneficial effect is to improve the comparison speed.

[0023] As shown in Figure 3 , the working state waveform diagram of the comparator, it can be seen from the figure that the comparator has three states.

[0024] The comparator first enters the self-zeroing state, the self-zeroing signal AZ is high, the self-zeroing circuit switches AZ1 and AZ2 are closed, the reset signal RST is low, the reset circuit switch is opened, the input signal is shorted to the common mode voltage of the circuit, and the capacitors C az1 and C az2 in the self-zeroing circuit collect the offset voltage and low-frequency noise of the amplifier itself.

[0025] Then enter the reset stage, the self-zeroing signal AZ is low, the self-zeroing circuit switch is opened, and due to the charge conservation theorem of the capacitor, C az1 and C az2The offset voltage and low frequency voltage noise of the storage amplifier itself are reset, and the reset signal RST is high and RST_N is low, the reset switch of the reset circuit is closed, the switch of the bridge switch is opened, the signal is reset, and the charging during comparison is reduced.

[0026] Finally, the comparison stage is entered, the auto-zero signal AZ is low, the switch of the auto-zero circuit is opened, the reset signal RST is low and RST_N is high, the reset switch of the reset circuit is opened, the offset voltage and low frequency noise stored in the auto-zero circuit are converted into currents through the second NMOS and the sixth NMOS and summed at the output node of the first preamplifier, the offset voltage and low frequency noise stored are offset with the offset voltage and low frequency noise of the device itself. The switch of the bridge switch is closed, the first preamplifier and the latch are connected, and the latch completes the latching of the output signal through the positive feedback mechanism.

Claims

1. A high-precision self-zero comparator, characterized in that, It includes a cascaded first-stage preamplifier (100), a bridge switch (300), and a second-stage latch (200); The first-stage preamplifier includes a first input amplifier (110), a first self-zeroing circuit (120), and a second self-zeroing circuit (130); the first input amplifier (110) includes a current source, a first PMOS transistor MP1, a second PMOS transistor MP2, a third PMOS transistor MP3, a fourth PMOS transistor MP4, a reset switch, a second NMOS transistor MN2, a third NMOS transistor MN3, a fourth NMOS transistor MN4, and a fifth NMOS transistor MN5; the source of the first PMOS transistor MP1 is connected to the current source, its gate is the positive input terminal of the comparator, and its drain is connected to the source of the third PMOS transistor MP3; The source of the second PMOS transistor MP2 is connected to a current source, its gate is the negative input terminal of the comparator, and its drain is connected to the source of the fourth PMOS transistor MP4. The gates of the third PMOS transistor MP3 and the fourth PMOS transistor MP4 are connected to a bias voltage. The drain of the third PMOS transistor MP3 is connected to one end of the reset switch, the drain and gate of the second NMOS transistor MN2, and the gate of the fourth NMOS transistor MN4. The drain of the fourth PMOS transistor MP4 is connected to the other end of the reset switch, the drain and gate of the fifth NMOS transistor MN5, and the gate of the third NMOS transistor MN3. The sources of the second NMOS transistor MN2, the third NMOS transistor MN3, the fourth NMOS transistor MN4, and the fifth NMOS transistor MN5 are grounded. The first self-reset circuit (120) includes a first switch, a first sampling capacitor and a first NMOS transistor MN1; one end of the first switch is connected to the drain of the first NMOS transistor MN1 and the drain of the third PMOS transistor MP3, and the other end of the first switch is connected to the gate of the first NMOS transistor MN1 and one end of the first sampling capacitor; the other end of the first sampling capacitor and the source of the first NMOS transistor MN1 are grounded. The second self-reset circuit (130) includes a second switch, a second sampling capacitor and a sixth NMOS transistor MN6; one end of the second switch is connected to the drain of the sixth NMOS transistor MN6 and the drain of the fourth PMOS transistor MP4, and the other end of the second switch is connected to the gate of the sixth NMOS transistor MN6 and one end of the second sampling capacitor; the other end of the second sampling capacitor and the source of the sixth NMOS transistor MN6 are grounded. The bridging switch (300) includes a third switch and a fourth switch; one end of the third switch is connected to the drain of the third PMOS transistor MP3, and one end of the fourth switch is connected to the drain of the fourth PMOS transistor MP4. The second-stage latch (200) includes a first inverter and a second inverter; the input terminal of the first inverter is connected to the other end of the third switch and the output terminal of the second inverter, which is defined as the first connection point; the input terminal of the second inverter is connected to the output terminal of the first inverter and the other end of the fourth switch, which is defined as the second connection point; the first connection point and the second connection point are the differential output ports of the comparator, respectively. The control signals for the third and fourth switches are the inverted signals of the reset switch control signal; The first switch and the second switch are controlled by a self-zeroing control signal AZ. During the self-zeroing phase, the self-zeroing control signal AZ is at a high level, causing the first switch and the second switch to close. During the reset and comparison phase, the self-zeroing control signal AZ is at a low level, causing the first switch and the second switch to open.

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