A calibratable output mismatched folded interpolation architecture adc preamplifier array circuit

Abstract

The application provides a pre-amplifier array circuit of a fold interpolation architecture ADC with calibratable output offset, which comprises a calibration logic control circuit, a reference voltage DAC, a calibration current DAC circuit and a pre-amplifier array circuit; each amplifier of the pre-amplifier array circuit is connected in parallel with a positive output calibration resistor at a differential positive output end and a negative output calibration resistor at a negative output end; the calibration logic control circuit is used for generating a reference voltage signal V c <n:0>and comparing the V c <n:0>Output V of the ADC core o <n:0>and a reference voltage signal V c <n:0>, to obtain the calibration vector D <n:0>The calibration vector D is calculated as follows: <n:0>conversion into misalignment calibration control code Q0 <n:0> ‑Q m <n:0>The calibration current steering DAC circuit generates a differential current signal related to the calibration vector, which is injected into the calibration resistor after being scaled and mirrored to compensate for the error of the output of the pre-amplifier.< / n:0> < / n:0>

Description

TECHNICAL FIELD

[0001] The application relates to a fold-interpolation architecture ADC pre-amplifier array circuit capable of calibrating output offset, and belongs to the technical field of digital-analog hybrid integrated circuits. BACKGROUND

[0002] With the rapid development of digital processing technology, there is an urgent need for higher speed and higher precision ADCs, and a fold-interpolation architecture ADC inherits the high-speed characteristics of a full-parallel ADC, and meanwhile reduces the number of comparators in the circuit, so the fold-interpolation architecture ADC becomes one of the preferred architectures for designing ultra-high-speed ADCs. Since the fold-interpolation ADC is a full open-loop structure, the precision is extremely sensitive to process deviation. Meanwhile, under the condition of process size reduction and power voltage reduction, the mismatch problem is one of the difficulties in circuit design. Therefore, a calibration technology needs to be introduced to compensate for non-ideal factors such as offset error, so as to ensure the realization of high-precision performance.

[0003] The pre-amplifier is an important structure for processing the input signal and the reference voltage in the first stage in the fold-interpolation structure, and the zero-crossing point generated by the pre-amplifier corresponds to high-bit quantization information. The fold circuit can make the zero-crossing points of the folded signals merge and shift, and through the subsequent interpolation circuit, phase-shifted folded signals and zero-crossing points that can be used for secondary quantization are generated, and the quantization information of subsequent stages is gradually reduced. At present, a continuous-time automatic zero-reset technology is used to eliminate the offset of the pre-amplifier. The calibration mode adopts analog domain calibration, and there is a certain limitation in precision improvement, and is suitable for ADC design below 8 bits. SUMMARY

[0004] The technical problem of the application is to overcome the shortcomings of the prior art, and provide a fold-interpolation architecture ADC pre-amplifier array circuit capable of calibrating output offset, which compensates for the error of the output of the pre-amplifier and improves the precision of the ADC.

[0005] The technical scheme of the application is a fold-interpolation architecture ADC pre-amplifier array circuit capable of calibrating output offset, which comprises a calibration logic control circuit, a reference voltage DAC, a calibration current DAC circuit and a pre-amplifier array circuit.

[0006] The pre-amplifier array circuit is used for generating reference zero-crossing points and preliminarily realizing the coarse quantization process of the input signal. The differential positive output end of each amplifier of the pre-amplifier array circuit is connected in parallel with the positive output end calibration resistor, and the negative output end is connected in parallel with the negative output end calibration resistor.

[0007] The calibration logic control circuit is used for generating a reference voltage signal V c <n:0>The output V of the ADC core is sent to a reference voltage DAC and compared o <n:0>and a reference voltage signal V c <n:0>D = D - (D - D0) difference, to obtain the calibration vector D <n:0>, the calibration vectors D <n:0>Converting into the misalignment calibration control code Q0 for each amplifier in the preamplifier array circuit <n:0> -Q m <n:0>; the reference voltage signal is the expected output signal of the ADC core corresponding to when the ADC input is a 0V voltage signal, and n+1 is the number of bits of the ADC;

[0008] The reference reference voltage DAC outputs a reference voltage signal V c <n:0>converted into a differential analog signal and output to the differential input terminal of the ADC;

[0009] a mismatch calibration control code Q0 for calibrating the logic control circuit <n:0> -Q m <n:0>The input end of the calibration current steering DAC is connected, the calibration current steering DAC circuit controls the turn-on and turn-off of the MOS transistor through the offset calibration control code, generates a differential current signal related to the calibration vector, and the differential current signal is injected into the calibration resistor after proportional mirroring to compensate for the error of the output of the preamplifier.

[0010] Preferably, the preamplifier array circuit comprises amplifiers preamp_0-preamp_m, negative output end current mirrors CMN0-CMNm, positive output end current mirrors CMP0-CMPm, negative output end calibration resistors RON0-RONm, positive output end calibration resistors ROP0-ROPm, annular average negative offset resistors RN0-RNm and annular average positive offset resistors RP0-RPm, the annular average negative offset resistor RN0 is connected with the annular average positive offset resistor RPm, the annular average positive offset resistor RP0 is connected with the annular average negative offset resistor RNm, and an annular resistor string is formed;

[0011] The analog input positive end signal Vip is connected to the positive phase input end of the amplifiers preamp_0-preamp_m;

[0012] The analog input negative end signal Vin is connected to the negative phase input end of the amplifiers preamp_0-preamp_m;

[0013] The i-th reference voltage signal Vref a differential comparison positive input terminal of the connection amplifier preamp_i;

[0014] an mth reference voltage signal Vref <m-i>the differential negative input of the amplifier preamp_i;

[0015] the negative output current mirror CMNi is connected to the negative output calibration resistor RONi, which is connected to the differential negative output Von of the amplifier preamp_i ;

[0016] The positive output current mirror CMPi is connected to a positive output trim resistor ROPi, which is connected to the differential negative phase output Von of the amplifier preamp_i ;

[0017] Calibration control current Ip and In Calibrate the output of the preamplifier preamp_i, i = 0 to m + 1;

[0018] The differential negative phase output terminal Von of the amplifier preamp_i connected between the annular average negative bias resistance RNi and the annular average negative bias resistance RNi+1;

[0019] a differential positive phase output terminal Vop of the amplifier preamp_i Connected between the ring average positive offset resistor RP i and the ring average positive offset resistor RP i+1.

[0020] Preferably, the calibration logic control circuit comprises a counter, a decoder, a register circuit, a calibration algorithm module; wherein:

[0021] The counter, the input end is connected with reset signal Rst and clock signal CP, the reset signal Rst is zeroed to the counter, and the counter is counted on the clock rising edge, and the output is m1+1 bit count value S <m1:0>;

[0022] a calibration algorithm module that compares the output V o <n:0>and a reference voltage signal V c <n:0>D = D - (D - D0) = D0 <n:0>D = D + D <n:0>to the register circuit;

[0023] a decoder to decode the weighted count value S <m1:0>transforming the (m+1) -bit unweighted digital code Z into a (m+1) -bit weighted digital code Z <m:0>, and output to a register circuit;

[0024] The register circuit comprises m+1 shift register groups each consisting of n+1 registers, the bit width of each shift register group is n+1, and the jth shift register group is represented by a digital code Z <m:0>Z at the jth position of the n-mer of SEQ ID NO: 1 <j>As a calibration clock signal, the jth shift register group is clocked by a calibration clock signal Z <j>under the control of the calibration vector D <n:0>Shifted output gives n+1 bit misalignment calibration control code Q j <n:0>j = 0 ~ m.

[0025] Preferably, the decoder converts the m1+1-bit binary number into a decimal number, and sets the decimal number to 1 in the corresponding position and 0 in the rest of the positions.

[0026] Preferably, the number of bits of the count value output by the counter is not less than [log2(m+1)], where [ ] is the rounding symbol.

[0027] Preferably, the calibration current steering DAC circuit comprises 2(m+1) calibration current steering DAC units, including (m+1) positive calibration current steering units and (m+1) negative calibration current steering units; the jth positive current steering unit is configured to output a positive calibration current according to Q j <n:0>, output differential current positive signal Ip1 <j>; the jth negative current steering cell pair according to Q j <n:0>Output differential current negative signal In1 <j>, j = 0 ~ m.

[0028] Preferably, the output of the positive calibration current steering unit and the negative calibration current steering unit are:

[0029]

[0030] Wherein, I represents the current in a single MOS tube.

[0031] Preferably, the positive calibration current Ip The negative output terminal calibration resistor RONi, the negative calibration current In The positive output end calibration resistor ROPi compensates for the unbalanced voltage flowing through the pre-amplifier array, i=0~m.

[0032] Preferably, the positive calibration current Ip<0:m> and the negative calibration current In<0:m> are in the order of microamperes.

[0033] Preferably, the resistance values of the negative output end calibration resistors RON0- RONm and the positive output end calibration resistors ROP0- ROPm are in the order of hundreds of ohms.

[0034] Compared with the prior art, the present application has the following advantages:

[0035] (1) The pre-amplifier array circuit with calibratable output unbalance provided by the present application can generate a differential output current signal through the current steering DAC controlled by the calibration logic control circuit, and the current signal can be proportionally imaged and injected into the calibration resistor to realize error compensation for the output unbalance of the pre-amplifier.

[0036] (2) The calibration logic control circuit provided by the present application can generate multiple non-overlapping calibration clocks Z<0:m>, and under the control of the calibration clock, the output unbalance of each pre-amplifier can be calibrated in sequence, which can effectively prevent the adjacent pre-amplifiers from interfering with each other during calibration and realize accurate calibration.

[0037] (3) The current steering DAC circuit provided by the present application adopts a binary search algorithm to generate a digital compensation code value, which can find the accurate input control code value of the current steering DAC circuit in a short clock period, and has a small design complexity.

[0038] (4) The unbalance calibration circuit in the digital-analog hybrid domain has important research significance and application value. BRIEF DESCRIPTION OF DRAWINGS

[0039] Figure 1 FIG. 1 is a structure schematic diagram of the pre-amplifier array circuit with calibratable output unbalance according to an embodiment of the present application;

[0040] Figure 2 FIG. 2 is a structure schematic diagram of the calibration logic control circuit according to an embodiment of the present application;

[0041] Figure 3 FIG. 3 is a structure schematic diagram of the register circuit according to an embodiment of the present application;

[0042] Figure 4 FIG. 4 is a structure schematic diagram of the calibration current steering DAC circuit according to an embodiment of the present application;

[0043] Figure 5 FIG. 5 is a structure schematic diagram of the pre-amplifier array circuit according to an embodiment of the present application. DETAILED DESCRIPTION

[0044] The present invention will be described in further detail below with reference to the accompanying drawings and specific embodiments:

[0045] Example:

[0046] like Figure 1 As shown, the present invention provides a pre-amplifier array circuit capable of calibrating output offset, the circuit comprising a calibration logic control circuit, a reference voltage DAC, a calibration current steering DAC circuit and a pre-amplifier array circuit.

[0047] The pre-amplifier array circuit is used to generate a reference zero-crossing point (the intersection of the differential output signal of the pre-amplifier is called the zero-crossing point), initially realize the coarse quantization process of the input signal, realize the comparison function of the input signal and the reference voltage, and at the same time amplify the difference between the input signal and the reference voltage signal. The differential positive output terminal of each amplifier in the pre-amplifier array circuit is connected in parallel to the positive output calibration resistor, and the negative output terminal is connected in parallel to the negative output calibration resistor; the differential input terminal of the pre-amplifier receives the analog input signal Vip, the analog input signal Vin and the reference voltage Vref <m:0>The gain of the pre-amplifier circuit can suppress the offset of the DAC post-stage circuit and reduce the settling time of the post-stage circuit. <m:0>and Von <m:0>To programmably adjust the output of a preamplifier array circuit.

[0048] Calibration logic control circuit for generating a reference voltage signal V c <n:0>The output V of the ADC core is sent to a reference voltage DAC and compared o <n:0>and a reference voltage signal V c <n:0>D = D - (D - D0) = D0 <n:0>, in turn, the calibration vector D <n:0>Converted to the offset calibration control code Q0 for each amplifier in the preamplifier array circuit <n:0> -Q m <n:0>; the reference voltage signal is the expected output signal of the ADC core corresponding to when the ADC input is a 0V voltage signal, and n+1 is the number of bits of the ADC;

[0049] The reference reference voltage DAC outputs a reference voltage signal V c <n:0>converted into a differential analog signal and output to the differential input of the ADC.

[0050] a misalignment calibration control code Q0 of the calibration logic control circuit <n:0> -Q m <n:0>The input end of the calibration current steering DAC is connected, and the calibration current steering DAC circuit generates a differential current signal related to the calibration vector by controlling the turn-on and turn-off of the MOS transistor according to the offset calibration control code, and the differential current signal is injected into the calibration resistor after proportional mirroring to perform error compensation on the output of the preamplifier.

[0051] As shown in Figure 2 The calibration logic control circuit includes a counter, a decoder, a register circuit, and a calibration algorithm module.

[0052] The counter has an input end connected to a flip-flop reset signal Rst and a clock signal CP, the flip-flop reset signal Rst clears the counter, the counter counts the clock at the rising edge of the clock, and outputs an m1+1-bit count value S <m1:0>; the number of bits of the count value output by the counter is not less than [log2(m+1)], where [ ] is the rounding symbol. S <m1:0>Calibration for selecting individual preamplifiers in a preamplifier array

[0053] a calibration algorithm module comparing the output V o <n:0>and a reference voltage signal V c <n:0>D = D - (D - D0) difference, to obtain the calibration vector D <n:0>The calibration vector D is calculated as follows: <n:0>to the register circuit;

[0054] a decoder to decode the weighted count value S output by the counter <m1:0>transforming the (m+1) -bit unweighted digital code Z into a (m+1) -bit weighted digital code Z <m:0>, output to register circuit; digital code Z without weight <m:0>For the calibration of the sampling rate and the like, the calibration of the output offset of each preamplifier can be performed in turn under the control of the rising edge of the calibration clock;

[0055] The register circuit comprises m+1 shift register groups composed of n+1 registers, the bit width of each shift register group is n+1, the jth shift register group is represented by a digital code Z <m:0>The jth Z <j>As a calibration clock signal, the jth shift register group is clocked by a calibration clock signal Z <j>under the control of the calibration vector D <n:0>The shift output gets an n+1 bit misalignment calibration control code Q j <n:0>j = 0 ~ m, a total of m + 1 n + 1 bit misalignment calibration control code Q0 <n:0> -Q m <n:0>As shown in Figure 3

[0056] The calibration logic control circuit generates calibration clock by m1+1 bit counter and m1+1 bit decoder, when the clock signal of the control of a preamplifier calibration is "1", the output offset of the preamplifier is calibrated, while the calibration clock signal of other preamplifiers is "0", waiting for calibration or has completed calibration. In order to prevent adjacent preamplifiers from interfering during calibration, it is necessary to require that the m+1 calibration clock signals do not overlap each other.

[0057] Preferably, the decoder converts m1+1 bit binary number into decimal number, and sets the rest to 0 corresponding to position 1.

[0058] Preferably, the calibration current DAC circuit includes 2(m+1) calibration current DAC units, including (m+1) positive calibration current DAC units and (m+1) negative calibration current DAC units; the jth positive current DAC unit is controlled by Q j <n:0>, output differential current positive signal Ip1 <j>; the jth negative current steering cell pair is enabled according to Q j <n:0>output differential current negative signal In1 <j>, j = 0 ~ m.

[0059] Preferably, the output of the positive calibration current steering unit and the negative calibration current steering unit is:

[0060]

[0061] Wherein, I represents the current in a single MOS tube. The current value of the output of the positive calibration current steering unit and the negative calibration current steering unit is determined by binary search method, and has redundant bits of low 2 bits, which can realize accurate compensation of error. <n-1>is the n-1th bit of Q, Q <n>The nth bit of Q.

[0062] When the pre-amplifier differential output is offset, the current steering DAC calibration circuit should generate a differential output current, so the current steering DAC_P and current steering DAC_N should be designed. When the current steering DAC circuit is used for error compensation, its compensation accuracy and compensation range should meet the pre-amplifier output offset. The compensation accuracy refers to the minimum current of compensation, which can also be regarded as the maximum error allowed by the pre-amplifier output after calibration. The compensation range refers to the maximum error current of calibration. Once the range is exceeded, the error compensation system cannot provide enough compensation voltage to offset the offset error in the actual circuit. According to the large calibration range, a 6-bit current steering DAC circuit is designed to realize the calibration of the pre-amplifier output offset. When designing the 6-bit segmented current steering DAC circuit, the "4+2" segmented form is adopted, that is, the combination of 4-bit thermometer code controlled unit current source and 2-bit binary code controlled weighted current source. When calibrating each pre-amplifier, in order to find the corresponding current steering DAC circuit digital compensation code value, the binary search algorithm is adopted. The current steering DAC default value is half of the entire calibration range, that is, the highest bit digital code is 1 and the rest is 0. After calibration, the output open signal of the error detection system is used to determine the current output code value. If the error detection system output open is 0, the high bit digital code does not change, the next high bit digital code changes from 0 to 1, and the rest remains unchanged. If the error detection system output open is 1, the high bit digital code changes from 1 to 0, the next high bit digital code changes from 0 to 1. The step length of the current steering DAC circuit changes every time is half of the last time. This method can find the accurate current steering DAC circuit input control code value in a short clock cycle.

[0063] As shown in Figure 4 , the calibration current steering DAC_N circuit is used to control the generation of a pre-amplifier calibration vector, and the calibration current steering DAC circuit includes n+1 inverters, 2 n-1 +1 control switches and 2 n-1 +1 PMOS tubes;

[0064] The control switch is a two-way selection switch, which includes a control end, an output end, a first branch end and a second branch end. The control end is used to select the connection of the output end with the first branch end or the second branch end. Q <n:1>is an input control signal, the binary input digital code is inverted by the inverter to produce the inverse code QN <n:1>wherein Q <n:0>and QN <n:0>are produced, respectively, by the following reactions: <m:0>and In <m:0>The control word is then applied to the switches. The control word QN<1> controls switch SW1, QN<2> controls switches SW2 and SW3, QN<3> controls switches SW4-SW7, QN <n-2>Control SW2 n-3 -SW2 n-2 -1, QN <n-1>Control SW2 n-2 , QN <n>Control SW2 n-2 +1, SW1-SW2 n-2 +1 According to the binary arrangement, one end of SW1 is connected to the input of SW2 n (n = {1, 2, …, n-3}) is connected, and the other end is connected to the input of SW2 n -1 (n = {2, …, n-2}) is connected, and the control code QN<1:n-2> controls the current array with the same weight, and the current size is I, QN <n-1>The signal directly controls a current of size I, QN <n>The signal also directly controls a current of size I as a redundant calibration current.

[0065] For example, n = 6, it is composed of 6 inverters, 17 control switches SW1-SW17 and PMOS M1-M17. Q<1:6> is the input control signal, the binary input digital code is inverted to generate the inverse code QN<1:6>, and then the switches are controlled according to the weight.

[0066] The first branch ends of control switches SW1, SW2, SW4, SW8, SW16, and SW17 are commonly connected to the ground, and the second branch ends of control switches SW1, SW3, SW7, SW15, SW16, and SW17 are commonly connected to the power supply; the second branch ends of control switches SW2, SW5, and SW11 and the first branch ends of control switches SW3, SW6, and SW12 are connected to the output end of control switch SW1; the second branch ends of control switches SW4 and SW9 and the first branch ends of control switches SW5 and SW10 are connected to the output end of control switch SW2, and the second branch ends of control switches SW6 and SW13 and the first branch ends of control switches SW7 and SW14 are connected to the output end of control switch SW3; the second branch end of control switch SW8 and the first branch end of control switch SW9 are connected to the output end of control switch SW4, the second branch end of control switch SW10 and the first branch end of control switch SW11 are connected to the output end of control switch SW5, the second branch end of control switch SW12 and the first branch end of control switch SW13 are connected to the output end of control switch SW6, and the second branch end of control switch SW14 and the first branch end of control switch SW15 are connected to the output end of control switch SW7. SW1-SW17 correspond to the gate signals of M8, M4, M12, M2, M6, M10, M14, M1, M3, M5, M7, M9, M11, M13, M15, M16, and M17, respectively.

[0067] Thus, when the control code QN<0> = 0 controls the first branch end of SW1 to be conductive, no matter what values QN<1> ~ QN<5> are, the two branch ends and the output end of the control switches SW2, SW4, SW5, SW8, SW9, SW10, SW11 are connected to the ground, at this time M1 ~ M8 are all conductive; when the control code QN<0> = 1 controls the second branch end of SW1 to be conductive, no matter what values QN<1> ~ QN<5> are, the two branch ends and the output end of the control switches SW3, SW6, SW7, SW12, SW13, SW14, SW15 are connected to the power supply, at this time M8 ~ M15 are all cut off; the bisection of the first stage is realized, and the control method of the control switches SW2 ~ SW15 is similar by analogy, the control switches SW16, SW17 control the currents of M16, M17 alone as a redundant branch. That is, the high 4-bit control code QN<6:3> controls 15 current arrays with the same weight, the current size is I, the QN<2> signal directly controls a current with the size of I, and the QN<1> signal also directly controls a current with the size of I.

[0068] As shown in Figure 5 The preamplifier array circuit includes amplifiers preamp_0 ~ preamp_m, negative output end current mirrors CMN0-CMNm, positive output end current mirrors CMP0-CMPm, negative output end calibration resistors RON0-RONm, positive output end calibration resistors ROP0-ROPm, annular average negative offset resistors RN0-RNm and annular average positive offset resistors RP0-RPm, the annular average negative offset resistor RN0 is connected with the annular average positive offset resistor RPm, the annular average positive offset resistor RP0 is connected with the annular average negative offset resistor RNm, forming a ring-shaped resistor string;

[0069] The analog input positive end signal Vip is connected to the positive phase input end of the amplifiers preamp_0-preamp_m;

[0070] The analog input negative end signal Vin is connected to the negative phase input end of the amplifiers preamp_0-preamp_m;

[0071] The reference voltage signal Vref a differential comparison positive input terminal of the connection amplifier preamp_i;

[0072] a reference voltage signal Vref <m-i>the differential negative input of the amplifier preamp_i;

[0073] the negative output current mirror CMNi is connected to the negative output calibration resistor RONi, which is connected to the differential negative output Von of the amplifier preamp_i ;

[0074] The positive output current mirror CMPi is connected to a positive output trim resistor ROPi, which is connected to the differential negative phase output Von of the amplifier preamp_i ;

[0075] Calibration control current Ip and In The output of the preamplifier preamp_i is calibrated, i = 0 ~ m + 1; the differential negative phase output terminal Von of the amplifier preamp_i connected between the annular average negative bias resistance RNi and the annular average negative bias resistance RNi+1;

[0076] a differential positive phase output terminal Vop of the amplifier preamp_i connected between the ring average positive offset resistors RP i and RP i+1, i = 0 ~ m;

[0077] For example: the ring average offset resistors RN0-RNm and RP0-RPm are connected in turn to the output signals of two adjacent preamplifiers, one end of the preamplifier preamp_0 is connected to RN0 and RN1, and the other end is connected to RP0 and RP1; one end of the preamplifier preamp_1 is connected to RN1 and RN2, and the other end is connected to RP1 and RP2; one end of the preamplifier preamp_m is connected to RNm and RN0, and the other end is connected to RPm and RP0.

[0078] The preamplifier is located at the front end of the quantization path, and mainly realizes two functions in the entire folding interpolation A / D converter. The first is to generate a reference zero crossing point, realize the coarse quantization process of the input signal, and complete the comparison of the input signal and the reference voltage. The second is to realize the amplification of the signal, and the gain of the amplifier can effectively suppress the offset of the circuit, while reducing the setup time of the post-stage preprocessing circuit of the ADC, and ensuring the post-stage preprocessing of the ADC. The differential output end VOP of the preamplifier array <m:0>and VOM <m:0>The output of the preamplifier array circuit is programmed to adjust the output imbalance.

[0079] Preferably, the positive calibration current Ip The negative output terminal calibration resistor RONi, the negative calibration current In The positive output end calibration resistors ROPi compensate for the offset voltage of the preamplifier array, i=0~m. The greater the resistance of RON0-RONm and ROP0-ROPm, the greater the compensation range and the lower the compensation accuracy. Therefore, the resistance is designed to be a compromise between the compensation range and the compensation accuracy. Preferably, the positive calibration current Ip<0:m> and the negative calibration current In<0:m> are in the order of microamperes. Preferably, the resistance of the negative output end calibration resistors RON0-RONm and the positive output end calibration resistors ROP0-ROPm is in the order of hundreds of ohms.

[0080] Although the present application has been disclosed with reference to the preferred embodiments thereof, it is not intended to limit the application, and any person skilled in the art can make possible changes and modifications to the technical solutions of the present application using the methods and technical contents disclosed above without departing from the spirit and scope of the present application. Therefore, any simple modification, equivalent change and modification made to the above embodiments according to the technical essence of the present application, which does not depart from the technical solutions of the present application, shall fall within the protection scope of the present application. < / n> < / n> < / n> < / j> < / j> ​ < / n:0> < / j> < / j> < / n:0> < / n:0> < / j> < / j> < / j> < / j> < / n:0> < / n:0>

Claims

1. A folding interpolation architecture ADC pre-amplifier array circuit capable of calibrating output offset, characterized in that It includes a calibration logic control circuit, a reference voltage DAC, a calibration current steering DAC circuit and a pre-amplifier array circuit; The pre-amplifier array circuit is used to generate a reference zero-crossing point and preliminarily implement a coarse quantization process of the input signal. The differential positive output terminal of each amplifier in the pre-amplifier array circuit is connected in parallel to the positive output calibration resistor, and the negative output terminal is connected in parallel to the negative output calibration resistor. Calibration logic control circuit for generating reference voltage signal V c <n:0>Sent to the reference voltage DAC and compared with the output V o <n:0>and the reference voltage signal V c <n:0>The difference between the two is the calibration vector D <n:0>, in turn, the calibration vector D <n:0>Converted to the offset calibration control code Q0 for each amplifier in the preamplifier array circuit <n:0> -Q m <n:0> ; The reference voltage signal is the expected output signal of the ADC core corresponding to the ADC input of 0V voltage signal, and n+1 is the number of bits of ADC; < / n:0> The reference voltage DAC converts the reference voltage signal V c <n:0> Convert it into a differential analog signal and output it to the differential input of the ADC; Calibration logic control circuit offset calibration control code Q0 <n:0> -Q m <n:0> Connect to the input of the calibration current steering DAC. The calibration current steering DAC circuit controls the on and off of the MOS tube through the offset calibration control code, generating a differential current signal related to the calibration vector. The differential current signal is proportionally mirrored and injected into the calibration resistor to compensate for the error of the pre-amplifier output. < / n:0> 2. The folded interpolation architecture ADC pre-amplifier array circuit capable of calibrating output offset according to claim 1, characterized in that The pre-amplifier array circuit includes amplifiers preamp_0-preamp_m, negative output end current mirrors CMN0-CMNm, positive output end current mirrors CMP0-CMPm, negative output end calibration resistors RON0-RONm, positive output end calibration resistors ROP0-ROPm, ring-shaped average negative offset resistors RN0-RNm and ring-shaped average positive offset resistors RP0-RPm, the ring-shaped average negative offset resistor RN0 is connected to the ring-shaped average positive offset resistor RPm, and the ring-shaped average positive offset resistor RP0 is connected to the ring-shaped average negative offset resistor RNm to form a ring resistor string; The analog input positive terminal signal Vip is connected to the non-inverting input terminal of the amplifier preamp_0-preamp_m; The analog input negative terminal signal Vin is connected to the negative phase input terminal of the amplifier preamp_0-preamp_m; The i-th reference voltage signal Vref Connect to the differential comparator non-inverting input terminal of amplifier preamp_i; mi-th reference voltage signal Vref <m-i> The differential comparator negative input terminal of the amplifier preamp_i; The negative output current mirror CMNi is connected to the negative output calibration resistor RONi, and the negative output calibration resistor RONi is connected to the differential negative phase output Von of the amplifier preamp_i. ； The positive output current mirror CMPi is connected to the positive output calibration resistor ROPi, and the positive output calibration resistor ROPi is connected to the differential positive phase output terminal Vop of the amplifier preamp_i ； Positive calibration current Ip and negative calibration current In Calibrate the output of the preamplifier preamp_i, i = 0 to m + 1; The differential negative phase output terminal Von of the amplifier preamp_i connected between the ring average negative offset resistor RNi and the ring average negative offset resistor RNi+1; The differential positive-phase output terminal Vop of the amplifier preamp_i Connected between the ring-shaped average positive offset resistor RPi and the ring-shaped average positive offset resistor RPi+1.

3. The folded interpolation architecture ADC pre-amplifier array circuit capable of calibrating output offset according to claim 1, characterized in that The calibration logic control circuit includes a counter, a decoder, a register circuit, and a calibration algorithm module; wherein: The counter has a reset signal Rst and a clock signal CP connected to its input. The reset signal Rst clears the counter to zero. On the rising edge of the clock, the counter counts the clock and outputs the m1+1 bit count value S. <m1:0> ；< / m1:0> The calibration algorithm module compares the ADC core output V o <n:0>and the reference voltage signal V c <n:0>The difference between the two is the calibration vector D <n:0>, the calibration vector D <n:0> Send to register circuit; The decoder converts the weighted count value S output by the counter <m1:0>Converted into (m+1)-bit unweighted digital code Z <m:0> , output to the register circuit; The register circuit includes m+1 shift register groups composed of n+1 registers, the bit width of each shift register group is n+1, and the jth shift register group uses the digital code Z <m:0>The jth Z <j>As the calibration clock signal, the jth shift register group is in the calibration clock signal Z <j>The calibration vector D is controlled by <n:0>The shift output is the n+1-bit offset calibration control code Q. j <n:0> ,j=0~m. < / j> < / j> 4. The folded interpolation architecture ADC pre-amplifier array circuit capable of calibrating output offset according to claim 3, characterized in that The decoder converts the m1+1-bit binary number into a decimal number, sets the corresponding position of the decimal number to 1 and the rest to 0.

5. The folded interpolation architecture ADC pre-amplifier array circuit capable of calibrating output offset according to claim 3, characterized in that The number of bits of the count value S output by the counter is not less than [log2(m+1)], where [] is a rounding symbol.

6. The folded interpolation architecture ADC pre-amplifier array circuit capable of calibrating output offset according to claim 3, characterized in that The calibration current steering DAC circuit includes 2 (m+1) calibration current steering DAC units, including (m+1) positive calibration current steering units and (m+1) negative calibration current steering units; the jth positive current steering unit is based on Q j <n:0>, output differential current positive signal Ip1 <j>; The jth negative current steering unit is based on Q j <n:0>Output differential current negative signal In1 <j> , j=0~m.< / j> < / j> 7. The folded interpolation architecture ADC pre-amplifier array circuit capable of calibrating output offset according to claim 6, characterized in that The outputs of the positive calibration current steering unit and the negative calibration current steering unit are: Among them, I represents the current in a single MOS tube.

8. The folded interpolation architecture ADC pre-amplifier array circuit capable of calibrating output offset according to claim 2, characterized in that The positive calibration current Ip Flowing through the negative output terminal calibration resistor RONi, negative calibration current In The current flowing through the positive output calibration resistor ROPi compensates for the offset voltage of the pre-amplifier array, i = 0 ~ m.

9. The folded interpolation architecture ADC pre-amplifier array circuit capable of calibrating output offset according to claim 2, characterized in that The positive calibration current Ip<0:m> and the negative calibration current In<0:m> are in the microampere level.

10. The folding interpolation architecture ADC pre-amplifier array circuit capable of calibrating output offset according to claim 2, characterized in that The resistance values ​​of the negative output end calibration resistors RON0-RONm and the positive output end calibration resistors ROP0-ROPm are in the hundreds of ohms.

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