A parallel interleaver and method suitable for 5G-LDPC

Abstract

The application provides a parallel interleaver and method suitable for 5G-LDPC, and is used for solving the technical problems of high complexity of interleaving address calculation and low throughput in the prior art. The parallel interleaver comprises a read-write cache module and a bit interleaving module connected in sequence, and a parameter calculation module and a parameter storage module connected in sequence; the output end of the parameter storage module is connected with the bit interleaving module; wherein the bit interleaving module comprises Q cyclic shift units arranged in parallel and a code word merging module cascaded with the output end of the Q cyclic shift units, and Q is greater than or equal to 1; the parameter storage module comprises an information storage unit and a counter connected in sequence. The implementation steps are as follows: 1. the read-write cache module stores the data after 5G-LDPC encoding; 2. the parameter calculation module calculates the bit length at the end of the interleaving layer; 3. the parameter storage module calculates the cyclic shift factor; and 4. the bit interleaving module obtains the interleaving result.

Description

Technical Field

[0001] This invention belongs to the field of basic electronic circuit technology and relates to a parallel interleaver and method suitable for 5G-LDPC. Background Technology

[0002] Low-density parity-check (LDPC) codes, as high-performance linear error-correcting codes, have been established as one of the digital channel coding schemes in 5G systems due to their excellent performance and high throughput. 5G-LDPC codes employ quasi-cyclic LDPC codes. The quasi-cyclic characteristic means that its parity-check matrix can be divided into multiple square matrices of equal size, the size of which is called the spread factor Z. Each square matrix is ​​either a cyclic shift matrix of the identity matrix or a matrix of all zeros, facilitating memory storage and addressing, thereby reducing the coding complexity of 5G-LDPC codes. Since 5G-LDPC codes are susceptible to signal distortion during transmission due to various channel interferences, interleaving techniques are needed to disperse burst errors, making them random errors. However, the quasi-cyclic characteristic of its square matrix storage significantly increases the computational complexity of the interleaving address. Furthermore, due to the short coding time and long code length of 5G-LDPC codes, the throughput of the interleaver determines the throughput of the 5G-LDPC code encoder. Therefore, improving the throughput of the 5G-LDPC code interleaver has become a research hotspot.

[0003] Parallel interleaving of 5G-LDPC refers to the simultaneous input or output of multiple bits of the 5G-LDPC code. For example, the University of Electronic Science and Technology of China disclosed a parallel interleaver and method for 5G-LDPC in its patent application "A Parallel Interleaver, Deinterleaver and Method Applicable to 5G-NR" (Application No.: 202010525423, Publication No.: CN 111555761 A). The parallel interleaver includes at least two bit interleaving modules, a ping-pong controller, an input channel switching module, and an output channel switching module. The bit interleaving module includes a read / write buffer and a matrix construction unit. The matrix construction unit includes at least eight independent RAM memories, and the read / write buffer includes at least eight data registers that accommodate parallel buses. The bit interleaving module receives the encoded binary 5G-LDPC code through the read / write buffer. The matrix construction unit in the bit interleaver stores the encoded binary 5G-LDPC code cached in the read / write buffer according to the interleaving address. After the data storage is completed, the codewords are concatenated according to the output parallelism, and the interleaving result is output. The interleaving method stores the 5G-LDPC code by calculating the interleaving address of the 5G-LDPC code. However, the interleaving address is irregular and the calculation complexity is high. Moreover, as the interleaving parallelism increases, the bit interleaving module needs a large amount of RAM resources to store the encoded binary 5G-LDPC code. The total amount of RAM resources required is 105592. However, the limited RAM resources in the chip result in low parallelism, which affects the throughput of the interleaver. Summary of the Invention

[0004] The purpose of this invention is to address the shortcomings of the prior art by providing a parallel interleaver and method suitable for 5G-LDPC, thereby solving the technical problems of low interleaving efficiency and low throughput of the interleaver in the prior art.

[0005] To achieve the above objectives, the technical solution adopted by the present invention is as follows:

[0006] A parallel interleaver suitable for 5G-LDPC includes a read / write cache module and a bit interleaving module connected in sequence, as well as a parameter calculation module and a parameter storage module connected in sequence; the output of the parameter storage module is connected to the bit interleaving module; wherein, the bit interleaving module includes Q cyclic shift units arranged in parallel and a codeword merging module cascaded with the output of the Q cyclic shift units; Q≥1, and the parameter storage module includes an information storage unit and a counter connected in sequence.

[0007] An interleaving method suitable for 5G-LDPC parallel interleavers includes the following steps:

[0008] (1) The read / write cache module stores 5G-LDPC encoded data:

[0009] The read / write cache module receives the binary 5G-LDPC A = {a1, a2, ..., a...} encoded by the Q columns. q ,...,a Q},a q ={a q,1 ,a q,2 ,...,a q,z ,...,a q,Z} and cache it, where a q This represents the binary 5G-LDPC encoded in column q, a q,z Indicates a q The z-th bit in the array, Z≥1, where Z represents the expansion factor whose size is equal to the total number of bits.

[0010] (2) The parameter calculation module calculates the end bit length of the interleaving layer:

[0011] The parameter calculation module receives the physical layer transmission parameters, including the spread factor Z, the shortened bit length N, and the interleaving length E, and calculates the end bit length T of the interleaving layer based on the physical layer transmission parameters, and sends T and Z to the parameter storage module.

[0012] (3) The parameter storage module calculates the cyclic shift factor O:

[0013] (3a) The information storage unit in the parameter storage module receives the end bit length T of the interleaving layer and the spread factor Z, and stores T; at the same time, it initializes the number of cycles to k, the maximum number of cycles to K, K = ZT, and the current cycle shift factor and the cycle effective bits are 0. k And let k = 1;

[0014] (3b) The counter in the parameter storage module corresponds to the cyclic shift factor O k The update is performed to obtain the updated cyclic shift factor O'. k ;

[0015] (3c) Determine if k = K is true. If yes, obtain the optimized cyclic shift factor O. * If k = k + 1, then send it; otherwise, let k = k + 1 and execute step (3b).

[0016] (4) The bit interleaving module obtains the interleaving result:

[0017] (4a) In the bit interleaving module, each cyclic shift unit uses a cyclic shift factor of 0 to process each column of the encoded binary 5G-LDPC cached by the read / write cache module. q Perform a logical left circular shift (SLL) operation to obtain the Q-column pre-interleaved binary 5G-LDPC: B = {b1, b2, ..., b} q ,...,b Q}, b q ={b q,1 ,b q,2 ,...,b q,z ,...,b q,Z}, where b q Indicates a q The corresponding pre-interleaved binary 5G-LDPC, b q,z Indicates a q,z The corresponding bit;

[0018] (4b) The codeword merging module selects each column of the pre-interleaved binary 5G-LDPCB in the Q column pre-interleaved binary 5G-LDPCB. q The former The bits are concatenated into codewords to obtain the interleaved result C, which is then output.

[0019]

[0020] Compared with the prior art, the present invention has the following advantages:

[0021] First, the bit interleaving module constructed in this invention includes Q cyclic shift units arranged in parallel and a codeword merging module. During interleaving, the bit interleaving module only reads Q encoded binary 5G-LDPC codes from the read / write cache module, without needing to store other transmitted 5G-LDPC codes. The total amount of RAM resources used is much smaller than that of existing technologies, thus improving the throughput of the interleaver.

[0022] Second, the parallel interleaver constructed in this invention also includes a parameter calculation module and a parameter storage module connected in sequence; each cyclic shift unit in the bit interleaving module obtains multiple pre-interleaving results through the cyclic shift factor calculated by the parameter storage module, and the multiple pre-interleaving results are spliced ​​together by the codeword merging module to achieve interleaving, which avoids the defect of complex interleaving address calculation in the prior art and effectively improves the interleaving efficiency. Attached Figure Description

[0023] Figure 1 This is a schematic diagram of the parallel interleaver of the present invention;

[0024] Figure 2 This is a schematic diagram of the bit interleaving module of the present invention;

[0025] Figure 3 This is a flowchart illustrating the implementation of the parallel interleaving method of the present invention. Detailed Implementation

[0026] The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments:

[0027] Reference Figure 1The parallel interleaver of this invention includes a read / write buffer module and a bit interleaving module connected in sequence, as well as a parameter calculation module and a parameter storage module connected in sequence. The parameter storage module includes an information storage unit and a counter connected in sequence, with its output connected to the bit interleaving module. The bit interleaving module includes Q parallel cyclic shift units and a codeword merging module with an output parallelism of M cascaded with the outputs of the Q cyclic shift units, where Q ≥ 1, M ≥ Q, and M is an integer multiple of Q. In this embodiment, Q = 2, M = 8.

[0028] Reference Figure 2 The bit interleaving module includes Q cyclic shift units arranged in parallel and a codeword merging module with an output parallelism of M cascaded with the outputs of the Q cyclic shift units.

[0029] Reference Figure 3 The parallel interleaving method of the present invention includes the following steps:

[0030] (1) The read / write cache module stores 5G-LDPC encoded data:

[0031] The read / write cache module receives the binary 5G-LDPC A = {a1, a2, ..., a...} encoded by the Q columns. q ,...,a Q},a q ={a q,1 ,a q,2 ,...,a q,z ,...,a q,Z} and cache it, where a q This represents the binary 5G-LDPC encoded in column q, a q,z Indicates a q The z-th bit in the equation, where Z represents an expansion factor equal to the total number of bits. In this embodiment, Z = 384.

[0032] (2) The parameter calculation module calculates the end bit length of the interleaving layer:

[0033] The parameter calculation module receives physical layer transmission parameters, including the spread factor Z, the shortening bit length N, and the interleaving length E, and calculates the end-of-interleaving bit length T based on the physical layer transmission parameters. It then sends T and Z to the parameter storage module. The formula for calculating the end-of-interleaving bit length T is:

[0034]

[0035] In this embodiment, N=260, E=864, T=308, where the shortened bit length N is the length of data that does not participate in transmission in the encoded binary 5G-LDPC, the interleaving length E is the actual output length of the encoded binary 5G-LDPC, and the interleaving layer end length T refers to the remaining bit length at the end of the interleaving of the Q-column encoded 5G-LDPC code.

[0036] (3) The parameter storage module calculates the cyclic shift factor O:

[0037] (3a) The information storage unit in the parameter storage module receives the end bit length T of the interleaving layer and the spread factor Z, and stores T; at the same time, it initializes the number of cycles to k, the maximum number of cycles to K, K = ZT, and the current cycle shift factor and the cycle effective bits are 0. k Let k = 1, and in this example, the maximum number of loops is K = 76;

[0038] (3b) The counter in the parameter storage module corresponds to the cyclic shift factor O k The update is performed to obtain the updated cyclic shift factor O'. k ; Cyclic shift factor O k The particle size is 1, O k Updated formula:

[0039]

[0040] (3c) Determine if k = K is true. If yes, obtain the optimized cyclic shift factor O. * Otherwise, let k = k + 1 and execute step (3b);

[0041] In this embodiment, the cyclic shift factor O updated by the parameter calculation module * =76, indicating that the interleaved bit is at the 76th bit in the cyclic shift unit. The bit interleaving module can utilize the updated cyclic shift factor O. * , will O * The interleaved bits at the position are shifted to the beginning position of the cyclic shift unit to complete the pre-interleaving process. In this embodiment, the cyclic shift unit of the bit interleaving cyclically shifts the 76th bit data to the 1st bit of the cyclic shift unit to perform pre-interleaving processing, which avoids the defect of complex interleaving address calculation in the prior art and reduces the computational complexity.

[0042] (4) The bit interleaving module obtains the interleaving result:

[0043] (4a) The bit interleaving module includes Q parallel cyclic shift units and a codeword merging module; each cyclic shift unit in the bit interleaving module uses a cyclic shift factor of 0 to process each column of encoded binary 5G-LDPC codewords cached in the read / write cache module.q Perform a logical left circular shift (SLL) operation to obtain the Q-column pre-interleaved binary 5G-LDPC B = {b1, b2, ..., b}. q ,...,b Q}, b q ={b q,1 ,b q,2 ,...,b q,z ,...,b q,Z}, where b q Indicates a q The corresponding pre-interleaved binary 5G-LDPC, b q,z Indicates a q,z The corresponding bit;

[0044] a q The corresponding pre-interleaved binary 5G-LDPC b q The calculation formula is:

[0045]

[0046] Because the most significant bit of 5G-LDPC code is on the left during encoding, a logical left circular shift operation (SLL) is performed. The logical left circular shift operation refers to the operation of the encoded binary 5G-LDPC... q The shift operation is performed to the left, with the left direction as the high priority. Lower-order data overwrites higher-order data, and the least significant bit is padded with zeros. During pre-interleaving processing using Q cyclic shift units, only Q encoded binary 5G-LDPC codes are read from the read / write buffer module. Other 5G-LDPC codes transmitted in this frame are not stored. The total RAM resources required for the Q encoded binary 5G-LDPC codes are R. n =Q*Z,R n The maximum value is 1536, which is much smaller than the total resources required by existing technologies, thus avoiding the problem of limited RAM resources affecting the throughput of the interleaver in existing technologies.

[0047] (4b) The codeword merging module selects each column of the pre-interleaved binary 5G-LDPCB in the Q column pre-interleaved binary 5G-LDPCB. q The former Each bit is concatenated to obtain the interleaved result C, which is then output.

[0048]

[0049] The above description is merely a specific example of the present invention. Obviously, those skilled in the art, after understanding the content and principles of the present invention, may make various modifications and changes in form and detail without departing from the principles and structure of the present invention. However, these modifications and changes based on the ideas of the present invention are still within the scope of protection of the claims of the present invention.

Claims

1. A parallel interleaving method suitable for 5G-LDPC, characterized in that, The parallel interleaver is realized by a read-write buffer module and a bit interleaving module connected in sequence, and a parameter calculation module and a parameter storage module connected in sequence; the parameter storage module comprises an information storage unit and a counter connected in sequence, and an output end of the parameter storage module is connected with the bit interleaving module; the bit interleaving module comprises a plurality of cyclic shift units arranged in parallel and a code word merging module with an output parallel degree of connected with output ends of the cyclic shift units in cascade, wherein, is an integer multiple of, and the specific implementation steps are as follows:​​​​​ (1) The read-write cache module stores the 5G-LDPC encoded data: The read-write cache module receives column-encoded binary 5G-LDPC , and caches them, wherein denotes the column-encoded binary 5G-LDPC denotes the bit in , denotes an extension factor of the same size as the total number of bits​ (2) The parameter calculation module calculates the length of the interleaving layer end bits: The parameter calculation module receives physical layer transmission parameters, including spreading factor , shortened bit length , and interleaving length , and calculates interleaving layer end bit length according to the physical layer transmission parameters, and sends and to the parameter storage module; (3) The parameter storage module calculates the cyclic shift factor : (3a) The information storage unit in the parameter storage module receives the length of the end bit of the interleaving layer. and expansion factor and to Store the data; simultaneously initialize the loop count to 1. The maximum number of loops is , The current cyclic shift factor and cyclic significant bits are respectively and order ; (3b) a counter in the parameter storage module counts the cyclic shift factor is updated to obtain an updated cyclic shift factor ; (3c) determine if is true, if yes, get the optimized cyclic shift factor ; otherwise, let and perform step (3b); (4) The bit interleaving module obtains the interleaving result: (4a) Each cyclic shift unit in the bit interleaving module is shifted by a cyclic shift factor Each column of the encoded binary 5G-LDPC is logically left circularly shifted by SLL to obtain The column pre-interleaved binary 5G-LDPC , denotes the corresponding pre-interleaved binary 5G-LDPC, denotes the corresponding bit position;​ (4b) Selection of codeword merging module Column pre-interleaved binary 5G-LDPC Pre-interleaved binary 5G-LDPC in each column The former Each bit is concatenated with a codeword to obtain the interleaved result. And output: 。 2. The interleaving method of claim 1, wherein, calculating the interleaving layer end bit length in step (2) The calculation formula is: wherein denotes a summation operation, denotes a modulo operation.

3. The interleaving method of claim 1, wherein, The cyclic shift factor in step (3b) The update formula is: wherein denotes a max operation.

4. The interleaving method of claim 1, wherein, the read-write cache module in step (4a) is column-encoded binary 5G-LDPC column-encoded binary 5G-LDPC a logical left circular shift operation SLL is performed, and the calculation formula is: wherein denotes a min operation.

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