Three-dimensional memory and methods of manufacturing three-dimensional memory

Abstract

Embodiments of the present application provide a three-dimensional memory. The three-dimensional memory includes a peripheral circuit chip and a memory array chip, the peripheral circuit chip includes: a first substrate; a first circuit element layer disposed on the first substrate and including a first device layer, the first device layer including a plurality of high-voltage transistors; a second substrate disposed on the first circuit element layer and in contact with the first circuit element layer; and a second circuit element layer disposed on the second substrate and including a second device layer, the second device layer including a plurality of low-voltage transistors; the memory array chip is disposed on the second circuit element layer.

Description

[0001] This application is a divisional application of Chinese invention patent application filed on April 30, 2021, entitled "Three-dimensional memory and method for manufacturing three-dimensional memory" with application number 202110483965.0. Technical Field

[0002] This invention relates to semiconductor devices and their manufacturing methods, particularly to a three-dimensional memory comprising a memory array chip and peripheral circuit chips and its manufacturing method. Background Technology

[0003] As the integration level of 3D memory increases, it has evolved from 32 layers to 64 layers or even higher. With the increase in the number of layers, the complexity of the memory array increases, leading to an increase in the design complexity of the corresponding peripheral circuits. Generally speaking, increasing memory density will increase the difficulty of designing peripheral circuits within a limited area, thus increasing the area of ​​the peripheral circuits. Summary of the Invention

[0004] The present invention provides a three-dimensional memory including peripheral circuit chips and a method for manufacturing the same, which can at least partially solve the above-mentioned problems existing in the prior art.

[0005] According to one aspect of the present invention, a three-dimensional memory including a peripheral circuit chip is provided, wherein the peripheral circuit chip includes: a first substrate; a first circuit element layer disposed on the first substrate and including a first device layer and a first connection layer, the first connection layer being used for signal transmission of the first device layer; a second substrate disposed on the first circuit element layer; and a second circuit element layer disposed on the second substrate and including a second device layer and a second connection layer, the second connection layer being used for signal transmission of the second device layer.

[0006] In one embodiment, the first device layer may include a plurality of first transistors, the second device layer may include a plurality of second transistors, and the operating voltage of the first transistors may be greater than the operating voltage of the second transistors.

[0007] In one implementation, the size of the first transistor may be larger than the size of the second transistor.

[0008] In an implementation, each of the first connecting layer and the second connecting layer may include a conductive material, and the melting point of the conductive material in the first connecting layer may be greater than or equal to the melting point of the conductive material in the second connecting layer.

[0009] In this embodiment, the conductive material of the first connecting layer may be WSi or TiSi, and the conductive material of the second connecting layer may be TiSi or CoSi.

[0010] In an embodiment, the peripheral circuit chip may further include: a third substrate disposed on the second circuit element layer; and a third circuit element layer disposed on the third substrate, which includes a third device layer and a third connection layer, wherein the third connection layer is used for signal transmission of the third device layer.

[0011] In an embodiment, the peripheral circuit chip may further include at least one of a first interconnect layer, a second interconnect layer, and a third interconnect layer. The first interconnect layer electrically connects the first connection layer and the second connection layer for signal transmission between the first device layer and the second device layer. The second interconnect layer electrically connects the third connection layer to one of the first and second connection layers for signal transmission between the third connection layer and one connection layer. The third interconnect layer electrically connects the third connection layer to the other connection layer among the first and second connection layers for signal transmission between the third connection layer and the other connection layer.

[0012] In an implementation, at least one of the first interconnect layer, the second interconnect layer, and the third interconnect layer may include W.

[0013] In one embodiment, the first device layer may include a plurality of first transistors, the second device layer may include a plurality of second transistors, and the third device layer may include a plurality of third transistors. In another embodiment, the operating voltage of at least one first transistor may be greater than the operating voltage of at least one second transistor, and the operating voltage of at least one second transistor may be greater than the operating voltage of at least one third transistor.

[0014] In an implementation, the size of at least one first transistor may be larger than the size of at least one second transistor, and the size of at least one second transistor may be larger than the size of at least one third transistor.

[0015] In an implementation, at least one of the first transistor, the second transistor, and the third transistor may be a metal-oxide-semiconductor field-effect transistor.

[0016] In an embodiment, each of the first connecting layer, the second connecting layer, and the third connecting layer may include a conductive material, wherein the melting point of the conductive material in the first connecting layer may be greater than or equal to the melting point of the conductive material in the second connecting layer, and the melting point of the conductive material in the second connecting layer may be greater than or equal to the melting point of the conductive material in the third connecting layer.

[0017] In this embodiment, the conductive material of the first connecting layer may be WSi or TiSi, the conductive material of the second connecting layer may be TiSi or CoSi, and the conductive material of the third connecting layer may be NiSi.

[0018] In an embodiment, the first connection layer may further include a first dielectric layer for electrically isolating the conductive material of the first connection layer; the second connection layer may further include a second dielectric layer for electrically isolating the conductive material of the second connection layer; and the third connection layer may further include a third dielectric layer for electrically isolating the conductive material of the third connection layer.

[0019] In one embodiment, the three-dimensional memory further includes a memory array chip, wherein the memory array chip may include a memory array layer and a first bonding layer disposed on the memory array layer. The memory array layer includes a plurality of memory strings disposed in a stacked structure, and the first bonding layer is used to bond with a second bonding layer in a peripheral circuit chip.

[0020] In one embodiment, the second bonding layer may be disposed on the second circuit element layer.

[0021] According to another aspect of the present invention, a method for manufacturing a three-dimensional memory is provided, the method comprising forming a peripheral circuit chip based on a first substrate, including: sequentially forming a first device layer and a first connection layer for signal transmission of the first device layer on the first substrate; forming a second substrate on the first connection layer, and sequentially forming a second device layer and a second connection layer for signal transmission of the second device layer on the second substrate; and forming a bonding layer having conductive contacts on the second connection layer.

[0022] In an implementation, the first device layer may include a plurality of first transistors, the second device layer may include a plurality of second transistors, and the operating voltage of at least one first transistor may be greater than the operating voltage of at least one second transistor.

[0023] In an implementation, the size of at least one first transistor may be larger than the size of at least one second transistor.

[0024] In one embodiment, forming the first connection layer may include: forming a first dielectric layer on the first device layer; and forming conductive wiring and conductive contacts for signal transmission in the first dielectric layer using a first conductive material. In another embodiment, forming the second connection layer may include: forming a second dielectric layer on the second device layer; and forming conductive wiring and conductive contacts for signal transmission in the second dielectric layer using a second conductive material. In another embodiment, the melting point of the first conductive material is greater than or equal to the melting point of the second conductive material.

[0025] In an embodiment, the method may further include: forming a third substrate on the second interconnect layer, and sequentially forming a third device layer and a third interconnect layer for signal transmission of the third device layer on the third substrate, wherein the bonding layer is formed on the third interconnect layer.

[0026] In an embodiment, the method may further include forming at least one of a first interconnect layer, a second interconnect layer, and a third interconnect layer, wherein the first interconnect layer can electrically connect the first connection layer to the second connection layer, the second interconnect layer can electrically connect the second connection layer and the third connection layer, and the third interconnect layer can electrically connect the first connection layer and the third connection layer; and forming a bonding layer with conductive contacts on the third connection layer.

[0027] In one embodiment, the first device layer may include a plurality of first transistors, the second device layer may include a plurality of second transistors, and the third device layer may include a plurality of third transistors. In another embodiment, the operating voltage of at least one first transistor may be greater than the operating voltage of at least one second transistor, and the operating voltage of at least one second transistor may be greater than the operating voltage of at least one third transistor.

[0028] In an implementation, the size of at least one first transistor may be larger than the size of at least one second transistor, and the size of at least one second transistor may be larger than the size of at least one third transistor.

[0029] In one embodiment, forming the first connection layer may include: forming a first dielectric layer on a first device layer; and forming conductive wiring and conductive contacts for signal transmission in the first dielectric layer using a first conductive material. In another embodiment, forming the second connection layer may include: forming a second dielectric layer on a second device layer; and forming conductive wiring and conductive contacts for signal transmission in the second dielectric layer using a second conductive material. In yet another embodiment, forming the third connection layer may include: forming a third dielectric layer on a third device layer; and forming conductive wiring and conductive contacts for signal transmission in the third dielectric layer using a third conductive material. In another embodiment, the melting point of the conductive material in the first conductive layer may be greater than or equal to the melting point of the conductive material in the second conductive layer, and the melting point of the conductive material in the second conductive layer may be greater than or equal to the melting point of the conductive material in the third conductive layer.

[0030] According to another aspect of the present invention, another three-dimensional memory is provided, the three-dimensional memory including a peripheral circuit chip and a memory array chip, the peripheral circuit chip including: a first substrate; a first circuit element layer disposed on the first substrate and including a first device layer, the first device layer including a plurality of high-voltage transistors; a second substrate disposed on the first circuit element layer and in contact with the first circuit element layer; and a second circuit element layer disposed on the second substrate and including a second device layer, the second device layer including a plurality of low-voltage transistors; the memory array chip is disposed on the second circuit element layer.

[0031] The three-dimensional memory and its manufacturing method described above can effectively reduce the area of ​​the peripheral circuit chip by allowing the devices in the peripheral circuit chip to be placed on different substrates, which is beneficial for increasing the storage density of the three-dimensional memory. Simultaneously, since devices with different operating voltages are formed on different substrates, the fabrication process can be simplified and the stability of the device can be improved. Attached Figure Description

[0032] The accompanying drawings are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification. The drawings illustrate exemplary embodiments of the invention and, together with the description, serve to explain the inventive concept. In the drawings:

[0033] Figure 1 This is a schematic cross-sectional view showing the peripheral circuit chip of a three-dimensional memory according to the prior art;

[0034] Figure 2 This is a schematic cross-sectional view showing the peripheral circuit chip of a three-dimensional memory according to an exemplary embodiment of the present invention;

[0035] Figure 3 This illustrates an exemplary embodiment of the invention, including a NAND memory array chip and... Figure 2 A schematic cross-sectional view of the NAND memory's peripheral circuit chips;

[0036] Figure 4 This is a schematic cross-sectional view illustrating the peripheral circuit chip of a three-dimensional memory according to another exemplary embodiment of the present invention;

[0037] Figure 5 This is another exemplary embodiment of the invention, including a NAND memory array chip and Figure 4 A schematic cross-sectional view of the NAND memory's peripheral circuit chips;

[0038] Figure 6 This illustrates the manufacturing process according to the invention, including... Figure 2 A flowchart of a portion of the method for a three-dimensional memory of a peripheral circuit chip shown; and

[0039] Figure 7 This illustrates the manufacturing process according to the invention, including... Figure 4 The flowchart shows a portion of the method for a three-dimensional memory of a peripheral circuit chip. Detailed Implementation

[0040] The present invention will now be described in detail with reference to the accompanying drawings. The exemplary embodiments mentioned herein are for illustrative purposes only and are not intended to limit the scope of the invention.

[0041] Crosshairs and / or shading are typically used in the accompanying drawings to clarify the boundaries between adjacent elements. Therefore, the presence or absence of crosshairs or shading does not convey or indicate any preference or requirement for particular materials, material properties, dimensions, scale, commonalities between the elements shown, and / or any other characteristics, properties, etc., of the elements, unless otherwise stated. Furthermore, in the accompanying drawings, the dimensions and relative dimensions and shapes of the elements have been adjusted for clarity and / or descriptive purposes. It should be understood that the accompanying drawings are for illustrative purposes only and are not strictly to scale.

[0042] Throughout this specification, the same reference numerals refer to the same elements. The expression "and / or" includes any and all combinations of one or more of the associated listed items.

[0043] As used herein, the terms “approximately,” “about,” and similar terms are used to indicate approximation, not degree, and are intended to describe inherent deviations in measured or calculated values ​​that will be recognized by one of ordinary skill in the art. It should be understood that in this specification, the terms “first,” “second,” etc., are used only to distinguish one feature from another and do not imply any limitation on the features, or in particular any order of precedence.

[0044] It should also be understood that expressions such as "comprising," "having," and / or "including" are open-ended rather than closed-ended expressions in this specification, indicating the presence of the stated features, elements, and / or components, but not excluding the presence of one or more other features, elements, components, and / or combinations thereof. Furthermore, when expressions such as "at least one of..." appear after a list of listed features, they modify the entire list of features, not just individual elements in the list. Additionally, when describing embodiments of the invention, the word "may" is used to mean "one or more embodiments of the invention." And the term "exemplary" is intended to refer to an example or illustration.

[0045] Various exemplary embodiments may be different, but are not necessarily exclusive. For example, specific shapes, configurations, and characteristics of exemplary embodiments may be used or implemented in another exemplary embodiment without departing from the inventive concept.

[0046] Unless otherwise stated, the exemplary embodiments shown should be understood as exemplary features providing details of variations in some ways in which the inventive concept can be implemented in practice. Therefore, unless otherwise stated, features, molecules, components, modules, layers, films, panels, regions and / or aspects of various embodiments (hereinafter individually or collectively referred to as “elements”) may be combined, separated, interchanged and / or rearranged in other ways without departing from the inventive concept.

[0047] It should be noted that references to "one implementation / embodiment," "implementation / embodiment," "exemplary implementation / embodiment," "some implementations / embodiments," etc., in the specification indicate that the described implementation / embodiment may include specific features, structures, or characteristics, but not every implementation / embodiment necessarily includes that specific feature, structure, or characteristic. Furthermore, such phrases do not necessarily refer to the same implementation / embodiment. Additionally, when a specific feature, structure, or characteristic is described in connection with an implementation / embodiment, whether explicitly described or not, implementing such a feature, structure, or characteristic in conjunction with other implementations / embodiments will be within the knowledge of those skilled in the art.

[0048] It should be understood that the terms "on," "on," and "directly on" in this disclosure should be interpreted in the broadest possible sense, such that "on" means not only "directly on" something, but also includes "on" something with intermediate features or layers in between, and that "on" or "directly on" means not only "on" something or "directly on" something, but also includes "on" something or "directly on" something without intermediate features or layers in between (i.e., directly on) something. In addition to the orientations shown in the figures, spatially relative terms are intended to cover different orientations of the device in use or operation. The device may be oriented in other ways (rotated 90 degrees or along other orientations) and the spatially relative descriptors used herein shall be interpreted accordingly.

[0049] As used herein, the term "layer" refers to a portion of material comprising a region having thickness. A layer may extend throughout the entire underlying or upper structure, or may have a extent smaller than that of the underlying or upper structure. Furthermore, a layer may be a region of a homogeneous or heterogeneous continuous structure with a thickness less than the thickness of that continuous structure. For example, a layer may be located between the top and bottom surfaces of a continuous structure or between any pair of horizontal planes at the top and bottom surfaces. A layer may extend laterally, vertically, and / or along a tapered surface. A substrate may be a layer, in which one or more layers may be included, and / or one or more layers may be present on, above, and / or below it. A layer may include multiple layers. For example, an interconnect layer may include one or more conductors and contact layers (where interconnects / connections and / or via contacts are formed) and one or more dielectric layers.

[0050] As used herein, the term “about” refers to a value of a given quantity that may vary based on a particular technology node associated with the subject semiconductor device. Based on a particular technology node, the term “about” may refer to a value of a given quantity that varies, for example, within 10% to 30% of that value (e.g., ±10%, ±20%, or ±30% of the value).

[0051] It should be noted that the illustrations provided in the embodiments are only schematic representations of the basic concept of the present invention. Therefore, the illustrations only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the shape, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0052] It should also be understood that, unless explicitly defined or contradicted by the context, the specific steps included in the methods described in this invention are not necessarily limited to the described order. For example, a particular process sequence may be performed differently from the described sequence. For instance, two consecutively described processes may be performed substantially simultaneously, or in the reverse order of their description.

[0053] The present invention will now be described in detail with reference to the accompanying drawings and embodiments.

[0054] Figure 1 This is a schematic cross-sectional view showing the peripheral circuit chip of a prior art three-dimensional memory.

[0055] In the prior art three-dimensional memory, the peripheral circuit chip 20 includes a substrate 201 and a circuit element layer 200 located on the substrate 201.

[0056] The circuit element layer 200 includes any suitable digital, analog, and mixed-signal control and sensing circuitry for facilitating the three-dimensional memory, including but not limited to page buffers, decoders (e.g., row decoders and column decoders), sense amplifiers, drivers (e.g., word line drivers), charge pumps, current and voltage references, or any active or passive components of the circuitry (e.g., transistors, diodes, resistors, or capacitors). Therefore, the circuit element layer 200 includes a device layer 210 (which includes devices such as transistors 211) implementing these functions and a connection layer 220 (which includes connection wiring 221 and contacts 222, etc.) for receiving or transmitting electrical signals to or from the device layer 210. The devices in the device layer 210 are electrically connected to each other via connection wiring 221 and contacts 222 in the connection layer 220. The peripheral circuit chip 20 also includes a bonding layer 230 for bonding the peripheral circuit chip 20 to a memory array chip (not shown), the bonding layer 230 including conductive contacts 231. The location of the substrate of the memory array chip can overlap with the location of the substrate 201 of the peripheral circuit chip 20 in the direction perpendicular to the thickness of the substrate 201 of the peripheral circuit chip 20 (such as in a three-dimensional memory in X-tacking technology, where the peripheral circuit chip 20 and the memory array chip are stacked vertically), or it can overlap with the substrate 201 in the lateral direction (e.g., the peripheral circuit chip 20 and the memory array chip are placed horizontally side by side).

[0057] Because the peripheral circuit chip 20 in the prior art consists of only one substrate, and therefore the circuit element layer 200 is disposed on the same substrate, this architecture will lead to an increase in the area required for the peripheral circuit as storage density increases.

[0058] To reduce the area of ​​the peripheral circuit design, this invention proposes a three-dimensional memory architecture that differs from existing technologies. The following will combine... Figures 2 to 5 A three-dimensional memory according to an embodiment of the present invention is described.

[0059] Figure 2 This is a schematic cross-sectional view showing the peripheral circuit chip of a three-dimensional memory according to an exemplary embodiment of the present invention.

[0060] like Figure 2 As shown, a three-dimensional memory according to an exemplary embodiment of the present invention may include a storage array chip (not shown) and a peripheral circuit chip 40.

[0061] The peripheral circuit chip 40 may include a substrate 401, a first circuit element layer 402 located on the substrate 401, a substrate 403, and a second circuit element layer 404 located on the substrate 403.

[0062] Substrate 401 may include monocrystalline silicon, polycrystalline silicon, amorphous silicon, germanium (Ge) substrate, silicon germanide (SiGe), gallium arsenide (GaAs), SOI (Silicon-on-insulator) substrate or GOI (Germanium-on-insulator), self-aligned silicide, or any other suitable material. In one embodiment of the invention, substrate 401 may be, for example, a silicon wafer, but the invention is not limited thereto.

[0063] The first circuit element layer 402 may include any suitable digital, analog, and mixed-signal control and sensing circuitry for facilitating the three-dimensional memory, including but not limited to page buffers, decoders (e.g., row decoders and column decoders), sense amplifiers, drivers (e.g., word line drivers), charge pumps, current and voltage references, or any active or passive components of the circuitry (e.g., transistors, diodes, resistors, or capacitors). Therefore, the first circuit element layer 402 may include a device layer (including devices such as transistors) implementing these functions and a connection layer (including connection wiring and contacts, etc.) for receiving or transmitting electrical signals from or to the device layer. For example, the first circuit element layer 402 may include a first device layer 410 for implementing at least a portion of the functions of the peripheral circuit chip 40 and a first connection layer 420 for signal transmission of the first device layer 410. The first device layer 410 may include various devices that form part of the circuitry of the peripheral circuit chip 40, such as… Figure 2The plurality of first transistors 411 shown.

[0064] Devices in the first device layer 410 can receive or transmit electrical signals through connection wiring 421 and connection access (via) contacts 422 (hereinafter also referred to as "contacts 422") in the first connection layer 420. The first connection layer 420 may include multiple connection wirings 421 and contacts 422 as needed for chip design. The first connection layer 420 may also include one or more interlayer dielectric (ILD) layers (also referred to as "intermetallic dielectric (IMD) layers," not shown), in which connection wirings 421 and contacts 422 can be formed. In other words, the first connection layer 420 may include connection wirings 421 and contacts 422 located in the ILD layer. The connection wirings 421 and contacts 422 in the first connection layer 420 may include conductive materials, including but not limited to W, Co, Cu, Al, silicides, or any combination thereof. The ILD layer in the first connection layer 420 may further include a dielectric material, including but not limited to silicon oxide, silicon nitride, silicon oxynitride, low-k dielectric, or any combination thereof, to electrically isolate the connection wiring 421 and contacts 422 in the first connection layer 420 from other components. The connection wiring 421 and contacts 422 in the first connection layer 420 may be formed of a conductive material deposited by one or more thin-film deposition processes, including but not limited to chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), electroplating, electroless plating, or any combination thereof. The manufacturing process for forming the connection wiring 421 and contacts 422 may also include photolithography, chemical mechanical polishing (CMP), wet / dry etching, or any other suitable process. The ILD layer of the first connection layer 420 may be formed of a dielectric material deposited by one or more thin-film deposition processes, including but not limited to CVD, PVD, ALD, or any combination thereof.

[0065] The substrate 403 can be formed by a single-crystal silicon growth process, or by first growing polycrystalline silicon and then heating the polycrystalline silicon. It should be understood that the substrate 403 is not limited to a silicon substrate, but can also be any other suitable material such as a germanium substrate.

[0066] Devices in the second device layer 430 can receive or transmit electrical signals through connection wiring 441 and connection access (via) contacts 442 (hereinafter also referred to as "contacts 442") in the second connection layer 440. The second connection layer 440 may include multiple connection wirings 441 and contacts 442 as needed for chip design. The second connection layer 440 may also include one or more interlayer dielectric (ILD) layers (also referred to as "intermetallic dielectric (IMD) layers," not shown), in which connection wirings 441 and contacts 442 can be formed. In other words, the second connection layer 440 may include connection wirings 441 and contacts 442 located in the ILD layer. The connection wirings 441 and contacts 442 in the second connection layer 440 may include conductive materials, including but not limited to W, Co, Cu, Al, silicides, or any combination thereof. The ILD layer in the second interconnect layer 440 may further include a dielectric material, including but not limited to silicon oxide, silicon nitride, silicon oxynitride, low-k dielectric, or any combination thereof, to electrically isolate the interconnect wiring 441 and contacts 442 in the second interconnect layer 440 from other components. Similar to the first interconnect layer 420, the interconnect wiring 441 and contacts 442 in the second interconnect layer 440 may also be formed of a conductive material deposited by one or more thin-film deposition processes, including but not limited to chemical CVD, PVD, ALD, electroplating, electroless plating, or any combination thereof. The manufacturing process for forming the interconnect wiring 441 and contacts 442 may also include photolithography, CMP, wet / dry etching, or any other suitable process. The ILD layer of the second interconnect layer 440 may also be formed of a dielectric material deposited by one or more thin-film deposition processes, including but not limited to CVD, PVD, ALD, or any combination thereof.

[0067] The first device layer 410 and the second device layer 430 respectively include a plurality of first transistors 411 and a plurality of second transistors 431 formed on substrates 401 and 403. It should be understood that, in this invention, "transistor formed on substrate" can mean that the transistor is wholly or partially formed in the substrate (e.g., below the top surface of the substrate) and / or directly formed on the substrate, depending on the substrate material and the type and material of the transistor, which is not limited by this invention. Transistors 411 and 431 can be formed by a variety of processes, including but not limited to photolithography, dry / wet etching, thin film deposition, thermal growth, implantation, CMP, and any other suitable processes. For example, in the case of a silicon substrate, doped regions can be formed in the silicon substrate, for example, by ion implantation and / or thermal diffusion, to serve as source and / or drain regions of the transistor; isolation regions (e.g., STI) can also be formed in the silicon substrate, for example, by wet / dry etching and thin film deposition processes, but the invention is not limited thereto.

[0068] The peripheral circuit chip 40 may further include a first interconnect layer (not shown) for electrically connecting the first connection layer 420 and the second connection layer 440 to enable signal transmission between the first circuit element layer 402 and the second circuit element layer 404. The first interconnect layer may include multiple interconnects 451 (also referred to herein as “contacts”) depending on the chip design requirements, for example, including vertical interconnect access (via) contacts. The first interconnect layer may also include one or more interlayer dielectric (ILD) layers (also referred to as “intermetallic dielectric (IMD) layers”, not shown), in which the contacts 451 may be formed. In other words, the first interconnect layer may include contacts 451 located in the ILD layer. The contacts 451 in the first interconnect layer may include conductive materials, including but not limited to materials such as W, Co, Cu, Al, etc. In an optional embodiment, the conductive material of the first interconnect layer is W. The ILD layer in the first interconnect layer may also include dielectric materials, including but not limited to silicon oxide, silicon nitride, silicon oxynitride, low-k dielectrics, or any combination thereof, to electrically isolate the contacts 451 in the first interconnect layer from other components. It should be understood that, although the above references Figure 2 In the described embodiment, the peripheral circuit chip 40 includes a first interconnect layer that electrically connects the first interconnect layer 420 and the second interconnect layer 440; however, the invention is not limited thereto. In exemplary embodiments conceived in this invention, the peripheral circuit chip 40 may also omit the first interconnect layer.

[0069] The peripheral circuit chip 40 may further include a bonding layer 490 for bonding the peripheral circuit chip 40 to the memory array chip. The bonding layer 490 is located on the substrate 401, the first circuit element layer 402, the substrate 403, and the second circuit element layer 404, and may include a plurality of bonding contacts 491 and a dielectric (not shown) electrically isolating the bonding contacts 491. The bonding contacts 491 may include conductive materials, including but not limited to W, Co, Cu, Al, silicides, or any combination thereof. The remaining area of ​​the bonding layer 490 may be formed of a dielectric, including but not limited to silicon oxide, silicon nitride, silicon oxynitride, low-k dielectrics, or any combination thereof. The bonding contacts 491 in the bonding layer 490 and the surrounding dielectric may be used for hybrid bonding.

[0070] According to the present invention, since the peripheral circuit chip 40 includes two substrates 401 and 403 and two circuit element layers 402 and 404 formed on the two substrates, and with Figure 1 Compared to the existing technology shown, more devices can be integrated per unit area, which can effectively reduce the peripheral area.

[0071] Furthermore, considering that the performance of the transistors formed first in the lower layer, along with their interconnects and contacts, may be affected by the process of the transistors formed later in the upper layer, and that the resistivity of contacts in contact with transistors operating at lower voltages is typically required to be very low, in order to simplify the process of forming transistors in the circuit element layer and improve transistor stability, transistors with different operating voltages to be used in the peripheral circuit chip 40 can be formed on different substrates, that is, transistors with different operating voltages can be formed in different circuit element layers. In a preferred embodiment of the invention, transistors with higher operating voltages (hereinafter referred to as "high-voltage transistors") and interconnects and contacts formed of high-temperature resistant conductive materials are formed in the lower first circuit element layer 402, while transistors with lower operating voltages (hereinafter referred to as "low-voltage transistors") and interconnects and contacts formed of conductive materials with very low resistivity are formed in the upper second circuit element layer 404. For example, the operating voltage of each of the first transistors 411 can be greater than the operating voltage of each of the second transistors 431. The transistors can be any type of transistor, for example, a metal-oxide-semiconductor field-effect transistor (MOSFET). More specifically, the transistors can be, for example, complementary metal-oxide-semiconductor (CMOS) transistors. According to some embodiments, transistors can achieve high speeds using advanced logic processes (e.g., technology nodes such as 90nm, 65nm, 45nm, 32nm, 28nm, 20nm, 16nm, 14nm, 10nm, 7nm, 5nm, 3nm, etc.). It should also be understood that the terms "high voltage" and "low voltage" here are relative and not particularly limiting. Figure 2 In the exemplary embodiments shown, for example, the operating voltage of the high-voltage transistor may be greater than 10 volts (V), for example, 15V to 35V, and the operating voltage of the low-voltage transistor may be less than 5V, for example, 3.3V. In a preferred embodiment of the invention, the size of the high-voltage transistor may be larger than the size of the low-voltage transistor. For example, the thickness of the gate layer of the high-voltage transistor may be greater than the thickness of the gate layer of the low-voltage transistor, and for example, the thickness of the gate layer of the high-voltage transistor may be more than three times the thickness of the gate layer of the low-voltage transistor. In a preferred embodiment of the invention, the operating voltage of each of the first transistors 411 may be greater than the operating voltage of each of the second transistors 431. Furthermore, in a preferred embodiment of the invention, the size of each of the first transistors 411 may be larger than the size of each of the second transistors 431.

[0072] As described above, the lower-layer high-voltage transistor is formed before the upper-layer low-voltage transistor. To prevent damage to the high-voltage transistor and its interconnects (first interconnect layer 420) during the formation of the low-voltage transistor, the conductive material of the first interconnect layer 420 needs to be heat-resistant and have good conductivity so that the performance of the devices in the first device layer 410 is not affected by the subsequent process of forming the second circuit element layer 404. Because the upper-layer low-voltage transistor operates at a lower voltage, it requires low resistivity of the contacts. Therefore, the resistivity of the interconnects and contacts (conductive material) of the second interconnect layer 440 connecting the upper-layer low-voltage transistor is required to be low. Furthermore, the process temperature for forming the interconnects and contacts of the second interconnect layer 440 should be lower than the melting point of the interconnects and contacts (conductive material) of the first interconnect layer 420. Consequently, the melting point of the interconnects and contacts (conductive material) of the first interconnect layer 420 is greater than or equal to the melting point of the interconnects and contacts (conductive material) of the second interconnect layer 440. Accordingly, the resistivity of the connection wiring and contacts (conductive material) of the second connection layer 440 is less than that of the connection wiring and contacts (conductive material) of the first connection layer 420.

[0073] In some exemplary embodiments of the present invention, the connection wiring 441 and contact 442 of the second connection layer 440 may include WSi or TiSi, which can be formed by any suitable WSi or TiSi process, and the connection wiring 421 and contact 422 of the first connection layer 420 may include TiSi, CoSi, or NiSi, which can be formed by any suitable TiSi, CoSi, or NiSi process. For example, when the connection wiring 421 and contact 422 of the first connection layer 420 includes WSi, the connection wiring 441 and contact 442 of the second connection layer 440 may include TiSi, CoSi, or NiSi; when the connection wiring 421 and contact 422 of the first connection layer 420 includes TiSi, the connection wiring 441 and contact 442 of the second connection layer 440 may include CoSi or NiSi, but the present invention is not limited thereto. In some exemplary embodiments of the present invention, the conductive material of the first connection layer 420 is, for example, able to maintain the required contact resistance with the gate, source or drain of the first transistor 411 at at least 500 degrees Celsius (°C) so that the performance of the first transistor 411 is not affected, while the conductive material of the second connection layer 440 is, for example, able to maintain the required contact resistance with the second transistor 431 at around 450°C so that the performance of the second transistor 431 is not affected.

[0074] The above describes a preferred embodiment in which the operating voltage of each of the first transistors 411 is greater than the operating voltage of each of the second transistors 431, and the size of each of the first transistors 411 is greater than the size of each of the second transistors 431. However, it should be understood that the invention is not limited thereto. For example, in some other embodiments, the operating voltage of at least one first transistor 411 may be greater than the operating voltage of the second transistor 431. In still other embodiments, the size of at least one first transistor 411 may be greater than the size of at least one second transistor 431.

[0075] The following uses NAND 3D memory in X-tacking technology as an example to illustrate the invention. Figure 2 The three-dimensional memory of the peripheral circuit chip 40 shown is illustrated. However, it should be understood that... Figure 2 The peripheral circuit chip 40 shown can be arranged side by side with the memory array chip to form a three-dimensional memory, or it can be stacked face to face with the memory array chip. The present invention does not limit the combination method of the peripheral circuit chip 40 and the memory array chip, or the type and specific structure of the memory array chip.

[0076] Figure 3 It includes, according to exemplary embodiments Figure 2 A schematic cross-sectional view of the NAND memory array chip with peripheral circuitry shown.

[0077] For ease of understanding, Figure 3 In this paper, NAND 3D memory is shown as an example of 3D memory, and NAND memory array chip is shown as an example of memory array chip 30. However, it should be understood that the 3D memory of the present invention is not limited to NAND 3D memory, and the corresponding memory array chip 30 is not limited to NAND memory array chip. Any other type of 3D memory and corresponding memory array chip are also applicable.

[0078] like Figure 3 As shown, the memory array chip 30 may include a substrate 301, a NAND memory array layer 310, a connection layer 340 for signal transmission of the NAND memory array layer 310, and a bonding layer 360 for bonding with peripheral circuit chips.

[0079] The storage array chip 30 can connect to the peripheral circuit chip 40 via bonding contacts 362 in bonding layer 360 and bonding contacts 491 in bonding layer 490 (see reference). Figure 2The bonding layers 360 and 490 are bonded face-to-face at the bonding interface BB. In some embodiments, the bonding interface BB is disposed between the bonding layers 360 and 490 as a result of hybrid bonding (also known as “metal-dielectric hybrid bonding”). Hybrid bonding is a direct bonding technique (e.g., forming a bond between surfaces without the use of an intermediate layer such as solder or adhesive) and can simultaneously achieve metal-to-metal bonding and dielectric-to-dielectric bonding. In some embodiments, the bonding interface BB is the location where the bonding layers 360 and 490 meet and bond. The bonding interface BB may have a thickness, such as the distance from the top surface of the bonding layer 490 of the peripheral circuit chip 40 to the bottom surface of the bonding layer 360 of the memory array chip 30.

[0080] The connection layer 340 may include a plurality of connection lines 341 and connection access (via) contacts 342 (e.g., bit line contacts and word line contacts, collectively referred to below as "contacts 342"). The connection layer 340 may also include one or more ILD layers (not shown) in which the connection lines 341 and contacts 342 may be formed. The connection lines 341 and contacts 342 in the connection layer 340 may include conductive materials, including but not limited to W, Co, Cu, Al, silicides, or any combination thereof.

[0081] NAND memory array layer 310 may be formed on substrate 301. Substrate 301 may be a thinned semiconductor substrate. In some embodiments, substrate 301 may include monocrystalline silicon, polycrystalline silicon, amorphous silicon, germanium (Ge) substrate, silicon germanide (SiGe), gallium arsenide (GaAs), SOI (Silicon-on-insulator) substrate or GOI (Germanium-on-insulator), self-aligned silicide, or any other suitable material. Substrate 301 may also include isolation regions and doped regions (e.g., used as the array common source (ACS) of 3D NAND channel structure 318, not shown). The isolation region (not shown) may extend across the entire thickness or a portion of the thickness of substrate 301 to electrically isolate the doped regions. In some embodiments, an oxide layer including silicon oxide is disposed between the stacked structure and substrate 301.

[0082] In NAND memory array layer 310, memory cells are provided in the form of an array of 3D NAND channel structures 318 (also referred to as “memory strings”). According to some embodiments, each 3D NAND channel structure 318 extends vertically through multiple pairs, each including a conductor layer 314 and a dielectric layer 316. The stacked and interleaved conductor layers 314 and dielectric layers 316 are also referred to herein as a stacked structure. According to some embodiments, the interleaved conductor layers 314 and dielectric layers 316 in the stacked structure alternate in the vertical direction. In other words, except for those at the top or bottom of the stacked structure, each conductor layer 314 may be adjacent to two dielectric layers 316 on both sides, and each dielectric layer 316 may be adjacent to two conductor layers 314 on both sides. The conductor layers 314 may all have the same thickness or different thicknesses. Similarly, the dielectric layers 316 may all have the same thickness or different thicknesses. The conductor layers 314 may include conductive materials, including but not limited to W, Co, Cu, Al, doped silicon, silicides, or any combination thereof. The dielectric layer 316 may include a dielectric material, including but not limited to silicon oxide, silicon nitride, silicon oxynitride, or any combination thereof.

[0083] The NAND memory array layer 310 may further include a common-source structure (not shown) that penetrates the stacked structure and is spaced from the channel structure 318. The common-source structure includes a common-source via (not shown) and a fill layer (not shown) disposed in the common-source via. The NAND memory array layer 310 may also include a stepped structure formed at the edge of the stacked structure and connected to the channel structure 318 via a conductor layer 314. A plurality of contacts 342 in the connection layer 340 may be disposed on the stepped structure for signal transmission.

[0084] In some embodiments, each 3D NAND channel structure 318 is a "charge-trapping" type NAND channel structure, including a semiconductor channel (not shown) and a memory film (not shown). In some embodiments, the semiconductor channel includes silicon, such as amorphous silicon, polycrystalline silicon, or monocrystalline silicon. In some embodiments, the memory film is a composite dielectric layer including a tunneling layer, a storage layer (also referred to as a "charge-trapping / storage layer"), and a barrier layer. Each 3D NAND channel structure 318 may have a cylindrical shape (e.g., columnar). According to some embodiments, the semiconductor channel, the tunneling layer of the memory film, the storage layer, and the barrier layer are arranged sequentially from the center of the column toward the outer surface. The tunneling layer may include silicon oxide, silicon oxynitride, or any combination thereof. The storage layer may include silicon nitride, silicon oxynitride, silicon, or any combination thereof. The barrier layer may include silicon oxide, silicon oxynitride, a high dielectric constant (high k) dielectric, or any combination thereof. In some embodiments of the invention, the barrier layer may include a composite layer of silicon oxide / silicon oxynitride / silicon oxide (ONO). In another example, the barrier layer may include a high-k dielectric layer, such as an aluminum oxide (Al2O3), hafnium oxide (HfO2), or tantalum oxide (Ta2O5) layer.

[0085] In some embodiments, the 3D NAND channel structure 318 may further include a plurality of control gates (each control gate being a portion of a word line). Each conductor layer 314 in the stacked structure may serve as a control gate for each memory cell of the 3D NAND channel structure 318 (therefore, conductor layer 314 may also be referred to as gate layer 314). In some embodiments, each 3D NAND channel structure 318 includes two plugs 311 and 319 at corresponding ends in the vertical direction. Plug 311 may comprise a semiconductor material, such as monocrystalline silicon, epitaxially grown from substrate 301. Plug 319 may serve as a channel controlled by a source select gate of the 3D NAND channel structure 318. Plug 311 may be at one end of the 3D NAND channel structure 318 and in contact with the semiconductor channel. The other plug 319 may comprise a semiconductor material (e.g., polycrystalline silicon). By covering the other end of the 3D NAND channel structure 318 during the fabrication of the memory array chip 30, the plug 319 can serve as an etch stop layer to prevent etching of the dielectric, such as silicon oxide and silicon nitride, filling the 3D NAND channel structure 318. In some embodiments, the plug 319 serves as the drain of the 3D NAND channel structure 318.

[0086] It should be understood that the 3D NAND channel structure 318 is not limited to a "charge trap" type 3D NAND channel structure, and in other embodiments may be a "floating gate" type 3D NAND channel structure. The substrate 301 may include polysilicon as the source plate of the "floating gate" type 3D NAND channel structure.

[0087] like Figure 3 As shown, the memory array chip 30 may further include a pad-out interconnect layer 350 on the substrate 301. The pad-out interconnect layer 350 may include interconnects in one or more ILD layers, such as contact pads 352. The pad-out interconnect layer 350 and the connection layer 340 may be formed on opposite sides of the substrate 301. In some embodiments, the interconnects in the pad-out interconnect layer 350 may transmit electrical signals between the three-dimensional memory and external circuitry, for example, for the purpose of pad out.

[0088] In some embodiments, the memory array chip 30 further includes one or more contacts 354 extending through the substrate 301 to electrically connect the pad-out interconnect layer 350 to the connection layers 340 and 490. As a result, the peripheral circuit chip 40 and the memory array chip 30 can be electrically connected via the connection layers 340 and 490 and the bonding contacts 362 and 491. Furthermore, the peripheral circuit chip 40 and the memory array chip 30 can be electrically connected to external circuitry via the contacts 354 and the pad-out interconnect layer 350.

[0089] It should be understood that Figure 3 The memory array chip 30 shown is merely exemplary, and the memory array chip 30 according to embodiments of the present invention is not limited thereto.

[0090] Figure 4 This is a schematic cross-sectional view of the peripheral circuit chip of a three-dimensional memory according to another exemplary embodiment of the present invention. Figure 5 This is another exemplary embodiment of the invention, including a NAND memory array chip and Figure 4 A schematic cross-sectional view of the NAND memory's peripheral circuit chips.

[0091] To avoid redundancy, the following description will only describe the differences from the exemplary embodiments described above, and the description of the same or similar parts as the embodiments described above will be omitted or simplified.

[0092] like Figure 4 As shown, the peripheral circuit chip 60 of the three-dimensional memory according to another exemplary embodiment of the present invention may include a substrate 601, a first circuit element layer 602, a substrate 603, a second circuit element layer 604, a substrate 605, and a third circuit element layer 606.

[0093] The first circuit element layer 602, the second circuit element layer 604, and the third circuit element layer 606 may include any suitable digital, analog, and mixed-signal control and sensing circuitry for facilitating the three-dimensional memory, including but not limited to page buffers, decoders (e.g., row decoders and column decoders), sense amplifiers, drivers (e.g., word line drivers), charge pumps, current and voltage references, or any active or passive components of the circuitry (e.g., transistors, diodes, resistors, or capacitors). Therefore, the first circuit element layer 602, the second circuit element layer 604, and the third circuit element layer 606 may each include device layers (including devices such as transistors) that implement these functions and connection layers (including connection wiring and contacts, etc.) for receiving or transmitting electrical signals from or to the device layers. For example, the first circuit element layer 602 may include a first device layer 610 and a first connection layer 620, the second circuit element layer 604 may include a second device layer 630 and a second connection layer 640, and the third circuit element layer 606 may include a third device layer 660 and a third connection layer 670.

[0094] As described above, substrate 601 may include monocrystalline silicon, polycrystalline silicon, amorphous silicon, germanium (Ge) substrate, silicon germanide (SiGe), gallium arsenide (GaAs), SOI (Silicon-on-insulator) substrate or GOI (Germanium-on-insulator), self-aligned silicide or any other suitable material.

[0095] As mentioned above, considering that the performance of the transistors formed first in the lower layer, their interconnections, and contacts may be affected by the process of the transistors formed later in the upper layer, and that the resistivity of the contacts that contact transistors with lower operating voltages usually requires very low resistance, in order to simplify the process of forming transistors in the circuit element layer and improve the stability of the transistors, the transistors with different operating voltages to be used in the peripheral circuit chip 60 can be formed on different substrates, that is, transistors with different operating voltages can be formed in different circuit element layers. Figure 4 In the example shown, the devices in the first device layer 610 may include high-voltage devices (e.g., high-voltage transistors), the devices in the second device layer 630 may include low-voltage devices (e.g., low-voltage transistors), and the devices in the third device layer 660 may include extremely low-voltage devices (e.g., extremely low-voltage transistors). For example, the operating voltage of each of the first transistors 611 may be greater than the operating voltage of each of the second transistors 631, and the operating voltage of each of the second transistors 631 may be greater than the operating voltage of each of the third transistors 661. It should be noted that high voltage, low voltage, and extremely low voltage are relative terms and can be defined according to chip design without particular limitation. Figure 4In the exemplary embodiments shown, for example, high voltage can represent greater than 10 volts, low voltage can represent 2.2 volts to 6 volts, and very low voltage can represent less than 1.8 volts. In a preferred embodiment of the invention, the size of the high voltage transistor can be larger than the size of the low voltage transistor, and the size of the low voltage transistor can be larger than the size of the very low voltage transistor. For example, the thickness of the gate layer of the high voltage transistor can be larger than the thickness of the gate layer of the low voltage transistor, and the thickness of the gate layer of the low voltage transistor can be larger than the thickness of the gate layer of the very low voltage transistor. For example, the size of each of the first transistors 611 can be larger than the size of each of the second transistors 631, and the size of each of the second transistors 631 can be larger than the size of each of the third transistors 661.

[0096] In such Figure 4In the illustrated embodiment, the melting point of the conductive material of the connecting wires 621 and contacts 622 of the first connection layer 620 can be greater than or equal to the melting point of the conductive material of the connecting wires 641 and contacts 642 of the second connection layer 640, and the melting point of the conductive material of the connecting wires 641 and contacts 642 of the second connection layer 640 can be greater than or equal to the melting point of the conductive material of the connecting wires 671 and contacts 672 of the third connection layer 670. In some examples of the present invention, the resistivity of the conductive material of the connecting wires 671 and contacts 672 of the third connection layer 670 can be less than the resistivity of the conductive material of the connecting wires 641 and contacts 642 of the second connection layer 640, and the resistivity of the conductive material of the connecting wires 641 and contacts 642 of the second connection layer 640 can be less than the resistivity of the conductive material of the connecting wires 621 and contacts 622 of the first connection layer 620. In some exemplary embodiments of the present invention, the conductive material of the first interconnect layer 620 may be, for example, a silicide of WSi or TSi; the conductive material of the second interconnect layer 640 may be, for example, a silicide of TSi or CoSi; and the conductive material of the third interconnect layer 670 may be, for example, a silicide of NiSi. However, the present invention is not limited thereto. For example, when the interconnect wiring 621 and contact 622 of the first interconnect layer 620 include WSi, the interconnect wiring 641 and contact 642 of the second interconnect layer 640 may include TiSi or CoSi, and the interconnect wiring 671 and contact 672 of the third interconnect layer 670 may include NiSi; when the interconnect wiring 621 and contact 622 of the first interconnect layer 620 include TiSi, the interconnect wiring 641 and contact 642 of the second interconnect layer 640 may include CoSi, and the interconnect wiring 671 and contact 672 of the third interconnect layer 670 may be NiSi; however, the present invention is not limited thereto. In an exemplary embodiment of the present invention, the conductive material of the first connection layer 620 is able to maintain the required contact resistance with the gate, source or drain of the first transistor 611 at a temperature of at least 500 degrees Celsius (°C) so that the performance of the first transistor 611 is not affected, and the conductive material of the second connection layer 640 is able to maintain the required contact resistance with the second transistor 631 at a temperature of at least 450°C so that the performance of the second transistor 631 is not affected; however, the present invention is not limited thereto.

[0097] The above describes a preferred embodiment in which the operating voltage of the first transistor 611 is greater than the operating voltage of the second transistor 631, the operating voltage of the second transistor 631 is greater than the operating voltage of the third transistor 661, and the size of the first transistor 611 is greater than the size of the second transistor 631, and the size of the second transistor 631 is greater than the size of the third transistor 661. However, it should be understood that the invention is not limited thereto. For example, in some other embodiments, the operating voltage of at least one first transistor 611 may be greater than the operating voltage of at least one second transistor 631, and the operating voltage of at least one second transistor 631 may be greater than the operating voltage of at least one third transistor 661. In still other embodiments, the size of at least one first transistor 611 may be greater than the size of at least one second transistor 631, and the size of at least one second transistor 631 may be greater than the size of at least one third transistor 661.

[0098] The peripheral circuit chip 60 may further include a first interconnect layer having contacts 651, which electrically connects the first connection layer 620 to the second connection layer 640. The peripheral circuit chip 60 may further include a second interconnect layer having contacts 655, which electrically connects the second connection layer 640 to the third connection layer 670. Although in reference... Figure 4 In the described embodiments, the peripheral circuit chip 60 includes a first interconnect layer electrically connecting the first connection layer 620 and the second connection layer 640, and a second interconnect layer electrically connecting the second connection layer 640 and the third connection layer 670. However, those skilled in the art will understand that the present invention is not limited thereto. For example, in other embodiments of the present invention, the peripheral circuit chip 60 may not include these interconnect layers according to chip design needs, or it may include a third interconnect layer electrically connecting the first connection layer 620 and the third connection layer 670; or the peripheral circuit chip 60 may include at least one of the first interconnect layer, the second interconnect layer, and the third interconnect layer according to chip design needs.

[0099] The following is Figure 4The peripheral circuit chip 60 is illustrated using a first interconnect layer and a second interconnect layer as an example, but the invention is not limited thereto. Each of the first and second interconnect layers may include multiple interconnects (also referred to as "contacts") as needed for chip design, for example, vertical interconnect access (via) contacts. Each of the contacts 651 of the first interconnect layer and the contacts 655 of the second interconnect layer may be formed using a conductive material (including but not limited to W, Co, Cu, Al, etc.). In an optional embodiment, at least one of the contacts 651 of the first interconnect layer and the contacts 655 of the second interconnect layer is W as the conductive material. Each of the first and second interconnect layers may also include one or more interlayer dielectric (ILD) layers (also referred to as "intermetallic dielectric (IMD) layers," not shown), in which contacts may be formed. The ILD layers in each of the first and second interconnect layers may also include dielectric materials, including but not limited to silicon oxide, silicon nitride, silicon oxynitride, low-k dielectrics, or any combination thereof, to electrically isolate the contacts in each of the first and second interconnect layers from other components.

[0100] The transistors in the first device layer 610, the second device layer 630, and the third device layer 660 may be formed on substrates 601, 603, and 605, respectively. As described above, in this invention, "on" a transistor can mean that the transistor is wholly or partially formed in the substrate (e.g., below the top surface of the substrate) and / or directly formed on the substrate, depending on the material of the substrate and the type and material of the transistor.

[0101] Substrates 603 and 605 can be formed using a single-crystal silicon growth process, or they can be formed by first growing polycrystalline silicon and then heating the polycrystalline silicon. It should be understood that substrates 603 and 605 are not limited to silicon substrates, but can also be any other suitable material such as germanium substrates.

[0102] and Figure 2 Similarly, the peripheral circuit chip 60 may also include a bonding layer 690 for bonding the peripheral circuit chip 60 to the memory array chip. The bonding layer 690 may include a plurality of conductive contacts 691, which can form a three-dimensional memory by bonding with corresponding conductive contacts in the memory array chip. Figure 5 As shown, the NAND memory array chip 30 can be bonded to the peripheral circuit chip 60 through corresponding bonding contacts in the bonding layers 690 and 360 to form a NAND three-dimensional memory. It should be understood that, as Figure 4 The peripheral circuit chip 60 shown can be applied to any three-dimensional memory, and is not limited to this. Figure 5 The NAND three-dimensional memory shown.

[0103] The following will be tested Figures 6 to 7A method for manufacturing a three-dimensional memory including a peripheral circuit chip according to the present invention is described.

[0104] Figure 6 This illustrates the manufacturing process according to the invention, including... Figure 2 The flowchart shows a portion of the method for a three-dimensional memory of a peripheral circuit chip. Figure 7 This illustrates the manufacturing process according to the invention, including... Figure 4 The flowchart shows a method for constructing a three-dimensional memory using peripheral circuit chips.

[0105] According to an exemplary embodiment of the present invention, a method 1000 for manufacturing a three-dimensional memory may form a peripheral circuit chip based on a first substrate.

[0106] refer to Figure 2 and Figure 6 Method 1000 may include: step S110, forming a first device layer 410 and a first connection layer 420 for signal transmission of the first device layer 410 sequentially on a first substrate 401; step S120, forming a second substrate 403 on the first connection layer 420, and forming a second device layer 430 and a second connection layer 440 for signal transmission of the second device layer 430 on the second substrate 403; step S130, forming a bonding layer 490 having conductive contacts (i.e., bonding contacts 491) on the second connection layer 440.

[0107] For reference Figure 2 As described, the first device layer 410 may include a plurality of first transistors 411, and the second device layer 430 may include a plurality of second transistors 431. In a preferred embodiment of the invention, the operating voltage of each of the first transistors 411 may be greater than the operating voltage of each of the second transistors 431. In another preferred embodiment of the invention, the size of each of the first transistors 411 may be greater than the size of each of the second transistors 431; for example, the thickness of the gate layer of each of the first transistors 411 may be greater than the thickness of the gate layer of each of the second transistors 431. However, the invention is not limited thereto. For example, in some other embodiments, the operating voltage of at least one first transistor 411 may be greater than the operating voltage of at least one second transistor 431. In still other embodiments, the size of at least one first transistor 411 may be greater than the size of at least one second transistor 431.

[0108] Forming the first connection layer 420 may include: forming a first dielectric layer on the first device layer 410; and forming conductive wiring (connection wiring 421) and contacts 422 for signal transmission in the first dielectric layer using a first conductive material. In this invention, the first conductive material includes, but is not limited to, W, Co, Cu, Al, silicides, or any combination thereof, and the first dielectric material includes, but is not limited to, silicon oxide, silicon nitride, silicon oxynitride, low-k dielectrics, or any combination thereof. In some embodiments of this invention, the first conductive material may be WSi or TiSi.

[0109] Forming the second connection layer 440 may include: forming a second dielectric layer on the second device layer 430; and forming conductive wiring (connection wiring 441) and contacts 442 for signal transmission in the second dielectric layer using a second conductive material. In embodiments of the invention, the second conductive material includes, but is not limited to, W, Co, Cu, Al, silicides, or any combination thereof, and the second dielectric material includes, but is not limited to, silicon oxide, silicon nitride, silicon oxynitride, low-k dielectrics, or any combination thereof. In some embodiments of the invention, the second conductive material may be TiSi, CoSi, or NiSi. According to exemplary embodiments of the invention, the melting point of the first conductive material may be greater than or equal to the melting point of the second conductive material.

[0110] Furthermore, depending on chip design requirements, method 1000 may further include: forming a first interconnect layer that electrically connects the first interconnect layer 420 and the second interconnect layer 440 before forming the bonding layer 490. According to some exemplary embodiments of the present invention, the first interconnect layer may include W.

[0111] According to an exemplary embodiment of the present invention, a method 2000 for manufacturing a three-dimensional memory may form a peripheral circuit chip based on a first substrate.

[0112] refer to Figure 4 and Figure 7 Method 2000 may include: step S210, forming a first device layer 610 and a first connection layer 620 for signal transmission of the first device layer 610 sequentially on a first substrate 601; step S220, forming a second substrate 603 on the first connection layer 620, and forming a second device layer 630 and a second connection layer 640 for signal transmission of the second device layer 630 sequentially on the second substrate 603; step S230, forming a third substrate 605 on the second connection layer 640, and forming a third device layer 660 and a third connection layer 670 for signal transmission of the third device layer 660 sequentially on the third substrate 605; step S240, forming a bonding layer 690 having conductive contacts 691 on the third connection layer 670.

[0113] For reference Figure 4As described, the first device layer 610 may include a plurality of first transistors 611, the second device layer 630 may include a plurality of second transistors 631, and the third device layer 660 may include a plurality of third transistors 661. In a preferred embodiment of the invention, the operating voltage of each of the first transistors 611 may be greater than the operating voltage of each of the second transistors 631, and the operating voltage of each of the second transistors 631 may be greater than the operating voltage of each of the third transistors 661. In yet another preferred embodiment of the invention, the size of each of the first transistors 611 may be greater than the size of each of the second transistors 631, and the size of each of the second transistors 631 may be greater than the size of each of the third transistors 661. For example, the thickness of the gate layer of each of the first transistors 611 may be greater than the thickness of the gate layer of each of the second transistors 631, and the thickness of the gate layer of each of the second transistors 631 may be greater than the thickness of the gate layer of each of the third transistors 661. However, it should be understood that the invention is not limited thereto. For example, in some other embodiments, the operating voltage of at least one first transistor 611 may be greater than the operating voltage of at least one second transistor 631, and the operating voltage of at least one second transistor 631 may be greater than the operating voltage of at least one third transistor 661. In still other embodiments of the invention, the size of at least one first transistor 611 may be greater than the size of at least one second transistor 631, and the size of at least one second transistor 631 may be greater than the size of at least one third transistor 661.

[0114] Forming the first connection layer 620 may include: forming a first dielectric layer on the first device layer 610; and forming conductive wiring (connection wiring 621) and contacts 622 for signal transmission in the first dielectric layer using a first conductive material. In this invention, the first conductive material includes, but is not limited to, W, Co, Cu, Al, silicides, or any combination thereof, and the first dielectric material includes, but is not limited to, silicon oxide, silicon nitride, silicon oxynitride, low-k dielectrics, or any combination thereof. In some embodiments of this invention, the first conductive material may be WSi or TiSi.

[0115] Forming the second connection layer 640 may include: forming a second dielectric layer on the second device layer 630; and forming conductive wiring (connection wiring 641) and contacts 642 for signal transmission in the second dielectric layer using a second conductive material. In embodiments of the invention, the second conductive material includes, but is not limited to, W, Co, Cu, Al, silicides, or any combination thereof, and the second dielectric material includes, but is not limited to, silicon oxide, silicon nitride, silicon oxynitride, low-k dielectrics, or any combination thereof. In some embodiments of the invention, the second conductive material may be TiSi or CoSi.

[0116] Forming the third connection layer 670 may include: forming a third dielectric layer on the third device layer 660; and forming conductive wiring (connection wiring 671) and contacts 672 for signal transmission in the third dielectric layer using a third conductive material. In embodiments of the invention, the third conductive material includes, but is not limited to, W, Co, Cu, Al, silicides, or any combination thereof, and the second dielectric material includes, but is not limited to, silicon oxide, silicon nitride, silicon oxynitride, low-k dielectrics, or any combination thereof. In some embodiments of the invention, the third conductive material may be NiSi. According to exemplary embodiments of the invention, the melting point of the first conductive material may be greater than or equal to the melting point of the second conductive material, and the melting point of the second conductive material may be greater than or equal to the melting point of the third conductive material.

[0117] Furthermore, depending on chip design requirements, method 2000 may further include forming at least one of a first interconnect layer, a second interconnect layer, and a third interconnect layer, wherein the first interconnect layer electrically connects the first interconnect layer 620 to the second interconnect layer 640, the second interconnect layer electrically connects the second interconnect layer 640 and the third interconnect layer 670, and the third interconnect layer electrically connects the first interconnect layer 620 and the third interconnect layer 670. According to some exemplary embodiments of the present invention, at least one of the first interconnect layer, the second interconnect layer, and the third interconnect layer includes W.

[0118] Using references Figures 6 to 7 After the peripheral circuit chip according to the present invention is manufactured by the method described herein, the corresponding memory array chip can be bonded to the peripheral circuit chip to form a three-dimensional memory.

[0119] The above description is merely an illustration of the embodiments of the present invention and the technical principles employed. Those skilled in the art should understand that the scope of protection involved in this invention is not limited to technical solutions formed by specific combinations of the above-described technical features, but should also cover other technical solutions formed by arbitrary combinations of the above-described technical features or their equivalents without departing from the technical concept. For example, technical solutions formed by substituting the above-described features with (but not limited to) technical features with similar functions disclosed in this invention.

Claims

1. A three-dimensional memory, characterized in that, The three-dimensional memory is a NAND three-dimensional memory and includes peripheral circuit chips and memory array chips. The peripheral circuit chips are used to facilitate signal control and sensing of the NAND three-dimensional memory. The peripheral circuit chips include: First substrate; A first circuit element layer is disposed on the first substrate and includes a first device layer, the first device layer including a plurality of high voltage transistors; A second substrate is disposed on the first circuit element layer, and the second substrate is in contact with the first circuit element layer; and A second circuit element layer is disposed on the second substrate and includes a second device layer, the second device layer including a plurality of low-voltage transistors; The storage array chip is disposed on the second circuit element layer.

2. The three-dimensional memory according to claim 1, wherein, The first circuit element layer further includes a first connection layer; the second circuit element layer further includes a second connection layer.

3. The three-dimensional memory according to claim 2, wherein, The first and second connection layers comprise conductive materials; The melting point of the conductive material in the first connecting layer is greater than or equal to the melting point of the conductive material in the second connecting layer.

4. The three-dimensional memory according to claim 3, wherein, The resistivity of the conductive material in the second connecting layer is less than that of the conductive material in the first connecting layer.

5. The three-dimensional memory according to claim 1, wherein, At least one of the high-voltage transistors is larger in size than at least one of the low-voltage transistors.

6. The three-dimensional memory according to claim 3, wherein, The conductive material of the first connecting layer includes WSi or TiSi, and the conductive material of the second connecting layer includes TiSi or CoSi.

7. The three-dimensional memory according to claim 2, wherein, The peripheral circuit chip also includes: A third substrate is disposed on the second circuit element layer, and the third substrate is in contact with the second circuit element layer; and A third circuit element layer is disposed on the third substrate and includes a third device layer comprising a plurality of ultra-low voltage transistors.

8. The three-dimensional memory according to claim 7, wherein, The third circuit element layer also includes a third connection layer.

9. The three-dimensional memory according to claim 8, wherein, The peripheral circuit chip further includes at least one of a first interconnect layer, a second interconnect layer, and a third interconnect layer, wherein, The first interconnect layer connects the first connection layer and the second connection layer; The second interconnect layer connects the third interconnect layer and the second interconnect layer; The third interconnect layer connects the third connection layer and the first connection layer.

10. The three-dimensional memory according to claim 9, wherein, At least one of the first interconnect layer, the second interconnect layer, and the third interconnect layer includes W.

11. The three-dimensional memory according to claim 7, wherein, The high-voltage transistor includes transistors with an operating voltage greater than 10V; The low-voltage transistor includes transistors with an operating voltage greater than 2.2V and less than 6V; The ultra-low voltage transistor includes transistors with an operating voltage of less than 1.8V.

12. The three-dimensional memory according to claim 7, wherein, The size of at least one of the high-voltage transistors is larger than the size of at least one of the low-voltage transistors, and the size of at least one of the low-voltage transistors is larger than the size of at least one of the ultra-low-voltage transistors.

13. The three-dimensional memory according to claim 12, wherein, At least one of the high-voltage transistor, the low-voltage transistor, and the ultra-low-voltage transistor is a metal-oxide-semiconductor field-effect transistor.

14. The three-dimensional memory according to claim 8, wherein, The first connecting layer, the second connecting layer, and the third connecting layer comprise conductive materials; The melting point of the conductive material in the first connecting layer is greater than or equal to the melting point of the conductive material in the second connecting layer, and the melting point of the conductive material in the second connecting layer is greater than or equal to the melting point of the conductive material in the third connecting layer.

15. The three-dimensional memory according to claim 14, wherein, The resistivity of the conductive material in the third connecting layer is less than that of the conductive material in the second connecting layer, and the resistivity of the conductive material in the second connecting layer is less than that of the conductive material in the first connecting layer.

16. The three-dimensional memory according to claim 14, wherein, The conductive material of the first connecting layer includes WSi or TiSi, the conductive material of the second connecting layer includes TiSi or CoSi, and the conductive material of the third connecting layer includes NiSi.

17. The three-dimensional memory according to claim 8, wherein, The first connection layer further includes a first dielectric layer; The second connection layer further includes a second dielectric layer; The third connection layer also includes a third dielectric layer.

18. The three-dimensional memory according to claim 1, wherein, The memory array chip includes a memory array layer and a first bonding layer; The storage array layer includes a stacked structure and multiple storage strings disposed in the stacked structure.

19. The three-dimensional memory according to claim 18, wherein, The peripheral circuit chip includes a second bonding layer; The second bonding layer is disposed on the second circuit element layer; The first bonding layer is bonded to the second bonding layer.

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