Doherty Amplifier

Abstract

A Doherty amplifier, wherein the passing phase of a path passing through a first input phase delay circuit (2), a carrier amplifier (4) and a second output phase delay circuit (7) is the same as the passing phase of a path passing through a second input phase delay circuit (3), a peak amplifier (5) and a second output phase delay circuit (7) in an operating frequency band. When viewed from a first transistor (10), a parasitic capacitance on the drain side of the first transistor (10) and a first output phase delay circuit (6) form a 90-degree line at the center frequency of the operating frequency band. When viewed from a second transistor (12), a parasitic capacitance on the drain side of the second transistor (12) and a second output phase delay circuit (7) form a 0-degree line at the center frequency. When the peak amplifier (5) is cut off, the value obtained by dividing the susceptance of the circuit formed by the second transistor (12) and the second output phase delay circuit (7) by the frequency has a positive slope relative to the frequency.

Description

Technical Field

[0001] The present disclosure relates to a Doherty amplifier that is compact and capable of wideband operation. Background Art

[0002] In recent years, in terrestrial microwave communications and mobile communications, signal multiplexing and common amplification of multiple channels are often used. In this case, since the difference between the saturated output power of the amplifier amplifying the signal and the peak power of the signal increases, the signal distortion increases and the working efficiency of the amplifier decreases. Therefore, in order to make the amplifier work efficiently even when the difference between the peak power and the average power is large, load modulation amplifiers represented by Doherty amplifiers are sometimes used.

[0003] In the Doherty amplifier, the input high-frequency input signal is divided into two signals, one of which is input to the carrier amplifier and the other is input to the peak amplifier. The carrier amplifier operates, for example, with a Class A or AB bias, and always amplifies the input signal. On the other hand, the peak amplifier operates with a Class C bias and amplifies input signals above a specified power. When the input signal is small, the peak amplifier does not work, so the impedance of the peak amplifier observed from the synthesis point is roughly open. At this time, the output impedance of the carrier amplifier is modulated by the phase delay circuit and becomes several times, and the saturated output becomes low, but it works efficiently.

[0004] In addition, since the peak amplifier also works at high output, it can be seen that the impedance at the synthesis point is divided into the carrier amplifier side and the peak amplifier side. Therefore, the impedance at the synthesis point on the carrier amplifier side becomes higher. Accompanying this, the output impedance of the transistor becomes lower, so the output power becomes larger.

[0005] Recently, with the further development of mobile communications, there has emerged a system in which multiple amplifiers are arranged on one surface of an antenna for operation, as represented by 5G, and therefore a small and wide-band Doherty amplifier is further required. For example, it has been proposed to reduce the number of components by actively using the parasitic capacitance on the drain side of the transistor, thereby realizing a miniaturized Doherty amplifier (for example, see patent document 1). In addition, in order to achieve wide-band operation, a Doherty amplifier has been proposed in which a line of n×180 degrees is configured in the output circuit of the peak amplifier as viewed from the drain electrode, and a line of (n-1)×180+90 degrees is configured in the output circuit of the carrier amplifier.

[0006] Patent Document 1: Japanese Patent Application Publication No. 2010-50611

[0007] In the existing Doherty amplifier using the parasitic capacitance of the transistor, it is difficult to achieve wideband operation due to the small number of circuit elements. In addition, in the Doherty amplifier with lines configured on the peak amplifier side and the carrier amplifier side, the circuit size is very large. Therefore, it has been difficult to obtain a small and wideband Doherty amplifier in the past. Summary of the invention

[0008] The present disclosure has been made to solve the above-mentioned problems, and an object of the present disclosure is to obtain a Doherty amplifier that is compact and capable of operating over a wide frequency band.

[0009] The Doherty amplifier disclosed in the present invention is characterized in that it comprises: a distributor that distributes an input signal into a first input signal and a second input signal; a first input phase delay circuit that delays the first input signal; a second input phase delay circuit that delays the second input signal; a carrier amplifier that has a first transistor that amplifies an output signal of the first input phase delay circuit; a peak amplifier that has a second transistor that amplifies an output signal of the second input phase delay circuit; a first output phase delay circuit that delays an output signal of the carrier amplifier; a second output phase delay circuit that delays an output signal of the peak amplifier; and an impedance conversion circuit that converts an output impedance of a synthesis point of an output of the first output phase delay circuit and an output of the second output phase delay circuit, The passing phase of the path passing through the first input phase delay circuit, the carrier amplifier and the first output phase delay circuit is the same as the passing phase of the path passing through the second input phase delay circuit, the peak amplifier and the second output phase delay circuit in the operating frequency band. When observed from the first transistor, the parasitic capacitance on the drain side of the first transistor and the first output phase delay circuit form a 90-degree line at the center frequency of the operating frequency band. When observed from the second transistor, the parasitic capacitance on the drain side of the second transistor and the second output phase delay circuit form a 0-degree line at the center frequency. When the peak amplifier is cut off, the value obtained by dividing the inductance of the circuit composed of the second transistor and the second output phase delay circuit observed from the synthesis point by the frequency has a positive slope relative to the frequency.

[0010] In the present disclosure, the parasitic capacitance on the drain side of the first transistor of the carrier amplifier and the first output phase delay circuit constitute a 90-degree line, and the parasitic capacitance on the drain side of the second transistor of the peak amplifier and the second output phase delay circuit constitute a 0-degree line. In this way, the parasitic capacitance of the transistor is actively used to reduce the number of components. In addition, since a line with a long electrical length is not included, the circuit is small. In addition, the value obtained by dividing the electrical resistance of the circuit composed of the second transistor and the second output phase delay circuit observed from the synthesis point when the peak amplifier is cut off by the frequency has a positive slope relative to the frequency. As a result, the phase difference between the carrier amplifier side and the peak amplifier side can be suppressed to be small over a wide band. Therefore, both sides during saturation operation and compensation operation can obtain wide-band characteristics. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1 : is a circuit diagram showing a Doherty amplifier according to the first embodiment.

[0012] Figure 2 1 is a diagram showing the frequency dependency of a value obtained by dividing the susceptance of a circuit including the second transistor and the second output phase delay circuit according to the first embodiment by the frequency.

[0013] Figure 3 1 is a circuit diagram showing an output circuit of a carrier amplifier when the Doherty amplifier according to Embodiment 1 operates in saturation.

[0014] Figure 4 It is a diagram showing a specific example of a compensation circuit.

[0015] Figure 5 This is a diagram showing the characteristics of a carrier amplifier when the output circuit does not include a compensation circuit and is saturated.

[0016] Figure 6 This is a diagram showing characteristics of a carrier amplifier when the output circuit does not include a compensation circuit.

[0017] Figure 7 This is a diagram showing the characteristics of a carrier amplifier when the output circuit includes a compensation circuit at the time of saturation.

[0018] Figure 8 This is a diagram showing characteristics when the output circuit of the carrier amplifier includes a compensation circuit.

[0019] Fig. 9 It is a diagram for explaining the behavior of the carrier amplifier and the peak amplifier when saturated.

[0020] Fig.10 This is a circuit diagram showing a specific example of the Doherty amplifier according to the first embodiment.

[0021] Fig.11This is a circuit diagram showing a specific example of the Doherty amplifier according to the first embodiment.

[0022] Fig.12 It is a diagram for explaining the behavior of the carrier amplifier and the peak amplifier during compensation.

[0023] Fig.13 1 is a diagram showing the frequency band characteristics of the output circuit of the Doherty amplifier according to the first embodiment when in a saturated state.

[0024] Fig.14 1 is a diagram showing the frequency band characteristics of the output circuit of the Doherty amplifier according to the first embodiment during the compensation operation.

[0025] Fig.15 FIG. 1 is a diagram showing the frequency band characteristics of a conventional Doherty amplifier during compensation.

[0026] Fig.16 This is a diagram showing the frequency dependency of a value obtained by dividing the susceptance of the second output phase delay circuit according to the second embodiment by the frequency.

[0027] Fig.17 FIG. 1 is a diagram showing an equivalent circuit of the output circuit of the second embodiment at the time of saturated output.

[0028] Fig.18 FIG. 1 is a diagram showing an equivalent circuit of an output circuit according to Embodiment 2 during compensation.

[0029] Fig.19 This is a diagram showing an output circuit of a Doherty amplifier according to a third embodiment.

[0030] Fig. 20 1 is a diagram showing the pass characteristic of the first output phase delay circuit of the Doherty amplifier according to the third embodiment.

[0031] Fig.21 1 is a circuit diagram showing an output circuit of a carrier amplifier and a peak amplifier of a Doherty amplifier according to a fourth embodiment.

[0032] Fig. 22 1 is a circuit diagram showing an output circuit of a carrier amplifier and a peak amplifier of a Doherty amplifier according to a fifth embodiment.

[0033] Fig.23 This is a diagram showing the pass characteristics of the Doherty amplifier according to the fourth embodiment.

[0034] Fig.24 This is a diagram showing the frequency dependency of a value obtained by dividing the susceptance of the Doherty amplifier according to the fourth embodiment by the frequency.

[0035] Fig.25This is a circuit diagram showing an output circuit of a carrier amplifier and a peak amplifier of a Doherty amplifier according to a sixth embodiment. DETAILED DESCRIPTION

[0036] The Doherty amplifier according to the embodiment will be described with reference to the drawings. The same reference numerals are used for the same or corresponding components, and repeated description may be omitted.

[0037] Implementation method 1.

[0038] Figure 1 1 is a circuit diagram showing a Doherty amplifier according to Embodiment 1. A distributor 1, a first input phase delay circuit 2, a second input phase delay circuit 3, a carrier amplifier 4, a peak amplifier 5, a first output phase delay circuit 6, a second output phase delay circuit 7, and an impedance conversion circuit 8 are formed on a high frequency substrate.

[0039] The distributor 1 distributes the input signal from the input terminal IN to the carrier amplifier 4 and the peak amplifier 5 so that the power becomes a desired value. The greater the difference between the average power and the peak power of the input signal, the greater the distribution ratio. Here, the ratio of the power of the first input signal distributed to the carrier amplifier 4 and the power of the second input signal distributed to the peak amplifier 5 is set to 1:n (=1.4). The carrier amplifier 4 operates, for example, with a class A or AB bias and always amplifies the input signal. The peak amplifier 5 operates with a class C bias and amplifies the input signal above the specified power.

[0040] The first input phase delay circuit 2 delays the first input signal and inputs it to the carrier amplifier 4. The second input phase delay circuit 3 delays the second input signal and inputs it to the peak amplifier 5. The carrier amplifier 4 has an input matching circuit 9 and a first transistor 10. The peak amplifier 5 has an input matching circuit 11 and a second transistor 12. The first transistor 10 and the second transistor 12 are, for example, FETs (Field effect transistors).

[0041] The first transistor 10 amplifies the output signal of the first input phase delay circuit 2 input via the input matching circuit 9 . The second transistor 12 amplifies the output signal of the second input phase delay circuit 3 input via the input matching circuit 11 .

[0042] The first output phase delay circuit 6 delays the output signal of the carrier amplifier 4. The second output phase delay circuit 7 delays the output signal of the peak amplifier 5. The output terminal of the first output phase delay circuit 6 and the output terminal of the second output phase delay circuit 7 are directly connected at a synthesis point 13. An impedance conversion circuit 8 is connected between the synthesis point 13 and the output terminal OUT. The impedance conversion circuit 8 converts the output impedance of the synthesis point 13 of the output of the first output phase delay circuit 6 and the output of the second output phase delay circuit 7.

[0043] When both the carrier amplifier 4 and the peak amplifier 5 are operating, it is necessary to minimize the difference in the passing phase between the path passing through the carrier amplifier 4 and the path passing through the peak amplifier 5 within the operating frequency band. Therefore, a correction circuit (not shown) is provided in the first input phase delay circuit 2 and the second input phase delay circuit 3 so that the difference in the passing phase between the path from the input terminal IN through the carrier amplifier 4 side to the synthesis point 13 and the path from the input terminal IN through the peak amplifier 5 side to the synthesis point 13 becomes smaller in a wide band during saturation operation. Therefore, the passing phase of the path passing through the first input phase delay circuit 2, the carrier amplifier 4 and the second output phase delay circuit 7 and the passing phase of the path passing through the second input phase delay circuit 3, the peak amplifier 5 and the second output phase delay circuit 7 are the same in the operating frequency band.

[0044] When viewed from the first transistor 10, the parasitic capacitance Cdsc on the drain side of the first transistor 10 and the first output phase delay circuit 6 form a 90-degree line at the center frequency of the operating frequency band. Therefore, the phase difference between the output signal of the first transistor 10 excluding the parasitic capacitance Cdsc and the output signal of the first output phase delay circuit 6 becomes 90 degrees at the center frequency fc of the operating frequency band. In addition, this phase difference slightly deviates from 90 degrees in actual design. In particular, when optimizing the circuit for the double wave, the characteristics are sometimes improved by slightly shifting this phase difference from 90 degrees.

[0045] When viewed from the second transistor 12, the parasitic capacitance Cdsp on the drain side of the second transistor 12 and the second output phase delay circuit 7 form a 0 degree line at the center frequency. Therefore, the phase difference between the output signal of the second transistor 12 excluding the parasitic capacitance Cdsp and the output signal of the second output phase delay circuit 7 becomes 0 degree at the center frequency fc.

[0046] The second output phase delay circuit 7 is configured so that a value obtained by dividing the susceptance of the circuit composed of the second transistor 12 and the second output phase delay circuit 7 viewed from the synthesis point 13 by the frequency when the peak amplifier 5 is turned off has a positive slope with respect to the frequency. Figure 2: is a graph showing the frequency dependency of the value obtained by dividing the susceptance by the frequency of the circuit composed of the second transistor and the second output phase delay circuit according to Embodiment 1. It can be seen that the value obtained by dividing the susceptance by the frequency increases as the frequency increases.

[0047] Figure 3 4 is a circuit diagram showing an output circuit of a carrier amplifier of the Doherty amplifier of embodiment 1 when the Doherty amplifier is in saturation operation. In the Doherty amplifier, the frequency characteristics of the output circuit of the carrier amplifier 4 affect the frequency characteristics of the amplifier as a whole. If the frequency band of the output circuit of the carrier amplifier 4 is narrow, the characteristics of the Doherty amplifier as a whole also become narrow-band, and if it is wide, the characteristics of the Doherty amplifier as a whole also become wide-band. Below, as an example, a Doherty amplifier with a frequency band of 3.3 GHz to 3.7 GHz is used for explanation.

[0048] TC1 represents a terminal of an intrinsic drain terminal that does not include a parasitic component of the first transistor 10 of the carrier amplifier 4. TC2 represents a terminal of the synthesis point 13. The impedance of the terminal TC1 is adjusted to match Roc, and the impedance of the terminal TC2 is adjusted to match Rjc. Cdsc is a parasitic capacitance of the drain terminal of the first transistor 10 of the carrier amplifier 4. The compensation circuit Cmp1 is a circuit that has a pass phase of 0 degrees relative to the center frequency fc and a value obtained by dividing the capacitance by the frequency has a positive slope relative to the frequency. The circuit composed of the parasitic capacitance Cdsc, the first output phase delay circuit 6, and the compensation circuit Cmp1 is adjusted to have a characteristic impedance of The electrical length is equivalent to 90 degrees at the center frequency fc.

[0049] On the other hand, during the compensation operation of the Doherty amplifier, the peak amplifier 5 is in the off state, so the impedance of TC2 becomes Rjc / (1+n) (where n is the division ratio), and the impedance of TC1 becomes Roc·(1+n).

[0050] Figure 4 The figure shows a specific example of a compensation circuit. The specific example on the left is a parallel inductor. The value obtained by dividing the susceptance of the circuit by the frequency f is -1 / 2πf 2 L. The specific example in the middle is a short-circuited stub. The value obtained by dividing the susceptance of the circuit by the frequency f is -1 / Z. l ftan(kf). The specific example on the right is a shunt LC circuit. The value obtained by dividing the susceptance of the circuit by the frequency f is 2πC / (1-4π 2 f 2 CL). In any case, the value obtained by dividing the susceptance by the frequency increases with increasing frequency.

[0051] Figure 5This is a diagram showing the characteristics of a carrier amplifier when the output circuit does not include a compensation circuit and is saturated. Figure 6 This is a diagram showing the characteristics of the carrier amplifier when the output circuit does not include a compensation circuit. It can be seen that a wide-band performance is obtained when saturated, but becomes a narrow-band when compensated.

[0052] Figure 7 This is a diagram showing the characteristics of a carrier amplifier when the output circuit includes a compensation circuit at the time of saturation. Figure 8 This is a diagram showing the characteristics of a carrier amplifier when the output circuit includes a compensation circuit. It can be seen that a wide-band performance is obtained during compensation, but a narrow-band performance is obtained during saturation operation.

[0053] As can be seen from the above, if the output circuit of the carrier amplifier includes the compensation circuit Cmp1 during compensation and does not include the compensation circuit Cmp1 during saturation, a Doherty amplifier capable of wideband operation is obtained.

[0054] Next, the operation of the Doherty amplifier according to the first embodiment will be described. Fig. 9 It is a diagram for explaining the behavior of the carrier amplifier and the peak amplifier when saturated. TP1 represents the terminal of the intrinsic drain terminal that does not include the parasitic component of the second transistor 12 of the peak amplifier 5. TP2 represents the terminal of the synthesis point 13. The impedance of the terminal TP1 is adjusted to match Roc / n, and the impedance of the terminal TP2 is adjusted to match Rjc / n. Cdsp is the parasitic capacitance of the drain terminal of the second transistor 12 of the peak amplifier 5.

[0055] In this embodiment, the structures of the first input phase delay circuit 2 and the second input phase delay circuit 3 are adjusted so that the passing phase of the path passing through the first input phase delay circuit 2, the carrier amplifier 4 and the second output phase delay circuit 7 and the passing phase of the path passing through the second input phase delay circuit 3, the peak amplifier 5 and the second output phase delay circuit 7 are the same in the operating frequency band. Fig. 9 As shown in FIG. 1 , the operation at saturation can be considered as the parallel operation of the circuit on the carrier amplifier 4 side and the circuit on the peak amplifier 5 side. Therefore, since the compensation circuit Cmp1 is not included in the path of the carrier amplifier 4, Figure 5 As shown, it becomes a wide-band characteristic.

[0056] Fig.10 and Fig.11: is a circuit diagram showing a specific example of the Doherty amplifier of embodiment 1. The numbers on the left side of the lower layer in the first input phase delay circuit 2, the second input phase delay circuit 3, the first output phase delay circuit 6, and the second output phase delay circuit 7 in the figure represent the pass phase at the center frequency fc. The numbers on the upper right represent the deviation of the pass phase at the lower limit frequency fl from the center frequency fc. The numbers on the lower right represent the deviation of the pass phase at the upper limit frequency fh from the center frequency fc. Among these numbers, positive values ​​represent phase delay, and negative values ​​represent phase advance. Here, consider the case where the in-band deviation of the compensation circuit Po is ±5 degrees.

[0057] exist Fig.10 In the first input phase delay circuit 2, a compensation circuit Ci is inserted. The passing phase of the compensation circuit Ci at the center frequency fc is 0, and the phase deviation at the lower limit frequency fl and the upper limit frequency fh are -5 degrees and +5 degrees respectively. The compensation circuit Ci can be realized by a parallel-connected LC circuit resonating with fc, etc. The deviation within the frequency band can be easily adjusted by changing the ratio of L to C. The second input phase delay circuit 3 and the first output phase delay circuit 6 are composed of 90-degree lines. Since the non-band accounts for about 11% in the frequency band of 3.3 to 3.7 GHz, the deviation within the frequency band is approximately 10 degrees. If the passing phase of the carrier amplifier 4 is the same as the passing phase of the peak amplifier 5, the phase of the input phase delay circuit and the output phase delay circuit can be considered. The delay of the first input phase delay circuit 2 and the first output phase delay circuit 6 on the carrier amplifier 4 side is 90±10 degrees. In contrast, the delay of the second input phase delay circuit 3 and the second output phase delay circuit 7 on the peak amplifier 5 side is also 90±10 degrees. Therefore, since the carrier amplifier 4 and the peak amplifier 5 operate in the same phase, they can be considered to operate independently of each other. At this time, since the first output phase delay circuit 6 of the carrier amplifier 4 does not include a compensation circuit, wideband operation can be achieved. Similarly, the peak amplifier 5 side can also achieve wideband operation.

[0058] exist Fig.11In the first input phase delay circuit 2, a 45-degree high-pass filter (HPF) is used. In the second input phase delay circuit 3, a 45-degree low-pass filter (LPF) is used. The HPF can be composed of, for example, a parallel inductor and a series capacitor. The LPF can be composed of, for example, a parallel capacitor and a series inductor. The in-band deviation of the phase of the LPF and the HPF is about half of that of a 90-degree phase shifter. The delay of the first input phase delay circuit 2 and the first output phase delay circuit 6 on the carrier amplifier 4 side is 45±7.5 degrees. In contrast, the delay of the second input phase delay circuit 3 and the second output phase delay circuit 7 on the peak amplifier 5 side is also 45±7.5 degrees. Therefore, since the carrier amplifier 4 and the peak amplifier 5 operate in the same phase, they can be considered independently of each other. At this time, since the compensation circuit is not included in the first output phase delay circuit 6 of the carrier amplifier 4, wide-band operation can be achieved. Similarly, wide-band operation can also be achieved on the peak amplifier 5 side.

[0059] In the case where the deviation in the second output phase delay circuit 7 deviates from ±5 degrees in the LPF and HPF, the phase deviation can be adjusted by adjusting the phases of the LPF and HPF. For example, when the deviation in the second output phase delay circuit 7 is ±10 degrees, the LPF is omitted and the delay of the LPF is set to 0 degrees, and the delay in the HPF is set to -90 degrees. As a result, the pass phase on the carrier amplifier 4 side and the pass phase on the peak amplifier 5 side become 0±10 degrees, and in-phase operation can be achieved. In addition, by combining the LPF, HPF, and the resonant circuit, it is possible to cope with various changes in the pass characteristics of the second output phase delay circuit 7.

[0060] Fig.12 1 is a diagram for explaining the behavior of the carrier amplifier and the peak amplifier during compensation. Since the second transistor 12 of the peak amplifier 5 is in the off state, the terminal TP1 becomes an open end. In addition, when viewed from the synthesis point 13, the value obtained by dividing the susceptance of the 0-degree line composed of the parasitic capacitance Cdsp of the second transistor 12 and the second output phase delay circuit 7 by the frequency increases as the frequency increases. Therefore, due to Figure 3 As shown in FIG. 1 , the compensation circuit Cmp1 is added. Therefore, Figure 8 As shown, it becomes a wide-band characteristic.

[0061] Fig.13 1 is a diagram showing the frequency band characteristics of the output circuit of the Doherty amplifier according to the first embodiment when in a saturated state. Fig.14 This is a diagram showing the frequency band characteristics of the output circuit of the Doherty amplifier in the compensation operation according to Embodiment 1. If the standard of the wide-band characteristic is set to the point where the pass characteristic deteriorates by 0.2 dB, it can be seen that both obtain a frequency band of about 1 GHz.

[0062] Fig.15 This is a diagram showing the frequency band characteristics of a conventional Doherty amplifier when compensating. It can be seen that the frequency band at the point where the characteristics deteriorate by 0.2 dB is narrowed to 500 MHz because a compensation circuit cannot be added.

[0063] As described above, in this embodiment, the parasitic capacitance on the drain side of the first transistor 10 of the carrier amplifier 4 and the first output phase delay circuit 6 constitute a 90-degree line, and the parasitic capacitance on the drain side of the second transistor 12 of the peak amplifier 5 and the second output phase delay circuit 7 constitute a 0-degree line. In this way, the parasitic capacitance of the transistor is actively used to reduce the number of components. In addition, since a line with a long electrical length is not included, the circuit is small.

[0064] In addition, the value obtained by dividing the susceptance of the circuit composed of the second transistor 12 and the second output phase delay circuit 7 by the frequency when the peak amplifier 5 is turned off from the synthesis point 13 has a positive slope with respect to the frequency. As a result, the phase difference between the carrier amplifier 4 side and the peak amplifier 5 side can be suppressed to be small in a wide band. Therefore, both in the saturation operation and the compensation operation, the wide-band characteristics can be obtained.

[0065] Implementation method 2.

[0066] Fig.16 1 is a diagram showing the frequency dependency of the value obtained by dividing the susceptance X of the second output phase delay circuit by the frequency in Embodiment 2. In this embodiment, the circuit structure of the second output phase delay circuit 7 is set so that the value obtained by dividing the susceptance X of the second output phase delay circuit 7 by the frequency in the structure of Embodiment 1 has a constant value at the center frequency fc.

[0067] Fig.17 : is a diagram showing an equivalent circuit of the output circuit of embodiment 2 at saturated output. The circuit constants are adjusted so that the parasitic capacitance Cdsc of the transistor of the carrier amplifier 4, the first output phase delay circuit 6, and the susceptance X1 of the first output phase delay circuit 6 become a 90-degree line at the center frequency. The circuit constants are adjusted so that the parasitic capacitance Cdsp of the transistor of the peak amplifier 5, the second output phase delay circuit 7, and the susceptance X2 of the second output phase delay circuit 7 become a 0-degree line at the center frequency. Here, the value of the susceptance X1 is X, and the value of the susceptance X2 is -X, and since they are connected to the synthesis point 11, they do not physically exist. The susceptance X1 on the carrier amplifier side is part of the output delay circuit on the peak amplifier side in the equivalent circuit. In addition, by making the phase from the input to the synthesis point the same on the carrier amplifier side and the peak amplifier side, as shown in FIG. Fig.17 As shown, it functions as an independent circuit.

[0068] Fig.18 : is a diagram showing an equivalent circuit of the output circuit of the second embodiment during compensation. The parasitic capacitance Cdsp of the second transistor 12 on the peak amplifier 5 side, the second output phase delay circuit 7, and the susceptance X2 function as a compensation circuit. Here, the value of the susceptance X1 is X, and the value of the susceptance X2 is -X, which are in a mutually canceling relationship. In addition, the susceptance X1 and the susceptance X2 are virtual existences and do not exist physically.

[0069] The function of this embodiment is the same as that of the first embodiment, and wideband characteristics can be obtained in both saturation operation and compensation operation as in the first embodiment. In addition, since a circuit with a long electrical length is not included, the carrier amplifier 4 and the peak amplifier 5 share a constant susceptance, so the circuit is small. In addition, the degree of freedom of the circuit structure is increased, and the slope of the frequency characteristic of the value obtained by dividing the susceptance by the frequency can be adjusted.

[0070] Implementation method 3.

[0071] Fig.19 : This is a diagram showing an output circuit of a Doherty amplifier according to Embodiment 3. The first output phase delay circuit 6 includes a conductor W1, transmission lines TL1, TL2, TL3, capacitors C1, and C2. One end of the conductor W1 is connected to the drain of the first transistor 10 of the carrier amplifier 4. One end of the transmission line TL1 is connected to the other end of the conductor W1. One end of the transmission line TL2 is connected to the other end of the transmission line TL1. A pad Vd_C for applying a drain voltage to the first transistor 10 is connected to the connection point between the capacitor C1 and the transmission line TL2. The capacitor C1 for DC cutoff is connected between the other end of the transmission line TL2 and the grounding point. One end of the transmission line TL3 is connected to the connection portion between the transmission line TL1 and the transmission line TL2, and the other end of the transmission line TL3 is connected to the synthesis point 13. The capacitor C2 is connected between the other end of the transmission line TL3 and the grounding point. The length of the transmission line TL1 is longer than the length of the transmission line TL3. The circuit is set so that the passing phase from the drain of the first transistor 10 to the synthesis point 13 becomes 90 degrees at the center frequency fc.

[0072] The second output phase delay circuit 7 has a conductor W2, transmission lines TL4, TL5, capacitors C3, C4, and C5. One end of the conductor W2 is connected to the drain of the second transistor 12. One end of the transmission line TL4 is connected to the other end of the conductor W2. The capacitor C3 for DC cutoff is connected between the other end of the transmission line TL4 and the grounding point. A pad Vd_p for applying a drain voltage to the second transistor 12 is connected to the connection point between the capacitor C3 and the transmission line TL4. One end of the capacitor C4 is connected to the connection point between the conductor W2 and the transmission line TL4, and the other end of the capacitor C4 is connected to the synthesis point 13. One end of the transmission line TL5 is connected to the other end of the capacitor C4. The capacitor C5 for DC cutoff is connected between the other end of the transmission line TL5 and the grounding point. The circuit is set so that the passing phase from the drain of the second transistor 12 to the synthesis point 13 becomes 0 degrees at the center frequency fc.

[0073] The impedance conversion circuit 8 includes a transmission line TL6 and capacitors C6 and C7. One end of the transmission line TL6 is connected to the combining point 13. The capacitor C6 is connected between the other end of the transmission line TL6 and the ground point. The capacitor C7 is connected between the other end of the transmission line TL6 and the output terminal OUT.

[0074] Since the circuit configuration of this embodiment functions in the same manner as in Embodiment 1, the same effects as in Embodiment 1 can be obtained. In addition, since the length of the transmission line TL1 is set longer than that of the transmission line TL3 , the first output phase delay circuit 6 also includes the function of a phase compensation circuit. Fig. 20 : is a diagram showing the pass characteristics of the first output phase delay circuit of the Doherty amplifier in Embodiment 3. In the figure, characteristic a is a characteristic when the length of the transmission line L1 is longer than the transmission line L3, and characteristic b is a characteristic when the length of the transmission line L1 is shorter than the transmission line L3. It can be seen that if the length of the transmission line L1 is longer than the transmission line L3, the first output phase delay circuit 6 itself becomes broadband.

[0075] Implementation method 4.

[0076] Fig.21 1 is a circuit diagram showing the output circuit of the carrier amplifier and the peak amplifier of the Doherty amplifier according to Embodiment 4. The capacitor C2 is removed from the first output phase delay circuit 6 of Embodiment 3, and the transmission line TL5 and the capacitor C5 are removed from the second output phase delay circuit 7. By adjusting the circuit constants, the same function as Embodiment 3 can be exerted. Compared with Embodiment 4, the circuit elements are reduced, so it can be further miniaturized.

[0077] Implementation method 5.

[0078] Fig. 221 is a circuit diagram showing an output circuit of a carrier amplifier and a peak amplifier of a Doherty amplifier according to Embodiment 5. In this embodiment, the transmission line TL4 of Embodiment 4 is replaced by two transmission lines TL41 and TL42 connected in series and a capacitor C31 connected between a connection point of the transmission lines TL41 and TL42 and a ground point.

[0079] In the fourth embodiment, the broadband characteristics are sacrificed due to the reduction of circuit elements. The broadband characteristics can be maintained by reducing or lengthening the characteristic impedance of the transmission line TL4, but the circuit size increases. Fig.23 This is a diagram showing the pass characteristics of the Doherty amplifier according to the fourth embodiment. Fig.24 This is a diagram showing the frequency dependency of the value obtained by dividing the susceptance of the Doherty amplifier by the frequency in Embodiment 4. The frequency band is wider than that of the conventional circuit, but narrower than that of Embodiment 1. This is because the slope of the value obtained by dividing the susceptance of the output circuit of the peak amplifier 5 by the frequency is insufficient.

[0080] In contrast, in this embodiment, the transmission line TL4 of the fourth embodiment is replaced by transmission lines TL41, TL42 and capacitor C31. As a result, since the slope of the value obtained by dividing the susceptance of the output circuit of the peak amplifier 5 by the frequency can be increased, it is possible to obtain a broadband characteristic equivalent to that of the first embodiment. In addition, the T-shaped transmission line composed of the transmission lines TL41, TL42 and the capacitor C31 is set to have the same characteristics as the transmission line TL4 of the third embodiment at the center frequency fc.

[0081] Implementation method 6.

[0082] Fig.25 1 is a circuit diagram showing the output circuit of the carrier amplifier and the peak amplifier of the Doherty amplifier of the sixth embodiment. In the fifth embodiment, the broadband property can be made the same as that of the third embodiment, but the passing loss outside the band becomes larger. In contrast, in the present embodiment, the transmission line TL4 and the capacitor C31 of the fifth embodiment are replaced by a plurality of transmission lines TL41, TL42, TL43 connected in series, and a plurality of capacitors C31 and C32 respectively connected between the connection points of adjacent transmission lines and the grounding points. In this way, by using a plurality of capacitors, no unnecessary resonance is generated near the frequency band, so a wider bandwidth characteristic than that of the fifth embodiment can be achieved. The other structures and effects are the same as those of the first embodiment, etc.

[0083] Description of reference numerals:

[0084] 1…distributor; 2…first input phase delay circuit; 3…second input phase delay circuit; 4…carrier amplifier; 5…peak amplifier; 6…first output phase delay circuit; 7…second output phase delay circuit; 8…impedance conversion circuit; 10…first transistor; 12…second transistor; 13…synthesis point; C1, C2, C3, C4, C5, C31, C32…capacitors; TL1, TL2, TL3, TL4, TL5, TL41, TL42, TL43…transmission lines; W1, W2…wires.

Claims

1. A Doherty amplifier, It is characterized in that have: a distributor that distributes an input signal into a first input signal and a second input signal; A first input phase delay circuit, which delays the first input signal; a second input phase delay circuit, which delays the second input signal; a carrier amplifier having a first transistor for amplifying an output signal of the first input phase delay circuit; a peak amplifier having a second transistor for amplifying an output signal of the second input phase delay circuit; a first output phase delay circuit, which delays the output signal of the carrier amplifier; a second output phase delay circuit, which delays the output signal of the peak amplifier; as well as an impedance conversion circuit that converts an output impedance of a synthesis point of an output of the first output phase delay circuit and an output of the second output phase delay circuit, The passing phase of the path passing through the first input phase delay circuit, the carrier amplifier and the first output phase delay circuit is the same as the passing phase of the path passing through the second input phase delay circuit, the peak amplifier and the second output phase delay circuit in the operating frequency band, When viewed from the first transistor, the parasitic capacitance on the drain side of the first transistor and the first output phase delay circuit form a 90-degree line at the center frequency of the operating frequency band. When viewed from the second transistor, the parasitic capacitance on the drain side of the second transistor and the second output phase delay circuit form a 0 degree line at the center frequency. A value obtained by dividing the susceptance of the circuit composed of the second transistor and the second output phase delay circuit viewed from the synthesis point when the peak amplifier is turned off by the frequency has a positive slope with respect to the frequency.

2. The Doherty amplifier according to claim 1, It is characterized in that A value obtained by dividing the susceptance of the second output phase delay circuit by the frequency has a constant value at the center frequency, In a circuit for subtracting the susceptance from the second output phase delay circuit, the phase is 0 degrees at the center frequency, In the circuit in which the susceptance is added to the first output phase delay circuit, the pass phase becomes 90 degrees at the center frequency.

3. The Doherty amplifier according to claim 1 or 2, It is characterized in that The first output phase delay circuit has: A first wire, one end of which is connected to the drain of the first transistor; a first transmission line, one end of which is connected to the other end of the first conductor; a second transmission line, one end of which is connected to the other end of the first transmission line; A first capacitor connected between the other end of the second transmission line and a ground point; A third transmission line, one end of which is connected to the connection portion between the first transmission line and the second transmission line, and the other end of which is connected to the synthesis point. The passing phase from the drain of the first transistor to the synthesis point is 90 degrees at the center frequency, The second output phase delay circuit has: a second wire, one end of which is connected to the drain of the second transistor; a fourth transmission line, one end of which is connected to the other end of the second conductor; a second capacitor connected between the other end of the fourth transmission line and a grounding point; as well as A third capacitor, one end of which is connected to the connection point between the second conductor and the fourth transmission line, and the other end of which is connected to the synthesis point. A passing phase from the drain of the second transistor to the synthesis point is 0 degrees at the center frequency.

4. The Doherty amplifier according to claim 3, It is characterized in that The length of the first transmission line is longer than the length of the third transmission line.

5. The Doherty amplifier according to claim 3 or 4, It is characterized in that The first output phase delay circuit further includes a fourth capacitor connected between the other end of the third transmission line and a ground point. The second output phase delay circuit further comprises: a fifth transmission line, one end of which is connected to the other end of the third capacitor; and a fifth capacitor connected between the other end of the fifth transmission line and a grounding point.

6. The Doherty amplifier according to claim 3 or 4, characterized in that: The fourth transmission line has two transmission lines connected in series, The second output phase delay circuit further includes a sixth capacitor connected between a connection point of the two transmission lines and a ground point.

7. The Doherty amplifier according to claim 3 or 4, It is characterized in that The fourth transmission line has a plurality of transmission lines connected in series, The second output phase delay circuit further includes a plurality of sixth capacitors respectively connected between connection points of adjacent transmission lines and ground points.

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