Test circuit and usage of ring oscillator

Abstract

This invention provides a test circuit for a ring oscillator (RO). In existing ring oscillator design rules, the NMOS and PMOS transistors in the same inverter are usually MOS field-effect transistors with the same threshold voltage level. This invention flexibly applies test key design rules and logic operations to design a ring oscillator with mixed NMOS and PMOS threshold voltage types (Mixed Vt). This invention can investigate the impact of the saturation current ratio of NMOS and PMOS transistors on the DC performance of the ring oscillator within a single wafer, solving the problem of measurement errors caused by differences between different wafers; it can obtain more sets of experimental designs, save production resources, reduce R&D costs, and improve testing efficiency.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a test circuit for a ring oscillator and its usage method. Background Technology

[0002] A CMOS ring oscillator is a ring circuit consisting of three or more odd-numbered inverters connected end-to-end (e.g., ...). Figure 1 As shown in the image, CMOS ring oscillators are widely used in various integrated circuit systems due to their wide tuning range, low power consumption, simple structure, and small area. The CMOS inverter, as the most basic functional unit, consists of two enhancement-mode MOS field-effect transistors (NMOS and PMOS). As the threshold voltage (Vt) and saturation current (IDSAT) of the NMOS and PMOS transistors change, the static leakage current (IDDQ), dynamic current (IDDA), and gate delay (Td) of the ring oscillator will also change, thus affecting the performance of the CMOS ring oscillator. For existing ring oscillator design guidelines, please refer to... Figure 2 In the same inverter, the NMOS and PMOS transistors are typically MOSFETs with the same voltage threshold (Vt level) (e.g., RNVT and RPVT, LNVT and LPVT, HNVT and HPVT, etc.). Besides the capacitance and resistance of the devices, the performance of a ring oscillator is also affected by the N / P MOS saturation current ratio (N / P IDSAT Ratio). In actual production, to obtain the best-performing ring oscillator, a wafer splitting method is often used during R&D. This involves adjusting the threshold voltages of the NMOS and PMOS transistors to adjust their saturation current ratio, monitoring the ring oscillator performance to find the optimal ratio. However, this method is susceptible to differences between wafers and can easily lead to resource waste and increased R&D costs.

[0003] To solve the above problems, it is necessary to propose a new test circuit for a ring oscillator and its usage method. Summary of the Invention

[0004] In view of the shortcomings of the prior art described above, the purpose of this invention is to provide a test circuit for a ring oscillator and its usage method. This addresses the problem that in the prior art, to obtain a ring oscillator with optimal performance, a method of sacrificing silicon wafers is typically used during the research and development process. This involves adjusting the threshold voltages of NMOS and PMOS transistors to adjust the saturation current ratio of the NMOS and PMOS transistors, monitoring the ring oscillator performance, and thus finding the optimal saturation current ratio of the NMOS and PMOS transistors. However, this method is susceptible to differences between wafers and also easily leads to resource waste and increased research and development costs.

[0005] To achieve the above and other related objectives, the present invention provides a test circuit for a ring oscillator, comprising:

[0006] A ring oscillator, wherein the ring oscillator is composed of x inverters connected end to end, where x is an odd number greater than or equal to three;

[0007] Each inverter consists of an NMOS and a PMOS;

[0008] Both the NMOS transistor and the PMOS transistor include n types of threshold voltages, where n is an integer greater than one;

[0009] The threshold voltage of the NMOS in the ring oscillator is of type 1, and the threshold voltage of the PMOS is of type 2. The number of possible combinations of threshold voltages of the NMOS and PMOS in the ring oscillator is n*n.

[0010] Preferably, both the NMOS and the PMOS are enhancement-mode MOS transistors.

[0011] Preferably, the threshold voltage types of the NMOS transistor and the PMOS transistor include: low threshold voltage, medium threshold voltage, and high threshold voltage.

[0012] Preferably, the ring oscillators with multiple threshold voltage combinations are all disposed on a semiconductor substrate.

[0013] Preferably, the test circuit is used to measure the saturation current ratio of the NMOS and PMOS of the ring oscillator.

[0014] Preferably, the threshold voltage adjustment method for the NMOS transistor and the PMOS transistor includes: providing the NMOS transistor and the design layout; designing a photomask pattern to define the open regions of the NMOS transistor and the PMOS transistor; transferring the photomask pattern onto a photoresist layer on a semiconductor substrate, and then adjusting the threshold voltage of the NMOS transistor and the PMOS transistor.

[0015] Preferably, the threshold voltages of the NMOS and PMOS transistors are adjusted using an ion implantation method.

[0016] This invention provides a method for using a test circuit for a ring oscillator, comprising:

[0017] Step 1: Provide a semiconductor substrate, and form a plurality of ring oscillators on the semiconductor substrate. Each ring oscillator is composed of x inverters connected end to end, where x is an odd number greater than or equal to three.

[0018] Each inverter consists of an NMOS and a PMOS;

[0019] Both the NMOS transistor and the PMOS transistor include n types of threshold voltages, where n is an integer greater than one;

[0020] The threshold voltage of the NMOS in the ring oscillator is of type 1, and the threshold voltage of the PMOS is of type 2. The number of possible combinations of threshold voltages of the NMOS and PMOS in the ring oscillator is n*n.

[0021] Step 2: In the ring oscillator for each threshold voltage combination, change the threshold voltage of the PMOS and the NMOS, and obtain the saturation current ratio data of the NMOS and the PMOS;

[0022] Step 3: Obtain the required setting parameters based on the saturation current ratio data.

[0023] Preferably, both the NMOS and the PMOS in step one are enhancement-mode MOS transistors.

[0024] Preferably, the threshold voltage types of the NMOS transistor and the PMOS transistor in step one include: low threshold voltage, medium threshold voltage, and high threshold voltage.

[0025] Preferably, the threshold voltage adjustment method for the NMSO and PMOS transistors in step one includes: providing the NMOS transistor and the design layout; designing a photomask pattern to define the open regions of the NMOS transistor and PMOS transistor; transferring the photomask pattern onto a photoresist layer on a semiconductor substrate, and then adjusting the threshold voltage of the NMOS transistor and PMOS transistor.

[0026] Preferably, in step one, the threshold voltages of the NMOS and PMOS transistors are adjusted using ion implantation.

[0027] As described above, the test circuit and method of using the ring oscillator of the present invention have the following beneficial effects:

[0028] This invention enables the investigation of the effect of the saturation current ratio of NMOS and PMOS on the DC performance of a ring oscillator within a single wafer, solving the problem of measurement errors caused by differences between different wafers; it also allows for more sets of experimental designs, saving production resources, reducing R&D costs, and improving testing efficiency. Attached Figure Description

[0029] Figure 1 The diagram shown is a schematic representation of a prior art ring oscillator structure.

[0030] Figure 2 The diagram shown is a schematic representation of an inverter structure in the prior art.

[0031] Figure 3 The diagram shown is a schematic representation of an inverter structure according to an embodiment of the present invention.

[0032] Figure 4 The diagram shown is a schematic diagram of an inverter structure according to another embodiment of the present invention;

[0033] Figure 5 The diagram shown illustrates the usage of the test circuit of this invention. Detailed Implementation

[0034] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0035] This invention provides a test circuit for a ring oscillator, comprising:

[0036] A ring oscillator is composed of x inverters connected end to end, where x is an odd number greater than or equal to three.

[0037] Each inverter consists of an NMOS and a PMOS;

[0038] Both NMOS and PMOS transistors include n types of threshold voltages, where n is an integer greater than one.

[0039] The threshold voltage of the NMOS in the ring oscillator is of type 1, and the threshold voltage of the PMOS is of type 2. There are n*n possible combinations of threshold voltages for the NMOS and PMOS in the ring oscillator. Changing the threshold voltage of one of the MOS transistors will generate n new sets of NMOS and PMOS saturation current ratio data. In existing ring oscillator design rules, the NMOS and PMOS transistors in the same inverter are usually MOS field-effect transistors with the same threshold voltage level. This invention flexibly utilizes the Testkey design rule and logic operations to design a ring oscillator device with mixed NMOS and PMOS threshold voltage types (MixedVt).

[0040] In the embodiments of the present invention, both NMOS and PMOS are enhancement-mode MOS transistors.

[0041] In embodiments of the present invention, the threshold voltage types of NMOS and PMOS transistors include: low threshold voltage, medium threshold voltage, and high threshold voltage. It should be noted that the threshold voltage type here can also be any threshold voltage well-known to those skilled in the art, and is not specifically limited here.

[0042] For example, if the threshold voltage types of NMOS and PMOS transistors are low threshold voltage, medium threshold voltage, and high threshold voltage, then there are nine possible combinations of threshold voltages for the NMOS and PMOS transistors in a ring oscillator. These include: NMOS with low threshold voltage and PMOS with low threshold voltage; NMOS with low threshold voltage and PMOS with medium threshold voltage; NMOS with low threshold voltage and PMOS with high threshold voltage; NMOS with medium threshold voltage and PMOS with low threshold voltage (e.g., ...). Figure 3 (as shown); NMOS is the middle threshold voltage, PMOS is the middle threshold voltage (as shown). Figure 2 (as shown); NMOS is for medium threshold voltage, PMOS is for high threshold voltage (as shown). Figure 4 (As shown); NMOS is the high threshold voltage, PMOS is the low threshold voltage; NMOS is the high threshold voltage, PMOS is the medium threshold voltage; NMOS is the high threshold voltage, PMOS is the high threshold voltage.

[0043] In embodiments of the present invention, ring oscillators with various threshold voltage combinations are disposed on a semiconductor substrate. The semiconductor substrate includes a bulk semiconductor substrate or a silicon-on-insulator (SOI) substrate. The SOI substrate includes an insulating layer located beneath a thin semiconductor layer serving as the active layer. The semiconductor of the active layer and the bulk semiconductor typically include the crystalline semiconductor material silicon, but may also include one or more other semiconductor materials, such as germanium, silicon-germanium alloys, compound semiconductors (e.g., GaAs, AlAs, InAs, GaN, AlN, etc.) or alloys thereof (e.g., GaxAl1-xAs, GaxAl1-xN, InxGa1-xAs, etc.), oxide semiconductors (e.g., ZnO, SnO2, TiO2, Ga2O3, etc.) or combinations thereof. The semiconductor material may be doped or undoped. Other substrates that can be used include multilayer substrates, gradient substrates, or mixed-orientation substrates.

[0044] In embodiments of the present invention, the threshold voltage adjustment method for NMOS and PMOS transistors includes: providing design layouts for the NMOS and PMOS transistors; designing photomask patterns to define the open regions of the NMOS and PMOS transistors; transferring the photomask patterns onto a photoresist layer on a semiconductor substrate; and then performing corresponding process adjustments in the open regions to regulate the threshold voltages of the NMOS and PMOS transistors. The corresponding threshold voltages can be adjusted by regulating the open regions of the PMOS and NMOS transistors. The method for adjusting the threshold voltages will differ on different process platforms. When a region is defined as an NMOS or PMOS transistor of a certain threshold voltage type, each step in the process requiring the use of a photomask will use logical operations to define whether that region is open.

[0045] In embodiments of the present invention, the threshold voltage can be adjusted by ion implantation, or other processes well known to those skilled in the art can be used to adjust the threshold voltage.

[0046] In existing ring oscillator design rules, the NMOS and PMOS transistors in the same inverter are usually MOS field-effect transistors with the same threshold voltage level. However, this invention flexibly uses the Testkey design rule and logic operations to design a ring oscillator device with mixed NMOS and PMOS threshold voltage types (Mixed Vt).

[0047] Please see Figure 5 The present invention provides a method for using a test circuit for a ring oscillator, comprising:

[0048] Step 1: Provide a semiconductor substrate on which multiple ring oscillators are formed. Each ring oscillator consists of x inverters connected end-to-end, where x is an odd number greater than or equal to three. The semiconductor substrate may be a bulk semiconductor substrate or a silicon-on-insulator (SOI) substrate. The SOI substrate includes an insulating layer beneath a thin semiconductor layer serving as the active layer. The active layer semiconductor and bulk semiconductor typically include the crystalline semiconductor material silicon, but may also include one or more other semiconductor materials, such as germanium, silicon-germanium alloys, compound semiconductors (e.g., GaAs, AlAs, InAs, GaN, AlN, etc.) or their alloys (e.g., GaxAl1-xAs, GaxAl1-xN, InxGa1-xAs, etc.), oxide semiconductors (e.g., ZnO, SnO2, TiO2, Ga2O3, etc.), or combinations thereof. The semiconductor material may be doped or undoped. Other substrates that may be used include multilayer substrates, gradient substrates, or mixed-orientation substrates.

[0049] Each inverter consists of an NMOS and a PMOS;

[0050] Both NMOS and PMOS transistors include n types of threshold voltages, where n is an integer greater than one.

[0051] The threshold voltage of the NMOS in the ring oscillator is of type 1, and the threshold voltage of the PMOS is of type 2. There are n*n possible combinations of threshold voltages for the NMOS and PMOS in the ring oscillator. When the threshold voltage of one of the MOS transistors is changed, n new sets of saturation current ratio data for the NMOS and PMOS will be generated.

[0052] In the embodiments of the present invention, both the NMOS and PMOS in step one are enhancement-mode MOS transistors.

[0053] For example, the threshold voltage types of the NMOS and PMOS transistors in step one include: low threshold voltage, medium threshold voltage, and high threshold voltage. That is, this includes: NMOS with low threshold voltage and PMOS with low threshold voltage; NMOS with low threshold voltage and PMOS with medium threshold voltage; NMOS with low threshold voltage and PMOS with high threshold voltage; NMOS with medium threshold voltage and PMOS with low threshold voltage (e.g.) Figure 3 (as shown); NMOS is the middle threshold voltage, PMOS is the middle threshold voltage (as shown). Figure 2 (as shown); NMOS is for medium threshold voltage, PMOS is for high threshold voltage (as shown). Figure 4 (As shown); NMOS is the high threshold voltage, PMOS is the low threshold voltage; NMOS is the high threshold voltage, PMOS is the medium threshold voltage; NMOS is the high threshold voltage, PMOS is the high threshold voltage.

[0054] It should be noted that the threshold voltage type here can also be any threshold voltage known to those skilled in the art, and no specific limitation is made here.

[0055] In embodiments of the present invention, the threshold voltage adjustment method for NMOS and PMOS transistors includes: providing design layouts for the NMOS and PMOS transistors; designing photomask patterns to define the open regions of the NMOS and PMOS transistors; transferring the photomask patterns onto a photoresist layer on a semiconductor substrate; and then performing corresponding process adjustments in the open regions to regulate the threshold voltages of the NMOS and PMOS transistors. The corresponding threshold voltages can be adjusted by regulating the open regions of the PMOS and NMOS transistors. The method for adjusting the threshold voltages will differ on different process platforms. When a region is defined as an NMOS or PMOS transistor of a certain threshold voltage type, each step in the process requiring the use of a photomask will use logical operations to define whether that region is open.

[0056] In embodiments of the present invention, the threshold voltage can be adjusted by ion implantation, or other processes well known to those skilled in the art can be used to adjust the threshold voltage.

[0057] In existing ring oscillator design rules, the NMOS and PMOS transistors in the same inverter are usually MOS field-effect transistors with the same threshold voltage level. This invention flexibly applies the Testkey design rules and logic operations to design a ring oscillator device with mixed NMOS and PMOS threshold voltage types (Mixed Vt).

[0058] Step 2: In the ring oscillator for each threshold voltage combination, change the threshold voltage of PMOS and NMOS, and obtain the saturation current ratio data of NMOS and PMOS.

[0059] Step 3: Obtain the required setting parameters based on the saturation current ratio data.

[0060] It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the drawings only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0061] In summary, this invention enables the investigation of the impact of the saturation current ratio of NMOS and PMOS on the DC performance of a ring oscillator within a single wafer, resolving the measurement error problem caused by differences between different wafers. It also allows for more experimental designs, saving production resources, reducing R&D costs, and improving testing efficiency. Therefore, this invention effectively overcomes the various shortcomings of existing technologies and has high industrial applicability.

[0062] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A test circuit for a ring oscillator, characterized in that, include: A ring oscillator, wherein the ring oscillator is composed of x inverters connected end to end, where x is an odd number greater than or equal to three; Each of the inverters consists of an NMOS transistor and a PMOS transistor; Both the NMOS transistor and the PMOS transistor include n types of threshold voltages, where n is an integer greater than one; The threshold voltage of the NMOS transistor in the ring oscillator is a first type selected from the n types of threshold voltages, and the threshold voltage of the PMOS transistor is a second type selected from the n types of threshold voltages. The combination of the threshold voltages of the NMOS transistor and the PMOS transistor in the ring oscillator includes n*n possibilities.

2. The test circuit for the ring oscillator according to claim 1, characterized in that: Both the NMOS transistor and the PMOS transistor are enhancement-mode MOS transistors.

3. The test circuit for the ring oscillator according to claim 1, characterized in that: The threshold voltage types of the NMOS transistor and the PMOS transistor include: low threshold voltage, medium threshold voltage, and high threshold voltage.

4. The test circuit for the ring oscillator according to claim 1, characterized in that: Ring oscillators with various threshold voltage combinations are all mounted on a semiconductor substrate.

5. The test circuit for the ring oscillator according to claim 1, characterized in that: The threshold voltage adjustment method for the NMOS transistor and the PMOS transistor includes: providing a design layout for the NMOS transistor and the PMOS transistor; designing a photomask pattern to define the open regions of the NMOS transistor and the PMOS transistor; transferring the photomask pattern onto a photoresist layer on a semiconductor substrate; and then adjusting the threshold voltage of the NMOS transistor and the PMOS transistor.

6. The test circuit for the ring oscillator according to claim 5, characterized in that: The threshold voltages of the NMOS and PMOS transistors are adjusted using ion implantation.

7. The test circuit for the ring oscillator according to claim 1, characterized in that: The test circuit is used to measure the saturation current ratio of the NMOS transistor and the PMOS transistor in the ring oscillator.

8. A method of using the test circuit for the ring oscillator according to any one of claims 1 to 7, characterized in that, include: Step 1: Provide a semiconductor substrate, and form a plurality of ring oscillators on the semiconductor substrate. Each ring oscillator is composed of x inverters connected end to end, where x is an odd number greater than or equal to three. Each of the inverters consists of an NMOS transistor and a PMOS transistor; Both the NMOS transistor and the PMOS transistor include n types of threshold voltages, where n is an integer greater than one; The threshold voltage of the NMOS transistor in the ring oscillator is a first type selected from the n types of threshold voltages, and the threshold voltage of the PMOS transistor is a second type selected from the n types of threshold voltages. The combination of threshold voltages of the NMOS transistor and the PMOS transistor in the ring oscillator includes n*n possibilities. Step 2: In the ring oscillator for each threshold voltage combination, change the threshold voltage of the PMOS transistor and the NMOS transistor, and obtain the saturation current ratio data of the NMOS transistor and the PMOS transistor. Step 3: Obtain the required setting parameters based on the saturation current ratio data.

9. The method of using the test circuit for the ring oscillator according to claim 8, characterized in that: Both the NMOS transistor and the PMOS transistor mentioned in step one are enhancement-mode MOS transistors.

10. The method of using the test circuit for the ring oscillator according to claim 8, characterized in that: The threshold voltage types of the NMOS and PMOS transistors in step one include: low threshold voltage, medium threshold voltage, and high threshold voltage.

11. The method of using the test circuit for the ring oscillator according to claim 8, characterized in that: The threshold voltage adjustment method for the NMOS transistor and the PMOS transistor in step one includes: providing the design layout of the NMOS transistor and the PMOS transistor; designing a photomask pattern to define the open regions of the NMOS transistor and the PMOS transistor; transferring the photomask pattern onto a photoresist layer on a semiconductor substrate, and then adjusting the threshold voltage of the NMOS transistor and the PMOS transistor.

12. The method of using the test circuit for the ring oscillator according to claim 11, characterized in that: In step one, the threshold voltages of the NMOS and PMOS transistors are adjusted using ion implantation.

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