Method for testing the performance of high multilayer board near conductor CAF performance

Abstract

The present application relates to the technical field of circuit board, and discloses a kind of performance test methods for the CAF resistance of high multilayer board adjacent conductor, for improving the accuracy and efficiency when the CAF resistance of PCB is tested.The method comprises: target layer analysis is carried out on target high multilayer board, to determine the first target layer and the second target layer;First test pattern is set in the first target layer, and second test pattern is set in the second target layer, and hole position analysis is carried out through the first test pattern and the second test pattern, to determine hole position information;Drilling is carried out on target high multilayer board through hole position information, to obtain a plurality of drillings;Based on a plurality of drillings, third test pattern is set in the second target layer, and test pads are connected with third test pattern simultaneously;Resistance value detection is carried out on third test pattern through four-line micro-resistance testing machine, to determine a plurality of resistance values;CAF resistance analysis is carried out on target high multilayer board, to determine performance analysis result.

Description

Technical Field

[0001] This invention relates to the field of circuit board technology, and in particular to a performance testing method for the CAF resistance of adjacent conductors in high multilayer boards. Background Technology

[0002] With the rapid development of electronic information technology, PCBs are gradually becoming smaller, denser, thinner, and more precise. PCB wiring designs are becoming increasingly dense, and via diameters are getting smaller. Currently, 3mil / 3mil trace widths and spacings are common in high-multilayer boards and HDI boards, and the smallest via diameter has reached 0.15mm. This high-density wiring results in increasingly smaller spacing between different nets of PCB conductors. Generally, a conductor spacing of less than 0.3mm between different nets poses a risk of CAF (Conductivity-Aspect-Flattening) failure.

[0003] Currently, CAF failure evaluation is generally conducted using standard test patterns. The designed conductor spacing is typically ≥0.3mm, and these patterns cannot be applied to the same PCB design required by the customer. Furthermore, using these test patterns as a CAF failure evaluation method generally requires 1000 hours of testing. In the event of a short circuit, destructive cross-section analysis is necessary to pinpoint the layer where the problem occurs. This makes it impossible to provide a targeted and rapid evaluation of the CAF resistance of actual manufactured products. Moreover, if the customer stores the products for a period before use, they lack a good method to assess changes in the product's performance before subsequent use. Summary of the Invention

[0004] In view of this, embodiments of the present invention provide a performance testing method for the CAF resistance of adjacent conductors in multilayer boards, which solves the technical problem of low accuracy and efficiency when testing the CAF resistance of PCB boards.

[0005] This invention provides a performance testing method for the CAF resistance of adjacent conductors in a high-multilayer board, comprising: performing target layer analysis on the target high-multilayer board to determine the corresponding first target layer and second target layer; setting a first test pattern in a preset area of ​​the first target layer, and simultaneously setting a second test pattern in a preset area of ​​the second target layer, wherein the first test pattern has at least one detection line, and the second test pattern has at least one detection line; performing hole position analysis on the first test pattern and the second test pattern to determine the corresponding hole position information; drilling the target high-multilayer board using the hole position information, drilling from the first target layer to the second target layer to obtain multiple holes; setting a third test pattern on the second target layer based on the multiple holes, and simultaneously connecting a preset test pad to the third test pattern; using a preset four-wire microresistance tester to detect the resistance value of the third test pattern to determine multiple resistance values; and performing CAF resistance performance analysis on the target high-multilayer board using the multiple resistance values ​​to determine the corresponding performance analysis results.

[0006] In this invention, the step of performing target layer analysis on the target multilayer board to determine the corresponding first target layer and second target layer includes: performing adjacent layer spacing analysis on the target multilayer board to determine multiple adjacent layer spacing values; performing minimum value analysis on the multiple adjacent layer spacing values ​​to determine the corresponding minimum spacing value; and performing target layer analysis on the target multilayer board using the minimum spacing value to determine the corresponding first target layer and second target layer.

[0007] In this invention, the step of performing hole position analysis using the first test pattern and the second test pattern to determine the corresponding hole position information includes: performing a first hole position analysis on at least one detection line set in the first test pattern to determine a first hole position set; performing a second hole position analysis on at least one detection line set in the second test pattern to determine a second hole position set; and generating hole position information using the first hole position set and the second hole position set to determine the corresponding hole position information.

[0008] In this invention, the step of performing a first hole position analysis on at least one detection line set in the first test pattern to determine a first hole position set includes: performing an endpoint position analysis on at least one detection line set in the first test pattern to determine a corresponding endpoint position set; and performing a first hole position analysis on at least one detection line set in the first test pattern using the endpoint position set to determine a first hole position set.

[0009] In this invention, the step of setting a third test pattern on the second target layer based on the plurality of drill holes, and simultaneously connecting a preset test pad to the third test pattern, includes: analyzing the test pattern setting area of ​​the second target layer based on the plurality of drill holes to determine the corresponding image setting area; setting the test pattern on the second target layer based on the image setting area to generate a third test pattern; and connecting the preset test pad to the third test pattern.

[0010] In this invention, the step of detecting the resistance value of the third test pattern and determining multiple resistance values ​​using a pre-set four-wire microresistance tester includes: analyzing the measurement points of the third test pattern to determine multiple sets of corresponding measurement points; and detecting the resistance value of each set of measurement points using the four-wire microresistance tester to determine multiple resistance values.

[0011] In this invention, the step of performing CAF resistance performance analysis on the target high-multilayer board using the plurality of resistance values ​​and determining the corresponding performance analysis results includes: performing vector mapping on the plurality of resistance values ​​respectively to determine the corresponding plurality of resistance vectors; performing CAF resistance performance analysis on the target high-multilayer board using the plurality of resistance vectors and determining the corresponding performance analysis results.

[0012] In this invention, the step of performing CAF resistance performance analysis on the target high-multilayer board using the multiple resistance vectors and determining the corresponding performance analysis results includes: calculating the eigenvalue for each resistance vector to determine the eigenvalue corresponding to each resistance vector; performing threshold analysis on the eigenvalue corresponding to each resistance vector to determine the corresponding threshold analysis result; and performing CAF resistance performance analysis on the target high-multilayer board using the threshold analysis results to determine the corresponding performance analysis result.

[0013] In this invention, target layer analysis is performed on the target multilayer board to determine the corresponding first target layer and second target layer; a first test pattern is set in a preset area of ​​the first target layer, and a second test pattern is set in a preset area of ​​the second target layer, wherein the first test pattern has at least one detection line, and the second test pattern has at least one detection line; hole position analysis is performed using the first and second test patterns to determine the corresponding hole position information; drilling is performed on the target multilayer board using the hole position information, drilling from the first target layer to the second target layer to obtain multiple holes; based on the multiple holes, a third test pattern is set in the second target layer, and a preset test pad is connected to the third test pattern; the resistance value of the third test pattern is detected using a preset four-wire microresistance tester to determine multiple resistance values; the CAF resistance performance of the target multilayer board is analyzed using the multiple resistance values ​​to determine the corresponding performance analysis results. In this embodiment of the invention, an effective detection and control method for the CAF resistance of adjacent conductors in high-multilayer PCBs is provided. The method is simple to operate, does not require slicing and damaging the PCB, and ultimately improves the accuracy and efficiency of CAF resistance performance testing of PCBs. Attached Figure Description

[0014] To more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0015] Figure 1 This is a flowchart illustrating a performance testing method for the CAF resistance of adjacent conductors in a multilayer board according to an embodiment of the present invention. Detailed Implementation

[0016] The technical solution of the present invention will now be clearly and completely described with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0017] In the description of this invention, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing the invention and for simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on the invention. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0018] Furthermore, the technical features involved in the different embodiments of the present invention described below can be combined with each other as long as they do not conflict with each other.

[0019] For ease of understanding, the specific process of the embodiments of the present invention is described below. Please refer to [link / reference]. Figure 1 , Figure 1 This is a flowchart of a performance testing method for the CAF resistance of adjacent conductors in a multilayer board according to an embodiment of the present invention, as shown below. Figure 1 As shown, it includes the following steps:

[0020] S101. Perform target layer analysis on the target multilayer board to determine the corresponding first target layer and second target layer;

[0021] S102. Set a first test pattern in a preset area of ​​the first target layer, and set a second test pattern in a preset area of ​​the second target layer, wherein the first test pattern has at least one detection line and the second test pattern has at least one detection line.

[0022] S103. Analyze the hole positions using the first test pattern and the second test pattern to determine the corresponding hole position information;

[0023] S104. Drill holes in the target multilayer board using the hole location information, from the first target layer of the target multilayer board to the second target layer of the target multilayer board, to obtain multiple holes.

[0024] S105. Based on multiple drill holes, a third test pattern is set on the second target layer, and at the same time, the preset test pads are connected to the third test pattern.

[0025] S106. Using a pre-set four-wire micro-resistance tester, the resistance value of the third test pattern is detected to determine multiple resistance values.

[0026] S107. Perform CAF resistance performance analysis on the target high-multilayer board using multiple resistance values, and determine the corresponding performance analysis results.

[0027] In this invention, a test area is designed at the edge of the scrap board of the target high-multilayer board. The target layer is a layer with small spacing between different network conductors. In this embodiment, the target layer includes a first target layer and a second target layer. Two sets of test patterns are added at the scrap board edges of the first target layer and the second target layer, respectively. One or N test lines are added to each set of test patterns. It should be noted that the width of the test lines is consistent with the PCB pattern in the target high-multilayer board. Through holes with the same diameter as the holes in the PCB pattern are added on both sides of the test lines. The line width and the spacing between the holes are consistent with the pattern. All holes penetrate the entire PCB. Test pads are designed at the other end of the outer layer through holes in the form of lines. After the outer layer pattern is etched in the PCB process, a multimeter can be used at each end of the test pattern to determine whether the lines are broken or whether there is a complete short circuit of the adjacent conductors. Finally, a four-wire micro-resistance test can be used to determine whether there is a CAF aging problem of micro-connection of the adjacent conductors by measuring the resistance value.

[0028] By performing the above steps, target layer analysis is performed on the target multilayer board to determine the corresponding first and second target layers. A first test pattern is set in a preset area of ​​the first target layer, and a second test pattern is set in a preset area of ​​the second target layer. The first and second test patterns each contain at least one detection line. Hole position analysis is performed using the first and second test patterns to determine the corresponding hole position information. Drilling is then performed on the target multilayer board using the hole position information, drilling from the first target layer to the second target layer to obtain multiple holes. Based on these multiple holes, a third test pattern is set on the second target layer, and preset test pads are connected to the third test pattern. The resistance value of the third test pattern is detected using a preset four-wire microresistance tester to determine multiple resistance values. Finally, CAF resistance performance analysis is performed on the target multilayer board using these multiple resistance values ​​to determine the corresponding performance analysis results. In this embodiment of the invention, an effective detection and control method for the CAF resistance of adjacent conductors in high-multilayer PCBs is provided. The method is simple to operate, does not require slicing and damaging the PCB, and ultimately improves the accuracy and efficiency of CAF resistance performance testing of PCBs.

[0029] In one specific embodiment, the process of performing step S101 may specifically include the following steps:

[0030] (1) Analyze the spacing between adjacent layers of the target high-layer board and determine the values ​​of multiple adjacent layer spacings;

[0031] (2) Perform minimum value analysis on multiple adjacent layer spacing values ​​to determine the corresponding minimum spacing value;

[0032] (3) Target layer analysis is performed on the target high multilayer board by using the minimum spacing value to determine the corresponding first target layer and second target layer.

[0033] It's important to note that high-multilayer boards are a common type of circuit board, composed of multiple layers of copper foil and insulating layers. In high-multilayer board design, the spacing between adjacent layers is a crucial parameter. This spacing determines the board's performance indicators, including signal transmission speed, signal interference, and electromagnetic compatibility. Therefore, determining the appropriate spacing is paramount in high-multilayer board design. First, an adjacent layer spacing analysis is performed on the target high-multilayer board. The adjacent layer spacing refers to the distance between two adjacent copper foil layers. In high-multilayer board design, this spacing is determined by the designer based on the board's performance requirements and manufacturing process. When analyzing the adjacent layer spacing, the performance requirements and manufacturing limitations must be considered to determine suitable values. Second, a minimum value analysis is performed on multiple adjacent layer spacing values. This analysis requires comprehensive consideration of the board's performance requirements and manufacturing limitations to determine the minimum adjacent layer spacing value. The minimum adjacent layer spacing value determines the upper limit of the board's performance, thus requiring careful analysis and comparison. Finally, target layer analysis is performed on the target high-multilayer board using the minimum spacing values ​​to determine the corresponding first and second target layers. In multilayer boards, the target layer refers to the copper foil layer that requires special attention. When performing target layer analysis, the performance requirements of the circuit board and the limitations of the manufacturing process must be considered to determine the appropriate target layer. Typically, the target layer refers to the copper foil layer and power layer that are used for signal transmission.

[0034] In one specific embodiment, the process of executing step S103 may specifically include the following steps:

[0035] (1) Perform first hole position analysis on at least one detection line set in the first test pattern to determine the first hole position set;

[0036] (2) Perform second hole position analysis on at least one detection line set in the second test pattern to determine the second hole position set;

[0037] (3) Generate hole location information by using the first hole location set and the second hole location set, and determine the corresponding hole location information.

[0038] The detection lines in the first and second test patterns are used to check whether the hole positions and diameters on the PCB board meet the design requirements. The position and length of the detection lines determine the hole position and size. To determine the hole position information, first and second hole position analyses are required, and the corresponding hole position information is generated based on the hole position information. For at least one detection line in the first test pattern, the position and size of the hole can be determined by the position and length of the line. First, the position of the hole is determined by the position of the line, and then the size of the hole is determined by the length of the line. We can use professional PCB design software to measure the position and length of the detection lines, and determine the first hole position set based on the measurement results. The first hole position set refers to the set of all holes in the first test pattern that meet the requirements. Similarly, for at least one detection line in the second test pattern, the position and size of the hole can be determined by the position and length of the line. We can use professional PCB design software to measure the position and length of the detection lines, and determine the second hole position set based on the measurement results. The second hole position set refers to the set of all holes in the second test pattern that meet the requirements. By generating hole position information using the first and second hole position sets, the corresponding hole position information can be determined. Hole location information includes the position and size of the holes. When determining hole location information, the accuracy requirements for the position and size of the holes must be considered to ensure the quality and performance of the PCB board. Professional PCB design software can be used to generate hole location information, which can then be saved in a corresponding file for use during manufacturing and inspection. In summary, through first and second hole location analysis, the position and size of all compliant holes on the PCB board can be determined, thereby generating the corresponding hole location information.

[0039] In one specific embodiment, the process of performing a first hole position analysis on at least one detection line set in the first test pattern to determine the first hole position set may include the following steps:

[0040] (1) Analyze the endpoint positions of at least one detection line set in the first test pattern to determine the corresponding set of endpoint positions;

[0041] (2) Analyze the first hole position of at least one detection line set in the first test pattern by using the endpoint position set to determine the first hole position set.

[0042] In the first test pattern, for at least one detection line, we can determine its location by analyzing the endpoint positions. By measuring the coordinates of the line endpoints, we can determine the endpoint position set, which is the set of endpoint positions of all detection lines in the first test pattern. By performing a first hole position analysis on the at least one detection line in the first test pattern using the endpoint position set, we can determine the first hole position set. The specific steps are as follows: Based on the endpoint position set, draw the positions and lengths of all detection lines in the PCB design software. Determine the size and position range of the holes according to design and accuracy requirements. For each detection line, determine all the eligible hole positions. The specific method is to scan the line one by one at certain intervals within the position range at both ends of the line, checking if it falls within the hole position range. If it meets the requirements, add it to the first hole position set. Finally, we obtain the first hole position set, which is the set of all eligible hole positions in the first test pattern. In summary, through endpoint position analysis and first hole position analysis, we can determine the position and size of all eligible hole positions in the first test pattern.

[0043] In one specific embodiment, the process of executing step S105 may specifically include the following steps:

[0044] (1) Based on multiple boreholes, perform test graphic setting area analysis on the second target layer to determine the corresponding image setting area;

[0045] (2) Based on the image setting area, set the test pattern for the second target layer and generate the third test pattern;

[0046] (3) Connect the preset test pads to the third test pattern.

[0047] It should be noted that for multiple drill holes, the test pattern setting area analysis can determine the test pattern setting area based on their location and size. The specific steps are as follows: Determine the coverage area based on the location and size of the drill holes. Professional PCB design software can be used to calculate the coverage area. Determine the image area to be tested according to the test requirements. Select the target area within the coverage area as the test pattern setting area. The final test pattern setting area is the image area on the second target layer that needs to be tested. Using the test pattern setting area, the corresponding test pattern can be set on the second target layer. The test pattern should be designed according to the test requirements and accuracy requirements to ensure accurate detection of the hole position information in the target area. Draw the required test pattern within the test pattern setting area. Professional PCB design software can be used for this drawing.

[0048] Determine the position and size of the test pattern, as well as the length and position of the test lines. Ensure the test pattern can accurately detect the hole position information of the target area. Connect the test pads and the third test pattern. Connecting the preset test pads to the third test pattern can be achieved using PCB design software. The specific steps are as follows: In the third test pattern, draw the test pattern corresponding to the test pad. Determine the position and size of the test pattern, as well as the length and position of the test lines. Connect them according to the positional relationship between the test pads and the test patterns. This connection can be achieved by drawing connecting lines. The final connected test pattern and test pads can be used to detect the hole position information of the PCB board.

[0049] In one specific embodiment, the process of executing step S106 may specifically include the following steps:

[0050] (1) Analyze the measurement points of the third test pattern and determine the corresponding multiple sets of measurement points;

[0051] (2) The resistance values ​​of each measurement point are detected by a four-wire micro-resistance tester to determine multiple resistance values.

[0052] Measurement point analysis and resistance value testing are crucial steps in PCB manufacturing and testing, ensuring that the circuit connections and electrical performance of the PCB meet design requirements. The following details the steps and implementation process for analyzing measurement points on the third test pattern and testing the resistance values ​​of each group of measurement points using a four-wire microresistance tester. For the third test pattern, we need to analyze measurement points to determine the points requiring resistance value testing. The specific steps are as follows: Based on the testing and accuracy requirements, determine the points requiring resistance value testing. Mark the positions of these points on the test pattern. Determine the coordinates and number of each point. Professional PCB design software can be used to measure the coordinates and numbers of the points. Based on the position and number of the points, determine multiple groups of measurement points. Each group of measurement points should contain multiple points to ensure the accuracy and reliability of the measurement results. Using a four-wire microresistance tester to test the resistance values ​​of each group of measurement points yields multiple resistance values. The specific steps are as follows: Place the PCB on the four-wire microresistance tester and connect the test probes to the points to be tested. According to the testing requirements, set the test parameters and test range. Automatic or manual testing can be selected, along with different test accuracies and ranges. Start the test and record the results. It is important to maintain a stable and consistent testing environment during the test to ensure the accuracy and reliability of the results. For multiple sets of measurement points, repeat the above steps until the resistance value of all points has been measured. Multiple resistance values ​​are ultimately obtained, which can be analyzed and compared to determine whether the electrical performance and connections of the PCB board meet the design requirements. In summary, measurement point analysis and resistance value testing are crucial steps in PCB board manufacturing and testing. By analyzing the measurement points on the third test pattern, the points requiring resistance value testing and multiple sets of measurement points are determined. Then, a four-wire microresistance tester is used to measure the resistance value of each set of measurement points, ultimately obtaining multiple resistance values.

[0053] In one specific embodiment, the process of executing step S107 may specifically include the following steps:

[0054] (1) Perform vector mapping on multiple resistance values ​​respectively to determine the corresponding multiple resistance vectors;

[0055] (2) The CAF resistance performance of the target high multilayer board is analyzed by multiple resistance vectors, and the corresponding performance analysis results are determined.

[0056] First, multiple resistance values ​​need to be vectorized to determine the corresponding resistance vectors. The specific steps are as follows: Multiple resistance values ​​are used as elements of a vector to form multiple resistance vectors. Each resistance vector is normalized to eliminate the order-of-magnitude differences between different resistance values. Dimensionality reduction algorithms such as PCA can be used to reduce the amount of data and improve the efficiency of performance analysis. The resulting multiple resistance vectors can be used for subsequent performance analysis. CAF resistance performance analysis of the target multilayer board is then performed using these multiple resistance vectors to obtain the corresponding performance analysis results. The specific steps are as follows: Based on the test requirements and the design requirements of the target board, the CAF resistance test conditions and methods are determined. Accelerated testing or natural testing, as well as different temperature and humidity conditions, can be selected. The target board is placed in the test environment and CAF resistance testing is performed. During the test, attention should be paid to the stability and consistency of the test environment, as well as the correct setting of test parameters and ranges. Based on the test results, the corresponding CAF resistance performance analysis results can be obtained. If the target board can maintain stable electrical performance under test conditions, and its CAF resistance time, current, area, and other indicators meet design requirements, it can be considered to have good CAF resistance and reliability. In summary, by analyzing the CAF resistance performance of the target multilayer board using multiple resistance vectors, its durability and reliability under high temperature and high humidity environments can be evaluated.

[0057] In one specific embodiment, the process of performing CAF resistance performance analysis on a target high-multilayer board using multiple resistance vectors and determining the corresponding performance analysis results may include the following steps:

[0058] (1) Calculate the eigenvalues ​​for each resistance vector to determine the eigenvalues ​​corresponding to each resistance vector;

[0059] (2) Perform threshold analysis on the eigenvalues ​​corresponding to each resistance vector and determine the corresponding threshold analysis results;

[0060] (3) The CAF resistance performance of the target high multilayer board is analyzed by the threshold analysis results, and the corresponding performance analysis results are determined.

[0061] First, eigenvalues ​​need to be calculated for each resistance vector to determine its corresponding eigenvalue. Dimensionality reduction algorithms such as PCA or other feature extraction methods can be used to extract the main features of the resistance vectors. The eigenvalues ​​for each resistance vector are then obtained. Threshold analysis is performed on the eigenvalues ​​for each resistance vector to determine the corresponding threshold analysis results. Different threshold analysis methods and threshold ranges can be selected based on the test requirements and the design requirements of the target board. For example, statistical analysis and machine learning methods can be used to determine the upper and lower limits of the threshold. If the eigenvalue exceeds the threshold range, it indicates that the resistance vector is abnormal or faulty. The CAF resistance performance of the target high-multilayer board is then analyzed based on the threshold analysis results to determine the corresponding performance analysis results. Online monitoring of the target board can be performed based on the threshold analysis results to evaluate its CAF resistance performance and reliability. If the target board can maintain stable electrical performance under test conditions and the threshold analysis results meet the design requirements, it can be considered to have good CAF resistance performance and reliability. In summary, by calculating the eigenvalues ​​of resistance vectors and performing threshold analysis, the durability and reliability of PCB boards in high-temperature and high-humidity environments can be evaluated. In practice, it is important to ensure the correct setting of the threshold analysis method and range, as well as the stability and consistency of the testing environment. Additionally, it is necessary to select appropriate performance evaluation metrics to ensure the accuracy and reliability of the evaluation results.

[0062] The above embodiments are only used to illustrate the technical solutions of the present invention and not to limit it. Although the present invention has been described in detail with reference to the embodiments, those skilled in the art should understand that modifications or equivalent substitutions can still be made to the specific implementation of the present invention. Any modifications or equivalent substitutions that do not depart from the spirit and scope of the present invention should be covered within the scope of the claims of the present invention.

Claims

1. A performance testing method for the CAF resistance of adjacent conductors in a multilayer board, characterized in that, The methods include: Perform target layer analysis on the target multilayer board to determine the corresponding first target layer and second target layer; A first test pattern is set in a preset area of ​​the first target layer, and a second test pattern is set in a preset area of ​​the second target layer. The first test pattern has at least one detection line, and the second test pattern has at least one detection line. By analyzing the hole positions using the first and second test patterns, the corresponding hole position information can be determined. The target multilayer board is drilled using the hole location information, from the first target layer of the target multilayer board to the second target layer of the target multilayer board, to obtain multiple holes; Based on the multiple drill holes, a third test pattern is set on the second target layer, and at the same time, a preset test pad is connected to the third test pattern; The resistance value of the third test pattern is detected using a pre-set four-wire microresistance tester to determine multiple resistance values; the step of detecting the resistance value of the third test pattern using a pre-set four-wire microresistance tester to determine multiple resistance values ​​includes: The measurement point analysis is performed on the third test pattern to determine the corresponding multiple sets of measurement points; The resistance values ​​of each group of measurement points are detected by the four-wire micro-resistance tester to determine multiple resistance values. The step of performing CAF resistance performance analysis on the target high-multilayer board using the multiple resistance values ​​and determining the corresponding performance analysis results includes: The plurality of resistance values ​​are vector-mapped respectively to determine the corresponding plurality of resistance vectors; The CAF resistance performance of the target high-multilayer board is analyzed by the multiple resistance vectors to determine the corresponding performance analysis results. The step of performing CAF resistance performance analysis on the target high-multilayer board using the multiple resistance vectors and determining the corresponding performance analysis results includes: Calculate the eigenvalues ​​for each resistance vector to determine the eigenvalues ​​corresponding to each resistance vector; Perform threshold analysis on the eigenvalues ​​corresponding to each resistance vector to determine the corresponding threshold analysis results; The CAF resistance performance of the target high-multilayer board is analyzed based on the threshold analysis results to determine the corresponding performance analysis results. The CAF resistance performance of the target multilayer board is analyzed by using the multiple resistance values ​​to determine the corresponding performance analysis results.

2. The performance test method for the CAF resistance of adjacent conductors in a high-multilayer board according to claim 1, characterized in that, The step of performing target layer analysis on the target multilayer board to determine the corresponding first target layer and second target layer includes: The target multilayer board is subjected to adjacent layer spacing analysis to determine multiple adjacent layer spacing values; Minimum value analysis is performed on the multiple adjacent layer spacing values ​​to determine the corresponding minimum spacing value; The target layer analysis is performed on the target multilayer board by using the minimum spacing value to determine the corresponding first target layer and second target layer.

3. The performance test method for the CAF resistance of adjacent conductors in a multilayer board according to claim 1, characterized in that, The step of analyzing the hole position using the first test pattern and the second test pattern to determine the corresponding hole position information includes: Perform first hole position analysis on at least one detection line set in the first test pattern to determine the first hole position set; Perform second hole position analysis on at least one detection line set in the second test pattern to determine the second hole position set; Hole position information is generated by using the first hole position set and the second hole position set to determine the corresponding hole position information.

4. The performance test method for the CAF resistance of adjacent conductors in a high-multilayer board according to claim 3, characterized in that, The step of performing first hole position analysis on at least one detection line set in the first test pattern to determine the first hole position set includes: Perform endpoint position analysis on at least one detection line set in the first test pattern to determine the corresponding endpoint position set; The first hole position set is determined by performing a first hole position analysis on at least one detection line set in the first test pattern using the set of endpoint positions.

5. The performance test method for the CAF resistance of adjacent conductors in a high-multilayer board according to claim 1, characterized in that, The step of setting a third test pattern on the second target layer based on the plurality of drill holes, and simultaneously connecting the preset test pads to the third test pattern, includes: Based on the multiple boreholes, the test pattern setting area of ​​the second target layer is analyzed to determine the corresponding image setting area; Based on the image setting area, test pattern settings are applied to the second target layer to generate a third test pattern; Connect the preset test pads to the third test pattern.

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