Inter-chip network topology and system suitable for multi-core die

Abstract

This invention relates to a topology and system for inter-chip interconnection networks suitable for multiple chips. It includes: a chip connection unit group, comprising a plurality of chip connection units for adapting and connecting connected chips; and a topology track line for adapting and connecting adjacent chip connection units within the chip connection unit group. For any two chip connection units to be interconnected within the chip connection unit group, based on the positional distribution of the two chip connection units, an interconnection path required for interconnection is configured to enable the interconnection of the two chip connection units using the configured interconnection path. This invention effectively solves the problems of signal attenuation, communication delay, and access congestion during long-distance transmission between multiple chips, improving the reliability of multi-chip interconnection interactions.

Description

Technical Field

[0001] This invention relates to an inter-chip interconnection network topology and system, and more particularly to an inter-chip interconnection network topology and system suitable for multi-chip components. Background Technology

[0002] With the rapid development of artificial intelligence, big data, and 5G, traditional SoC (System on Chip) designs can no longer meet the computing power requirements of these applications. Chiplet integration technology, as a high-computing-power solution, is considered the main development trend for the future.

[0003] The design philosophy of Chiplet is to cut a single SoC into chips with different process nodes, and then interconnect these chips through advanced packaging processes to form a homogeneous or heterogeneous multi-core processor system after packaging. Chiplet technology offers numerous benefits, including reduced reliance on advanced manufacturing processes, shorter design cycles, reduced design complexity, and lower costs.

[0004] However, Chiplet also faces many challenges, one of which is the design of chip-to-chip interconnect networks. Typically, NoC (network on chip), as a scalable modular design approach, has been widely used in multi-chip on-chip interconnect and communication designs. With the advent of active substrate technology, chip-to-chip interconnects have evolved from the traditional single NoC interconnect architecture to two different architecture design methods: NoC + NoI (network on interposer).

[0005] In Chiplet system integration technology, the substrates used for interconnecting the individual chips are usually manufactured using processes with lower process nodes. As a result, the distance between the interconnects between multiple chips is long, signal attenuation and delay are relatively high, and communication power consumption is large.

[0006] For active substrates, the existing NoC interconnect network design requires data transmission between chips to be forwarded through a router. When the transmission path is too long, the data packets will pass through multiple routing nodes during transmission, which will further lead to high communication latency, low data transmission efficiency, and data access congestion. Summary of the Invention

[0007] The purpose of this invention is to overcome the shortcomings of the prior art and provide a topology and system for inter-chip interconnection networks suitable for multi-chip components. This system can effectively solve the problems of signal attenuation, communication delay and access congestion during long-distance transmission between multi-chip components, and improve the reliability of multi-chip interconnection interaction.

[0008] According to the technical solution provided by the present invention, the inter-chip interconnection network topology suitable for multi-core chips includes:

[0009] The core-particle connection unit group includes a plurality of core-particle connection units for adapting and connecting core particles, wherein one core particle is adapted and connected to one core-particle connection unit respectively;

[0010] Topology track lines are used to adapt and connect adjacent core-particle connecting units within a core-particle connecting unit group. For any two core-particle connecting units to be interconnected within the core-particle connecting unit group, an interconnection path required for interconnection of the two core-particle connecting units is configured based on the positional distribution of the two core-particle connecting units to be interconnected, so that the two core-particle connecting units to be interconnected can be interconnected using the configured interconnection path.

[0011] When configuring an interconnect path, the core connection units within the configured interconnect path are configured to be in the required signal selection forwarding state, so as to form an interconnect path using the core connection units configured in the corresponding signal selection forwarding state and the topology track lines used to connect the core connection units.

[0012] The core-particle connecting unit group and the topological orbital line are fabricated on a substrate.

[0013] On the substrate, the core-particle connecting units within the core-particle connecting unit group are arranged in an array.

[0014] For any core-joint unit within the core-joint unit group, it includes at least one transposed connection circuit and several cross signal transmission circuits for configuring the signal transmission direction, wherein,

[0015] The core-to-core adapter unit is connected to a core-to-core via a transposed connection circuit, and uses the transposed connection circuit to perform the required signal interaction with the adapted core-to-core.

[0016] Within the core-particle connection unit, the transposed connection circuit is adapted to the cross signal transmission circuit via the track line within the unit. For signals interacting with the core, the cross signal transmission circuit forwards or rotates the signals to the transposed connection circuit. Alternatively, signals received by the transposed connection circuit are forwarded or rotated and transmitted via the cross signal transmission circuit.

[0017] For signals that are only transmitted through the core-joint unit, the signal transmission direction of the cross signal transmission circuit within the core-joint unit is configured so that the transmitted signal is transmitted to the adjacent core-joint unit.

[0018] Within the core-particle connecting unit, the internal track lines include a first track line body and a second track line body, wherein...

[0019] The cross signal transmission circuit is located at the intersection of the first track line and the second track line within the unit;

[0020] For any cross signal transmission circuit, there are several cross signal transmission units, wherein the cross signal transmission units are staggered in the cross signal transmission circuit so that the staggered cross signal transmission units correspond to the track lines corresponding to the first track line body and the second track line body in the unit body in the cross state respectively.

[0021] A cross signal transmission unit is used to forward signals transmitted through the cross signal transmission unit, or to rotate signals to another track line in a unit corresponding to the track line in the current unit for transmission.

[0022] For any cross signal transmission unit, there are four transmission unit connection ports, wherein,

[0023] The transmission unit connection port is used to connect with the corresponding track line of the first track line or the second track line within the unit;

[0024] The cross signal transmission unit includes a configurable cross signal transmission switch array. After configuring the switching state of the cross signal transmission switch array, the cross signal transmission switch array is used to adapt and connect a connection terminal of the connection port of one transmission unit to the corresponding connection terminal of the connection port of another transmission unit.

[0025] Within the cross signal transmission unit, the connection terminals of the transmission unit connection port are configured using a cross signal transmission switch array, including Wilton connections.

[0026] The transposed connection circuit includes a microbump array for mating with the core, a transposed connection switch array for mating with the microbump array, and a multiplexer for signal selection.

[0027] The microbump array includes a first microbump subarray and a second microbump subarray, which are located on both sides of the first or second track line body within a unit corresponding to the transposed connection circuit.

[0028] For a microbump in the first subarray or the second subarray of microbumps, a transpose connection switch array and a multiplexer are used to connect it to the corresponding track line of the first track line or the second track line in the unit.

[0029] For any given microbump, the microbump is electrically connected to a microbump connection line adapter via a microbump transceiver connection circuit, and is also connected to a transposed connection switch array adapter via the microbump connection line, wherein...

[0030] The microbump transceiver connection circuit includes a transceiver configuration circuit, a pull-up / pull-down circuit, and an ESD protection circuit connected in sequence.

[0031] The microbump is electrically connected to the ESD protection circuit and is also electrically connected to the microbump connection line via a transceiver configuration circuit.

[0032] The transceiver configuration circuit includes a configurable receiving branch and a transmitting branch that are not simultaneously operational.

[0033] When the receiving branch is configured to work, it is used to receive the signal loaded by the core.

[0034] When the transmit branch is configured to work, it sends signals to the core chip using the transmit branch.

[0035] The transmit branch includes a transmit driver TX and a delay unit connected in series with the transmit driver, the delay unit including a digitally controlled delay line DCDL.

[0036] The transposed connection switch array includes a first group of transposed connection switches corresponding to the first sub-array of microbumps and a second group of transposed connection switches corresponding to the second sub-array of microbumps, wherein...

[0037] The first unit group of the transposed connection switch includes a horizontal switching first switch and a vertical switching first switch, which are consistent with the number of rows in the first sub-array of microbumps. A horizontal switching first switch corresponds to the connection unit pad in the same row in the first sub-array of microbumps, and a vertical switching first switch corresponds to a horizontal switching first switch.

[0038] The transposed connection switch second unit group includes a horizontal switching second switch and a vertical switching second switch that are consistent with the row number in the microbump second sub-array. A horizontal switching second switch corresponds to the connection unit pad in the same row in the microbump second sub-array, and a vertical switching second switch corresponds to a horizontal switching second switch.

[0039] Within the first sub-array of microbumps, the pads of the connecting units in the same row are adapted to the first horizontal switching switch via corresponding pad connection lines, and the first horizontal switching switch is adapted to the first vertical switching switch corresponding to the first horizontal switching switch.

[0040] Within the second sub-array of microbumps, the connection unit pads in the same row are adapted to the horizontal switching second switch via corresponding pad connection lines, and the horizontal switching second switch is adapted to the vertical switching second switch corresponding to the horizontal switching second switch.

[0041] The first vertical switching switch and the second vertical switching switch are adapted and connected to the multiplexer.

[0042] The horizontal switching first switch, the horizontal switching second switch, the vertical switching first switch, and the vertical switching second switch each include a plurality of first-side ports located on a first side and a plurality of second-side ports located on a second side, wherein...

[0043] The number of first-side ports on the first side is the same as the number of second-side ports on the second side, and the first-side ports on the first side can be configured to connect to any second-side port on the second side of the switch.

[0044] The multiplexer includes several multiplexing units, wherein,

[0045] The number of multiplexing units in the multiplexer is half the number of microbumps in the microbump array, and the multiplexing unit is a 2-to-2 data selector;

[0046] When selecting, the 2-to-2 data selector is configured to either direct connection selection mode or cross-connection selection mode.

[0047] Within the multiplexing unit, the 2-to-2 data selector is connected to the corresponding track line of the first track line or the second track line within the unit through a selection buffer.

[0048] The corresponding track lines within the first track line body of the unit are perpendicular to the corresponding track lines within the second track line body of the unit.

[0049] The distance between adjacent cross signal transmission circuits shall not exceed 2mm.

[0050] An inter-chip interconnection network system suitable for multiple chips includes a plurality of chips to be interconnected, wherein any chip is assembled and connected to the above-mentioned inter-chip interconnection network topology.

[0051] For two or more chips connected by an inter-chip interconnection network topology, the chips are interconnected based on the inter-chip interconnection network topology.

[0052] The advantages of this invention are: for two core-to-core interconnection units within the inter-chip interconnection network topology, corresponding interconnection paths can be configured to form, so that cores adapted to the core-to-core interconnection unit can be interconnected and interacted using the configured interconnection paths. During interaction, the routing and forwarding method required in the prior art is avoided, which can effectively solve the problems of signal attenuation, communication delay and access congestion during long-distance transmission between multiple cores, and improve the reliability of multi-core interconnection and interaction. Attached Figure Description

[0053] Figure 1 This is a schematic diagram of an embodiment of the interconnect network topology connection between the chip and the substrate of the present invention.

[0054] Figure 2 This is a schematic diagram of one embodiment of the inter-chip interconnection network topology of the present invention on a substrate.

[0055] Figure 3 This is a schematic diagram of one embodiment of the cross signal transmission circuit of the present invention.

[0056] Figure 4 This is a schematic diagram of one connection embodiment within the cross signal transmission unit of the present invention.

[0057] Figure 5 This is a schematic diagram of one embodiment of the transpose connection circuit of the present invention.

[0058] Figure 6 This is a schematic diagram of one embodiment of the microbump transceiver connection circuit of the present invention.

[0059] Figure 7 This is a schematic diagram of one embodiment of the transposed connection switch of the present invention.

[0060] Figure 8 This is a schematic diagram of one embodiment of the multiplexer of the present invention.

[0061] Explanation of reference numerals in the attached figures: 100-substrate, 101-core chip, 102-inter-chip interconnection network topology, 103-transposed connection circuit, 104-core chip connection circuit, 105-topology track line, 201-cross signal transmission circuit, 202-first track line body within the unit, 203-second track line body within the unit, 301-cross signal transmission unit, 302-cross signal transmission single unit in / out track line, 401-transmission unit connects to the first port, 402-transmission unit connects to the second port, 403-transmission unit connects to the third port, 404-transmission unit connects to the fourth port, 601-microbump, 602-transposed connection switch array, 603-multiplexer, 801-2-to-2 data selector, 802-selection buffer. Detailed Implementation

[0062] The present invention will be further described below with reference to specific accompanying drawings and embodiments.

[0063] To effectively address the issues of signal attenuation, communication delay, and access congestion during long-distance transmission between multiple chips 101, and to improve the reliability of multi-chip interconnection interactions, one embodiment of the present invention, for an inter-chip interconnection network topology 102 suitable for multiple chips, includes:

[0064] The core-particle connection unit group includes a plurality of core-particle connection units for adapting and connecting core particles 101, wherein one core particle 101 is adapted and connected to one core-particle connection unit respectively.

[0065] Topology track line 105 is used to adapt and connect adjacent core-particle connecting units within the core-particle connecting unit group. For any two core-particle connecting units to be interconnected within the core-particle connecting unit group, based on the positional distribution of the two core-particle connecting units to be interconnected, an interconnection path required for the interconnection of the two core-particle connecting units is configured so that the two core-particle connecting units to be interconnected can be interconnected using the configured interconnection path.

[0066] When configuring an interconnection path, the core connection units within the configured interconnection path are configured to be in the required signal selection forwarding state, so as to form an interconnection path using the core connection units configured to be in the corresponding signal selection forwarding state and the topology track line 105 used to connect the core connection units.

[0067] The inter-chip interconnect network topology 102 is generally fabricated on a substrate 100, which can be a commonly used active substrate. Therefore, the chip interconnect unit groups and topology track lines 105 within the inter-chip interconnect network topology 102 are fabricated on a substrate 100.

[0068] On the substrate 100, the core-particle connecting units within the core-particle connecting unit group are arranged in an array. Thus, when the core-particle connecting units are arranged in an array and aligned and adapted to connect with the core 101, the core 101 is also arranged in an array on the substrate 100. Figure 1 The diagram illustrates an embodiment in which the array of core particles 101 is distributed on the substrate 100. The array distribution of the core particles 101 on the substrate 100 is related to the array distribution of the core particle connecting units within the core particle connecting unit group on the substrate 100.

[0069] In one embodiment of the present invention, a chip 101 is electrically connected to a chip connection unit, that is, there is a one-to-one correspondence between the chip 101 and the chip connection unit. Therefore, the number of chip connection units in the inter-chip interconnect network topology 102 can be configured according to the number of chips 101. The chips 101 can adopt commonly used forms, and the type of chips 101 can be selected according to actual needs to meet actual interconnection requirements. The chip 101 can be used to form a NoC (Network Component) and the inter-chip interconnect network topology 102 on the substrate 101 can be used to form a NoI (Network Component).

[0070] For the core-core connection units within the core-core connection unit group, adaptation connections are made using topology track lines 105. Generally, adjacent core-core connection units are adapted and connected using topology track lines 105. After corresponding connections are made through topology track lines 105, an inter-chip interconnection network topology 102 can be formed. For any two core-core connection units within the inter-chip interconnection network topology 102, corresponding interconnection paths can be configured to form. Thus, core-core 101 adapted to the core-core connection unit can be interconnected and interact using the configured interconnection paths. During interaction, the routing and forwarding methods required in the prior art are avoided, which effectively solves the problems of signal attenuation, communication delay, and access congestion during long-distance transmission between multiple core-core 101.

[0071] To meet the interaction requirements after the interconnection path is formed by the above configuration, the signal selection and forwarding state of the core link unit can be configured. The signal selection and forwarding state of the core link unit can be configured to interact with the information of the adapted connected core 101, or simply configured as an information transmission channel. The signal selection and forwarding state of the core link unit can be determined according to the actual interaction requirements.

[0072] Since the core 101 and the core connecting unit are correspondingly adapted and connected, the interconnection between core 101 can be achieved after configuring and interconnecting the core connecting units to be interconnected to form an interconnection path. Because the core connecting units are distributed in an array, the distribution positions of two core connecting units to be interconnected can be determined based on the array distribution. Based on their distribution positions within the array, the interconnection path required for interconnecting the two core connecting units can be configured using techniques commonly used in this technical field.

[0073] As can be seen from the above description, the interconnection path formed must include a topology track line 105 for connecting adjacent core connection units. The topology track line 105 is used to adapt and connect adjacent core connection units, specifically to meet the information transmission of signals between core connection units.

[0074] In one embodiment of the present invention, any core-particle connection unit within the core-particle connection unit group includes at least one transposed connection circuit 103 and a plurality of cross signal transmission circuits 201 for configuring the signal transmission direction, wherein,

[0075] The chip connection unit is adapted to connect with a chip 101 through the transposition connection circuit 103, and uses the transposition connection circuit 103 to perform the required signal interaction with the adapted chip 101.

[0076] Within the core-particle connection unit, the transposed connection circuit 103 is adapted to the cross signal transmission circuit 201 via the internal track line. For signals that interact with the core-particle 101, the cross signal transmission circuit 201 forwards or rotates the signals to the transposed connection circuit 103. Alternatively, signals received by the transposed connection circuit 103 are forwarded or rotated by the cross signal transmission circuit 201.

[0077] For signals that are only transmitted through the core-joint unit, the signal transmission direction of the cross signal transmission circuit 201 within the core-joint unit is configured so that the transmitted signals are transmitted to the adjacent core-joint unit.

[0078] The interconnected cores 101 generally take on different types or functions. To adapt to the connection and cooperation with the corresponding cores 101, the core connection units within the core connection unit group will generally be different. Specifically, a core connection unit generally includes at least one transposed connection circuit 103 and several cross signal transmission circuits 201. The transposed connection circuit 103 is used to adapt and connect with the core 101, while the cross signal transmission circuits 201 are used to configure the direction of signal transmission to meet the needs of signal transmission within and / or between core connection units.

[0079] After the core 101 is connected to the transposed connection circuit 103 in a core connection unit, when it needs to interact with another core 101, the core 101 must first perform signal interaction with the transposed connection circuit 103. The signal interaction means that the signal is transmitted to the core 101, or the signal of the core 101 is received by the transposed connection circuit 103 and transmitted to the position of the other core 101.

[0080] Multiple cross signal transmission circuits 201 within the core-joint unit are interconnected via internal track lines. When the transposed connection circuit 103 is adapted to the cross signal transmission circuit 201 via internal track lines, the transposed connection circuit 103 and all cross signal transmission circuits 201 can form a signal transmission path to satisfy the transmission of configuration signals in a specified direction within the core-joint unit.

[0081] As described above, for a core interconnect unit, the signals within the core interconnect unit include signals received from core 101, signals sent to core 101, or signals that need to be transmitted over the interconnect path. For signals received from core 101, the transposed connection circuit 103 connected to core 101 is used for reception, and then the cross signal transmission circuit 201 is used for forwarding or rotational transmission. For signals sent to core 101, the signals need to be forwarded or rotated to the transposed connection circuit 103 first, so that the transposed connection circuit 103 can send and load the signals to core 101 for reception and processing by core 101.

[0082] In one embodiment of the present invention, forwarding generally refers to not changing the direction of signal transmission, while rotation generally refers to changing the direction of signal transmission, such as changing the signal from a horizontal transmission direction to a vertical transmission direction, or from a vertical direction to a horizontal direction.

[0083] For signals that need to be transmitted over the interconnection path, it can be seen from the function of the transposed connection circuit 103 that the signals generally do not need to pass through the transposed connection circuit 103. At this time, the signal transmission direction of the cross signal transmission circuit 201 in the core connection unit is configured so as to transmit the transmitted signals to the adjacent core connection unit.

[0084] In one embodiment of the present invention, within the core-particle connecting unit, the track line within the unit includes a first track line body 202 and a second track line body 203, wherein...

[0085] The cross signal transmission circuit 201 is located at the intersection of the first track line 202 and the second track line 203 within the unit;

[0086] Any cross signal transmission circuit 201 includes a plurality of cross signal transmission units 301, wherein the cross signal transmission units 301 are staggered in the cross signal transmission circuit 201 so that the staggered cross signal transmission units 301 correspond to the track lines corresponding to the first track line body 202 and the second track line body 203 in the unit body in the cross state, respectively.

[0087] A cross signal transmission unit 301 is used to forward the signal transmitted through the cross signal transmission unit 301, or to rotate the signal to another track line in another unit corresponding to the track line in the current unit for transmission.

[0088] Figure 2 The diagram illustrates one embodiment of the inter-chip interconnect network topology 102 on substrate 100. Figure 2The track line within the unit includes a first track line body 202 and a second track line body 203. The track lines within the second track line body 203 are horizontally distributed, and the track lines within the first track line body 202 and the track lines within the second track line body 203 are perpendicular to each other.

[0089] Figure 2 In this design, the first track line 202 and the second track line 203 within the array-distributed cell simultaneously form intra-cell track lines and topological track lines 105. Of course, in specific implementations, only the first track line 202 and the second track line 203 within the cell can be used to form intra-cell track lines, while the topological track lines 105 can be formed in other desired forms. The specific form can be selected according to actual needs, prioritizing the required inter-chip interconnection. Furthermore, Figure 2 In the illustrated embodiment, the chip interconnect unit and the transpose interconnect circuit 103 within the chip interconnect unit adopt the same form. In specific implementation, it can be determined according to... Figure 2 The embodiments are adjusted as needed to meet the connection and fit of different core particles 101.

[0090] Figure 2 In this invention, the cross signal transmission circuits 201 are distributed at the intersection of the first track line 202 and the second track line 203 within the unit. Therefore, the number of cross signal selection circuits 201 is related to the layout of the track lines within the unit. When the cross signal transmission circuits 201 are located at the intersection of the first track line 202 and the second track line 203 within the unit, the required signal forwarding or transposition can be achieved using the cross signal transmission circuits 201. In one embodiment of the invention, when the target signal speed of the inter-chip interconnection network topology 102 is 1Gbps, considering signal integrity, the distance between the cross signal transmission circuits 201 should be limited to less than 2mm.

[0091] The cross signal transmission circuit 201 can generally adopt the same form. Generally, a number of cross signal transmission units 301 are provided in a cross signal transmission circuit 201. Figure 3 An embodiment of a cross signal transmission circuit 201 is shown. Figure 3 In this context, the COB unit is the cross signal transmission unit 301. The cross signal transmission units 301 are interleaved within the cross signal transmission circuit 201, such as... Figure 3 In the cross signal transmission unit 301, the cross signal transmission unit 301 is arranged sequentially from the upper left corner to the lower right corner in the cross signal transmission circuit 201.

[0092] The staggered distribution of the cross signal transmission units 301 specifically means that the track line corresponding to one cross signal transmission unit 301 is completely different from the track line corresponding to another cross signal transmission unit 301, so that the staggered distribution of the cross signal transmission units 301 corresponds to the track lines corresponding to the first track line body 202 and the second track line body 203 in the unit body in the cross state.

[0093] When both the first track line body 202 and the second track line body 203 within the unit contain 128 track lines, a cross signal transmission circuit 201 includes 16 cross signal transmission units 301. In this case, each cross signal transmission unit 301 corresponds to 8 track lines within the first track line body 202 and the second track line body 203 within the unit. That is, the 16 cross signal transmission units 301 are alternately distributed to achieve a correspondence with each of the 128 track lines. In specific implementation, when the first track line body 202 and the second track line body 203 within the unit contain other numbers of track lines, the number of cross signal transmission units 301 and their staggered distribution can be determined based on the number of track lines, ensuring the correspondence of all track lines is satisfied.

[0094] In one embodiment of the present invention, any cross signal transmission unit 301 includes four transmission unit connection ports, wherein,

[0095] The transmission unit connection port is used to connect with the corresponding track line of the first track line 202 or the second track line 203 in the unit body;

[0096] The cross signal transmission unit 301 includes a configurable cross signal transmission switch array. After configuring the switching state of the cross signal transmission switch array, the cross signal transmission switch array is used to make a connection terminal of the connection port of one transmission unit adapt and connect with the corresponding connection terminal of the connection port of another transmission unit.

[0097] Depend on Figure 2 As can be seen from the distribution of the cross signal transmission unit 301 in the cross signal transmission circuit 201, one cross signal transmission unit 301 includes four transmission unit connection ports. Figure 4 An embodiment of a cross signal transmission unit 301 with four transmission unit connection ports is shown, wherein the four transmission unit connection ports are: transmission unit connection to the first port 401, transmission unit connection to the second port 402, transmission unit connection to the third port 403, and transmission unit connection to the fourth port 404.

[0098] When both the first track line body 202 and the second track line body 203 within the aforementioned unit contain 128 track lines, each cross signal transmission unit 301 needs to correspond to 8 corresponding track lines. Therefore... Figure 4 In this configuration, the first port 401, the second port 402, the third port 403, and the fourth port 404 of the transmission unit each include eight connection terminals. When the first track line 202 and the second track line 203 within the unit contain other numbers of track lines, the number of connection terminals at each transmission unit connection port needs to be adjusted accordingly, as detailed in the above description.

[0099] As can be seen from the above description, the cross signal transmission unit 301 is used to achieve the forwarding or rotation of signals. Figure 4 In this embodiment, when a signal travels from the first port 401 of the transmission unit to the third port 403 of the transmission unit via the cross signal transmission switch array, signal forwarding occurs. When a signal travels from the first port 401 of the transmission unit to the second port 402 of the transmission unit or the fourth port 404 of the transmission unit via the cross signal transmission switch array, signal rotation occurs. Similarly, other signal forwarding or rotation scenarios can be derived, which will not be illustrated here.

[0100] As described above, a configurable cross signal transmission switch array is used to achieve signal forwarding or rotation. Figure 4 In the cross signal transmission unit 301, the connection terminals of the transmission unit connection port are configured using a cross signal transmission switch array, including Wilton connections.

[0101] Figure 4 In the illustrated Wilton connection, the terminal numbered 0 in the first port 401 of the transmission unit can be connected to the terminal numbered 6 in the second port 402 of the transmission unit, the terminal numbered 0 in the third port 403 of the transmission unit, or the terminal numbered 7 in the fourth port 404 of the transmission unit. The specific connection formed can be determined based on the configuration of the cross signal transmission switch array. Therefore, the specific configuration of the cross signal transmission switch array is based on satisfying the Wilton connection formed above. Of course, when other connection combinations are used, the cross signal transmission switch array needs to meet the corresponding connection combination form, that is, ultimately achieve the purpose of signal forwarding or rotation.

[0102] Figure 4In the embodiment, the cross signal transmission unit 301 has a total of 48 connections, therefore requiring 48 control bits. In addition, an additional 32 control bits are needed to control the direction of the 32 connection terminals of the four transmission unit connection ports of the cross signal transmission unit 301. Thus, a cross signal transmission unit 301 requires a total of 80 control bits, meaning that a cross signal transmission circuit 201 requires 80x16 (1280) bits.

[0103] In one embodiment of the present invention, the transposed connection circuit 103 includes a microbump array for mating connection with a chip, a transposed connection switch array 302 for mating connection with the microbump array, and a multiplexer 603 for signal selection, wherein,

[0104] The microbump array includes a first microbump subarray and a second microbump subarray, which are located on both sides of the first track line body 202 or the second track line body 203 within a unit corresponding to the transposed connection circuit 103.

[0105] For a microbump in the first subarray or the second subarray of microbumps, a transpose connection switch array 602 and a multiplexer 603 are used to connect it to the corresponding track line of the first track line 202 or the second track line 203 in the unit.

[0106] In the transpose connection circuit 103, a microbump array is used to adapt and connect with the core 101. Figure 1 In the process, the core 101 has a core connection circuit 104, which corresponds to the micro bump array. That is, the core connection circuit 104 is in a form that can meet the connection and cooperation with the micro bump array. At this time, the core 101 is aligned and connected to the micro bump array through the core connection circuit 104 to realize the adaptive electrical connection between the core 101 and the core connection unit.

[0107] To facilitate the adaptation and connection between the transposed connection circuit 103 and the cross signal transmission circuit 201, the microbump array includes a first microbump subarray and a second microbump subarray. The first microbump subarray and the second microbump subarray are respectively located on both sides of the first track line body 202 or the second track line body 203 within the unit corresponding to the transposed connection circuit 103.

[0108] Figure 5 An embodiment of the transpose connection circuit 103 is shown in the figure. Figure 5 The track is either the first track line 202 or the second track line 203 within the unit, and a first sub-array of microbumps and a second sub-array of microbumps are formed on both sides of the track, respectively. Figure 5In this configuration, both the first and second subarrays of microbumps contain 64 microbumps 601. At this time, the microbumps in the first and second subarrays of microbumps are arranged in an 8-row, 8-column configuration. In specific implementations, the first and second subarrays of microbumps can also have other quantities and array distributions, depending on whether they can meet the adaptation connection requirements with the core 101.

[0109] As explained above, after the core 101 is adapted and connected to the transposed connection circuit 103 via the microbump array, the signal needs to be forwarded or rotated via the cross signal transmission circuit 201. Therefore, it is connected to the corresponding track line of the first track line 202 or the second track line 203 within the unit through the transposed connection switch array 602 and the multiplexer 603. Figure 5 In the implementation case, that is, the microbump array is connected to Figure 5 The track.

[0110] Figure 5 In the middle, the microbump array includes 128 microbumps 601, the above-mentioned for Figure 3 In the description, the number of track lines in the first track line body 202 and the second track line body 230 within the unit cell is 128, thus, the microbumps 601 within the microbump array can interact with... Figure 5 The tracks contained in the middle track are in one-to-one correspondence.

[0111] In one embodiment of the present invention, for any microbump 601, the microbump 601 is electrically connected to a microbump connection line via a microbump transceiver connection circuit, and is also connected to a transposed connection switch array 302 via the microbump connection line.

[0112] The microbump transceiver connection circuit includes a transceiver configuration circuit, a pull-up / pull-down circuit, and an ESD protection circuit connected in sequence.

[0113] The microbump 601 is electrically connected to the ESD (Electro-Static discharge) protection circuit and is also electrically connected to the microbump connection line adapter via the transceiver configuration circuit.

[0114] As can be seen from the above description, the microbump 601 is adapted to the core 101. In order to realize the transmission and reception of signals between the microbump 601 and the core 101, each microbump 601 needs to be adapted to the microbump transceiver connection circuit. At this time, a microbump 601 is adapted to a microbump connection line through the connected microbump transceiver connection circuit, so as to adapt to the transposed connection switch array 302 using the microbump connection line.

[0115] To meet the signal transmission and reception requirements with the chip 101, the microbump transceiver connection circuit includes at least a transceiver configuration circuit, a pull-up / pull-down circuit, and an ESD protection circuit. The microbump 601 is electrically connected to the ESD protection circuit, and the transceiver configuration circuit is electrically connected to the microbump connection line adapter corresponding to the microbump 601. The transceiver configuration circuit can configure the microbump transceiver connection circuit to be in a receiving or transmitting state, the pull-up / pull-down circuit can be used to implement pull-up or pull-down, and the ESD protection circuit can provide the required ESD protection, thereby improving the reliability of the electrical connection between the microbump 601 and the chip 101.

[0116] In one embodiment of the present invention, the transceiver configuration circuit includes a configurable receiving branch and a transmitting branch that are not simultaneously operational, wherein,

[0117] When the receiving branch is configured to work, the receiving branch is used to receive the signal loaded by the core chip 101;

[0118] When the transmit branch is configured to work, it sends a signal to the core 101 using the transmit branch.

[0119] The transmit branch includes a transmit driver TX and a delay unit connected in series with the transmit driver, the delay unit including a digitally controlled delay line DCDL.

[0120] As can be seen from the above description, the transceiver configuration circuit can be configured to be in a receiving state or a transmitting state. Since the microbump 601 is adapted to connect with the chip 101, the receiving state specifically refers to configuring the transceiver configuration circuit to receive the signal from the chip 101; the transmitting state specifically refers to sending information to the chip 101 via the microbump 601.

[0121] To enable either receiving or transmitting functionality, the transceiver configuration circuit includes a receiving branch and a transmitting branch. The receiving and transmitting branches cannot be active simultaneously; that is, the transceiver configuration circuit can only receive or transmit signals. Specifically, when the receiving branch is configured to operate, it receives signals loaded onto the chip; when the transmitting branch is configured to operate, it transmits signals to the chip.

[0122] Figure 6 An embodiment of a microbump transceiver connection circuit is shown, wherein the transmitting branch includes a transmitting driver TX and a delay unit employing a digitally controlled delay line DCDL, the receiving branch includes a receiving driver RX, the receiving end of the receiving driver RX and the transmitting end of the transmitting driver TX are both adapted and connected to pull-up / pull-down circuits, and the receiving output end of the receiving driver RX and the digitally controlled delay line DCDL are adapted and connected to the microbump connection line.

[0123] The transmit driver TX and receive driver RX can adopt existing common forms. Both the transmit driver TX and receive driver RX are controlled by configuration bits. When the configuration bit is 1, the transmit driver TX can be configured to be in the working state; when the configuration bit is 0, the receive driver RX can be configured to be in the working state. When the transmit driver TX is in the working state, the transmit branch is in the working state; when the receive driver RX is in the working state, the receive branch is in the working state. The digital control delay line DCDL can adopt existing common time delay forms. The digital control delay line DCDL can meet the timing requirements when transmitting signals to chip 101.

[0124] Figure 6 In this circuit, the pull-up / pull-down circuit includes a pull-up section and a pull-down section. The pull-up section includes an NMOS transistor N1 and a resistor R1, and the pull-down section includes a PMOS transistor P1 and a resistor R2. The source terminal of the NMOS transistor N1 is connected to voltage VDD1, and the drain terminal of the NMOS transistor N1 is connected to one end of the resistor R1. The other end of the resistor R1 is connected to one end of the resistor R2, the receiver terminal of the receiver driver RX, and the transmitter terminal of the transmitter driver TX. The other end of the resistor R2 is connected to the drain terminal of the PMOS transistor P1, and the source terminal of the PMOS transistor P1 is grounded.

[0125] The voltage VDD1 can be selected and determined as needed. The gate terminals of NMOS transistor N1 and PMOS transistor P1 can be connected to the controller on substrate 100. The controller can be used to configure the switching states of NMOS transistor N1 and PMOS transistor P1. When NMOS transistor N1 is in the ON state, the pull-up / pull-down circuit is in the pull-up state; when PMOS transistor P1 is in the ON state, the pull-up / pull-down circuit is in the pull-down state. NMOS transistor N1 and PMOS transistor P1 are generally not in the ON state at the same time. Of course, other commonly used circuit forms can also be used for the pull-up / pull-down circuit, depending on whether they can meet the pull-up / pull-down requirements. Resistor R1 is generally 1.5KΩ, and resistor R2 is generally 15KΩ.

[0126] Figure 6 In this circuit, the ESD protection circuit includes diodes D1 and D2. The cathode of diode D1 is connected to voltage VDD2, and the anode of diode D1 is connected to the cathode of diode D2, as well as resistors R1 and R2. The anode of diode D2 is grounded. The ESD protection circuit using diodes D1 and D2 can provide protection against a 50V CDM (Charged Device Model).

[0127] In one embodiment of the present invention, the transposed connection switch array 602 includes a first transposed connection switch unit group corresponding to a first sub-array of microbumps and a second transposed connection switch unit group corresponding to a second sub-array of microbumps, wherein,

[0128] The first unit group of the transposed connection switch includes a horizontal switching first switch and a vertical switching first switch, which are consistent with the number of rows in the first sub-array of microbumps. A horizontal switching first switch corresponds to the connection unit pad in the same row in the first sub-array of microbumps, and a vertical switching first switch corresponds to a horizontal switching first switch.

[0129] The transposed connection switch second unit group includes a horizontal switching second switch and a vertical switching second switch that are consistent with the row number in the microbump second sub-array. A horizontal switching second switch corresponds to the connection unit pad in the same row in the microbump second sub-array, and a vertical switching second switch corresponds to a horizontal switching second switch.

[0130] Within the first sub-array of microbumps, the pads of the connecting units in the same row are adapted to the first horizontal switching switch via corresponding pad connection lines, and the first horizontal switching switch is adapted to the first vertical switching switch corresponding to the first horizontal switching switch.

[0131] Within the second sub-array of microbumps, the connection unit pads in the same row are adapted to the horizontal switching second switch via corresponding pad connection lines, and the horizontal switching second switch is adapted to the vertical switching second switch corresponding to the horizontal switching second switch.

[0132] The first vertical switching switch and the second vertical switching switch are adapted and connected to the multiplexer.

[0133] As can be seen from the above description, when the microbump array is divided into a first microbump subarray and a second microbump subarray, in order to meet the connection and cooperation with the microbump array, the transposed connection switch array 602 includes a first transposed connection switch unit group and a second transposed connection switch unit group.

[0134] In one embodiment of the present invention, the first unit group of the transposed connection switch includes a horizontal switching first switch and a vertical switching first switch, wherein the number of the horizontal switching first switches and the vertical switching first switches is consistent with the number of rows of the first sub-array of microbumps. Figure 5 In the illustrated embodiment, when both the first subarray and the second subarray of microbumps are 8*8 arrays, the number of horizontal switching first switches and vertical switching first switches are both 8, and the number of horizontal switching second switches and vertical switching second switches are also both 8.

[0135] Figure 5In the illustrated embodiment, the horizontal direction specifically refers to the direction parallel to the track in the diagram, and the vertical direction is perpendicular to the horizontal direction. For the first unit group of transposed connection switches, the horizontal switching first switch corresponds directly to a row of microbumps 601 within the first microbump subarray, and is generally fabricated directly below the corresponding row of microbumps 601 in the microbump subarray. The vertical switching first switch and the horizontal switching first switch are in one-to-one correspondence. The vertical switching first switch is located in... Figure 5 The microbumps are also distributed longitudinally on the outside of the first subarray of the microbumps.

[0136] For details regarding the second unit group of the transposed connection switch, including the horizontal switching of the second switch and the vertical switching of the second switch, please refer to the above description of the horizontal switching of the first switch and the vertical switching of the first switch; these details will not be repeated here.

[0137] In one embodiment of the present invention, the horizontal switching first switch, the horizontal switching second switch, the vertical switching first switch, and the vertical switching second switch each include a plurality of first-side ports located on a first side and a plurality of second-side ports located on a second side, wherein...

[0138] The number of first-side ports on the first side is the same as the number of second-side ports on the second side, and the first-side ports on the first side can be configured to connect to any second-side port on the second side of the switch.

[0139] right Figure 5 The embodiments shown in the figure, Figure 7 The illustration shows one embodiment of a horizontal switching first switch, a horizontal switching second switch, a vertical switching first switch, and a vertical switching second switch, which can employ the same transposed connection switch. The transposed connection switch has a first-side port on a first side and a second-side port on a second side corresponding to the first-side port. Figure 7 In the diagram, the port numbers corresponding to the first side port on the first side and the second side port on the second side are both 0 to 7. For the eight microbumps 601 / connection unit pads 21 in the same row, the pad connection lines that are adapted to and connected to the microbumps 601 are respectively connected to the eight ports of the first side port of the horizontal switching first switch or the horizontal switching second switch.

[0140] Within the transposed connection switch, the first port on the first side can be configured to be adapted and connected to any second port on the second side of the transposed connection switch. Figure 6 In the illustrated embodiment, port number 0 on the first side can be configured to connect with ports numbered 0 to 7 on the second side. In specific implementation, the transposition switch can adopt a commonly used form, as long as it can satisfy the corresponding connection between the first and second side ports of the transposition switch.

[0141] In one embodiment of the present invention, the multiplexer 603 includes a plurality of multiplexing units, wherein,

[0142] The number of multiplexing units in multiplexer 603 is half the number of microbumps 601 in microbump array, and the multiplexing unit is a 2-to-2 data selector 801;

[0143] When selecting, the 2-to-2 data selector 801 is configured to either direct connection selection mode or cross-connection selection mode.

[0144] As described above, when the microbump array includes 128 microbumps 601, the multiplexer 603 includes 64 multiplexing units. In one embodiment of the present invention, the multiplexing unit includes a 2-to-2 data selector 801, that is, the 2-to-2 data selector 801 can be used to connect the microbumps 601 to the array. Figure 5 Connection configuration for the track.

[0145] In one embodiment of the present invention, a 2-to-2 data selector 801 configured in a cross-connection selection state is provided, wherein...

[0146] One input terminal of the 2-to-2 data selector 801 corresponds to a pad connection line in the first subarray of microbumps, and the other input terminal of the 2-to-2 data selector 801 corresponds to a pad connection line in the second subarray of microbumps.

[0147] Figure 8 The diagram illustrates one embodiment of a multiplexer 603, wherein within a multiplexing unit, a 2-to-2 data selector 801 is connected to a corresponding track line of a first track line 202 or a second track line 203 within the unit via a selection buffer 802. The 2-to-2 data selector 801 and the selection buffer 802 can adopt existing commonly used forms, as long as they meet the requirements of selection and buffering.

[0148] Figure 8 In the 2-to-2 data selector 801 shown, the two input ports of the 2-to-2 data selector 801 can be connected to a bidirectional buffer in an inside pattern (= shape) or a cross-group pattern (x shape). Figure 5 The track in the code. In specific implementation, one control bit is used to control the selection connection style of the 2-to-2 data selector 801, and the multiplexing unit is used to implement the transpose connection circuit 103 and... Figure 5 Direct or cross-connection of the middle track, Figure 8 In the middle, a multiplexer unit and Figure 5 The two track lines within the middle track are connected, and the connection between the input terminal in1, the input terminal in2 and the corresponding two track lines can be selected.

[0149] Figure 8The two tracks are track0 and track64. In a direct connection, input in1 is selected to connect to track0 via a multiplexer, and input in2 is selected to connect to track64 via a multiplexer. In a cross-connection, input in1 is selected to connect to track64 via a multiplexer, and input in2 is selected to connect to track0 via a multiplexer. Therefore, by configuring the connection method of the multiplexer, the connectivity of the circuit can be increased.

[0150] In addition, the input terminals in1 and in2 in the figure are micro-bumps 601 corresponding to the switch array 602 via transposition connection, that is, input terminals in1 and in2 each correspond to a micro-bump 601.

[0151] When the aforementioned microbump array includes 128 microbumps 601, the corresponding numbers obtained according to the distribution of the microbump array are: [0:63][64:127]. At this time, it can be... Figure 6 The track numbers in the diagram are track lines [0:63][64:127]. As explained above, there are 64 2-to-2 data selectors 801. These 64 2-to-2 data selectors 801 can correspond to 128 track lines, and each of the 64 2-to-2 data selectors can correspond to one of the 128 micro-bumps 601.

[0152] Specifically, the correspondence is as follows: a microbump 601 in the first microbump subarray is connected to a selection input terminal of a 2-to-2 data selector 801 via a corresponding pad connection line, a horizontal switching first switch, and a vertical switching first switch; at the same time, a microbump 601 in the second microbump subarray is connected to another selection input terminal of the 2-to-2 data selector 801 via a corresponding pad connection line, a horizontal switching second switch, and a vertical switching second switch.

[0153] Based on this encoding method, in a direct connection, the micro-bump 601 numbered [0:63] is adapted and connected to the track line [0:63], and the micro-bump 601 numbered [64:127] is adapted and connected to the track line [64:127]. In a cross connection, the micro-bumps 601 numbered [0:63] and [64:127] are respectively connected to the track lines [64:127] and [0:63].

[0154] In summary, a multi-chip interconnection network system suitable for multiple chips can be obtained, including a number of chips 101 to be interconnected, wherein any chip 101 is assembled and connected to the above-mentioned inter-chip interconnection network topology 102.

[0155] For two or more chips connected by an inter-chip interconnection network topology 102, the chips 101 are interconnected based on the inter-chip interconnection network topology 102.

[0156] In one embodiment of the present invention, the inter-chip interconnection network system is used to realize the interconnection and interaction of multiple chips 101 using the inter-chip interconnection network topology 102. The inter-chip interconnection network topology 102, and the manner and process of interconnection and interaction using the inter-chip interconnection network topology 102 can be referred to the above description, and will not be repeated here.

Claims

1. A chip-to-chip interconnect network topology suitable for multi-core chips, characterized in that, include: The core-particle connection unit group includes a plurality of core-particle connection units for adapting and connecting core particles, wherein one core particle is adapted and connected to one core-particle connection unit respectively; Topology track lines are used to adapt and connect adjacent core-particle connecting units within a core-particle connecting unit group. For any two core-particle connecting units to be interconnected within the core-particle connecting unit group, an interconnection path required for interconnection of the two core-particle connecting units is configured based on the positional distribution of the two core-particle connecting units to be interconnected, so that the two core-particle connecting units to be interconnected can be interconnected using the configured interconnection path. When configuring an interconnection path, the core connection units within the configured interconnection path are configured to be in the required signal selection forwarding state, so as to form an interconnection path using the core connection units configured to be in the corresponding signal selection forwarding state and the topology track lines used to connect the core connection units. For any core-joint unit within the core-joint unit group, it includes at least one transposed connection circuit and several cross signal transmission circuits for configuring the signal transmission direction, wherein, The core-to-core adapter unit is connected to a core-to-core via a transposed connection circuit, and uses the transposed connection circuit to perform the required signal interaction with the adapted core-to-core. Within the core-particle connection unit, the transposed connection circuit is adapted to the cross signal transmission circuit via the track line within the unit. For signals interacting with the core, the cross signal transmission circuit forwards or rotates the signals to the transposed connection circuit. Alternatively, signals received by the transposed connection circuit are forwarded or rotated and transmitted via the cross signal transmission circuit. For signals that are only transmitted through the core-joint unit, the signal transmission direction of the cross signal transmission circuit within the core-joint unit is configured so that the transmitted signal is transmitted to the adjacent core-joint unit.

2. The interconnect network topology of claim 1, adapted for multi-core chips, wherein: The core-particle connecting unit group and the topological orbital line are fabricated on a substrate. On the substrate, the core-particle connecting units within the core-particle connecting unit group are arranged in an array.

3. The interconnect network topology of claim 1, adapted for multi-core chips, wherein: Within the core-particle connecting unit, the internal track lines include a first track line body and a second track line body, wherein... ​ The cross signal transmission circuit is located at the intersection of the first track line and the second track line within the unit; For any cross signal transmission circuit, there are several cross signal transmission units, wherein the cross signal transmission units are distributed alternately in the cross signal transmission circuit so that the alternately distributed cross signal transmission units correspond to the corresponding track lines of the first track line body and the second track line body in the cross state unit body respectively. A cross signal transmission unit is used to forward signals transmitted through the cross signal transmission unit, or to rotate signals to another track line in a unit corresponding to the track line in the current unit for transmission.

4. The inter-chip interconnection network topology suitable for multi-core chips according to claim 3, characterized in that: For any cross signal transmission unit, there are four transmission unit connection ports, wherein, The transmission unit connection port is used to connect with the corresponding track line of the first track line or the second track line within the unit; The cross signal transmission unit includes a configurable cross signal transmission switch array. After configuring the switching state of the cross signal transmission switch array, the cross signal transmission switch array is used to adapt and connect a connection terminal of the connection port of one transmission unit to the corresponding connection terminal of the connection port of another transmission unit.

5. The interconnect network topology of claim 4, adapted for a multi-core die, wherein: Within the cross signal transmission unit, the connection terminals of the transmission unit connection port are configured using a cross signal transmission switch array, including Wilton connections. ​ 6. A chip-to-chip interconnect network topology suitable for a multi-core die according to any one of claims 3 to 5, wherein: The transposed connection circuit includes a microbump array for mating with the core, a transposed connection switch array for mating with the microbump array, and a multiplexer for signal selection. The microbump array includes a first microbump subarray and a second microbump subarray, which are located on both sides of the first or second track line body within a unit corresponding to the transposed connection circuit. For a microbump in the first subarray or the second subarray of microbumps, a transpose connection switch array and a multiplexer are used to connect it to the corresponding track line of the first track line or the second track line in the unit.

7. The interconnect network topology of claim 6, adapted for a multi-core die, wherein: For any given microbump, the microbump is electrically connected to a microbump connection line adapter via a microbump transceiver connection circuit, and is also connected to a transposed connection switch array adapter via the microbump connection line, wherein... ​ The microbump transceiver connection circuit includes a transceiver configuration circuit, a pull-up / pull-down circuit, and an ESD protection circuit connected in sequence. The microbump is electrically connected to the ESD protection circuit and is also electrically connected to the microbump connection line via a transceiver configuration circuit.

8. The interconnect network topology of claim 7, adapted for a multi-core chip, wherein: The transceiver configuration circuit includes a configurable receiving branch and a transmitting branch that are not simultaneously operational. ​ When the receiving branch is configured to work, it is used to receive the signal loaded by the core. When the transmit branch is configured to work, it sends signals to the core chip using the transmit branch. The transmit branch includes a transmit driver TX and a delay unit connected in series with the transmit driver, the delay unit including a digitally controlled delay line DCDL.

9. The interconnect network topology of claim 6, adapted for a multi-core chip, wherein: The transposed connection switch array includes a first group of transposed connection switches corresponding to the first sub-array of microbumps and a second group of transposed connection switches corresponding to the second sub-array of microbumps, wherein... ​ The first unit group of the transposed connection switch includes a horizontal switching first switch and a vertical switching first switch, which are consistent with the number of rows in the first sub-array of microbumps. A horizontal switching first switch corresponds to the connection unit pad in the same row in the first sub-array of microbumps, and a vertical switching first switch corresponds to a horizontal switching first switch. The transposed connection switch second unit group includes a horizontal switching second switch and a vertical switching second switch that are consistent with the row number in the microbump second sub-array. A horizontal switching second switch corresponds to the connection unit pad in the same row in the microbump second sub-array, and a vertical switching second switch corresponds to a horizontal switching second switch. Within the first sub-array of microbumps, the connection unit pads in the same row are adapted to the horizontal switching first switch via corresponding pad connection lines, and the horizontal switching first switch is adapted to the vertical switching first switch corresponding to the horizontal switching first switch. Within the second sub-array of microbumps, the connection unit pads in the same row are adapted to the lateral switching second switch via corresponding pad connection lines, and the lateral switching second switch is adapted to the vertical switching second switch corresponding to the lateral switching second switch. The first vertical switching switch and the second vertical switching switch are adapted and connected to the multiplexer.

10. The interconnect network topology of claim 9, adapted for a multi-core chip, wherein: Each of the horizontal switching first switch, the horizontal switching second switch, the vertical switching first switch, and the vertical switching second switch includes a plurality of first-side ports located on a first side and a plurality of second-side ports located on a second side, wherein... ​ The number of first-side ports on the first side is the same as the number of second-side ports on the second side, and the first-side ports on the first side can be configured to connect to any second-side port on the second side of the switch.

11. The interconnect network topology of claim 6, adapted for a multi-core chip, wherein: The multiplexer includes several multiplexing units, wherein, ​ The number of multiplexing units in the multiplexer is half the number of microbumps in the microbump array, and the multiplexing unit is a 2-to-2 data selector; When selecting, the 2-to-2 data selector is configured to either direct connection selection mode or cross-connection selection mode.

12. The inter-chip interconnection network topology suitable for multi-core chips according to claim 6, characterized in that: multiple paths Within the selection unit, the 2-to-2 data selector is connected to the corresponding track line of the first track line or the second track line within the unit through a selection buffer.

13. A multi-chip interconnect network topology suitable for a tile according to any one of claims 3 to 5, characterized by: The corresponding track lines within the first track line body of the unit are perpendicular to the corresponding track lines within the second track line body of the unit. The distance between adjacent cross signal transmission circuits shall not exceed 2mm.

14. An inter-chip network system suitable for multi-core dies, characterized by, It includes a plurality of chips to be interconnected, wherein, for any one chip, it is assembled and connected to the inter-chip interconnection network topology of any one of claims 1 to 13 above; For two or more chips connected by an inter-chip interconnection network topology, the chips are interconnected based on the inter-chip interconnection network topology.

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