Pixel circuit and display panel

Abstract

The application discloses a pixel circuit and a display panel. The pixel circuit comprises a driving module, a light-emitting module, a first leakage suppression module, a second leakage suppression module, a first storage module and a threshold compensation module; the first leakage suppression module is connected between the control end of the driving module and the first node, and is used for suppressing the leakage of the control end of the driving module; the second leakage suppression module is connected between the second node and the first node, and is used for suppressing the leakage of the control end of the driving module; the first storage module is connected to the first node, and is used for storing the voltage of the first node, so as to reduce the voltage difference between the control end of the driving module and the first node; and the threshold compensation module is connected between the first end of the driving module and the second node. The technical scheme of the application helps to alleviate the influence of the leakage of the driving module on the display brightness, thereby improving the display effect.

Description

TECHNICAL FIELD

[0001] Embodiments of the present application relate to the technical field of display, and in particular, to a pixel circuit and a display panel. BACKGROUND

[0002] With the continuous development of display technology, people have higher and higher requirements for the performance of display panels. The display panel includes a pixel circuit, and the pixel circuit includes a driving transistor for driving a light emitting device to emit light for display. The existing pixel circuit generally has a large leakage current problem, which will make the gate voltage of the driving transistor unstable, thereby affecting the brightness of the light emitting device and the display effect of the display panel. SUMMARY

[0003] Embodiments of the present application provide a pixel circuit and a display panel to alleviate the impact of the leakage problem of the pixel circuit on display brightness, thereby improving the display effect.

[0004] In a first aspect, embodiments of the present application provide a pixel circuit, comprising:

[0005] a driving module and a light emitting module, connected between a first power line and a second power line, the driving module being configured to drive the light emitting module according to the voltage of its control terminal;

[0006] a first leakage suppression module, connected between the control terminal of the driving module and a first node, configured to suppress the leakage of the control terminal of the driving module;

[0007] a second leakage suppression module, connected between a second node and the first node, configured to suppress the leakage of the control terminal of the driving module;

[0008] a first storage module, connected to the first node, configured to store the voltage of the first node to reduce the voltage difference between the control terminal of the driving module and the first node;

[0009] a threshold compensation module, connected between the first terminal of the driving module and the second node, configured to compensate the threshold voltage of the driving module.

[0010] Optionally, a first terminal of the first storage module is connected to the first node, and a second terminal of the first storage module is connected to a fixed voltage.

[0011] Preferably, a first initialization module is connected between an initialization signal line and the second node, configured to write the voltage on the initialization signal line to the control terminal of the driving module.

[0012] Preferably, the second end of the first storage module is connected to the initialization signal line, and the initialization signal line is connected to an initialization voltage, and the initialization voltage is multiplexed as the fixed voltage.

[0013] Preferably, the pixel circuit further comprises a second initialization module connected between the initialization signal line and the first end of the light-emitting module, and the second initialization module is configured to write the voltage on the initialization signal line to the first end of the light-emitting module.

[0014] Preferably, the initialization signal line comprises a first initialization signal line and a second initialization signal line, the first initialization signal line is connected to a first initialization voltage, the second initialization signal line is connected to a second initialization voltage, the first initialization module is connected to the first initialization signal line, and the second initialization module is connected to the second initialization signal line; the second end of the first storage module is connected to the first initialization signal line, the first initialization voltage is multiplexed as the fixed voltage, or the second end of the first storage module is connected to the second initialization signal line, and the second initialization voltage is multiplexed as the fixed voltage.

[0015] Preferably, the first power supply line is connected to a first power supply voltage, the second end of the first storage module is connected to the first power supply line, and the first power supply voltage is multiplexed as the fixed voltage.

[0016] Optionally, the pixel circuit further comprises a data writing module, a first end of the data writing module is connected to a data line, and a second end of the data writing module is connected to the second end of the driving module.

[0017] The control end of the first initialization module is connected to a first scan line, the control end of the threshold compensation module and the control end of the data writing module are connected to a second scan line, and the control end of the first leakage suppression module and the control end of the second leakage suppression module are both connected to a leakage control signal line.

[0018] The first initialization module is turned on in an initialization stage in response to a signal on the first scan line, and the first leakage suppression module and the second leakage suppression module are turned on in the initialization stage in response to a signal on the leakage control signal line, so as to write the voltage on the initialization signal line to the control end of the driving module.

[0019] The data writing module and the threshold compensation module are turned on in a data writing stage in response to a signal on the second scan line, and the first leakage suppression module and the second leakage suppression module are turned on in the data writing stage in response to a signal on the leakage control signal line, so as to write the voltage on the data line to the control end of the driving module, and simultaneously compensate the threshold voltage of the driving module.

[0020] The first leakage suppression module and the second leakage suppression module are turned off in response to a signal on the leakage control signal line in a light emitting stage to suppress leakage of the control end of the driving module;

[0021] Preferably, the pixel circuit further comprises a second initialization module and a light emitting control module, a control end of the second initialization module is connected to a third scan line, a control end of the light emitting control module is connected to a light emitting control signal line, and the light emitting control module is connected between the first power supply line and the light emitting module;

[0022] The first leakage suppression module and the second leakage suppression module are turned off in response to a signal on the leakage control signal line in a black insertion stage, the light emitting control module is turned off in response to a voltage on the light emitting control signal line in the black insertion stage, and the second initialization module is turned on in response to a voltage on the third scan line in the black insertion stage to write a voltage on the initialization signal line to the first end of the light emitting module.

[0023] Optionally, the leakage control signal line is configured to input a pulse signal in an initialization stage and a data writing stage in a display frame, respectively.

[0024] The second scan line is configured to input a pulse signal in a data writing stage in a display frame.

[0025] Preferably, in a display frame, a signal waveform input by the second scan line is the same as a signal waveform input by the leakage control signal line, a pulse signal timing input by the second scan line is later than a pulse signal timing input by the leakage control signal line, and a first pulse signal input by the second scan line overlaps a second pulse signal input by the leakage control signal line in timing.

[0026] Optionally, the first scan line is configured to input a pulse signal in an initialization stage in a display frame.

[0027] Preferably, in a display frame, a signal waveform input by the first scan line is the same as a signal waveform input by the leakage control signal line, a pulse signal timing input by the first scan line is earlier than a pulse signal timing input by the leakage control signal line, and a second pulse signal input by the first scan line overlaps a first pulse signal input by the leakage control signal line in timing.

[0028] Optionally, the pixel circuit further comprises a coupling module, a first end of the coupling module is connected to the first node, a second end of the coupling module is connected to a jump voltage, and the coupling module is configured to couple the jump voltage to the first node to reduce a voltage difference between the control end of the driving module and the first node in a light emitting stage.

[0029] Preferably, the pixel circuit further comprises a light-emitting control module, a control end of the light-emitting control module is connected to a light-emitting control signal line, the light-emitting control module is turned on or turned off in response to a voltage on the light-emitting control signal line, and a second end of the coupling module is connected to the light-emitting control signal line, and the voltage on the light-emitting control signal line is multiplexed as the jump voltage.

[0030] In a second aspect, an embodiment of the present application provides a display panel, comprising a substrate, a leakage control signal line, a switching part, and the pixel circuit of the first aspect, wherein the leakage control signal line, the switching part, and the pixel circuit are all located on the substrate.

[0031] The driving module comprises a driving transistor, the first leakage suppression module comprises a first transistor, and the second leakage suppression module comprises a second transistor, wherein a gate of the first transistor and a gate of the second transistor are connected to the leakage control signal line.

[0032] The first transistor is connected between the gate of the driving transistor and the second transistor, a semiconductor layer of the first transistor is connected to the gate of the driving transistor through the switching part, the leakage control signal line is located on a first metal layer, the switching part is located on a second metal layer, and a vertical projection of the leakage control signal line on the substrate and a vertical projection of the switching part on the substrate overlap each other, so as to couple the gate voltage of the driving transistor through the voltage on the leakage control signal line.

[0033] Optionally, the second metal layer is located on a side of the semiconductor layer of the first transistor away from the substrate, and the vertical projection of the switching part on the substrate and the vertical projection of the semiconductor layer of the first transistor on the substrate overlap each other.

[0034] Optionally, along a first direction, the semiconductor layer of the first transistor and the semiconductor layer of the second transistor are located on the same side of the semiconductor layer of the driving transistor, the leakage control signal line extends along a second direction, the vertical projection of the semiconductor layer of the first transistor on the substrate and the vertical projection of the semiconductor layer of the second transistor on the substrate both overlap the vertical projection of the leakage control signal line on the substrate, and the first direction intersects the second direction.

[0035] Optionally, the threshold compensation module comprises a third transistor, a first electrode of the first transistor is connected to a gate electrode of the driving transistor, a second electrode of the first transistor is connected to a first electrode of the second transistor, the third transistor is connected between a first electrode of the driving transistor and a second electrode of the second transistor, and the pixel circuit further comprises a fourth transistor, a gate electrode of the fourth transistor is connected to the leakage control signal line, and the fourth transistor is connected between the second transistor and the third transistor.

[0036] The semiconductor layer of the fourth transistor is located on the same side of the semiconductor layer of the driving transistor as the semiconductor layer of the first transistor and the semiconductor layer of the second transistor, and a vertical projection of the semiconductor layer of the fourth transistor on the substrate overlaps a vertical projection of the leakage control signal line on the substrate.

[0037] Preferably, the semiconductor layer of the first transistor, the semiconductor layer of the second transistor and the semiconductor layer of the fourth transistor are arranged in sequence along the second direction.

[0038] Optionally, the pixel circuit further comprises a data writing module and a fifth transistor, a gate electrode of the fifth transistor is connected to the leakage control signal line, and the fifth transistor is connected between a data line and the data writing module.

[0039] The semiconductor layer of the fifth transistor is located on the same side of the semiconductor layer of the driving transistor as the semiconductor layer of the first transistor and the semiconductor layer of the second transistor, and a vertical projection of the semiconductor layer of the fifth transistor on the substrate overlaps a vertical projection of the leakage control signal line on the substrate.

[0040] Preferably, the semiconductor layer of the first transistor, the semiconductor layer of the second transistor and the semiconductor layer of the fifth transistor are arranged in sequence along the second direction.

[0041] Optionally, the first storage module comprises a first capacitor, a first plate of the first capacitor is connected to the first node, and a second plate of the first capacitor is connected to a fixed voltage.

[0042] The second plate of the first capacitor is located in a third metal layer, the third metal layer is located between the first metal layer and the second metal layer, the display panel further comprises a semiconductor part, the semiconductor part is arranged in the same layer as the semiconductor layer of the first transistor and the semiconductor layer of the second transistor, and the semiconductor part is electrically connected to the semiconductor layer of the first transistor and the semiconductor layer of the second transistor, a vertical projection of the second plate of the first capacitor on the substrate overlaps a vertical projection of the semiconductor part on the substrate, and the semiconductor part serves as the first plate of the first capacitor.

[0043] Preferably, the initialization signal line is located at the third metal layer, the initialization signal line is connected to an initialization voltage, the initialization voltage is multiplexed as the fixed voltage, a vertical projection of the initialization signal line on the substrate intersects with a vertical projection of the semiconductor part on the substrate, and the initialization signal line is multiplexed as a second plate of the first capacitor.

[0044] In a third aspect, an embodiment of the present application provides a display panel, the display panel having a display area and a non-display area, the display panel comprising a first scan circuit group and a plurality of rows of pixel circuits as described in the first aspect;

[0045] The pixel circuits are located in the display area, the first scan circuit group is located in the non-display area, the first scan circuit group comprises a plurality of cascaded first scan circuits, each of the first scan circuits generates a scan signal with a time sequence that is sequentially delayed, and an output end of each of the first scan circuits is connected to at least one row of the pixel circuits to provide the scan signal to the pixel circuits.

[0046] Among the pixel circuits in the same row, a control end of the threshold compensation module is connected to an output end of one of the first scan circuits, a control end of the first leakage suppression module and a control end of the second leakage suppression module are connected to an output end of another of the first scan circuits, and the first scan circuit connected to the control end of the control end of the first leakage suppression module and the control end of the second leakage suppression module is located before the first scan circuit connected to the control end of the threshold compensation module.

[0047] Optionally, the display panel further comprises a second scan line and a leakage control signal line.

[0048] The control end of the first leakage suppression module and the control end of the second leakage suppression module in the i-th row of pixel circuits are connected to the output end of the i-th first scan circuit through the leakage control signal line, and the control end of the threshold compensation module in the i-th row of pixel circuits is connected to the output end of the i+2-th first scan circuit through the second scan line, where i is greater than or equal to 1 and less than or equal to the total number of rows of pixel circuits.

[0049] Optionally, among the pixel circuits in the same row, the control end of the first initialization module, the control end of the threshold compensation module, and the control end of the first leakage suppression module are respectively connected to the output ends of different first scan circuits, and the first scan circuit connected to the control end of the first initialization module is located before the first scan circuit connected to the control end of the first leakage suppression module and the control end of the second leakage suppression module.

[0050] Preferably, the display panel further comprises a first scan line, a control end of the first initialization module in the i-th row of the pixel circuit, an output end of the i-th first scan circuit connected through the first scan line, a control end of the first leakage suppression module and a control end of the second leakage suppression module in the i-th row of the pixel circuit, an output end of the i+2-th first scan circuit connected through a leakage control signal line, a control end of the threshold compensation module in the i-th row of the pixel circuit, an output end of the i+4-th first scan circuit connected through a second scan line.

[0051] Optionally, the display panel further comprises a second scan circuit group and a first scan line, the second scan circuit group is located in the non-display area, the second scan circuit group comprises a plurality of cascaded second scan circuits, each second scan circuit generates a scan signal with time sequence sequentially delayed step by step;

[0052] An output end of the j-th second scan circuit is connected to control ends of the first initialization modules in the 2j-1-th row and the 2j-th row of the pixel circuit through the first scan line, to provide the scan signal to the control ends of the first initialization modules in the corresponding pixel circuit;

[0053] Alternatively, an output end of the j-th second scan circuit is connected to a control end of the first initialization module in the j-th row of the pixel circuit through the first scan line, to provide the scan signal to the control end of the first initialization module in the corresponding pixel circuit;

[0054] Wherein, j is greater than or equal to 1 and less than or equal to the total number of the second scan circuits.

[0055] Optionally, the pixel circuit further comprises a light-emitting control module, the display panel further comprises a light-emitting control signal generation circuit group and a light-emitting control signal line, the light-emitting control signal generation circuit group is located in the non-display area, the light-emitting control signal generation circuit group comprises a plurality of cascaded light-emitting control signal generation circuits, each light-emitting control signal generation circuit generates a light-emitting control signal with time sequence sequentially delayed step by step;

[0056] An output end of the k-th light-emitting control signal generation circuit is connected to control ends of the light-emitting control modules in the 2k-1-th row and the 2k-th row of the pixel circuit through the light-emitting control signal line, to provide the light-emitting control signal to the control ends of the light-emitting control modules in the corresponding pixel circuit;

[0057] Alternatively, an output terminal of the kth light-emitting control signal generation circuit is connected to a control terminal of the light-emitting control module in the kth row of pixel circuits through the light-emitting control signal line, so as to provide the light-emitting control signal to the control terminal of the light-emitting control module in the corresponding pixel circuit.

[0058] wherein k is greater than or equal to 1 and less than or equal to the total number of the light-emitting control signal generation circuits.

[0059] Optionally, the second scan circuit group and the light-emitting control signal generation circuit group are located in the non-display area on the same side of the display area.

[0060] The display panel further comprises a first clock signal line and a second clock signal line, in the case that the number of the pixel circuits connected to each light-emitting control signal generation circuit is the same as the number of the pixel circuits connected to each second scan circuit, the second scan circuit and the light-emitting control signal generation circuit are connected to the first clock signal line and the second clock signal line, so that the second scan circuit generates the scan signal in response to the signals on the first clock signal line and the second clock signal line, and the light-emitting control signal generation circuit generates the light-emitting control signal in response to the signals on the first clock signal line and the second clock signal line.

[0061] Preferably, the first clock signal line and the second clock signal line have the same extension direction, the second scan circuit group is located on one side of the first clock signal line and the second clock signal line, and the light-emitting control signal generation circuit group is located on the other side of the first clock signal line and the second clock signal line.

[0062] The pixel circuit and the display panel provided by the embodiments of the present application have the following advantages. The first leakage suppression module is arranged between the control terminal of the driving module of the pixel circuit and the first node, the second leakage suppression module is arranged between the second node and the first node, the threshold compensation module is arranged between the first end of the driving module and the second node, and the first initialization module is arranged between the initialization signal line and the second node, which helps to block the conduction path between the control terminal of the driving module and the threshold compensation module and the conduction path between the control terminal of the driving module and the initialization signal line in the light-emitting stage, so as to alleviate the leakage problem of the driving module. The first storage module is arranged to store the voltage of the first node, which can reduce the voltage difference between the control terminal of the driving module and the first node, i.e., the voltage difference between the two ends of the first leakage suppression module, so as to reduce the leakage current of the first leakage suppression module, further alleviate the leakage problem of the driving module, help to improve the stability of the voltage of the control terminal of the driving module, weaken the influence of the leakage problem of the driving module on the display brightness, and thus improve the display effect.

[0063] It is to be understood that the details described in this section are not intended to identify key or critical elements of the embodiments of the application or to limit the scope of the application. Other features of the present application will be apparent from the following description. BRIEF DESCRIPTION OF DRAWINGS

[0064] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the embodiments will be briefly introduced as follows. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative effort based on these drawings.

[0065] Figure 1 is a structural schematic diagram of a pixel circuit provided by an embodiment of the present application;

[0066] Figure 2 is a structural schematic diagram of another pixel circuit provided by an embodiment of the present application;

[0067] Figure 3 is a driving timing schematic diagram of a pixel circuit provided by an embodiment of the present application;

[0068] Figure 4 is a driving timing schematic diagram of another pixel circuit provided by an embodiment of the present application;

[0069] Figure 5 is a driving timing schematic diagram of another pixel circuit provided by an embodiment of the present application;

[0070] Figure 6 is a driving timing schematic diagram of another pixel circuit provided by an embodiment of the present application;

[0071] Figure 7 is a structural schematic diagram of another pixel circuit provided by an embodiment of the present application;

[0072] Figure 8 is a structural schematic diagram of another pixel circuit provided by an embodiment of the present application;

[0073] Figure 9 is a top view of a display panel provided by an embodiment of the present application;

[0074] Figure 10 is Figure 9 is a sectional view of the display panel in FIG. 8 along section line BB';

[0075] Figure 11 is Figure 9 is a sectional view of the display panel in FIG. 9 along section line CC';

[0076] Figure 12is a top view of another display panel provided by an embodiment of the present application;

[0077] Figure 13 is Figure 12 is a sectional view of the display panel in along section line DD' in

[0078] Figure 14 is Figure 12 is a sectional view of the display panel in along section line EE' in

[0079] Figure 15 is a structural schematic diagram of a display panel provided by an embodiment of the present application;

[0080] Figure 16 is a structural schematic diagram of another display panel provided by an embodiment of the present application;

[0081] Figure 17 is a structural schematic diagram of another display panel provided by an embodiment of the present application;

[0082] Figure 18 is a driving timing schematic diagram of another pixel circuit provided by an embodiment of the present application;

[0083] Figure 19 is a driving timing schematic diagram of another pixel circuit provided by an embodiment of the present application;

[0084] Figure 20 is a structural schematic diagram of another display panel provided by an embodiment of the present application. DETAILED DESCRIPTION

[0085] In order to enable persons skilled in the art to better understand the present application, the technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by persons skilled in the art without creative labor should belong to the protection scope of the present application.

[0086] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0087] As described in the background section, existing pixel circuits generally suffer from high leakage current, which causes instability in the gate voltage of the driving transistor, thereby affecting the brightness of the light-emitting device and the display effect of the display panel. In view of this, embodiments of the present invention provide a pixel circuit to alleviate the impact of pixel circuit leakage current on display brightness, thereby improving the display effect.

[0088] Figure 1 This is a schematic diagram of a pixel circuit provided in an embodiment of the present invention. See also... Figure 1 The pixel circuit includes: a driving module 110, a light-emitting module 120, a first leakage current suppression module 130, a second leakage current suppression module 140, a first storage module 150, a threshold compensation module 160, and a first initialization module 170.

[0089] The driving module 110 and the light-emitting module 120 are connected between the first power line VDD and the second power line VSS. The driving module 110 drives the light-emitting module 120 according to the voltage of its control terminal G. The first leakage current suppression module 130 is connected between the control terminal G of the driving module 110 and the first node N1 to suppress leakage current at the control terminal G of the driving module 110. The second leakage current suppression module 140 is connected between the second node N2 and the first node N1 to suppress leakage current at the control terminal G of the driving module 110. The first storage module 150 is connected to the first node N1 to store the voltage of the first node N1, thereby reducing the voltage difference between the control terminal G of the driving module 110 and the first node N1. The threshold compensation module 160 is connected between the first terminal of the driving module 110 and the second node N2 to compensate for the threshold voltage of the driving module 110. The first initialization module 170 is connected between the initialization signal line Vref and the second node N2 to write the voltage on the initialization signal line Vref to the control terminal G of the driving module 110.

[0090] Specifically, the first power line VDD is connected to a first power voltage, the second power line VSS is connected to a second power voltage, the first power voltage is greater than the second power voltage, the first power voltage can be a positive voltage, and the second power voltage can be a negative voltage or 0V. The initialization signal line Vref is connected to an initialization voltage. The working stage of the pixel circuit includes at least an initialization stage, a data writing stage and an emitting stage.

[0091] In the initialization stage, the first leakage suppression module 130, the second leakage suppression module 140 and the first initialization module 170 are controlled to be turned on, so that the initialization voltage on the initialization signal line Vref is transmitted to the control end G of the driving module 110 through the first initialization module 170, the second leakage suppression module 140 and the first leakage suppression module 130 in sequence, the voltage of the control end G of the driving module 110 is initialized, the influence of the residual charge of the control end G of the driving module 110 on the display effect is weakened, and the driving module 110 is controlled to be turned on.

[0092] In the data writing stage, the first leakage suppression module 130, the second leakage suppression module 140 and the threshold compensation module 160 are controlled to be turned on, and the data voltage is transmitted to the control end G of the driving module 110 through the driving module 110, the threshold compensation module 160, the second node N2, the second leakage suppression module 140, the first node N1 and the first leakage suppression module 130 in sequence, so that the voltage of the control end G of the driving module 110 is related to the data voltage and the threshold voltage of the driving module 110, so as to compensate the threshold voltage of the driving module 110 while the data voltage is written to the control end G of the driving module 110. The first storage module 150 can store the voltage of the first node N1, so that the voltage of the control end G of the driving module 110 and the voltage of the first node N1 are close to each other, so as to reduce the voltage difference between the control end G of the driving module 110 and the first node N1.

[0093] In the emitting stage, a discharge path is formed between the first power line VDD and the second power line VSS, and the first leakage suppression module 130 and the second leakage suppression module 140 are controlled to be turned off, so that the driving module 110 can generate a driving current according to the voltage of the control end G thereof, so as to drive the light emitting module 120 to emit light with a corresponding brightness.

[0094] Since the first leakage suppression module 130 and the second leakage suppression module 140 are connected between the control terminal G of the driving module 110 and the threshold compensation module 160, and connected between the control terminal G of the driving module 110 and the first initialization module 170, in the light-emitting stage, by controlling the first leakage suppression module 130 and the second leakage suppression module 140 to be turned off, the conduction path between the control terminal G of the driving module 110 and the threshold compensation module 160 is blocked, and the conduction path between the control terminal G of the driving module 110 and the initialization signal line Vref is blocked, so as to alleviate the leakage problem of the driving module 110. At the same time, by storing the voltage of the first node N1 through the first storage module 150, the voltage difference between the control terminal G of the driving module 110 and the first node N1 is reduced, that is, the voltage difference between the two ends of the first leakage suppression module 130 is reduced, so as to reduce the leakage current of the first leakage suppression module 130, thereby further alleviating the leakage problem of the driving module 110, and keeping the voltage of the control terminal G of the driving module 110 stable.

[0095] In summary, the technical scheme of the embodiment of the present application, by setting the first leakage suppression module between the control terminal of the driving module and the first node, setting the second leakage suppression module between the second node and the first node, setting the threshold compensation module between the first end of the driving module and the second node, and setting the first initialization module between the initialization signal line and the second node, helps to block the conduction path between the control terminal of the driving module and the threshold compensation module, and the conduction path between the control terminal of the driving module and the initialization signal line in the light-emitting stage, so as to alleviate the leakage problem of the driving module. By setting the first storage module to store the voltage of the first node, the voltage difference between the control terminal of the driving module and the first node can be reduced, that is, the voltage difference between the two ends of the first leakage suppression module can be reduced, so as to reduce the leakage current of the first leakage suppression module, thereby further alleviating the leakage problem of the driving module, helping to improve the stability of the voltage of the control terminal of the driving module, and weakening the influence of the leakage problem of the driving module on the display brightness, thereby improving the display effect.

[0096] Continuing to refer to Figure 1 Optionally, the pixel circuit further comprises a data writing module 180, a first end of the data writing module 180 is connected to the data line Data, and a second end of the data writing module 180 is connected to the second end of the driving module 110. The data line Data inputs a data voltage, and the data writing module 180 is used for writing the data voltage on the data line Data to the control terminal G of the driving module 110.

[0097] Continuing to refer to Figure 1Optionally, a first end of the first storage module 150 is connected to the first node N1, and a second end of the first storage module 150 is connected to a fixed voltage, which can be any constant voltage. In an embodiment, the second end of the first storage module 150 is connected to an initialization signal line Vref, and an initialization voltage input to the initialization signal line Vref is multiplexed as the fixed voltage.

[0098] Figure 2 is another structure diagram of a pixel circuit provided by an embodiment of the present application. Referring to Figure 2 Optionally, the pixel circuit further comprises a second initialization module 190 connected between the initialization signal line and the first end of the light-emitting module 120, and the second initialization module 190 is configured to write the voltage on the initialization signal line to the first end of the light-emitting module 120.

[0099] In an embodiment, the first initialization module 170 and the second initialization module 190 can be connected to the same initialization signal line, so as to reduce the number of signal lines in the display panel and facilitate the layout of the signal lines in the display panel. In another embodiment, the initialization signal line specifically comprises a first initialization signal line Vref1 and a second initialization signal line Vref2, the first initialization signal line Vref1 is connected to a first initialization voltage, and the second initialization signal line Vref2 is connected to a second initialization voltage, the first initialization module 170 is connected to the first initialization signal line Vref1, and the second initialization module 190 is connected to the second initialization signal line Vref2. In this way, the first initialization voltage used for initializing the control end G of the driving module 110 and the second initialization voltage used for initializing the first end of the light-emitting module 120 can be adjusted respectively, so as to select appropriate voltage values to initialize the voltage of the control end G of the driving module 110 and the voltage of the first end of the light-emitting module 120 respectively, which helps to improve the display effect.

[0100] In the embodiment, the second end of the first storage module 150 can be connected to the first initialization signal line Vref1, so as to multiplex the first initialization voltage as the fixed voltage. Alternatively, the second end of the first storage module 150 can be connected to the second initialization signal line Vref2, so as to multiplex the second initialization voltage as the fixed voltage. Alternatively, the second end of the first storage module 150 can also be connected to the first power supply line VDD, so as to multiplex the first power supply voltage input to the first power supply line VDD as the fixed voltage. By multiplexing the first initialization voltage, the second initialization voltage or the first power supply voltage as the fixed voltage input to the first storage module 150, it is not necessary to additionally set a signal line in the display panel to provide the fixed voltage to the first storage module 150, so as to reduce the number of signal lines in the display panel and facilitate the layout of the signal lines in the display panel.

[0101] See also Figure 2 The pixel circuit also includes a second storage module 210. The first terminal of the second storage module 210 is connected to the control terminal G of the driving module 110, and the second terminal of the second storage module 210 is connected to a fixed voltage. The second storage module 210 is used to store the voltage at the control terminal G of the driving module 110. The fixed voltage connected to the second terminal of the second storage module 210 can also be any constant voltage, such as a first initialization voltage, a second initialization voltage, or a first power supply voltage. Figure 2 The diagram schematically illustrates the situation where the second end of the second storage module 210 is connected to the first power line VDD, and the second end of the second storage module 210 is connected to the first power supply voltage.

[0102] The pixel circuit also includes a light-emitting control module 220. The control terminal of the light-emitting control module 220 is connected to the light-emitting control signal line EM. The light-emitting control module 220 is connected between the first power line VDD and the light-emitting module 120. The light-emitting control module 220 is used to turn on or off in response to the signal on the light-emitting control signal line EM. There are two light-emitting control modules 220, one of which is connected between the first power line VDD and the driver module 110, and the other is connected between the driver module 110 and the light-emitting module 120.

[0103] See also Figure 2 Furthermore, the control terminal of the first initialization module 170 is connected to the first scan line S1, the control terminal of the threshold compensation module 160 and the control terminal of the data writing module 180 are connected to the second scan line S2, and the control terminals of the first leakage current suppression module 130 and the second leakage current suppression module 140 are both connected to the leakage current control signal line EMB.

[0104] The first initialization module 170 is turned on during the initialization phase in response to the signal on the first scan line S1, and the first leakage current suppression module 130 and the second leakage current suppression module 140 are turned on during the initialization phase in response to the signal on the leakage current control signal line EMB, so as to write the voltage on the initialization signal line Vref into the control terminal G of the drive module 110.

[0105] The data writing module 180 and the threshold compensation module 160 are turned on during the data writing phase in response to the signal on the second scan line S2. The first leakage current suppression module 130 and the second leakage current suppression module 140 are turned on during the data writing phase in response to the signal on the leakage current control signal line EMB, so as to write the voltage on the data line Data to the control terminal G of the drive module 110, and store the voltage of the control terminal G of the drive module 110 through the second storage module 210, while compensating the threshold voltage of the drive module 110.

[0106] The first leakage suppression module 130 and the second leakage suppression module 140 are turned off in response to the signals on the leakage control signal line EMB in the light emitting stage to suppress the leakage of the control terminal G of the driving module 110.

[0107] Figure 3 is a driving timing diagram of a pixel circuit provided by an embodiment of the present application, which is applicable to driving the pixel circuit shown in Figure 1 and Figure 2 . The following will be described in combination with Figure 2 and Figure 3 . Alternatively, the leakage control signal line EMB is configured to input pulse signals in the initialization stage and the data writing stage in a display frame respectively. The second scan line S2 is configured to input pulse signals in the data writing stage in a display frame. The first scan line S1 is configured to input pulse signals in the initialization stage in a display frame.

[0108] Specifically, the pulse signals input by the leakage control signal line EMB, the first scan line S1 and the second scan line S2 refer to pulse signals required for turning on the modules connected to the signal lines. Exemplarily, when the average voltage for turning on the first leakage suppression module 130, the second leakage suppression module 140, the threshold compensation module 160, the first initialization module 170 and the data writing module 180 is a low voltage, the pulse signals input by the leakage control signal line EMB, the first scan line S1 and the second scan line S2 are low voltage pulse signals. In this way, the first leakage suppression module 130, the second leakage suppression module 140 and the first initialization module 170 can be turned on in the initialization stage to write the voltage on the initialization signal line Vref to the control terminal G of the driving module 110, to initialize the voltage of the control terminal G of the driving module 110, to turn on the driving module 110, and to turn on the first leakage suppression module 130, the second leakage suppression module 140, the threshold compensation module 160 and the data writing module 180 and the threshold compensation module 160 in the data writing stage to write the voltage on the data line Data to the control terminal G of the driving module 110, while compensating the threshold voltage of the driving module 110.

[0109] It can be understood that the voltage for turning on the modules in the pixel circuit can be either a low voltage or a high voltage. When the voltage for turning on the modules is a high voltage, the pulse signals input by the leakage control signal line EMB, the first scan line S1 and the second scan line S2 can be high voltage pulse signals, and the corresponding working principle can be understood with reference to the above embodiment, which will not be described herein again.

[0110] in combination with Figure 2 and Figure 3In an embodiment, in a display frame, the signal waveform inputted by the second scan line S2 is the same as the signal waveform inputted by the electric leakage control signal line EMB, the pulse signal timing inputted by the second scan line S2 is later than the pulse signal timing inputted by the electric leakage control signal line EMB, and the first pulse signal inputted by the second scan line S2 overlaps the timing of the second pulse signal inputted by the electric leakage control signal line EMB.

[0111] For example, in a display frame, the signals inputted by the second scan line S2 and the electric leakage control signal line EMB both include two low pulse signals with the same time interval, the first low pulse signal inputted by the second scan line S2 overlaps the timing of the second low pulse signal inputted by the electric leakage control signal line EMB, and the time interval corresponding to the overlap of the pulse signal timing of the second scan line S2 and the electric leakage control signal line EMB corresponds to the time interval of the data writing stage of the pixel circuit. Since the signal waveform inputted by the second scan line S2 is the same as the signal waveform inputted by the electric leakage control signal line EMB, the difference between the two is only the timing of the pulse signal, so the same set of cascaded scan circuits can be used to provide signals to the second scan line S2 and the electric leakage control signal line EMB, and the scan circuit for providing signals to the electric leakage control signal line EMB is located before the scan circuit for providing signals to the second scan line S2, so that the pulse signal timing inputted by the second scan line S2 is later than the pulse signal timing inputted by the electric leakage control signal line EMB, without the need to separately set two sets of cascaded scan circuits to provide signals to the second scan line S2 and the electric leakage control signal line EMB, which is beneficial to reduce the space occupied by the scan circuit in the display panel, thereby realizing a narrow frame design.

[0112] Figure 4 is another driving timing diagram of a pixel circuit provided by an embodiment of the present application, which is suitable for driving Figure 1 and Figure 2 pixel circuits. The following description is made in combination with Figure 2 and Figure 4 . Alternatively, the control end of the second initialization module 190 is connected to the third scan line S3, the first electric leakage suppression module 130 and the second electric leakage suppression module 140 are turned off in response to the signal on the electric leakage control signal line EMB in the black insertion stage, the light emitting control module 220 is turned off in response to the voltage on the light emitting control signal line EM in the black insertion stage, and the second initialization module 190 is turned on in response to the voltage on the third scan line S3 in the black insertion stage, so as to write the voltage on the initialization signal line (for example, the second initialization signal line Vref2) to the first end of the light emitting module 120.

[0113] Exemplarily, during the black insertion stage in each display frame, a level signal, for example, a high level signal, is provided to the light emitting control signal line EM to control the light emitting control module 220 to be turned off, so as to control the conduction path between the first power supply line VDD and the second power supply line VSS to be disconnected, a level signal, for example, a high level signal, is provided to the leakage control signal line EMB to control the first leakage suppression module 130 and the second leakage suppression module 140 to be turned off, so as to block the leakage path of the control end G of the driving module 110, and the voltage of the control end G of the driving module 110 is kept stable, a signal, for example, a low level pulse signal, is provided to the third scan line S3 to control the second initialization module 190 to be turned on, so as to write the voltage on the second initialization signal line Vref2 to the first end of the light emitting module 120 through the second initialization module 190, and the voltage of the first end of the light emitting module 120 is initialized, so as to make the current of the light emitting module 120 decrease rapidly, and the light emitting module 120 is controlled to stop emitting light, so as to enable the display panel to display a black screen sufficiently.

[0114] Optionally, the first scan line S1 and the third scan line S3 are configured to input pulse signals with same waveforms and timing. The advantage of such a setting is that the same scan circuit can be used to provide the same signals to the first scan line S1 and the third scan line S3, and it is not necessary to separately set two groups of cascaded scan circuits to provide signals to the first scan line S1 and the third scan line S3, respectively, which is beneficial to reduce the space occupied by the scan circuit in the display panel, so as to realize a narrow frame design.

[0115] Referring to Figure 2 On the basis of the above embodiments, the driving module 110 includes a driving transistor DT, the light emitting module 120 includes a light emitting device D1, the first leakage suppression module 130 includes a first transistor T1, the second leakage suppression module 140 includes a second transistor T2, the threshold compensation module 160 includes a third transistor T3, the first initialization module 170 includes a sixth transistor T6, the data writing module 180 includes a seventh transistor T7, the second initialization module 190 includes an eighth transistor T8, the light emitting control module 220 includes a ninth transistor T9 and a tenth transistor T10, the first storage module 150 includes a first capacitor C1, and the second storage module 210 includes a second capacitor C2.

[0116] The gate of the first transistor T1 and the gate of the second transistor T2 are connected to the discharge control signal line EMB, the first electrode of the first transistor T1 is connected to the gate of the driving transistor DT, the second electrode of the first transistor T1 is connected to the first electrode of the second transistor T2, and the first transistor T1 and the second transistor T2 are connected to the first node N1. The gate of the third transistor T3 is connected to the second scan line S2, the first electrode of the third transistor T3 is connected to the first electrode of the driving transistor DT, the second electrode of the third transistor T3 is connected to the second electrode of the second transistor T2, and the second transistor T2 and the third transistor T3 are connected to the second node N2. The gate of the sixth transistor T6 is connected to the first scan line S1, the first electrode of the sixth transistor T6 is connected to the first initialization signal line Vref1, and the second electrode of the sixth transistor T6 is connected to the second node N2. The gate of the seventh transistor T7 is connected to the second scan line S2, the first electrode of the seventh transistor T7 is connected to the data line Data, and the second electrode of the seventh transistor T7 is connected to the second electrode of the driving transistor DT. The gate of the eighth transistor T8 is connected to the third scan line S3, the first electrode of the eighth transistor T8 is connected to the second initialization signal line Vref2, and the second electrode of the eighth transistor T8 is connected to the first electrode (for example, the anode) of the light emitting device D1. The gates of the ninth transistor T9 and the tenth transistor T10 are connected to the light emitting control signal line EM, the ninth transistor T9, the driving transistor DT, the tenth transistor T10, and the light emitting device D1 are sequentially connected between the first power supply line VDD and the second power supply line VSS. The first plate of the first capacitor C1 is connected to the first node N1, and the second plate of the first capacitor C1 is connected to a fixed voltage. For example, the second plate of the first capacitor C1 can be connected to the first power supply line VDD, the first initialization signal line Vref1, or the second initialization signal line Vref2 to access the fixed voltage on the corresponding signal line. The first plate of the second capacitor C2 is connected to the gate of the driving transistor DT, and the second plate of the second capacitor C2 is connected to a fixed voltage. For example, the second plate of the second capacitor C2 can be connected to the first power supply line VDD to access the first power supply voltage.

[0117] The light emitting device D1 includes an organic light emitting diode (OLED), a micro-LED, and the like. Each transistor in the pixel circuit can be a P-type transistor or an N-type transistor. In the case where each module in the pixel circuit is composed of only one transistor, the gate of the transistor can be used as the control terminal of the corresponding module, the first electrode of the transistor can be used as the first terminal of the corresponding module, the second electrode of the transistor can be used as the second terminal of the corresponding module, one of the first electrode and the second electrode of the transistor is a source electrode, and the other is a drain electrode.

[0118] The following will be described in combination with Figure 2 to Figure 4Taking an example of each transistor in the pixel circuit being a P-type transistor, the working principle of the pixel circuit is described.

[0119] Exemplarily, in the first stage t1, the light-emitting control signal line EM inputs a low-level signal, the ninth transistor T9, the tenth transistor T10 and the driving transistor DT are turned on, and the remaining transistors are turned off. The driving transistor DT generates a driving current according to the gate voltage of the driving transistor DT, and drives the light-emitting device D1 to emit light.

[0120] In the second stage t2, the light-emitting control signal line EM inputs a high-level signal, and the ninth transistor T9 and the tenth transistor T10 are turned off.

[0121] The third stage t3 is an initialization stage. In the third stage t3, the first scan line S1, the third scan line S3 and the leakage control signal line EMB input low-level signals, the first transistor T1, the second transistor T2 and the sixth transistor T6 are turned on, the first initialization voltage on the first initialization signal line Vref1 is transmitted to the gate of the driving transistor DT through the sixth transistor T6, the second transistor T2 and the first transistor T1 in sequence, the gate voltage of the driving transistor DT is initialized, the influence of the residual charge of the gate of the driving transistor DT on the display effect is reduced, and the driving transistor DT is controlled to be turned on. The eighth transistor T8 is turned on, the second initialization voltage on the second initialization signal line Vref2 is transmitted to the first electrode of the light-emitting device D1 through the eighth transistor T8, and the voltage of the first electrode of the light-emitting device D1 is initialized, so as to reduce the influence of the residual charge of the first electrode of the light-emitting device D1 on the display effect.

[0122] Subsequently, the signal input by the leakage control signal line EMB jumps from a low-level signal to a high-level signal, and the first transistor T1 and the second transistor T2 are both turned off.

[0123] The fourth stage t4 is a data writing stage. In the fourth stage t4, the first scan line S1 and the third scan line S3 input high-level signals, and the sixth transistor T6 and the eighth transistor T8 are turned off. The second scan line S2 and the leakage control signal line EMB input low-level signals, the first transistor T1, the second transistor T2, the third transistor T3 and the seventh transistor T7 are turned on, the data voltage on the data line Data is written to the gate of the driving transistor DT through the seventh transistor T7, the driving transistor DT, the third transistor T3, the second node N2, the second transistor T2, the first node N1 and the first transistor T1 in sequence, so that the gate voltage of the driving transistor DT is related to the data voltage and the threshold voltage of the driving transistor DT. At the same time, the voltage of the first node N1 is stored through the first capacitor C1, and the gate voltage of the driving transistor DT is stored through the second capacitor C2.

[0124] In the fifth stage t5, when the light emitting control signal line EM, the first scan line S1, the second scan line S2, the third scan line S3 and the leakage control signal line EMB all input high level signals, the first transistor T1, the second transistor T2, the third transistor T3, the sixth transistor T6, the seventh transistor T7, the eighth transistor T8, the ninth transistor T9 and the tenth transistor T10 are all turned off. When the second scan line S2 inputs a low level, the third transistor T3 and the seventh transistor T7 are turned on, at this time, since the first transistor T1 and the second transistor T2 are turned off, the gate voltage of the driving transistor DT will not be affected.

[0125] The sixth stage t6 is a light emitting stage, in the sixth stage t6, the light emitting control signal line EM inputs a low level signal, the ninth transistor T9, the tenth transistor T10 and the driving transistor DT are turned on, and the remaining transistors are turned off, the driving transistor DT generates a driving current according to its own gate voltage to drive the light emitting device D1 to emit light. Since the gate voltage of the driving transistor DT is related to the data voltage and the threshold voltage of the driving transistor DT, it is helpful to eliminate the influence of the threshold voltage of the driving transistor DT on the driving current, so as to realize the threshold voltage compensation of the driving transistor DT, so as to improve the display uniformity. Since the first transistor T1 and the second transistor T2 are turned off, it is helpful to block the conduction path between the driving transistor DT and the third transistor T3, and to block the conduction path between the driving transistor DT and the first initialization signal line Vref1, so as to reduce the leakage current channel of the gate of the driving transistor DT, and to realize the reduction of the leakage current of the gate of the driving transistor DT. Since the first capacitor C1 stores the voltage of the first node N1, the voltage difference between the two poles of the first transistor T1 is small, so as to reduce the leakage current of the first transistor T1, so as to further alleviate the leakage problem of the driving transistor DT, so as to keep the gate voltage of the driving transistor DT stable, so as to reduce the influence of the leakage problem of the driving transistor DT on the brightness of the light emitting device D1, to improve the flicker phenomenon of the display panel, and to improve the display effect.

[0126] The seventh stage t7 is a black insertion stage, in which the signal input to the light emitting control signal line EM jumps from a low level signal to a high level signal, and the ninth transistor T9 and the tenth transistor T10 are turned off. When the first scan line S1 and the third scan line S3 input low level signals, the sixth transistor T6 and the eighth transistor T8 are turned on, the second initialization voltage on the second initialization signal line Vref2 is transmitted to the first electrode of the light emitting device D1 through the eighth transistor T8, the voltage of the first electrode of the light emitting device D1 is initialized, the current of the light emitting device D1 is rapidly reduced, the light emitting device D1 is controlled to stop emitting light, and the display panel can display a black screen. At the same time, since the first transistor T1 and the second transistor T2 are turned off, the voltage on the first initialization signal line Vref1 cannot be transmitted to the gate of the driving transistor DT, the gate voltage of the driving transistor DT is maintained, and the voltage difference between the two electrodes of the first transistor T1 is small, so that the leakage current of the first transistor T1 is reduced, and the stability of the gate voltage of the driving transistor DT is maintained.

[0127] In the eighth stage t8, the light emitting control signal line EM inputs a low level signal, the first scan line S1, the second scan line S2, the third scan line S3 and the leakage control signal line EMB all input high level signals. The ninth transistor T9, the tenth transistor T10 and the driving transistor DT are turned on, and the remaining transistors are turned off. The driving transistor DT generates a driving current according to the voltage maintained by its own gate, and drives the light emitting device D1 to emit light.

[0128] The technical scheme of the embodiment adds the seventh stage t7 (i.e. the black insertion stage) and the eighth stage t8 (i.e. the other light emitting stage) after the sixth stage t6 (i.e. the light emitting stage) in each display frame, which is equivalent to increasing the light emitting times of the light emitting device D1 in each display frame, and is equivalent to increasing the refresh frequency of the display panel in visual effect, while the actual refresh frequency remains unchanged. At the same time, it is helpful to convert the low frequency luminance component sensitive to the human eye into a high frequency luminance component insensitive to the human eye, thereby improving the flicker phenomenon of the display panel at a low refresh frequency.

[0129] In combination Figure 2 to Figure 4 Optionally, when the refresh frequency of the current display frame is lower than the preset frequency, the frequency of the pulse signal input by the third scan line S3 is configured as an integer multiple of the refresh frequency of the current display frame, the frequencies of the pulse signals input by the second scan line S2 and the leakage control signal line EMB are both configured as the same as the refresh frequency of the current display frame, the frequency of the pulse signal input by the light emitting control signal line EM is configured as an integer multiple of the refresh frequency of the current display frame, and the frequencies of the pulse signals input by the third scan line S3 and the light emitting control signal line EM are the same.

[0130] The preset frequency is a low frequency, and the specific value of the preset frequency can be set according to requirements. For example, the preset frequency can be a frequency lower than 60 Hz. The refresh frequency of the current display frame refers to the actual refresh frequency of the current display frame, that is, the frequency of writing the data voltage to the gate of the driving transistor DT. Since the pulse signals input by the second scan line S2 and the leakage control signal line EMB only arrive before the sixth stage t6, the frequency of the pulse signals input by the second scan line S2 and the leakage control signal line EMB can be configured to be the same as the refresh frequency of the current display frame. Since the pulse signals input by the third scan line S3 arrive before the sixth stage t6 and the seventh stage t7, respectively, and the pulse signals input by the light-emitting control signal line EM arrive at the sixth stage t6 and the eighth stage t8, respectively, the frequency of the pulse signals input by the third scan line S3 and the light-emitting control signal line EM can be configured to be an integer multiple of the refresh frequency of the current display frame, and the frequency of the pulse signals input by the third scan line S3 and the light-emitting control signal line EM is the same.

[0131] Figure 5 is another driving timing diagram of a pixel circuit provided by an embodiment of the present application, which is suitable for driving the pixel circuit shown in Figure 1 and Figure 2 . In combination with Figure 2 and Figure 5 , in another embodiment, within a display frame, the signal waveform input by the first scan line S1 can be the same as the signal waveform input by the leakage control signal line EMB, the pulse signal timing input by the first scan line S1 can be earlier than the pulse signal timing input by the leakage control signal line EMB, and the second pulse signal input by the first scan line S1 can overlap with the first pulse signal input by the leakage control signal line EMB.

[0132] For example, within a display frame, the signals input to the first scan line S1 and the leakage control signal line EMB both include two low-level pulse signals with the same time interval. The timing of the second low-level pulse signal input to the first scan line S1 overlaps with that of the first low-level pulse signal input to the leakage control signal line EMB. The time interval corresponding to the timing overlap of the pulse signals of the first scan line S1 and the leakage control signal line EMB is the time interval corresponding to the initialization phase of the pixel circuit. Since the signal waveforms input to the first scan line S1 and the leakage control signal line EMB are the same, the only difference between them is the timing of the pulse signals. This allows the same set of cascaded scanning circuits to provide signals to both the first scan line S1 and the leakage control signal line EMB. Furthermore, the scanning circuit providing signals to the first scan line S1 is located before the scanning circuit providing signals to the leakage control signal line EMB. This ensures that the timing of the pulse signals input to the first scan line S1 is earlier than that input to the leakage control signal line EMB. This eliminates the need to set up two separate sets of cascaded scanning circuits to provide signals to the first scan line S1 and the leakage control signal line EMB, thereby reducing the space occupied by the scanning circuits in the display panel and enabling a narrow bezel design.

[0133] Furthermore, it can be set that within a display frame, the signal waveforms input to the first scan line S1, the second scan line S2, and the leakage control signal line EMB are all the same. The timing of the pulse signal input to the first scan line S1 is earlier than the timing of the pulse signal input to the leakage control signal line EMB, and the timing of the pulse signal input to the leakage control signal line EMB is earlier than the timing of the pulse signal input to the second scan line S2. Moreover, the timing of the second pulse signal input to the first scan line S1 overlaps with the timing of the first pulse signal input to the leakage control signal line EMB, and the timing of the second pulse signal input to the leakage control signal line EMB overlaps with the timing of the first pulse signal input to the second scan line S2. That is, the pulse timing of the leakage control signal line EMB and the first scan line S1 overlaps in the third stage t3 (i.e., the initialization stage), and the pulse timing of the leakage control signal line EMB and the second scan line S2 overlaps in the fourth stage t4 (i.e., the data writing stage). The advantage of this setup is that it allows the same set of cascaded scanning circuits to provide signals to the first scan line S1, the second scan line S2, and the leakage control signal line EMB. The scanning circuit providing the signal to the first scan line S1 is located before the scanning circuit providing the signal to the leakage control signal line EMB, and the scanning circuit providing the signal to the leakage control signal line EMB is located before the scanning circuit providing the signal to the second scan line S2. This satisfies the signal and timing requirements of the first scan line S1, the second scan line S2, and the leakage control signal line EMB, eliminating the need for three separate sets of cascaded scanning circuits to provide signals to the first scan line S1, the second scan line S2, and the leakage control signal line EMB. This reduces the space occupied by the scanning circuits in the display panel, thus enabling a narrow bezel design.

[0134] Figure 5 and Figure 3 The driving timing of the pixel circuit shown works on a similar principle, and can be understood by referring to the above embodiments. It will not be repeated here.

[0135] Figure 6 This is a schematic diagram of the driving timing of another pixel circuit provided in an embodiment of the present invention. This driving timing is suitable for driving... Figure 1 and Figure 2 The pixel circuit shown is working. Combined with... Figure 2 and Figure 6 In the seventh stage t7 (i.e., the black insertion stage), the light emission control signal line EM receives a high-level signal, and the first scan line S1, the second scan line S2, the third scan line S3, and the leakage control signal line EMB all receive high-level signals. By controlling the ninth transistor T9 and the tenth transistor T10 to turn off, the light-emitting device D1 can also be controlled to stop emitting light during the black insertion stage, causing the display panel to display a black screen. In this embodiment, when the refresh frequency of the current display frame is lower than the preset frequency, the frequency of the pulse signal input to the light emission control signal line EM is configured to be an integer multiple of the refresh frequency of the current display frame, and the frequencies of the pulse signals input to the first scan line S1, the second scan line S2, and the third scan line S3 are all configured to be the same as the refresh frequency of the current display frame.

[0136] Figure 7 This is a schematic diagram of another pixel circuit structure provided in an embodiment of the present invention. See also... Figure 7 The pixel circuit also includes a coupling module 230. The first end of the coupling module 230 is connected to the first node N1, and the second end of the coupling module 230 is connected to the switching voltage. The coupling module 230 is used to couple the switching voltage to the first node N1 to reduce the voltage difference between the control terminal G of the driving module 110 and the first node N1 during the light emission stage.

[0137] Specifically, the switching voltage connected to the second terminal of the coupling module 230 experiences a level transition. When a level transition occurs on the leakage control signal line EMB connected to the gates of the first transistor T1 and the second transistor T2, it couples the voltage of the first node N1, thereby increasing the voltage difference between the control terminal G of the driving module 110 and the first node N1. By coupling the switching voltage to the first node N1 through the coupling module 230, the voltage of the first node N1 can be adjusted to reduce the voltage difference between the control terminal G of the driving module 110 and the first node N1 during the light-emitting stage, thereby reducing the leakage current of the first transistor T1 and maintaining the stability of the voltage at the control terminal G of the driving module 110.

[0138] In one embodiment, the second end of the coupling module 230 can be connected to the light emission control signal line EM, and the voltage on the light emission control signal line EM can be multiplexed as a switching voltage.Figure 5 The driving timing shown is also applicable to the operation of the pixel circuit in Figure 7 , which is described illustratively in conjunction with Figure 5 and Figure 7 At the end of the fourth phase t4, the signal inputted by the drain current control signal line EMB jumps from a low level signal to a high level signal, thereby coupling the voltage of the first node N1 to be higher than the gate voltage of the driving transistor DT. At the beginning of the sixth phase t6 (i.e. the light emitting phase), the signal inputted by the light emitting control signal line EM jumps from a high level signal to a low level signal. The coupling module 230 can couple the voltage of the first node N1 to be lowered according to the jump of the voltage at the second end of the coupling module 230, thereby reducing the voltage difference between the gate of the driving transistor DT and the first node N1 in the light emitting phase, reducing the drain current of the first transistor T1, and maintaining the stability of the voltage at the control end G of the driving module 110.

[0139] In actual applications, the jump voltage inputted at the second end of the coupling module 230 is not limited to the voltage on the light emitting control signal line EM. The jump voltage can be any voltage that jumps in level at the beginning of the sixth phase t6, and the jump trend of the level of the jump voltage is opposite to the jump trend of the level of the light emitting control signal line EMB at the end of the fourth phase t4.

[0140] Continuing to refer to Figure 7 , further, the coupling module 230 includes a third capacitor C3, the first plate of the third capacitor C3 is connected to the first node N1, and the second plate of the third capacitor C3 is inputted with the jump voltage. For example, the second plate of the third capacitor C3 can be connected to the light emitting control signal line EM to multiplex the voltage on the light emitting control signal line EM as the jump voltage.

[0141] Continuing to refer to Figure 7 , optionally, the pixel circuit further includes a fourth transistor T4, the gate of the fourth transistor T4 is connected to the drain current control signal line EMB, and the fourth transistor T4 is connected between the second node N2 and the third transistor T3. By arranging the fourth transistor T4 between the second node N2 and the third transistor T3, the fourth transistor T4 can be turned off in response to the signal on the drain current control signal line EMB in the light emitting phase, thereby further blocking the drain current path between the gate of the driving transistor DT and the third transistor T3, and helping to maintain the stability of the gate voltage of the driving transistor DT.

[0142] Figure 8 is a structural schematic diagram of another pixel circuit provided by an embodiment of the present application. Referring to Figure 8In another embodiment, the third transistor T3 can also be connected between the first electrode of the driving transistor DT and the first node N1. In the light emitting stage, by controlling the first transistor T1 and the second transistor T2 to be turned off in response to the signal on the leakage control signal line EMB, the leakage path between the gate of the driving transistor DT and the third transistor T3 can be blocked by the first transistor T1, and the leakage path between the gate of the driving transistor DT and the first initialization signal line Vref1 can be blocked by the first transistor T1 and the second transistor T2, which helps to maintain the stability of the gate voltage of the driving transistor DT.

[0143] Continuing to refer to Figure 8 , further, the pixel circuit further includes a fifth transistor T5, the gate of the fifth transistor T5 is connected to the leakage control signal line EMB, and the fifth transistor T5 is connected between the data line Data and the data writing module 180. Figure 5 and Figure 6 , the driving timing shown in Figure 8 is also applicable to the operation of the pixel circuit in Figure 5 , Figure 6 and Figure 8 , for example, in the fourth stage t4 (i.e. the data writing stage), the fifth transistor T5 is turned on in response to the low-level signal on the leakage control signal line EMB, so that the data voltage on the data line Data can be transmitted to the data writing module 180 through the fifth transistor T5, without affecting the writing of the data voltage to the control terminal G of the driving module 110 by the data writing module 180. In the seventh stage t7 (i.e. the black insertion stage), the fifth transistor T5 is turned off in response to the low-level signal on the leakage control signal line EMB, so as to avoid the transmission of the data voltage on the data line Data to the data writing module 180, thereby avoiding the influence on the voltage of the control terminal G of the driving module 110.

[0144] Based on the same inventive concept, the embodiments of the present application also provide a display panel, which includes the pixel circuit in any of the above embodiments, and thus has the corresponding functional modules and beneficial effects in the pixel circuit.

[0145] Figure 9 is a top view of a display panel provided by an embodiment of the present application, in which only part of the structure of the display panel is shown. Figure 10 is a sectional view of the display panel in Figure 9 , obtained by cutting along the section line BB'. Figure 11 is a sectional view of the display panel in Figure 9 , obtained by cutting along the section line CC'. In combination with Figure 2 , Figure 9 to Figure 11The display panel comprises a substrate 10, a leakage control signal line EMB, a switching part 310, and a pixel circuit in any of the above embodiments, wherein the leakage control signal line EMB, the switching part 310, and the pixel circuit are all located on the substrate 10.

[0146] The driving module 110 comprises a driving transistor DT, the first leakage suppression module 130 comprises a first transistor T1, the second leakage suppression module 140 comprises a second transistor T2, a gate of the first transistor T1 and a gate of the second transistor T2 are connected to the leakage control signal line EMB. The first transistor T1 is connected between the gate of the driving transistor DT and the second transistor T2, a semiconductor layer 20b of the first transistor T1 is connected to the gate of the driving transistor DT through the switching part 310, the leakage control signal line EMB is located on the first metal layer 30, the switching part 310 is located on the second metal layer 40, and a vertical projection of the leakage control signal line EMB on the substrate 10 and a vertical projection of the switching part 310 on the substrate 10 are overlapped, so as to couple the gate voltage of the driving transistor DT through the voltage on the leakage control signal line EMB.

[0147] Specifically, the display panel can be an organic light-emitting diode (OLED) display panel, a micro light-emitting diode (Micro-LED) display panel, or the like. The substrate 10 can provide buffering, protection, or support for the display panel. The substrate 10 can be a flexible substrate, and the material of the flexible substrate can be polyimide (PI), polyethylene naphthalate (PEN), polyethylene terephthalate (PET), or the like, or a mixed material of the above materials. The substrate 10 can also be a hard substrate formed of glass or the like. The display panel further comprises a semiconductor layer 20 located on one side of the substrate 10, wherein the semiconductor layer 20 comprises semiconductor layers of thin film transistors in the pixel circuit. The first metal layer 30 is located on a side of the semiconductor layer 20 away from the substrate 10, and the gates of the thin film transistors in the pixel circuit are all located in the first metal layer 30. The first metal layer 30 is arranged in a layer different from the second metal layer 40.

[0148] Figure 9The region where the semiconductor layer of each transistor is located is shown by the reference numerals of the transistors in the pixel circuit. The vertical projection of the leakage control signal line EMB on the substrate 10 overlaps the vertical projection of the semiconductor layer 20b of the first transistor T1 on the substrate 10, the semiconductor layer 20b of the first transistor T1 on the one side of the leakage control signal line EMB includes the source region of the first transistor T1, the semiconductor layer 20b of the first transistor T1 on the other side of the leakage control signal line EMB includes the drain region of the first transistor T1, and the semiconductor layer 20b of the first transistor T1 on the one side of the leakage control signal line EMB is connected to the semiconductor layer 20c of the second transistor T2, and the semiconductor layer 20b of the first transistor T1 on the other side of the leakage control signal line EMB is connected to the gate of the driving transistor DT through the adapter 310, so that the first transistor T1 is connected between the gate of the driving transistor DT and the second transistor T2, and the semiconductor layer 20b of the first transistor T1 and the gate of the driving transistor DT are electrically connected through the adapter 310.

[0149] By setting the vertical projection of the leakage control signal line EMB on the substrate 10 to overlap the vertical projection of the adapter 310 on the substrate 10, the gate voltage of the driving transistor DT connected by the adapter 310 can be coupled when the voltage on the leakage control signal line EMB jumps. For example, before the pixel circuit enters the light-emitting stage, when the signal on the leakage control signal line EMB jumps from a low-level signal to a high-level signal, the leakage control signal line EMB can couple the gate voltage of the driving transistor DT to raise the gate voltage of the driving transistor DT, thereby compensating for the voltage loss of the gate of the driving transistor DT due to leakage to ensure display effect.

[0150] In combination Figure 2 , Figure 9 to Figure 11 , on the basis of the above-mentioned embodiments, optionally, the second metal layer 40 is located on the side of the semiconductor layer 20b of the first transistor T1 away from the substrate 10, and the vertical projection of the adapter 310 on the substrate 10 overlaps the vertical projection of the semiconductor layer 20b of the first transistor T1 on the substrate 10. The advantage of such arrangement is that the adapter 310 can cover at least part of the semiconductor layer 20b of the first transistor T1 to shield the light for the semiconductor layer 20b of the first transistor T1 through the adapter 310, which helps to reduce the leakage current of the first transistor T1, thereby improving the stability of the gate voltage of the driving transistor DT.

[0151] Further, the first metal layer 30 is located at the side of the semiconductor layer 20b of the first transistor T1 away from the substrate 10, and the second metal layer 40 is located at the side of the first metal layer 30 away from the substrate 10, for example, the source / drain electrode of the driving transistor DT is located at the second metal layer 40, and the transfer part 310 can be arranged in the same layer as the source / drain electrode of the driving transistor DT.

[0152] In combination Figure 2 , Figure 9 to Figure 11 Optionally, along the first direction X, the semiconductor layer 20b of the first transistor T1 and the semiconductor layer 20c of the second transistor T2 are located at the same side of the semiconductor layer 20a of the driving transistor DT, and the leakage control signal line EMB extends along the second direction Y, the vertical projection of the semiconductor layer 20b of the first transistor T1 on the substrate 10 and the vertical projection of the semiconductor layer 20c of the second transistor T2 on the substrate 10 both overlap with the vertical projection of the leakage control signal line EMB on the substrate 10, and the first direction X intersects with the second direction Y. In this way, by arranging one leakage control signal line EMB extending along the same direction, and overlapping with the semiconductor layers 20 located at the same side of the semiconductor layer 20a of the driving transistor DT, the first transistor T1 and the second transistor T2 can be formed at the same time, which helps to simplify the layout structure of the pixel circuit.

[0153] In combination Figure 7 , Figure 9 to Figure 11 Optionally, the threshold compensation module 160 includes a third transistor T3, and the pixel circuit further includes a fourth transistor T4, the gate of the fourth transistor T4 is connected to the leakage control signal line EMB, and the fourth transistor T4 is connected between the second transistor T2 and the third transistor T3. The semiconductor layer 20d of the fourth transistor T4 is located at the same side of the semiconductor layer 20b of the first transistor T1 and the semiconductor layer 20c of the second transistor T2 as the semiconductor layer 20a of the driving transistor DT, and the vertical projection of the semiconductor layer 20d of the fourth transistor T4 on the substrate 10 overlaps with the vertical projection of the leakage control signal line EMB on the substrate 10. By arranging one leakage control signal line EMB extending along the same direction, and overlapping with the semiconductor layers 20 located at the same side of the semiconductor layer 20a of the driving transistor DT, the first transistor T1, the second transistor T2 and the fourth transistor T4 can be formed at the same time, which helps to simplify the layout structure of the pixel circuit.

[0154] Further, the semiconductor layer 20b of the first transistor T1, the semiconductor layer 20c of the second transistor T2 and the semiconductor layer 20d of the fourth transistor T4 are arranged in sequence along the second direction Y, so as to facilitate the connection between the first transistor T1, the second transistor T2, the third transistor T3 and the fourth transistor T4.

[0155] In combination Figure 7 , Figure 9 to Figure 11Optionally, the first storage module 150 includes a first capacitor C1, a first plate C11 of the first capacitor C1 is connected to the first node N1, and a second plate C12 of the first capacitor C1 is connected to a fixed voltage. The second plate C12 of the first capacitor C1 is located on the third metal layer 50, the third metal layer 50 is located between the first metal layer 30 and the second metal layer 40, the display panel further includes a semiconductor portion 20f, the semiconductor portion 20f is arranged in the same layer as the semiconductor layer 20b of the first transistor T1 and the semiconductor layer 20c of the second transistor T2, and the semiconductor portion 20f is electrically connected to the semiconductor layer 20b of the first transistor T1 and the semiconductor layer 20c of the second transistor T2. The vertical projection of the second plate C12 of the first capacitor C1 on the substrate 10 and the vertical projection of the semiconductor portion 20f on the substrate 10 overlap, and the semiconductor portion 20f serves as the first plate C11 of the first capacitor C1.

[0156] Since the semiconductor portion 20f is electrically connected to the semiconductor layer 20b of the first transistor T1 and the semiconductor layer 20c of the second transistor T2, by taking the semiconductor portion 20f in the semiconductor layer 20 as the first plate C11 of the first capacitor C1, the electrical connection of the first capacitor C1 to the first transistor T1 and the second transistor T2 can be realized, without the need to arrange a metal structure in the first metal layer 30 as the first plate C11 of the first capacitor C1, and without the need to realize the electrical connection of the first plate C11 of the first capacitor C1 to the semiconductor layer 20b of the first transistor T1 and the semiconductor layer 20c of the second transistor T2 by punching, which helps to simplify the manufacturing process of the display panel.

[0157] Further, the first initialization signal line Vref1 is located on the third metal layer 50, the first initialization signal line Vref1 is connected to a first initialization voltage, the first initialization voltage is multiplexed as the fixed voltage to which the second plate C12 of the first capacitor C1 is connected, the vertical projection of the first initialization signal line Vref1 on the substrate 10 and the vertical projection of the semiconductor portion 20f on the substrate 10 overlap, and the first initialization signal line Vref1 is multiplexed as the second plate C12 of the first capacitor C1. The advantage of such an arrangement is that the first initialization signal line Vref1 and the semiconductor portion 20f can be used to form the first capacitor C1, without the need to separately arrange the first initialization signal line Vref1 and the second plate C12 of the first capacitor C1, which helps to save the wiring space of the display panel.

[0158] Further, the second storage module 210 includes a second capacitor C2, a first plate C21 of the second capacitor C2 is connected to the gate of the driving transistor DT, and a second plate C22 of the second capacitor C2 is connected to a fixed voltage. The first plate C21 of the second capacitor C2 is located on the first metal layer 30, and the second plate C22 of the second capacitor C2 is located on the third metal layer 50.

[0159] Figure 12 is a top view of another display panel provided by an embodiment of the present application, in which only partial structure of the display panel is shown. Figure 13 is Figure 12 is a sectional view of the display panel in Figure 14 is Figure 12 is a sectional view of the display panel in

[0160] in combination with Figure 8 , Figure 12 to Figure 14 Optionally, the pixel circuit further includes a fifth transistor T5, a gate of the fifth transistor T5 is connected with an electric leakage control signal line EMB, and the fifth transistor T5 is connected between the data line Data and the data writing module 180. The semiconductor layer 20e of the fifth transistor T5 is located on the same side of the semiconductor layer 20a of the driving transistor DT as the semiconductor layer 20b of the first transistor T1 and the semiconductor layer 20c of the second transistor T2, and the vertical projection of the semiconductor layer 20e of the fifth transistor T5 on the substrate 10 overlaps the vertical projection of the electric leakage control signal line EMB on the substrate 10. By arranging one electric leakage control signal line EMB extending in the same direction and overlapping the semiconductor layers 20 located on the same side of the semiconductor layer 20a of the driving transistor DT, the first transistor T1, the second transistor T2 and the fifth transistor T5 can be formed at the same time, which helps to simplify the layout structure of the pixel circuit.

[0161] Further, the semiconductor layer 20b of the first transistor T1, the semiconductor layer 20c of the second transistor T2 and the semiconductor layer 20e of the fifth transistor T5 are arranged in the second direction Y in sequence, so as to facilitate the electrical connection between the transistors.

[0162] In the embodiment, the semiconductor part 20f can also be used as the first plate C11 of the first capacitor C1, the second plate C12 of the first capacitor C1 is located on the third metal layer 50, and the first power line VDD is electrically connected with the second plate C12 of the first capacitor C1, so as to input the first power voltage of the first power line VDD as the fixed voltage inputted by the second plate C12 of the first capacitor C1.

[0163] Based on the same inventive concept, the present application also provides a display panel, which includes the pixel circuit in any of the above embodiments, and thus has the corresponding functional modules and beneficial effects in the pixel circuit. Figure 15 is a structural schematic diagram of a display panel provided by an embodiment of the present application. Referring to Figure 15The display panel has a display area AA and a non-display area NAA. The display panel includes a first scan circuit group and a plurality of rows of pixel circuits 100 of any of the above embodiments. The pixel circuits 100 are located in the display area AA, and the first scan circuit group is located in the non-display area NAA. The first scan circuit group includes a plurality of cascaded first scan circuits 200. Each first scan circuit 200 generates a scan signal with a time sequence that is sequentially delayed. The output terminal OUT of each first scan circuit 200 is connected to at least one row of pixel circuits 100 to provide the scan signal to the pixel circuits 100.

[0164] In the same row of pixel circuits 100, the control terminal of the threshold compensation module 160 is connected to the output terminal OUT of one first scan circuit 200, the control terminal of the first leakage suppression module 130 and the control terminal of the second leakage suppression module 140 are connected to the output terminal OUT of another first scan circuit 200, and the first scan circuit 200 connected to the control terminal of the first leakage suppression module 130 and the control terminal of the second leakage suppression module 140 is located before the first scan circuit 200 connected to the control terminal of the threshold compensation module 160.

[0165] Specifically, the start signal terminal SIN1 of the first first scan circuit 200 in the first scan circuit group is connected to the first start signal line 410, and the first start signal line 410 inputs a first start signal. The first start signal is a pulse signal. The first scan circuit 200 is configured to delay the time sequence of the pulse signal input by the start signal terminal SIN1 to obtain a scan signal, and provide the scan signal to the corresponding pixel circuit 100 through the output terminal OUT. In each adjacent two-stage first scan circuit 200, the output terminal OUT of the previous first scan circuit 200 is connected to the start signal terminal SIN1 of the next first scan circuit 200, so that the scan signal output by the previous first scan circuit 200 is used as the start signal of the next first scan circuit 200. In this way, each first scan circuit 200 in the first scan circuit group can output a scan signal with a time sequence that is sequentially delayed.

[0166] In combination with Figure 2 , Figure 3 and Figure 15Specifically, the display panel further comprises a second scan line S2 and an electric leakage control signal line EMB, and in the pixel circuits 100 in the same row: the control end of the threshold compensation module 160 of each pixel circuit 100 is connected to the output end OUT of one first scan circuit 200 through the second scan line S2, the control end of the first electric leakage suppression module 130 and the control end of the second electric leakage suppression module 140 of each pixel circuit 100 are connected to the output end OUT of another first scan circuit 200 through the electric leakage control signal line EMB, and the first scan circuit 200 connected to the control end of the first electric leakage suppression module 130 and the control end of the second electric leakage suppression module 140 is located before the first scan circuit 200 connected to the control end of the threshold compensation module 160.

[0167] The advantage of such an arrangement is that one first scan circuit 200 in the first scan circuit group can provide a scan signal to the electric leakage control signal line EMB connected to the pixel circuits 100 in the same row, and another first scan circuit 200 located after the first scan circuit 200 can provide a scan signal to the second scan line S2 connected to the pixel circuits 100 in the same row, so that the same pulse signal is provided to the second scan line S2 and the electric leakage control signal line EMB in a display frame, and the pulse signal input by the second scan line S2 has a time sequence later than the pulse signal input by the electric leakage control signal line EMB, so that the electric leakage control signal line EMB can input a pulse signal in the initialization stage and the data writing stage in a display frame, and the second scan line S2 can input a pulse signal in the data writing stage, thereby meeting the working time sequence requirement of the pixel circuit.

[0168] Two first scan circuits 200 in the first scan circuit group can provide scan signals to the electric leakage control signal line EMB and the second scan line S2 connected to the pixel circuits 100 in the same row respectively, without the need to arrange two scan circuit groups in the display panel to provide scan signals to the electric leakage control signal line EMB and the second scan line S2 respectively, which is beneficial to reduce the space occupied by the scan circuit in the display panel, thereby realizing a narrow frame design.

[0169] In combination with Figure 2 , Figure 3 and Figure 15 , further, the control end of the first electric leakage suppression module 130 and the control end of the second electric leakage suppression module 140 in the i-th row of pixel circuits 100 are connected to the output end OUT of the i-th first scan circuit 200 through the electric leakage control signal line EMB, and the control end of the threshold compensation module 160 in the i-th row of pixel circuits 100 is connected to the output end OUT of the (i+2)-th first scan circuit 200 through the second scan line S2. Wherein, i is greater than or equal to 1 and less than or equal to the total number of rows of pixel circuits 100.

[0170] Figure 15Only 4 rows of pixel circuits 100 in the display panel and 5 first scan circuits 200 in the first scan circuit group are shown in the figure, in actual applications, the display panel can include multiple rows of pixel circuits 100, and the first scan circuit group can include multiple first scan circuits 200. The control end of the first leakage suppression module 130 and the control end of the second leakage suppression module 140 in the first row of pixel circuits 100 are connected to the output end OUT of the first first scan circuit 200 through the leakage control signal line EMB, the control end of the threshold compensation module 160 in the first row of pixel circuits 100 is connected to the output end OUT of the third first scan circuit 200 through the second scan line S2, the control end of the first leakage suppression module 130 and the control end of the second leakage suppression module 140 in the second row of pixel circuits 100 are connected to the output end OUT of the second first scan circuit 200 through the leakage control signal line EMB, the control end of the threshold compensation module 160 in the second row of pixel circuits 100 is connected to the output end OUT of the fourth first scan circuit 200 through the second scan line S2, and so on. The first scan circuit 200 connected to the control end of the first leakage suppression module 130, the second leakage suppression module 140 and the threshold compensation module 160 in each row of pixel circuits 100 can be determined, and will not be listed one by one.

[0171] Figure 3 The signals input by the leakage control signal line EMB and the second scan line S2 connected to the second n-1 row and the second n row of pixel circuits 100 are shown, where n is greater than or equal to 1, and 2n is less than or equal to the total number of rows of pixel circuits 100. For example, the second n-1 first scan circuit 200 outputs a scan signal S(2n-1) and provides the scan signal S(2n-1) to the leakage control signal line EMB connected to the second n-1 row of pixel circuits 100 to control the first leakage suppression module 130 and the second leakage suppression module 140 to work. The second n+1 first scan circuit 200 outputs a scan signal S(2n+1) and provides the scan signal S(2n+1) to the second scan line S2 connected to the second n-1 row of pixel circuits 100 to control the threshold compensation module 160 to work, so that the first pulse signal input by the second scan line S2 corresponding to the second n-1 row of pixel circuits 100 and the second pulse signal input by the leakage control signal line EMB overlap in time sequence, to meet the working time sequence requirement of the second n-1 row of pixel circuits 100.

[0172] Similarly, the 2n-th first scan circuit 200 outputs a scan signal S(2n) and provides the scan signal S(2n) to the drain control signal line EMB connected to the 2n-th row of pixel circuits 100 to control the first drain suppression module 130 and the second drain suppression module 140 to work. The 2n+2-th first scan circuit 200 outputs a scan signal S(2n+2) and provides the scan signal S(2n+2) to the second scan line S2 connected to the 2n-th row of pixel circuits 100 to control the threshold compensation module 160 to work. The first pulse signal input by the second scan line S2 corresponding to the 2n-th row of pixel circuits 100 and the second pulse signal input by the drain control signal line EMB are overlapped in time sequence, so as to meet the working time sequence requirement of the 2n-th row of pixel circuits 100.

[0173] On the basis of the above-mentioned embodiments, as shown in Figure 15 The number of the first scan circuit group can be 1, and each first scan circuit 200 in the first scan circuit group is located in the non-display area NAA on one side of the display area AA along the row direction of the pixel circuit 100. In another embodiment, the number of the first scan circuit group can also be 2, and each first scan circuit 200 in one of the first scan circuit groups is located in the non-display area NAA on one side of the display area AA, and each first scan circuit 200 in the other of the first scan circuit groups is located in the non-display area NAA on the other side of the display area AA, so as to supply the scan signal to the corresponding second scan line S2 or drain control signal line EMB through the first scan circuits 200 on both sides at the same time, which helps to avoid the influence of the voltage drop on the second scan line S2 or drain control signal line EMB on the display effect.

[0174] Figure 16 is another structure diagram of a display panel provided by an embodiment of the present application. Referring to Figure 16Optionally, the display panel further comprises a second scan circuit group, the second scan circuit group is located in the non-display area NAA, and the second scan circuit group comprises a plurality of cascaded second scan circuits 300, each second scan circuit 300 generates a scan signal with a time sequence that is sequentially delayed. Specifically, the first second scan circuit 300 in the second scan circuit group is connected with the second start signal line 420 at the start signal end SIN2, and the second start signal line 420 inputs a second start signal, which is a pulse signal. The second scan circuit 300 is configured to delay the time sequence of the pulse signal input at the start signal end SIN2 to obtain a scan signal, and provide the scan signal to the corresponding pixel circuit 100 through the output end OUT. In each adjacent two-stage second scan circuit 300, the output end OUT of the former second scan circuit 300 is connected with the start signal end SIN2 of the latter second scan circuit 300, so as to take the scan signal output by the former second scan circuit 300 as the start signal of the latter second scan circuit 300, so that each second scan circuit 300 in the second scan circuit group can sequentially output a scan signal with a time sequence that is sequentially delayed.

[0175] In combination with Figure 2 , Figure 3 and Figure 16 , further, the display panel further comprises a first scan line S1. In an embodiment, the output end OUT of the jth second scan circuit 300 can be connected with the control end of the first initialization module 170 in the 2j-1th row and the 2jth row pixel circuit 100 through the first scan line S1, so as to provide the scan signal to the control end of the first initialization module 170 in the corresponding pixel circuit 100. Wherein, j is greater than or equal to 1 and less than or equal to the total number of the second scan circuit 300.

[0176] Figure 16 In the above embodiment, only 4 rows of pixel circuits 100 in the display panel and 2 second scan circuits 300 in the second scan circuit group are shown, in actual application, the display panel can comprise a plurality of rows of pixel circuits 100, and the second scan circuit group can comprise a plurality of second scan circuits 300. Wherein, the output end OUT of the first second scan circuit 300 is connected with the control end of the first initialization module 170 in the 1st row and the 2nd row pixel circuit 100 through the first scan line S1, so as to provide the scan signal to the control end of the first initialization module 170 in the corresponding pixel circuit 100. The output end OUT of the second second scan circuit 300 is connected with the control end of the first initialization module 170 in the 3rd row and the 4th row pixel circuit 100 through the first scan line S1, so as to provide the scan signal to the control end of the first initialization module 170 in the corresponding pixel circuit 100. Similarly, the second scan circuit 300 connected with the control end of the first initialization module 170 in each row of pixel circuit 100 can be determined, and will not be listed one by one.

[0177] Figure 3 The first scan line S1 connected with the nth-1th row and the nth row pixel circuits 100 inputs a signal, and the nth second scan circuit 300 outputs a scan signal Scan(n) and provides the scan signal Scan(n) to the first scan line S1 connected with the nth-1th row and the nth row pixel circuits 100 to control the first initialization module 170 to work. The advantage of such an arrangement is that two rows of pixel circuits 100 can be driven to work by one second scan circuit 300, which is conducive to reducing the number of second scan circuits 300 and thus reducing the space occupied by the second scan circuit 300 in the display panel, achieving a narrow frame design.

[0178] In combination with Figure 2 , Figure 3 and Figure 16 , further, the pixel circuit 100 further comprises a light emitting control module 220, and the display panel further comprises a light emitting control signal generation circuit group, the light emitting control signal generation circuit group is located in the non-display area NAA, and the light emitting control signal generation circuit group comprises a plurality of cascaded light emitting control signal generation circuits 400, and each light emitting control signal generation circuit 400 generates a light emitting control signal with a time sequence sequentially shifted backward. Specifically, the first light emitting control signal generation circuit 400 in the light emitting control signal generation circuit group is connected with the third start signal line 430 at the start signal end EIN, and the third start signal line 430 inputs a third start signal, and the third start signal is a pulse signal. The light emitting control signal generation circuit 400 is used to shift the time sequence of the pulse signal input at the start signal end EIN to obtain a light emitting control signal, and provide the light emitting control signal to the corresponding pixel circuit 100 through the output end OUT. In each adjacent two-stage light emitting control signal generation circuit 400, the output end OUT of the former light emitting control signal generation circuit 400 is connected with the start signal end EIN of the latter light emitting control signal generation circuit 400, so as to take the scan signal output by the former light emitting control signal generation circuit 400 as the start signal of the latter light emitting control signal generation circuit 400, so that each light emitting control signal generation circuit 400 in the light emitting control signal generation circuit group can output a light emitting control signal with a time sequence sequentially shifted backward.

[0179] In combination with Figure 2 , Figure 3 and Figure 16Further, the display panel further comprises a light emitting control signal line EM. In an embodiment, the output terminal OUT of the kth light emitting control signal generation circuit 400 is connected to the control terminals of the light emitting control modules 220 in the 2k-1th row and the 2kth row of pixel circuits 100 through the light emitting control signal line EM, so as to provide the light emitting control signal to the control terminals of the light emitting control modules 220 in the corresponding pixel circuits 100. Wherein, k is greater than or equal to 1 and less than or equal to the total number of the light emitting control signal generation circuits 400.

[0180] Figure 16 Only two light emitting control signal generation circuits 400 in the light emitting control signal generation circuit group are shown in the figure, in actual application, the light emitting control signal generation circuit group can comprise a plurality of light emitting control signal generation circuits 400. Wherein, the output terminal OUT of the 1st light emitting control signal generation circuit 400 is connected to the control terminals of the light emitting control modules 220 in the 1st row and the 2nd row of pixel circuits 100 through the light emitting control signal line EM, so as to provide the light emitting control signal to the control terminals of the light emitting control modules 220 in the corresponding pixel circuits 100. The output terminal OUT of the 2nd light emitting control signal generation circuit 400 is connected to the control terminals of the light emitting control modules 220 in the 3rd row and the 4th row of pixel circuits 100 through the light emitting control signal line EM, so as to provide the light emitting control signal to the control terminals of the light emitting control modules 220 in the corresponding pixel circuits 100. Similarly, the light emitting control signal generation circuit 400 connected to the control terminals of the light emitting control modules 220 in each row of pixel circuits 100 can be determined, and will not be listed one by one.

[0181] Figure 3 The signal input by the light emitting control signal line EM connected to the 2n-1th row and the 2nth row of pixel circuits 100 is shown. Exemplarily, the nth light emitting control signal generation circuit 400 outputs the light emitting control signal E(n) and provides the light emitting control signal E(n) to the light emitting control signal line EM connected to the 2n-1th row and the 2nth row of pixel circuits 100, so as to control the light emitting control module 220 to work. The advantage of such arrangement is that one light emitting control signal generation circuit 400 can drive two rows of pixel circuits 100 to work, which is conducive to reducing the number of light emitting control signal generation circuits 400, thereby reducing the space occupied by the light emitting control signal generation circuit 400 in the display panel, and realizing narrow frame design.

[0182] Referring to Figure 16On the basis of the above embodiment, optionally, the second scan circuit group and the light-emitting control signal generation circuit group are located in the non-display area NAA on the same side of the display area AA. The display panel further comprises a first clock signal line 440 and a second clock signal line 450. In the case that the number of pixel circuits 100 connected to each light-emitting control signal generation circuit 400 is the same as the number of pixel circuits 100 connected to each second scan circuit 300, the second scan circuit 300 and the light-emitting control signal generation circuit 400 are both connected to the first clock signal line 440 and the second clock signal line 450, so that the second scan circuit 300 generates a scan signal in response to the signals on the first clock signal line 440 and the second clock signal line 450, and the light-emitting control signal generation circuit 400 generates a light-emitting control signal in response to the signals on the first clock signal line 440 and the second clock signal line 450.

[0183] Specifically, the first clock signal line 440 inputs a first clock signal, and the second clock signal line 450 inputs a second clock signal. Both the first clock signal and the second clock signal are clock signals that alternately change between high and low levels, and the pulse timing of the first clock signal is different from that of the second clock signal. In the case that each second scan circuit 300 is used to drive two rows of pixel circuits 100 to work, and each light-emitting control signal generation circuit 400 is used to drive two rows of pixel circuits 100 to work, the frequency of the scan signal generated by the second scan circuit 300 is the same as that of the light-emitting control signal generated by the light-emitting control signal generation circuit 400. By setting the second scan circuit 300 to generate a scan signal in response to the signals on the first clock signal line 440 and the second clock signal line 450, and the light-emitting control signal generation circuit 400 to generate a light-emitting control signal in response to the signals on the first clock signal line 440 and the second clock signal line 450, the second scan circuit group and the light-emitting control signal generation circuit group can share the first clock signal line 440 and the second clock signal line 450, and there is no need to set corresponding clock signal lines for the second scan circuit group and the light-emitting control signal generation circuit group, which is conducive to reducing the number of signal lines in the display panel and achieving a narrow frame design.

[0184] Further, the first clock signal line 440 and the second clock signal line 450 extend in the same direction. The second scan circuit group is located on one side of the first clock signal line 440 and the second clock signal line 450, and the light-emitting control signal generation circuit group is located on the other side of the first clock signal line 440 and the second clock signal line 450. The second scan circuit 300 in the second scan circuit group and the light-emitting control signal generation circuit 400 in the light-emitting control signal generation circuit group are respectively arranged on both sides of the first clock signal line 440 and the second clock signal line 450, so that the arrangement of each second scan circuit 300 and each light-emitting control signal generation circuit 400 does not affect each other, which is helpful to simplify the manufacturing process of the display panel.

[0185] On the basis of the above-mentioned embodiments, as shown in Figure 16 The number of the second scan circuit groups can be 1, and each second scan circuit 300 in the second scan circuit group is located in the non-display area NAA on one side of the display area AA along the row direction of the pixel circuit 100. In another embodiment, the number of the second scan circuit groups can also be 2, and each second scan circuit 300 in one of the second scan circuit groups is located in the non-display area NAA on one side of the display area AA, and each second scan circuit 300 in the other of the second scan circuit groups is located in the non-display area NAA on the other side of the display area AA, so as to help avoid the influence of the voltage drop on the first scan line S1 on the display effect by simultaneously supplying the scan signal to the corresponding first scan line S1 through the second scan circuits 300 on both sides.

[0186] The number of the light-emitting control signal generation circuit groups can be 1, and each light-emitting control signal generation circuit 400 in the light-emitting control signal generation circuit group is located in the non-display area NAA on one side of the display area AA along the row direction of the pixel circuit 100. In another embodiment, the number of the light-emitting control signal generation circuit groups can also be 2, and each light-emitting control signal generation circuit 400 in one of the light-emitting control signal generation circuit groups is located in the non-display area NAA on one side of the display area AA, and each light-emitting control signal generation circuit 400 in the other of the light-emitting control signal generation circuit groups is located in the non-display area NAA on the other side of the display area AA, so as to help avoid the influence of the voltage drop on the light-emitting control signal line EM on the display effect by simultaneously supplying the scan signal to the corresponding light-emitting control signal line EM through the light-emitting control signal generation circuits 400 on both sides.

[0187] When the number of the second scan circuit groups and the light-emitting control signal generation circuit groups is both 2, the second scan circuit group and the light-emitting control signal generation circuit group located on the same side of the display panel can be set to share one first clock signal line 440 and one second clock signal line 450, and the second scan circuit 300 in the second scan circuit group and the light-emitting control signal generation circuit 400 in the light-emitting control signal generation circuit group are respectively set on both sides of the first clock signal line 440 and the second clock signal line 450.

[0188] Figure 17 is another structural schematic diagram of a display panel provided by an embodiment of the present application; Figure 18 is a driving timing schematic diagram of another pixel circuit provided by an embodiment of the present application; Figure 19 is a driving timing schematic diagram of another pixel circuit provided by an embodiment of the present application. In combination with Figure 2 , Figure 17 to Figure 19In another embodiment, the output terminal OUT of the jth second scanning circuit 300 can be connected to the control terminal of the first initialization module 170 in the jth row of pixel circuits 100 through the first scanning line S1 to provide a scanning signal to the control terminal of the first initialization module 170 in the corresponding pixel circuit 100. Here, j is greater than or equal to 1 and less than or equal to the total number of second scanning circuits 300.

[0189] Figure 17 Only four second scanning circuits 300 in the second scanning circuit group are shown in FIG. 4, but in actual applications, the second scanning circuit group can include a plurality of second scanning circuits 300. The output terminal OUT of the first second scanning circuit 300 is connected to the control terminal of the first initialization module 170 in the first row of pixel circuits 100 through the first scanning line S1 to provide a scanning signal to the control terminal of the first initialization module 170 in the corresponding pixel circuit 100. The output terminal OUT of the second second scanning circuit 300 is connected to the control terminal of the first initialization module 170 in the second row of pixel circuits 100 through the first scanning line S1 to provide a scanning signal to the control terminal of the first initialization module 170 in the corresponding pixel circuit 100. Similarly, the control terminal of the first initialization module 170 in each row of pixel circuits 100 is connected to a second scanning circuit 300, which will not be listed one by one.

[0190] Figure 18 And Figure 19 The signals input by the first scanning line S1 connected to the 2n-1th and 2nth rows of pixel circuits 100 are shown in FIG. 5. For example, the 2n-1th second scanning circuit 300 outputs a scanning signal Scan(2n-1) and provides the scanning signal Scan(2n-1) to the first scanning line S1 connected to the 2n-1th row of pixel circuits 100 to control the first initialization module 170 to work. The 2nth second scanning circuit 300 outputs a scanning signal Scan(2n) and provides the scanning signal Scan(2n) to the first scanning line S1 connected to the 2nth row of pixel circuits 100 to control the first initialization module 170 to work. Figure 18 And Figure 19 The principle of driving the pixel circuit to work according to the driving timing shown in FIG. 6 is similar to the principle of driving the pixel circuit to work according to the driving timing shown in FIG. 4, and can be understood with reference to the above embodiment, which will not be described here. Figure 3 And Figure 4 The principle of driving the pixel circuit to work according to the driving timing shown in FIG. 7 is similar to the principle of driving the pixel circuit to work according to the driving timing shown in FIG. 4, and can be understood with reference to the above embodiment, which will not be described here.

[0191] Referring to Figure 17In the embodiment, the first scan circuit 200 is connected with the third clock signal line 460 and the fourth clock signal line 470, and generates a scan signal in response to the signals on the third clock signal line 460 and the fourth clock signal line 470. The third clock signal line 460 inputs a third clock signal, and the fourth clock signal line 470 inputs a fourth clock signal. Both the third clock signal and the fourth clock signal are clock signals with high level and low level alternately changing, and the pulse timing of the third clock signal is different from that of the fourth clock signal. The second scan circuit 300 is connected with the fifth clock signal line 480 and the sixth clock signal line 490, and generates a scan signal in response to the signals on the fifth clock signal line 480 and the sixth clock signal line 490. The fifth clock signal line 480 inputs a fifth clock signal, and the sixth clock signal line 490 inputs a sixth clock signal. Both the fifth clock signal and the sixth clock signal are clock signals with high level and low level alternately changing, and the pulse timing of the fifth clock signal is different from that of the sixth clock signal. The light-emitting control signal generation circuit 400 is connected with the first clock signal line 440 and the second clock signal line 450, and generates a light-emitting control signal in response to the signals on the first clock signal line 440 and the second clock signal line 450.

[0192] In another embodiment, the output end OUT of the kth light-emitting control signal generation circuit 400 is connected with the control end of the light-emitting control module 220 in the kth row of pixel circuits 100 through the light-emitting control signal line EM, so as to provide the light-emitting control signal to the control end of the light-emitting control module 220 in the corresponding pixel circuit 100. Herein, k is greater than or equal to 1 and less than or equal to the total number of the light-emitting control signal generation circuits 400. That is, each light-emitting control signal generation circuit 400 drives one row of pixel circuits 100 to work, and the specific principle will not be described herein.

[0193] Figure 20 is a structural schematic diagram of another display panel provided by the embodiment of the present application. In combination with Figure 2 , Figure 5 and Figure 20 , optionally, in the same row of pixel circuits 100, the control end of the first initialization module 170, the control end of the threshold compensation module 160 and the control end of the first leakage suppression module 130 are respectively connected with the output end OUT of different first scan circuits 200, and the first scan circuit 200 connected with the control end of the first initialization module 170 is located before the first scan circuit 200 connected with the control end of the first leakage suppression module 130 and the control end of the second leakage suppression module 140, and the first scan circuit 200 connected with the control end of the first leakage suppression module 130 and the control end of the second leakage suppression module 140 is located before the first scan circuit 200 connected with the control end of the threshold compensation module 160.

[0194] The advantage of such an arrangement is that the three first scan circuits 200 in the first scan circuit group can provide scan signals to the drain leakage control signal line EMB, the first scan line S1 and the second scan line S2 connected to the same row of pixel circuits 100 respectively, so that the same waveform pulse signals are provided to the drain leakage control signal line EMB, the first scan line S1 and the second scan line S2 in a display frame, and the timing of the pulse signal input by the first scan line S1 is earlier than the timing of the pulse signal input by the drain leakage control signal line EMB, and the timing of the pulse signal input by the drain leakage control signal line EMB is earlier than the timing of the pulse signal input by the second scan line S2, so that the first scan line S1 can input a pulse signal in the initialization stage in a display frame, the drain leakage control signal line EMB can input a pulse signal in the initialization stage and the data writing stage respectively, and the second scan line S2 can input a pulse signal in the data writing stage, so as to meet the working timing requirements of the pixel circuit.

[0195] By providing scan signals to the drain leakage control signal line EMB, the first scan line S1 and the second scan line S2 connected to the same row of pixel circuits 100 by the three first scan circuits 200 in the first scan circuit group, it is not necessary to provide scan signals to the drain leakage control signal line EMB, the first scan line S1 and the second scan line S2 by three scan circuit groups in the display panel, which is beneficial to reduce the space occupied by the scan circuit in the display panel, so as to realize the narrow frame design.

[0196] In combination with Figure 2 , Figure 5 and Figure 20 , further, the control end of the first initialization module 170 in the ith row of pixel circuits 100 is connected to the output end OUT of the ith first scan circuit 200 through the first scan line S1, the control end of the first drain leakage suppression module 130 and the control end of the second drain leakage suppression module 140 in the ith row of pixel circuits 100 are connected to the output end OUT of the ith+2 first scan circuit 200 through the drain leakage control signal line EMB, and the control end of the threshold compensation module 160 in the ith row of pixel circuits 100 is connected to the output end OUT of the ith+4 first scan circuit 200 through the second scan line S2, wherein i is greater than or equal to 1 and less than or equal to the total number of rows of pixel circuits 100.

[0197] Figure 20Only five first scan circuits 200 in the first scan circuit group are shown in the figure, and in actual applications, the first scan circuit group can include a plurality of first scan circuits 200. The control end of the first initialization module 170 in the first row of pixel circuits 100 is connected to the output end OUT of the first first scan circuit 200 through the first scan line S1, the control end of the first leakage suppression module 130 and the control end of the second leakage suppression module 140 in the first row of pixel circuits 100 are connected to the output end OUT of the third first scan circuit 200 through the leakage control signal line EMB, the control end of the threshold compensation module 160 in the first row of pixel circuits 100 is connected to the output end OUT of the fifth first scan circuit 200 through the second scan line S2. The control end of the first initialization module 170 in the second row of pixel circuits 100 is connected to the output end OUT of the second first scan circuit 200 through the first scan line S1, the control end of the first leakage suppression module 130 and the control end of the second leakage suppression module 140 in the second row of pixel circuits 100 are connected to the output end OUT of the fourth first scan circuit 200 through the leakage control signal line EMB, and the control end of the threshold compensation module 160 in the second row of pixel circuits 100 is connected to the output end OUT of the sixth first scan circuit 200 (not shown in the figure) through the second scan line S2. In this way, the first scan circuit 200 connected to the control end of the first leakage suppression module 130, the second leakage suppression module 140, the threshold compensation module 160 and the first initialization module 170 in each row of pixel circuits 100 can be determined, and it is not necessary to enumerate them one by one.

[0198] Figure 5The signals input by the drain leakage control signal line EMB, the first scan line S1 and the second scan line S2 connected with the (2n-1)th row and the 2nth row of pixel circuits 100 are shown, where n is greater than or equal to 1, and 2n is less than or equal to the total number of rows of pixel circuits 100. Exemplarily, the (2n-1)th first scan circuit 200 outputs a scan signal S(2n-1) and provides the scan signal S(2n-1) to the first scan line S1 connected with the (2n-1)th row of pixel circuits 100 to control the first initialization module 170 to work. The (2n+1)th first scan circuit 200 outputs a scan signal S(2n+1) and provides the scan signal S(2n+1) to the drain leakage control signal line EMB connected with the (2n-1)th row of pixel circuits 100 to control the first leakage suppression module 130 and the second leakage suppression module 140 to work. The (2n+3)th first scan circuit 200 outputs a scan signal S(2n+3) and provides the scan signal S(2n+3) to the second scan line S2 connected with the (2n-1)th row of pixel circuits 100 to control the threshold compensation module 160 to work, so that the second pulse signal input by the first scan line S1 corresponding to the (2n-1)th row of pixel circuits 100 and the first pulse signal input by the drain leakage control signal line EMB overlap in time sequence, and the second pulse signal input by the drain leakage control signal line EMB and the first pulse signal input by the second scan line S2 overlap in time sequence, to meet the working time sequence requirement of the (2n-1)th row of pixel circuits 100.

[0199] Similarly, the 2nth first scan circuit 200 outputs a scan signal S(2n) and provides the scan signal S(2n) to the first scan line S1 connected with the 2nth row of pixel circuits 100 to control the first initialization module 170 to work. The (2n+2)th first scan circuit 200 outputs a scan signal S(2n+2) and provides the scan signal S(2n+2) to the drain leakage control signal line EMB connected with the 2nth row of pixel circuits 100 to control the first leakage suppression module 130 and the second leakage suppression module 140 to work. The (2n+4)th first scan circuit 200 outputs a scan signal S(2n+4) and provides the scan signal S(2n+4) to the second scan line S2 connected with the 2nth row of pixel circuits 100 to control the threshold compensation module 160 to work, so that the second pulse signal input by the first scan line S1 corresponding to the 2nth row of pixel circuits 100 and the first pulse signal input by the drain leakage control signal line EMB overlap in time sequence, and the second pulse signal input by the drain leakage control signal line EMB and the first pulse signal input by the second scan line S2 overlap in time sequence, to meet the working time sequence requirement of the 2nth row of pixel circuits 100.

[0200] It should be understood that the various forms of flow shown above can be used to reorder, add, or remove steps. For example, the steps recited in the present application can be performed in parallel, in series, or in a different order, as long as the desired results of the technical solutions of the present application can be achieved, which are not limited herein.

[0201] The above detailed description does not constitute a limitation on the protection scope of the present application. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent replacements, and improvements made within the spirit and principles of the present application shall be included in the protection scope of the present application.

Claims

1. A pixel circuit, characterized in that, include: A driving module and a light-emitting module are connected between a first power line and a second power line. The driving module is used to drive the light-emitting module according to the voltage of its own control terminal. The first leakage current suppression module is connected between the control terminal of the drive module and the first node, and is used to suppress leakage current at the control terminal of the drive module. The second leakage current suppression module is connected between the second node and the first node and is used to suppress leakage current at the control terminal of the drive module; the control terminals of the first leakage current suppression module and the second leakage current suppression module are both connected to the leakage current control signal line; A first storage module, connected to the first node, is used to store the voltage of the first node in order to reduce the voltage difference between the control terminal of the drive module and the first node. A threshold compensation module is connected between the first end of the driving module and the second node, and is used to compensate the threshold voltage of the driving module; the control end of the threshold compensation module is connected to the second scan line. The pixel circuit further includes a coupling module. The first end of the coupling module is connected to the first node, and the second end of the coupling module is connected to a switching voltage. The coupling module is used to couple the switching voltage to the first node to reduce the voltage difference between the control terminal of the driving module and the first node during the light emission stage. Within a display frame, the signal waveform input by the second scan line is the same as the signal waveform input by the leakage control signal line. The timing of the pulse signal input by the second scan line is later than the timing of the pulse signal input by the leakage control signal line, and the timing of the first pulse signal input by the second scan line overlaps with the timing of the second pulse signal input by the leakage control signal line.

2. The pixel circuit according to claim 1, characterized in that, The first end of the first storage module is connected to the first node, and the second end of the first storage module is connected to a fixed voltage.

3. The pixel circuit according to claim 2, characterized in that, The pixel circuit further includes a first initialization module, which is connected between the initialization signal line and the second node, and is used to write the voltage on the initialization signal line into the control terminal of the driving module.

4. The pixel circuit according to claim 3, characterized in that, The second end of the first storage module is connected to the initialization signal line, the initialization signal line is connected to the initialization voltage, and the initialization voltage is multiplexed to the fixed voltage.

5. The pixel circuit according to claim 4, characterized in that, The pixel circuit further includes a second initialization module, which is connected between the initialization signal line and the first end of the light-emitting module. The second initialization module is used to write the voltage on the initialization signal line into the first end of the light-emitting module.

6. The pixel circuit according to claim 5, characterized in that, The initialization signal line includes a first initialization signal line and a second initialization signal line. The first initialization signal line is connected to a first initialization voltage, and the second initialization signal line is connected to a second initialization voltage. The first initialization module is connected to the first initialization signal line, and the second initialization module is connected to the second initialization signal line. The second end of the first storage module is connected to the first initialization signal line, and the first initialization voltage is multiplexed to the fixed voltage. Alternatively, the second end of the first storage module is connected to the second initialization signal line, and the second initialization voltage is multiplexed to the fixed voltage.

7. The pixel circuit according to claim 2, characterized in that, The first power line is connected to a first power supply voltage, and the second end of the first storage module is connected to the first power line. The first power supply voltage is multiplexed to the fixed voltage.

8. The pixel circuit according to any one of claims 3-6, characterized in that, The pixel circuit also includes a data writing module, with a first end connected to a data line and a second end connected to a second end of the driving module. The control terminal of the first initialization module is connected to the first scan line, and the control terminals of the threshold compensation module and the data writing module are connected to the second scan line. The first initialization module is turned on during the initialization phase in response to the signal on the first scan line, and the first leakage current suppression module and the second leakage current suppression module are turned on during the initialization phase in response to the signal on the leakage current control signal line, so as to write the voltage on the initialization signal line into the control terminal of the drive module; The data writing module and the threshold compensation module are turned on during the data writing phase in response to the signal on the second scan line, and the first leakage current suppression module and the second leakage current suppression module are turned on during the data writing phase in response to the signal on the leakage current control signal line, so as to write the voltage on the data line into the control terminal of the driving module and compensate the threshold voltage of the driving module at the same time. The first leakage current suppression module and the second leakage current suppression module are turned off during the light-emitting phase in response to the signal on the leakage current control signal line, so as to suppress leakage current at the control terminal of the drive module.

9. The pixel circuit according to claim 8, characterized in that, The pixel circuit further includes a second initialization module and a light emission control module. The control terminal of the second initialization module is connected to the third scan line, and the control terminal of the light emission control module is connected to the light emission control signal line. The light emission control module is connected between the first power line and the light emission module. The first leakage current suppression module and the second leakage current suppression module turn off during the black insertion phase in response to the signal on the leakage current control signal line. The light emission control module turns off during the black insertion phase in response to the voltage on the light emission control signal line. The second initialization module turns on during the black insertion phase in response to the voltage on the third scan line, so as to write the voltage on the initialization signal line to the first terminal of the light emission module.

10. The pixel circuit according to claim 9, characterized in that, The leakage current control signal line is configured to input pulse signals during the initialization phase and the data writing phase within a display frame, respectively. The second scan line is configured to input a pulse signal during the data writing phase within a display frame.

11. The pixel circuit according to claim 8, characterized in that, The first scan line is configured to input a pulse signal during the initialization phase within a display frame.

12. The pixel circuit according to claim 11, characterized in that, Within a display frame, the signal waveform input by the first scan line is the same as the signal waveform input by the leakage control signal line. The timing of the pulse signal input by the first scan line is earlier than the timing of the pulse signal input by the leakage control signal line, and the timing of the second pulse signal input by the first scan line overlaps with the timing of the first pulse signal input by the leakage control signal line.

13. The pixel circuit according to claim 12, characterized in that, The pixel circuit also includes a light emission control module. The control terminal of the light emission control module is connected to the light emission control signal line. The light emission control module turns on or off in response to the voltage on the light emission control signal line. The second terminal of the coupling module is connected to the light emission control signal line. The voltage on the light emission control signal line is multiplexed as the switching voltage.

14. A display panel, characterized in that, It includes a substrate, a leakage control signal line, an adapter, and a pixel circuit as described in any one of claims 1-13, wherein the leakage control signal line, the adapter, and the pixel circuit are all located on the substrate; The driving module includes a driving transistor, the first leakage suppression module includes a first transistor, the second leakage suppression module includes a second transistor, and the gates of the first transistor and the second transistor are connected to the leakage control signal line. The first transistor is connected between the gate of the driving transistor and the second transistor. The semiconductor layer of the first transistor is connected to the gate of the driving transistor through the adapter. The leakage control signal line is located on the first metal layer, and the adapter is located on the second metal layer. The vertical projection of the leakage control signal line on the substrate overlaps with the vertical projection of the adapter on the substrate, so as to couple the gate voltage of the driving transistor through the voltage on the leakage control signal line.

15. The display panel according to claim 14, characterized in that, The second metal layer is located on the side of the semiconductor layer of the first transistor away from the substrate, and the vertical projection of the transition portion on the substrate overlaps with the vertical projection of the semiconductor layer of the first transistor on the substrate.

16. The display panel according to claim 14, characterized in that, Along the first direction, the semiconductor layers of the first transistor and the second transistor are located on the same side of the semiconductor layer of the driving transistor. The leakage control signal line extends along the second direction. The vertical projections of the semiconductor layers of the first transistor and the second transistor on the substrate both overlap with the vertical projection of the leakage control signal line on the substrate. The first direction intersects with the second direction.

17. The display panel according to claim 16, characterized in that, The threshold compensation module includes a third transistor, the first terminal of the first transistor is connected to the gate of the driving transistor, the second terminal of the first transistor is connected to the first terminal of the second transistor, and the third transistor is connected between the first terminal of the driving transistor and the second terminal of the second transistor. The pixel circuit also includes a fourth transistor, the gate of the fourth transistor is connected to the leakage control signal line, and the fourth transistor is connected between the second transistor and the third transistor. The semiconductor layer of the fourth transistor is located on the same side of the semiconductor layer of the driving transistor as the semiconductor layers of the first transistor and the second transistor, and the vertical projection of the semiconductor layer of the fourth transistor on the substrate overlaps with the vertical projection of the leakage control signal line on the substrate.

18. The display panel according to claim 17, characterized in that, The semiconductor layers of the first transistor, the second transistor, and the fourth transistor are arranged sequentially along the second direction.

19. The display panel according to claim 14, characterized in that, The pixel circuit further includes a data writing module and a fifth transistor, the gate of which is connected to the leakage control signal line, and the fifth transistor is connected between the data line and the data writing module; The semiconductor layer of the fifth transistor is located on the same side of the semiconductor layer of the driving transistor as the semiconductor layers of the first transistor and the second transistor, and the vertical projection of the semiconductor layer of the fifth transistor on the substrate overlaps with the vertical projection of the leakage control signal line on the substrate.

20. The display panel according to claim 19, characterized in that, The semiconductor layers of the first transistor, the second transistor, and the fifth transistor are arranged sequentially along the second direction.

21. The display panel according to any one of claims 14-20, characterized in that, The first storage module includes a first capacitor, the first plate of the first capacitor is connected to the first node, and the second plate of the first capacitor is connected to a fixed voltage. The second electrode of the first capacitor is located on a third metal layer, which is located between the first metal layer and the second metal layer. The display panel further includes a semiconductor portion, which is disposed on the same layer as the semiconductor layers of the first transistor and the second transistor, and is electrically connected to the semiconductor layers of the first transistor and the second transistor. The vertical projection of the second electrode of the first capacitor on the substrate overlaps with the vertical projection of the semiconductor portion on the substrate, and the semiconductor portion serves as the first electrode of the first capacitor.

22. The display panel according to claim 21, characterized in that, The initialization signal line is located in the third metal layer. The initialization signal line is connected to the initialization voltage, which is multiplexed as the fixed voltage. The vertical projection of the initialization signal line on the substrate overlaps with the vertical projection of the semiconductor part on the substrate, and the initialization signal line is multiplexed as the second plate of the first capacitor.

23. A display panel, characterized in that, The display panel has a display area and a non-display area, and the display panel includes a first scanning circuit group and multiple rows of pixel circuits as described in any one of claims 1-13; The pixel circuit is located in the display area, and the first scanning circuit group is located in the non-display area. The first scanning circuit group includes multiple cascaded first scanning circuits. Each first scanning circuit generates a scanning signal with a sequentially shifted timing. The output terminal of each first scanning circuit is connected to at least one row of the pixel circuits to provide the scanning signal to the pixel circuits. In the same row of pixel circuits, the control terminal of the threshold compensation module is connected to the output terminal of one of the first scanning circuits, the control terminals of the first leakage current suppression module and the second leakage current suppression module are connected to the output terminal of another first scanning circuit, and the first scanning circuit connected to the control terminals of the first leakage current suppression module and the second leakage current suppression module is located before the first scanning circuit connected to the control terminal of the threshold compensation module.

24. The display panel according to claim 23, characterized in that, The display panel also includes a second scan line and a leakage control signal line; The control terminals of the first leakage current suppression module and the second leakage current suppression module in the pixel circuit of the i-th row are connected to the output terminal of the i-th first scanning circuit through the leakage current control signal line. The control terminal of the threshold compensation module in the pixel circuit of the i-th row is connected to the output terminal of the (i+2)-th first scanning circuit through the second scanning line, where i is greater than or equal to 1 and less than or equal to the total number of rows of the pixel circuit.

25. The display panel according to claim 23, characterized in that, In the pixel circuit described in the same row, the control terminal of the first initialization module, the control terminal of the threshold compensation module, and the control terminal of the first leakage current suppression module are respectively connected to the output terminals of different first scanning circuits, and the first scanning circuit connected to the control terminal of the first initialization module is located before the first scanning circuit connected to the control terminals of the first leakage current suppression module and the second leakage current suppression module.

26. The display panel according to claim 23, characterized in that, The display panel further includes a first scan line, the control terminal of the first initialization module in the pixel circuit of the i-th row is connected to the output terminal of the i-th first scan circuit through the first scan line, the control terminals of the first leakage current suppression module and the second leakage current suppression module in the pixel circuit of the i-th row are connected to the output terminal of the (i+2)-th first scan circuit through the leakage current control signal line, and the control terminal of the threshold compensation module in the pixel circuit of the i-th row is connected to the output terminal of the (i+4)-th first scan circuit through the second scan line.

27. The display panel according to any one of claims 23-26, characterized in that, The display panel further includes a second scanning circuit group and a first scanning line. The second scanning circuit group is located in the non-display area. The second scanning circuit group includes multiple cascaded second scanning circuits, and each second scanning circuit generates a scanning signal with a sequentially shifted timing. The output terminal of the j-th second scanning circuit is connected to the control terminal of the first initialization module in the pixel circuit of the 2j-1 row and the 2j-th row through the first scanning line, so as to provide the scanning signal to the control terminal of the first initialization module in the corresponding pixel circuit; Alternatively, the output terminal of the j-th second scanning circuit is connected to the control terminal of the first initialization module in the j-th row of pixel circuits via the first scanning line, so as to provide the scanning signal to the control terminal of the first initialization module in the corresponding pixel circuit; Where j is greater than or equal to 1 and less than or equal to the total number of the second scanning circuits.

28. The display panel according to claim 27, characterized in that, The pixel circuit also includes a light emission control module, and the display panel also includes a light emission control signal generation circuit group and a light emission control signal line. The light emission control signal generation circuit group is located in the non-display area. The light emission control signal generation circuit group includes multiple cascaded light emission control signal generation circuits, and each of the light emission control signal generation circuits generates a light emission control signal with a sequentially shifted timing. The output terminal of the kth light emission control signal generation circuit is connected to the control terminal of the light emission control module in the pixel circuit of the (2k-1)th and 2kth rows through the light emission control signal line, so as to provide the light emission control signal to the control terminal of the light emission control module in the corresponding pixel circuit; Alternatively, the output terminal of the kth light emission control signal generation circuit is connected to the control terminal of the light emission control module in the kth row of the pixel circuit through the light emission control signal line, so as to provide the light emission control signal to the control terminal of the light emission control module in the corresponding pixel circuit; Where k is greater than or equal to 1 and less than or equal to the total number of the light emission control signal generation circuits.

29. The display panel according to claim 28, characterized in that, The second scanning circuit group and the light emission control signal generation circuit group are located in the non-display area on the same side of the display area; The display panel further includes a first clock signal line and a second clock signal line. When the number of pixel circuits connected to each of the light emission control signal generation circuits is the same as the number of pixel circuits connected to each of the second scanning circuits, both the second scanning circuit and the light emission control signal generation circuit are connected to the first clock signal line and the second clock signal line, so that the second scanning circuit generates the scanning signal in response to the signals on the first clock signal line and the second clock signal line, and the light emission control signal generation circuit generates the light emission control signal in response to the signals on the first clock signal line and the second clock signal line.

30. The display panel according to claim 29, characterized in that, The first clock signal line and the second clock signal line extend in the same direction. The second scanning circuit group is located on one side of the first clock signal line and the second clock signal line, and the light emission control signal generation circuit group is located on the other side of the first clock signal line and the second clock signal line.

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