Data reading circuit of MRAM chip and method for screening failed cells

Abstract

The application provides a data reading circuit of an MRAM chip, comprising: a to-be-tested storage unit, a first gating transistor connected in series with the to-be-tested storage unit, a reference unit, a second gating transistor connected in series with the reference unit, and a readout amplifier, wherein the reference unit has three optional reference resistance branches, including a working mode branch, a first test mode branch and a second test mode branch, the working mode branch is used for reading data of the to-be-tested storage unit, the first test mode branch is used for screening out fixed failure units and high-resistance state out-of-range failure units with an open-circuit failure type, and the second test mode branch is used for screening out fixed failure units and low-resistance state out-of-range failure units with a short-circuit failure type.

Description

Technical Field

[0001] This invention relates to the field of MRAM memory technology, and in particular to a data reading circuit for an MRAM chip and a method for screening faulty cells. Background Technology

[0002] MRAM (Magnetic Random Access Memory) is a new type of memory that is non-volatile and allows for fast random read and write operations. An MRAM memory cell consists of a magnetic tunnel junction (MTJ) and a MOSFET. The MTJ comprises a magnetic fixed layer, an insulating layer, and a magnetic free layer. The parallel and antiparallel magnetization directions of the free and fixed layers correspond to the low-resistivity state (R0). p ) and high-resistivity state (R ap ), thus recording 0 or 1.

[0003] In MRAM chips, some memory cells are defective, remaining in a high-resistance or low-resistance state and unable to flip. These cells are generally called hard-fail bits. Failures in a high-resistance state are classified as open-circuit, while those in a low-resistance state are classified as short-circuit. Some memory cells exhibit outlier resistance distributions, indicating a probability of error. These read-erroneous cells can be corrected by adjusting the reference resistor value. These hard-fail bits and outlier bits need to be screened out through testing or marked and then repaired using redundant modules.

[0004] Current MRAM read circuits are mainly used to read data from normal memory cells, but they cannot effectively filter out faulty memory cells. Summary of the Invention

[0005] To address the aforementioned issues, this invention provides a data reading circuit for an MRAM chip that can quickly and accurately identify fixed failure memory cells and outlier memory cells, thereby improving the reliability of the MRAM chip.

[0006] In a first aspect, the present invention provides a data reading circuit for an MRAM chip, comprising:

[0007] The memory cell under test includes a magnetic tunnel junction under test and a memory cell transistor connected in series;

[0008] The first gating transistor is connected to the memory cell under test;

[0009] A reference unit having three selectable reference resistor branches;

[0010] The second gating transistor is connected to the reference cell;

[0011] The readout amplifier has two input terminals connected to the first gating transistor and the second gating transistor, respectively.

[0012] Optionally, the three optional reference resistor branches include: a working mode branch, a first test mode branch, and a second test mode branch. The working mode branch is used to read data from the memory cell under test. The first test mode branch is used to filter out fixed failure cells with open circuit failure type and high-resistance outlier failure cells. The second test mode branch is used to filter out fixed failure cells with short circuit failure type and low-resistance outlier failure cells.

[0013] Optionally, it also includes:

[0014] The reference unit register records the configuration information of the reference unit and is used to control the selection of the working mode branch, the first test mode branch, and the second test mode branch.

[0015] Optionally, when the reference cell register is configured to 100, the operating mode branch is selected;

[0016] When the reference cell register is configured to 010, the first test mode branch is selected;

[0017] When the reference cell register is configured to 001, the second test mode branch is selected.

[0018] Optionally, the reference resistor value of the operating mode branch is configured as (R... ap +R p ) / 2+R MOS R ap R represents the resistance of the magnetic tunnel junction under test when it is magnetized in an antiparallel state. p R represents the resistance of the magnetic tunnel junction under test when it is magnetized to a parallel state. MOS This represents the equivalent resistance of the memory cell transistor connected in series with the magnetic tunnel junction under test.

[0019] Optionally, the reference resistor for the first test mode branch is implemented using a resistor with a fixed resistance value, configured as R. max R max >R ap ;

[0020] The reference resistor for the second test mode branch is implemented using a resistor with a fixed resistance value, which is configured as R. min R min <R p .

[0021] Optionally, if the resistance of the magnetic tunnel junction under test follows a normal distribution N(μ,σ^2), then the reference resistor of the first test mode branch is implemented using a resistor network, and the resistance value is configured as R. max R max =(R ap +N*σ(R ap )), N=6, 5, 4, 3, 2, 1;

[0022] The reference resistor for the second test mode branch is implemented using a resistor network, and its resistance value is configured as R. min R min =(R p -N*σ(R p )), N=6, 5, 4, 3, 2, 1.

[0023] Optionally, if the resistance of the magnetic tunnel junction under test follows a normal distribution N(μ,σ^2), then the reference resistor of the first test mode branch is implemented using a resistor network, and the resistance value is configured as R. max R max =(R ap +N*σ(R ap )), N=6, 5, 4, 3, 2, 1;

[0024] The reference resistor for the second test mode branch is implemented using a resistor network, and its resistance value is configured as R. min R min =(R ap -N*σ(R ap )), N=6, 5, 4, 3, 2, 1.

[0025] Secondly, the present invention provides a method for screening failed cells in an MRAM chip, comprising:

[0026] Configure the reference unit register to 010, and select the first test mode branch;

[0027] Perform the following operations on each memory cell under test in sequence: first, magnetize the memory cell under test to a parallel state, then read the memory cell under test. If the reading result is 0, the memory cell under test is normal. If the reading result is 1, the memory cell under test is faulty. The fault type is open circuit and high impedance state outlier fault cell.

[0028] Configure the reference unit register to 001, and enable the second test mode branch selection;

[0029] Perform the following operations on each memory cell under test in sequence: first, magnetize the memory cell under test to an antiparallel state, and then read the memory cell under test. If the reading result is 1, the memory cell under test is normal. If the reading result is 0, the memory cell under test is faulty. The fault type is short circuit and low resistance outlier fault cell.

[0030] Thirdly, the present invention provides a method for screening failed cells in an MRAM chip, comprising:

[0031] Configure the reference unit register to 010, and select the first test mode branch;

[0032] Perform the following operations on each memory cell under test in sequence: first, magnetize the memory cell under test to the antiparallel state, then read the memory cell under test. If the reading result is 1, the memory cell under test is faulty, and the fault type is open circuit and high impedance state outlier fault cell.

[0033] Configure the reference unit register to 001, and enable the second test mode branch selection;

[0034] Perform the following operations on each memory cell under test in sequence: first, magnetize the memory cell under test to a parallel state, then read the memory cell under test. If the reading result is 0, the memory cell under test is faulty, and the fault type is short circuit and low resistance state outlier fault cell.

[0035] Fourthly, the present invention provides a method for screening failed cells in an MRAM chip, comprising:

[0036] The magnetic tunnel junctions of the MRAM chip are all magnetized to an antiparallel state;

[0037] Configure the reference unit register to 010, and select the first test mode branch;

[0038] Read each memory cell under test sequentially. If the reading result is 0, the memory cell under test is normal. If the reading result is 1, the memory cell under test is faulty. The fault type is open circuit and high impedance outlier fault cell.

[0039] Configure the reference unit register to 001, and enable the second test mode branch selection;

[0040] Each memory cell under test is read sequentially. If the reading result is 1, the memory cell under test is normal. If the reading result is 0, the memory cell under test is faulty. The fault type is short circuit and low resistance outlier failure cell.

[0041] The MRAM chip data readout circuit provided by this invention includes three selectable reference resistor branches in the reference cell, including a working mode branch, a first test mode branch, and a second test mode branch, to achieve rapid screening of fixed-failure memory cells and outlier memory cells. The reference resistor R in the first test mode branch... max Greater than R ap Used to screen for open-circuit fixed failure cells and high-resistance outlier cells with large resistance values; the reference resistor R of the second test mode branch. min Less than R p, or R min Less than R ap It is related to the initial magnetization state of the magnetic tunnel junction under test, and is used to screen for short-circuited fixed failure elements and low-resistance outlier elements with small resistance values. Attached Figure Description

[0042] Figure 1 This is a schematic diagram of the data reading circuit of an MRAM chip according to an embodiment of the present invention;

[0043] Figure 2 This is a schematic diagram of the data reading circuit of an MRAM chip according to another embodiment of the present invention. Detailed Implementation

[0044] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0045] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate for the embodiments of this application described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0046] In this application, the terms "upper," "lower," "left," "right," "front," "rear," "top," "bottom," "inner," "outer," "middle," "vertical," "horizontal," "lateral," and "longitudinal" indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. These terms are primarily for the purpose of better describing this application and its embodiments, and are not intended to limit the indicated device, element, or component to having a specific orientation, or to be constructed and operated in a specific orientation.

[0047] Furthermore, in addition to indicating location or positional relationship, some of the aforementioned terms may also have other meanings. For example, the term "above" may also be used in some cases to indicate a certain dependency or connection relationship. Those skilled in the art can understand the specific meaning of these terms in this application based on the specific circumstances.

[0048] Furthermore, the terms "installation," "setup," "equipped with," "connection," "linking," and "socketing" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral structure; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium, or an internal connection between two devices, components, or parts. Those skilled in the art can understand the specific meaning of these terms in this application based on the specific circumstances.

[0049] The following detailed description of some embodiments of the present invention is provided in conjunction with the accompanying drawings. Unless otherwise specified, the following embodiments and features can be combined with each other.

[0050] One embodiment of the present invention provides a data readout circuit for an MRAM chip, such as... Figure 1 As shown, the circuit includes: a memory cell under test 11, a first gating transistor M1, a reference cell 12, a second gating transistor M2, and a sense amplifier SA, wherein,

[0051] The memory cell under test 11 includes a magnetic tunnel junction MTJ under test and a memory cell transistor connected in series. The gate of the transistor is input with a control signal CSL, the source is connected to the MTJ, and the drain is connected to the source of M1.

[0052] The gate of the first selection transistor M1 is connected to the clamping voltage Vclamp, and the drain is connected to the read voltage VDD. When M1 is turned on, the transistor of the memory cell is turned on, and a voltage is generated at the drain of M1. This voltage can reflect the resistance of the magnetic tunnel junction MTJ under test.

[0053] Reference unit 12 has three selectable reference resistor branches, including a working mode branch ①, a first test mode branch ②, and a second test mode branch ③. Each branch includes a reference resistor and a transistor connected in series. The transistor is used to control whether the reference resistor branch is selected, such as... Figure 1 As shown, the three branches have the same structure. The gates of the series-connected transistors are respectively input to control signals CSL_1, CSL_2, and CSL_3. The source is connected to a reference resistor, and the drain is connected to the source of M2. The reference resistor value of the operating mode branch is configured as R. ref R ref =(R ap +R p ) / 2+R MOSThe reference resistor value for the first test mode branch is configured as R. max R max Greater than R ap The reference resistor value for the second test mode branch is configured as R. min R min Less than R p Or, R min Less than R ap R min It is related to the initial magnetization state of the magnetic tunnel junction under test, R ap R represents the resistance of the magnetic tunnel junction under test when it is magnetized in an antiparallel state. p R represents the resistance of the magnetic tunnel junction under test when it is magnetized to a parallel state. MOS This represents the equivalent resistance of the memory cell transistor connected in series in the magnetic tunnel junction under test.

[0054] The gate of the second gating transistor M2 is connected to the reference voltage V. ref With the drain connected to the read voltage VDD, M2 is turned on, and a reference resistor branch is turned on, generating a comparison voltage at the drain of M2.

[0055] The sense amplifier SA has two input terminals, which are connected to the drain of the first gating transistor M1 and the drain of the second gating transistor M2, respectively. By comparing the voltages at the two input terminals, it can be determined whether the memory cell is in a low-impedance state or a high-impedance state. In this embodiment, the sense amplifier is a voltage-type amplifier.

[0056] Furthermore, in the above circuit structure, a reference unit register can be set up to record the configuration information of the reference unit 12, which is used to control the selection of one of the three reference resistor branches of the reference unit. That is, the gates of the series-connected transistors are respectively input with control signals CSL_1, CSL_2, and CSL_3, and these control signals can be obtained by configuring the reference unit register.

[0057] Optionally, when the reference cell register is configured to 100, the operating mode branch ① is selected to read the data of the memory cell under test;

[0058] When the reference cell register is configured to 010, the first test mode branch ② is selected to filter out fixed failure cells with open circuit failure type and high impedance outlier failure cells.

[0059] When the reference cell register is configured to 001, the second test mode branch ③ is selected to filter out fixed failure cells with short circuit failure type and low resistance outlier failure cells.

[0060] refer to Figure 1 The reference resistor for branch ② in the first test mode is a resistor with a fixed resistance value, which is configured as R.max R max >R ap ;

[0061] The reference resistor for branch ③ in the second test mode is implemented using a resistor with a fixed resistance value, which is configured as R. min R min <R p .

[0062] For example, the R of an MRAM memory cell p The static resistance is between 3000-3500Ω, R ap The static resistance is between 8000-9000Ω, R max The selectable resistance value is 10000Ω, R min The available resistance value is 500Ω.

[0063] In practical circuits, since the resistance value of a single fixed resistor follows N(μ, σ^2), if each fixed resistor is composed of a series-parallel network of n resistors with the same distribution, when n is large, its standardized variable approximately follows N(μ, σ^2 / n), meaning the resistance distribution after series-parallel connection is more convergent. Current process monitoring has proven that the MTJ series-parallel network has very good convergence characteristics; even if one resistor is abnormal, its impact on the total resistance is very limited. It is very suitable for outlier memory cell detection; therefore, as an implementation method, R... min and R max The target resistance value can be achieved by connecting n*m resistors in series and parallel.

[0064] refer to Figure 2 If the resistance of the magnetic tunnel junction under test follows a normal distribution N(μ,σ^2), then the reference resistor of the first test mode branch is implemented using a resistor network, and the resistance value is configured as R. max R max =(R ap +N*σ(R ap N = 6, 5, 4, 3, 2, 1; the reference resistor for the second test mode branch is implemented using a resistor network, and the resistance value is configured as R. min R min =(R p -N*σ(R p )), N=6, 5, 4, 3, 2, 1.

[0065] For example, the R of an MRAM memory cell p The static resistance is between 3000-3500Ω, R ap The static resistance is between 8000-9000Ω, σR p ≈200Ω,σR ap ≈500Ω,

[0066] Rmax =R ap +6σ(R ap )≈11000-12000Ω, which can be formed by connecting m1*n1 antiparallel MTJs in series and then in parallel to form R. max m1 = 26, n1 = 20;

[0067] R min =R p -6σ(R p )≈1800-2300Ω, which can be achieved by connecting m2*n2 antiparallel MTJs in series and then in parallel to form R. min m2 = 10, n2 = 25.

[0068] Of course, it should be noted that there are other configuration methods for the reference resistors of the first test mode branch and the second test mode branch. As one implementation method, if the resistance of the magnetic tunnel junction under test follows a normal distribution N(μ,σ^2), then the reference resistor of the first test mode branch is implemented using a resistor network, and the resistance value is configured as R. max R max =(R ap +N*σ(R ap N = 6, 5, 4, 3, 2, 1; the reference resistor for the second test mode branch is implemented using a resistor network, and the resistance value is configured as R. min R min =(R ap -N*σ(R ap )), N=6, 5, 4, 3, 2, 1.

[0069] As can be seen, the main difference lies in R. min The resistance configuration, for example, in this configuration, R max =R ap +5σ(R ap )≈1.3*R ap R can be formed by connecting m1*n1 MTJs in series and then in parallel. max m1 = 26, n1 = 20. R min =R ap -5σ(R ap )≈0.7*R ap R can be formed by connecting m²*n² MTJs in series and then in parallel. min m2 = 14, n2 = 20.

[0070] Corresponding to the two configuration methods mentioned above, since the reference resistor value R min The configuration methods differ, and the testing methods for screening failed units using this circuit also differ slightly, which will be introduced in detail later.

[0071] The data readout circuit for the MRAM chip provided in this embodiment of the invention includes three selectable reference resistor branches in the reference cell, including a working mode branch, a first test mode branch, and a second test mode branch, to achieve rapid screening of fixed-failure memory cells and outlier memory cells. The reference resistor R of the first test mode branch... max Greater than R ap Used to screen for open-circuit fixed failure cells and high-resistance outlier cells with large resistance values; the reference resistor R of the second test mode branch. min Less than R p , or R min Less than R ap The initial magnetization state of the magnetic tunnel junction under test is related to the initial magnetization state of the junction. This is used to screen for fixed failure cells with short circuits and outliers with low resistance values. Furthermore, the reference resistor uses a series-parallel MTJ structure. Even with process fluctuations, such as uneven thin-film deposition thickness or MTJ CD size, resulting in individual resistance anomalies, the overall resistance will not be significantly affected. Even under overall process fluctuations, such as when the CD of the actual device fabricates shifts by a certain range, it can still be used.

[0072] On the other hand, by applying the data reading circuit of the MRAM chip provided in the above embodiment, the faulty units of the MRAM chip can be screened. Several optional implementation methods are listed below.

[0073] Test Method 1

[0074] Follow these steps to screen for faulty cells in the MRAM chip:

[0075] 1. Configure the reference cell register to 010, and select the first test mode branch ②. In this mode, perform the following operations on each memory cell under test in sequence: first magnetize the memory cell under test to the parallel state, and then read the memory cell under test. If the reading result is 0, the memory cell under test is normal. If the reading result is 1, the memory cell under test is faulty. The fault type is open circuit and high impedance state outlier fault cell.

[0076] 2. Configure the reference cell register to 001 and select the second test mode branch ③. In this mode, perform the following operations on each memory cell under test in sequence: first, magnetize the memory cell under test to the antiparallel state, and then read the memory cell under test. If the reading result is 1, the memory cell under test is normal. If the reading result is 0, the memory cell under test is faulty. The fault type is short circuit and low resistance state outlier fault cell.

[0077] In the above test method, when the memory cell under test writes R... p (0) state, using R max When reading data, because R max The large resistance, R max >Rap >R p Therefore, under normal circumstances, all reads are 0, and all R values ​​can be correctly identified. p If a faulty cell appears in the current state of the memory cell under test, the reading will be 1, indicating that the resistance of the memory cell under test is greater than R. max If the memory cell under test is open-circuited and in a high-impedance state, it is a stray failure cell. When the memory cell under test writes R... ap (1) state, because R min The small resistance, R min <R p <R ap It can correctly distinguish all R ap The memory cell under test is in a normal state, so under normal circumstances, it reads 1. If a faulty cell occurs, it reads 0, indicating that the resistance of the memory cell under test is less than R. min If the memory cell under test is short-circuited and in a low-resistance state, then it is a stray failure cell.

[0078] Test Method Two

[0079] Follow these steps to screen for faulty cells in the MRAM chip:

[0080] 1. Configure the reference cell register to 010, and select the first test mode branch ②. In this mode, perform the following operations on each memory cell under test in sequence: first magnetize the memory cell under test to the antiparallel state, and then read the memory cell under test. If the reading result is 1, the memory cell under test is faulty. The fault type is open circuit and high impedance state outlier fault cell.

[0081] 2. Configure the reference cell register to 001 and select the second test mode branch ③. In this mode, perform the following operations on each memory cell under test in sequence: first, magnetize the memory cell under test to a parallel state, and then read the memory cell under test. If the reading result is 0, the memory cell under test is faulty. The fault type is short circuit and low resistance state outlier fault cell.

[0082] In the above test method, when the memory cell under test is written to the Rap(1) state, because R max The large resistance, R max >R ap >R p Therefore, R will be ap If a memory cell in the test state is read as 0, and a failed cell is read as 1, then the memory cell under test has failed. The failure type is open circuit or high-impedance outlier failure. When the memory cell under test is written to R... p (0) state, because R min The small resistance, R min <R p <R ap Therefore, R will be pIf a storage cell in the current state is read as 1, and a failed cell is read as 0, then the storage cell under test is failed. The failure type is short circuit and low-resistance outlier failure cell.

[0083] Test Method 3

[0084] Follow these steps to screen for faulty cells in the MRAM chip:

[0085] 1. Magnetize all magnetic tunnel junctions of the MRAM chip to an antiparallel state; in this embodiment, since all MTJs are initialized to the AP state, there is no need to write to the P state, so R... min It can be configured as R min =R ap -5σ(R ap )≈0.7*R ap .

[0086] 2. Configure the reference unit register to 010 and select the first test mode branch ②; read each memory cell under test in sequence. If the reading result is 0, the memory cell under test is normal. If the reading result is 1, the memory cell under test is faulty. The fault type is open circuit and high impedance outlier fault cell.

[0087] 3. Configure the reference unit register to 001 and select the second test mode branch ③; read each memory cell under test in sequence. If the reading result is 1, the memory cell under test is normal. If the reading result is 0, the memory cell under test is faulty. The fault type is short circuit and low resistance state outlier fault cell.

[0088] In the above testing method, data is read using the first test mode branch, because R max The large resistance, R max >R ap , will R ap If a storage cell in the open circuit state is read as 0, and a faulty cell appears at this time, it is a faulty cell of the open circuit and high impedance outlier type. Data is read using the second test mode branch, because R... min The small resistance, R min <R ap , will R ap If a storage cell in a certain state is read as 1, and a failed cell appears at this time, it is a failed cell with the failure type of short circuit and low resistance state outlier.

[0089] As can be seen from the test methods listed above,

[0090] In the first test mode, branch selection is enabled because R... max With a high resistance, regardless of whether the data written to the memory cell under test is 0 or 1, the data read should be 0. If a 1 is read, it means that the memory cell under test has failed, and the failure type is open circuit and high resistance outlier failure cell.

[0091] The second test mode branch selection, because R min With a small resistance, regardless of whether the value written to the memory cell under test is 0 or 1, the read data should be 1. If 0 is read, it means that the memory cell under test has failed, and the failure type is short circuit and low resistance outlier failure cell.

[0092] Subsequently, after locating the failed storage unit using the above testing methods, it can be screened out or marked and then repaired with redundant modules.

[0093] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A data reading circuit for an MRAM chip, characterized in that, include: The memory cell under test includes a magnetic tunnel junction under test and a memory cell transistor connected in series; The first gating transistor is connected to the memory cell under test; The reference unit has three selectable reference resistor branches: a working mode branch, a first test mode branch, and a second test mode branch. The working mode branch is used to read data from the memory cell under test. The first test mode branch is used to filter out fixed failure cells with open circuit failure type and high-resistance outlier failure cells. The second test mode branch is used to filter out fixed failure cells with short circuit failure type and low-resistance outlier failure cells. Each reference resistor branch includes a reference resistor and a transistor connected in series. The transistor is used to control whether the reference resistor branch it belongs to is selected. The reference resistor of the first test mode branch is implemented using a resistor with a fixed resistance value configured as R. max R max >R ap The reference resistor for the second test mode branch is implemented using a resistor with a fixed resistance value, configured as R. min R min <R p R ap R represents the resistance of the magnetic tunnel junction under test when it is magnetized in an antiparallel state. p This represents the resistance of the magnetic tunnel junction under test when it is magnetized into a parallel state. The second gating transistor is connected to the reference cell; The readout amplifier has two input terminals connected to the first gating transistor and the second gating transistor, respectively.

2. A data reading circuit for an MRAM chip, characterized in that, include: The memory cell under test includes a magnetic tunnel junction under test and a memory cell transistor connected in series; The first gating transistor is connected to the memory cell under test; The reference unit has three selectable reference resistor branches: a working mode branch, a first test mode branch, and a second test mode branch. The working mode branch is used to read data from the memory cell under test. The first test mode branch is used to filter out fixed failure cells with open circuit failure type and high-resistance outlier failure cells. The second test mode branch is used to filter out fixed failure cells with short circuit failure type and low-resistance outlier failure cells. Each reference resistor branch includes a reference resistor and a transistor connected in series. The transistor is used to control whether the reference resistor branch it belongs to is selected. If the resistance of the magnetic tunnel junction under test follows a normal distribution N(μ, ^2), then the reference resistor of the first test mode branch is implemented using a resistor network, and the resistance value is configured as R. max R max = (R ap +N σ(R ap N=6, 5, 4, 3, 2, 1; the reference resistor for the second test mode branch is implemented using a resistor network, and the resistance value is configured as R. min R min =(R p -N σ(R p )), N=6, 5, 4, 3, 2, 1, R ap R represents the resistance of the magnetic tunnel junction under test when it is magnetized in an antiparallel state. p This represents the resistance of the magnetic tunnel junction under test when it is magnetized into a parallel state. The second gating transistor is connected to the reference cell; The readout amplifier has two input terminals connected to the first gating transistor and the second gating transistor, respectively.

3. A data reading circuit for an MRAM chip, characterized in that, include: The memory cell under test includes a magnetic tunnel junction under test and a memory cell transistor connected in series; The first gating transistor is connected to the memory cell under test; The reference unit has three selectable reference resistor branches: a working mode branch, a first test mode branch, and a second test mode branch. The working mode branch is used to read data from the memory cell under test. The first test mode branch is used to filter out fixed failure cells with open circuit failure type and high-resistance outlier failure cells. The second test mode branch is used to filter out fixed failure cells with short circuit failure type and low-resistance outlier failure cells. Each reference resistor branch includes a reference resistor and a transistor connected in series. The transistor is used to control whether the reference resistor branch it belongs to is selected. If the resistance of the magnetic tunnel junction under test follows a normal distribution N(μ, ^2), then the reference resistor of the first test mode branch is implemented using a resistor network, and the resistance value is configured as R. max R max = (R ap +N σ(R ap N=6, 5, 4, 3, 2, 1; the reference resistor for the second test mode branch is implemented using a resistor network, and the resistance value is configured as R. min R min =(R ap -N σ(R ap )), N=6, 5, 4, 3, 2, 1, R ap R represents the resistance of the magnetic tunnel junction under test when it is magnetized in an antiparallel state. p This represents the resistance of the magnetic tunnel junction under test when it is magnetized into a parallel state. The second gating transistor is connected to the reference cell; The readout amplifier has two input terminals connected to the first gating transistor and the second gating transistor, respectively.

4. The data reading circuit for the MRAM chip according to any one of claims 1 to 3, characterized in that, Also includes: The reference unit register records the configuration information of the reference unit and is used to control the selection of the working mode branch, the first test mode branch, and the second test mode branch.

5. The data reading circuit for the MRAM chip according to claim 4, characterized in that, When the reference cell register is configured to 100, the operating mode branch is selected; When the reference cell register is configured to 010, the first test mode branch is selected; When the reference cell register is configured to 001, the second test mode branch is selected.

6. The data reading circuit for the MRAM chip according to any one of claims 1 to 3, characterized in that, The reference resistor value of the operating mode branch is configured as (R ap +R p ) / 2 +R MOS R ap R represents the resistance of the magnetic tunnel junction under test when it is magnetized in an antiparallel state. p R represents the resistance of the magnetic tunnel junction under test when it is magnetized to a parallel state. MOS This represents the equivalent resistance of the memory cell transistor connected in series with the magnetic tunnel junction under test.

7. A method for screening failed cells in an MRAM chip, characterized in that, The data readout circuit of the MRAM chip as described in claim 1 or 2 is used to implement this, including: Configure the reference unit register to 010, and select the first test mode branch; Perform the following operations on each memory cell under test in sequence: first, magnetize the memory cell under test to a parallel state, then read the memory cell under test. If the reading result is 0, the memory cell under test is normal. If the reading result is 1, the memory cell under test is faulty. The fault type is open circuit and high impedance state outlier fault cell. Configure the reference unit register to 001, and enable the second test mode branch selection; Perform the following operations on each memory cell under test in sequence: first, magnetize the memory cell under test to an antiparallel state, and then read the memory cell under test. If the reading result is 1, the memory cell under test is normal. If the reading result is 0, the memory cell under test is faulty. The fault type is short circuit and low resistance outlier fault cell.

8. A method for screening failed cells in an MRAM chip, characterized in that, The data readout circuit of the MRAM chip as described in claim 1 or 2 is used to implement this, including: Configure the reference unit register to 010, and select the first test mode branch; Perform the following operations on each memory cell under test in sequence: first, magnetize the memory cell under test to the antiparallel state, then read the memory cell under test. If the reading result is 1, the memory cell under test is faulty, and the fault type is open circuit and high impedance state outlier fault cell. Configure the reference unit register to 001, and enable the second test mode branch selection; Perform the following operations on each memory cell under test in sequence: first, magnetize the memory cell under test to a parallel state, then read the memory cell under test. If the reading result is 0, the memory cell under test is faulty, and the fault type is short circuit and low resistance state outlier fault cell.

9. A method for screening failed cells in an MRAM chip, characterized in that, The data readout circuit of the MRAM chip as described in claim 3 is used to implement this, including: The magnetic tunnel junctions of the MRAM chip are all magnetized to an antiparallel state; Configure the reference unit register to 010, and select the first test mode branch; Read each memory cell under test sequentially. If the reading result is 0, the memory cell under test is normal. If the reading result is 1, the memory cell under test is faulty. The fault type is open circuit and high impedance outlier fault cell. Configure the reference unit register to 001, and enable the second test mode branch selection; Each memory cell under test is read sequentially. If the reading result is 1, the memory cell under test is normal. If the reading result is 0, the memory cell under test is faulty. The fault type is short circuit and low resistance outlier failure cell.

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