Method for adjusting etching uniformity and semiconductor processing equipment

Abstract

The embodiment of the present application provides a kind of etching uniformity adjustment method, it is related to semiconductor process technical field, the etching uniformity adjustment method includes: whether the inner circle etching uniformity parameter of wafer after etching processing is greater than first preset value, in the case where inner circle etching uniformity parameter is greater than first preset value, the relative position of wafer relative to upper electrode shielding piece is changed in horizontal direction, so that inner circle etching uniformity parameter is less than or equal to first preset value;Wafer is etched and is processed, to determine whether the inner circle circumferential etching rate trend of wafer and the outer circle circumferential etching rate trend of wafer are same, in the case where inner circle circumferential etching rate trend and outer circle circumferential etching rate trend are different, the inclination of upper electrode shielding piece relative to wafer is adjusted, so that inner circle circumferential etching rate trend and outer circle circumferential etching rate trend are same.

Description

Technical Field

[0001] This application relates to the field of semiconductor process technology, and in particular to a method for adjusting etching uniformity and semiconductor process equipment. Background Technology

[0002] In the semiconductor technology field, plasma etching is a crucial step. As technology nodes extend to 65 nanometers and more advanced processes according to Moore's Law, the impact on yield related to wafer edges and sides becomes particularly prominent. The interactions between thin film deposition, photolithography, etching, and chemical mechanical polishing can cause unstable film buildup at the wafer edges (also known as the wafer edge), thus affecting subsequent processes. Therefore, edge etching is necessary to remove the film buildup at the wafer edges, reducing defects and yield losses during production. The uniformity of edge etching is a key concern in this technology. Summary of the Invention

[0003] This application provides a method for adjusting etching uniformity and a semiconductor process apparatus to solve the problem of how to improve the uniformity of crystal edge etching.

[0004] In a first aspect, embodiments of this application provide a method for adjusting etching uniformity.

[0005] The etching uniformity adjustment method provided in this application embodiment is applied to semiconductor process equipment used to perform a crystal edge etching process. The etching uniformity adjustment method includes:

[0006] Determine whether the inner ring etching uniformity parameter of the etched wafer is greater than a first preset value. If the inner ring etching uniformity parameter is greater than the first preset value, change the relative position of the wafer with respect to the upper electrode shield in the horizontal direction so that the inner ring etching uniformity parameter is less than or equal to the first preset value.

[0007] The wafer is etched to determine whether the circumferential etching rate trend of the inner ring of the wafer is the same as that of the outer ring of the wafer. If the circumferential etching rate trends of the inner ring and the outer ring are different, the tilt angle of the upper electrode shield relative to the wafer is adjusted so that the circumferential etching rate trends of the inner ring and the outer ring are the same.

[0008] Optionally, changing the relative position of the wafer with respect to the upper electrode shield along the horizontal direction to make the inner ring etching uniformity parameter less than or equal to the first preset value includes:

[0009] Based on the inner ring etching rate of the wafer, a first relative offset parameter of the wafer relative to the upper electrode shielding member in the horizontal direction is determined;

[0010] Based on the first relative offset parameter, the wafer is translated horizontally, and / or the upper electrode shield is translated horizontally, so that the inner ring etching uniformity parameter is less than or equal to the first preset value.

[0011] Optionally, determining the first relative offset parameter of the wafer relative to the upper electrode shielding member in the horizontal direction based on the inner ring etching rate of the wafer includes:

[0012] In the etching area of ​​the wafer, a plurality of first reference points are selected along the circumferential direction of the inner circle of the wafer, and the first average etching rate of the plurality of first reference points is determined.

[0013] In the direction of the line connecting the center of the inner circle and each of the first reference points, a second reference point equal to the first average etching rate is determined.

[0014] The first fitted circle is obtained by fitting multiple second reference points;

[0015] A first center position deviation parameter is determined between the center of the inner circle and the center of the first fitted circle, and a first relative offset parameter is determined based on the first center position deviation parameter.

[0016] Optionally, after adjusting the tilt angle of the upper electrode shield relative to the wafer to make the circumferential etching rate trend of the inner ring the same as that of the outer ring, the method for adjusting the etching uniformity further includes:

[0017] The wafer is etched.

[0018] Determine whether the inner ring etching uniformity parameter of the wafer is greater than a second preset value, and determine whether the outer ring etching uniformity parameter of the wafer is greater than a third preset value.

[0019] If the inner ring etching uniformity parameter is greater than the second preset value, and / or the outer ring etching uniformity parameter is greater than the third preset value, the relative position of the wafer with respect to the upper electrode shield in the horizontal direction is changed so that the inner ring etching uniformity parameter is less than or equal to the second preset value, and the outer ring etching uniformity parameter is less than or equal to the third preset value.

[0020] Optionally, changing the horizontal relative position of the wafer to the upper electrode shield, so that the inner ring etching uniformity parameter is less than or equal to the second preset value and the outer ring etching uniformity parameter is less than or equal to the third preset value, includes:

[0021] Determine the etching uniformity deviation of the inner ring etching uniformity parameter relative to the second preset value, and the etching uniformity deviation of the outer ring etching uniformity parameter relative to the third preset value;

[0022] Using the larger etching uniformity deviation between the inner and outer rings of the wafer as an offset reference, a second relative offset parameter of the wafer relative to the wafer in the horizontal direction is determined.

[0023] Based on the second relative offset parameter, the wafer is translated horizontally, and / or the upper electrode shield is translated horizontally, so that the inner ring etching uniformity parameter is less than or equal to the second preset value, and the outer ring etching uniformity parameter is less than or equal to the third preset value.

[0024] Optionally, determining the second relative offset parameter of the wafer along the horizontal direction relative to the wafer, using the larger of the etching uniformity deviations of the inner and outer rings of the wafer as an offset reference, includes:

[0025] The inner circle and the outer circle with the larger corresponding etching uniformity deviation are used as the reference circle;

[0026] In the etched area of ​​the wafer, a plurality of third reference points are selected along the circumferential direction of the reference circle, and the second average etching rate of the plurality of third reference points is determined.

[0027] A fourth reference point, equal to the second average etching rate, is determined along the line connecting the center of the reference circle and each of the third reference points.

[0028] The multiple fourth reference points are fitted to obtain a second fitted circle;

[0029] A second center position deviation parameter is determined between the center of the reference circle and the center of the second fitted circle, and a second relative offset parameter is determined based on the second center position deviation parameter.

[0030] Optionally, adjusting the tilt angle of the upper electrode shield relative to the wafer to make the circumferential etching rate trend of the inner ring the same as that of the outer ring includes:

[0031] Based on the circumferential etching rate trend of the inner ring and the circumferential etching rate trend of the outer ring, a third relative offset parameter along the vertical direction is determined for multiple fifth reference points on the upper electrode shield.

[0032] The distance between the fifth reference point of the upper electrode shield and the wafer is adjusted based on the third relative offset parameter to adjust the tilt angle of the upper electrode shield relative to the wafer so that the circumferential etching rate trend of the inner ring is the same as that of the outer ring.

[0033] Optionally, the step of determining the third relative offset parameter in the vertical direction of the multiple fifth reference points on the upper electrode shielding member based on the inner circumferential etching rate trend and the outer circumferential etching rate trend includes:

[0034] Based on the deviation between the inner circumferential etching rate trend and the outer circumferential etching rate trend, and the displacement-etching rate ratio parameter, the third relative offset parameter of each of the fifth reference points along the vertical direction is determined.

[0035] Optionally, the third relative offset parameter is determined according to the formula: (ER2max-ER2min) / (2V); where ER2max is the maximum etching rate of the outer ring, ER2min is the minimum etching rate of the outer ring, and V is 18 to 30 angstroms per minute.

[0036] Optionally, one of the plurality of fifth reference points is used as the target reference point. The orthographic projection of the target reference point on the wafer coincides with the sixth reference point. The seventh reference point on the wafer is symmetrically distributed with the sixth reference point along the center of the wafer. Increasing the distance between the target reference point and the wafer reduces the etching rate of the sixth reference point on the wafer and increases the etching rate of the seventh reference point on the wafer.

[0037] Optionally, before determining whether the inner ring etching uniformity parameter of the etched wafer is greater than a first preset value, the etching uniformity adjustment method further includes:

[0038] The wafer is etched.

[0039] Determine whether the inner ring etching uniformity parameter of the wafer is greater than a fourth preset value, determine whether the outer ring etching uniformity parameter of the wafer is greater than a fifth preset value, and determine whether the inner ring circumferential etching rate trend and the outer ring circumferential etching rate trend of the wafer are the same.

[0040] When the inner ring etching uniformity parameter of the wafer is greater than the fourth preset value, the outer ring etching uniformity parameter of the wafer is greater than the fifth preset value, and the circumferential etching rate trends of the inner and outer rings of the wafer are the same, the relative position of the wafer with respect to the upper electrode shielding member in the horizontal direction is changed so that the inner ring etching uniformity parameter is less than or equal to the fourth preset value, and / or the outer ring etching uniformity parameter is less than or equal to the fifth preset value.

[0041] The wafer is then etched again.

[0042] Secondly, embodiments of this application provide a semiconductor process apparatus.

[0043] The semiconductor process equipment provided in this application includes: a chamber body, an upper electrode assembly, and a lower electrode assembly. The lower electrode assembly has a support surface for supporting a wafer. The upper electrode assembly includes an upper electrode shield disposed inside the chamber body, and the upper electrode shield is disposed opposite to the support surface. Any etching uniformity adjustment method provided in this application is executed in the semiconductor process equipment.

[0044] Optionally, the semiconductor process equipment further includes: a leveling component connected to the upper electrode assembly for adjusting the tilt angle of the upper electrode shielding member to adjust the tilt angle of the upper electrode shielding member relative to the wafer supported on the lower electrode assembly; a translation component and / or a transmission device connected to the upper electrode assembly for driving the upper electrode shielding member to translate horizontally relative to the wafer; and the transmission device for moving the wafer horizontally relative to the upper electrode shielding member.

[0045] The above-described technical solutions adopted in the embodiments of this application can achieve the following beneficial effects:

[0046] The etching uniformity adjustment method provided in this application embodiment can first improve the etching uniformity of the inner ring by changing the relative position of the wafer with respect to the upper electrode shield in the horizontal direction. Furthermore, by adjusting the tilt angle of the upper electrode shield relative to the wafer, the etching rate trends of the inner ring and the outer ring can be made the same, thereby improving the etching uniformity of the outer ring. Attached Figure Description

[0047] To more clearly illustrate the technical solutions in the embodiments or related technologies of this application, the drawings used in the description of the embodiments or related technologies will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0048] Figure 1 A schematic diagram of a semiconductor process apparatus provided in an embodiment of this application;

[0049] Figure 2 A top view of a semiconductor process apparatus provided in an embodiment of this application;

[0050] Figure 3 A schematic diagram of a first telescopic drive mechanism provided in an embodiment of this application;

[0051] Figure 4 A schematic diagram showing the distribution positions of a first displacement sensor and a second displacement sensor in a semiconductor process apparatus provided in an embodiment of this application;

[0052] Figure 5 A schematic diagram of a wafer provided for an embodiment of this application;

[0053] Figure 6 A flowchart illustrating a method for adjusting etching uniformity provided in this application embodiment;

[0054] Figure 7 A schematic diagram illustrating the principle of determining a first relative offset parameter as provided in an embodiment of this application;

[0055] Figure 8 A schematic diagram illustrating the positional relationship between a wafer and a second telescopic drive mechanism, provided for an embodiment of this application;

[0056] Figure 9 A flowchart of another method for adjusting etching uniformity provided in an embodiment of this application.

[0057] Explanation of reference numerals in the attached figures:

[0058] 100 - Semiconductor process equipment; 110 - Chamber body; 111 - Cavity; 112 - Cover; 120 - Upper electrode assembly; 121 - Upper electrode shield; 130 - Lower electrode assembly; 140 - Leveling assembly; 141 - Second telescopic drive mechanism; 142 - Second displacement sensor; 150 - Translation assembly; 151 - First telescopic drive mechanism; 1511 - First screw; 1512 - Connecting seat; 152 - First displacement sensor; 200 - Wafer; 210 - Edge circle; 220 - Projection circle; 230 - Inner circle; 231 - First reference point; 232 - Second reference point; 233 - First fitting circle; 240 - Outer circle. Detailed Implementation

[0059] To make the objectives, technical solutions, and advantages of this application clearer, the technical solutions of this application will be clearly and completely described below in conjunction with specific embodiments and corresponding drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. Based on the embodiments in this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0060] In the description of this application, it should be noted that, unless otherwise expressly specified and limited, the terms "installation," "connection," and "joining" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal communication between two components. Those skilled in the art can understand the specific meaning of the above terms in this application based on the specific circumstances.

[0061] Furthermore, although the terminology used in this application is selected from commonly known and used terms, some terms mentioned in this application specification may have been selected by the applicant at his or her own discretion, and their detailed meanings are explained in the relevant sections of this description.

[0062] Furthermore, this application is required to be understood not only through the actual terms used, but also through the meaning implied by each term.

[0063] The technical solutions provided by the various embodiments of this application are described in detail below with reference to the accompanying drawings.

[0064] This application provides a semiconductor process apparatus. (See reference...) Figures 1 to 5 The semiconductor process equipment 100 provided in this application embodiment may include: a chamber body 110, an upper electrode assembly 120, and a lower electrode assembly 130.

[0065] The lower electrode assembly 130 has a support surface for supporting the wafer 200. The upper electrode assembly 120 includes an upper electrode shield 121 disposed inside the chamber body 110. The upper electrode shield 121 is disposed opposite to the support surface.

[0066] It should be noted that due to the different plasma environments within the chamber body 110, the region outside the upper electrode shield 121 has a more abundant plasma, resulting in a faster etching rate for the area of ​​the wafer 200 corresponding to the region outside the upper electrode shield 121. The area covered by the upper electrode shield 121, closer to the center of the wafer 200, has less plasma, a slower etching rate, or even no etching at all. Therefore, the uniformity of edge etching can be adjusted by changing the relative position of the wafer 200 with respect to the upper electrode shield 121 in the horizontal direction, and by adjusting the tilt angle of the upper electrode shield 121 relative to the wafer 200.

[0067] It should also be noted that, for example, when the etching trends of the inner and outer rings of the wafer are opposite, by changing the relative position of the wafer with respect to the upper electrode shield in the horizontal direction, the etching rate uniformity of one of the inner or outer rings is preferentially adjusted, which will inevitably make the uniformity of the other ring worse.

[0068] Therefore, it is evident that simply changing the horizontal relative position of the wafer 200 with respect to the upper electrode shield 121 is insufficient to ensure that the edge etching uniformity meets process requirements. Consequently, in the embodiments of this application, the edge etching uniformity is adjusted by combining changes to the horizontal relative position of the wafer 200 with respect to the upper electrode shield 121 and adjusting the tilt angle of the upper electrode shield 121 relative to the wafer 200.

[0069] For example, the upper electrode shield 121 can be a dielectric plate or a ceramic window. An upper electrode extension ring 122 can be provided around the upper electrode shield 121. In other words, the upper electrode extension ring 122 is sleeved on the upper electrode shield 121, and the upper electrode extension ring 122 can move synchronously with the upper electrode shield 121. The upper electrode extension ring 122 has different sizes. According to process requirements, an upper electrode extension ring 122 of appropriate size can be sleeved on the electrode shield 121 to control the etching distance between the upper and lower surfaces of the wafer 200.

[0070] In some embodiments, the semiconductor process equipment 100 further includes a leveling component 140 connected to the upper electrode assembly 120, used to adjust the tilt angle of the upper electrode shield 121 to adjust the tilt angle of the upper electrode shield 121 relative to the wafer 200 supported on the lower electrode assembly 130. Thus, by adjusting the tilt angle of the upper electrode shield 121, the distance between each portion of the upper electrode shield 121 and its corresponding portion on the wafer 200 can be adjusted.

[0071] In some embodiments, the semiconductor process equipment 100 further includes a translation component 150 and / or a transfer device. The translation component 150 is connected to the upper electrode assembly 120 and is used to drive the upper electrode shielding member 121 to translate horizontally relative to the wafer 200. The transfer device is used to move the wafer 200 horizontally relative to the upper electrode shielding member 121. Exemplarily, the transfer device can be a robotic arm. Generally, the semiconductor process equipment 100 can be combined with a robotic arm to transfer the wafer 200, for example, by using a robotic arm to move the wafer 200 to the bearing surface of the lower electrode assembly 130 so that the semiconductor process equipment 100 can etch the wafer 200. After etching, the robotic arm can be used to remove the wafer 200. Therefore, in the embodiments of this application, a robotic arm for transferring the wafer 200 can be used to move the wafer 200 horizontally to change the relative position of the wafer 200 with respect to the upper electrode shielding member 121 in the horizontal direction.

[0072] For example, during the edge etching of wafer 200, the etching uniformity of outer ring 240 of wafer 200, the etching uniformity of inner ring 230 of wafer 200, and the circumferential etching rate trend of outer ring 240 and inner ring 230 can be adjusted by using translation component 150 to drive upper electrode shield 121 to translate relative to wafer in the horizontal direction, and using leveling component 140 to adjust the tilt angle of upper electrode shield 121 relative to wafer 200.

[0073] For example, combined Figure 5 In some embodiments, the diameter of wafer 200 is 300 mm, and the diameter of the edge circle 210 of wafer 200 is also 300 mm. The outer diameter of the upper electrode shield 121 of the upper electrode assembly 120 is 298.5 mm, and the projection of the outer circle of the upper electrode shield 121 onto wafer 200 is a projection circle 220, the diameter of which is 298.5 mm, and the distance between the projection circle 220 and the edge circle 210 is 0.75 mm. Those skilled in the art generally use a circle with a distance of 0.6 mm from the edge circle 210 as the outer circle 240, and a circle with a distance of 1.5 mm from the edge circle 210 as the inner circle 230. The inner circle 230 is located inside the projection circle 220, and the outer circle is located outside the projection circle 220.

[0074] It should be noted that if the dimensions of the wafer 200 and the upper electrode shield 121 change, those skilled in the art can redetermine the dimensions of the inner ring 230 and the outer ring 240 based on common knowledge in the art, which will not be elaborated here.

[0075] For example, refer to Figure 5 In some embodiments, eight directions can be selected, and 15 measurement points can be taken in each of the eight directions to detect the film thickness before and after wafer etching, so as to calculate the etching rate at each measurement point. For example, points with distances of 0.4 mm, 0.6 mm, 0.8 mm, 1.0 mm, 1.2 mm, 1.4 mm, 1.5 mm, 1.6 mm, 1.8 mm, 2.0 mm, 2.2 mm, 2.6 mm, 3.0 mm, 4.0 mm, and 10.0 mm from the edge circle 210 can be selected as measurement points in the eight directions, and the etching rate at each measurement point can be calculated.

[0076] The etching rate of the measurement point can be determined by the formula: ER=(S1-S2) / t; where ER is the etching rate of the measurement point, S1 is the thickness of the measurement point before etching, S2 is the thickness of the measurement point after etching, and t is the etching time.

[0077] Of course, in other embodiments, other numbers of directions can be selected according to actual needs, and other numbers of measurement points can be selected in each direction to calculate the etching rate of each measurement point. These will not be listed one by one here.

[0078] In the embodiments of this application, the inner ring etching uniformity parameter can be determined by the formula: (ER1max - ER1min) / (2ER1mean); where ER1max is the maximum etching rate of the inner ring, ER1min is the minimum etching rate of the inner ring, and ER1mean is the average etching rate of the inner ring. It should be noted that, referring to the example provided above, if the number of measurement points on the inner ring is 8, then ER1max is the etching rate of the point with the highest etching rate among the 8 measurement points, ER1min is the etching rate of the point with the lowest etching rate among the 8 measurement points, and ER1mean is the average etching rate of the 8 measurement points.

[0079] The etching uniformity parameter of the outer ring can be determined by the formula: (ER2max - ER2min) / (2ER2mean); where ER2max is the maximum etching rate of the outer ring, ER2min is the minimum etching rate of the outer ring, and ER2mean is the average etching rate of the outer ring. It should be noted that, referring to the example provided earlier, if the number of measurement points on the outer ring is 8, then ER2max is the etching rate of the point with the highest etching rate among the 8 measurement points, ER2min is the etching rate of the point with the lowest etching rate among the 8 measurement points, and ER2mean is the average etching rate of the 8 measurement points.

[0080] It should also be noted that the circumferential etching rate trend of the outer ring is used to represent the rate of etching along the circumferential direction of the outer ring. Combined with... Figure 5 For example, the etching rate trend of the outer circumferential ring can be: faster on the left and slower on the right. The etching rate trend of the inner circumferential ring can be: slower on the left and faster on the right.

[0081] When the circumferential etching rate trend of the outer ring is faster on the left and slower on the right, and the circumferential etching rate trend of the inner ring is slower on the left and faster on the right, it is generally referred to in the art as the etching rate trends of the inner and outer rings being different, or the etching rates of the inner and outer rings being opposite, or the inner and outer rings being "not concentric".

[0082] When the circumferential etching rate trend of the outer ring is faster on the left and slower on the right, and the circumferential etching rate trend of the inner ring is also faster on the left and slower on the right, it is generally said in the art that the etching rate trends of the inner and outer rings are the same, or that the inner and outer rings are "concentric".

[0083] It should be briefly explained here that, in the embodiments of this application, when the etching rate trends of the inner and outer rings are different, the etching rate trends of the inner and outer rings can be made substantially the same by adjusting the tilt angle of the upper electrode shield 121 relative to the wafer 200 supported by the lower electrode assembly 130. This solves the problem in related technologies where, when the etching trends of the inner and outer rings of the wafer are opposite, changing the relative horizontal position of the wafer with respect to the upper electrode shield to preferentially adjust the etching rate uniformity of one ring or the other inevitably results in poorer uniformity of the other.

[0084] To enable those skilled in the art to better understand the solutions provided in the embodiments of this application, a more detailed semiconductor process equipment is provided below, based on the semiconductor process equipment provided above.

[0085] refer to Figure 1 In some embodiments, the chamber body 110 may include a cavity 111 and a cover 112, with the cover 112 covering the cavity 111. The upper electrode assembly 120 may also include an adjustment frame 130, which is disposed above the cover 112. The leveling assembly 140 and the translation assembly 150 are respectively connected to the adjustment frame 123.

[0086] refer to Figure 2 and Figure 3 The translation component 150 may include at least two first telescopic drive mechanisms 151. Each first telescopic drive mechanism 151 is connected to the adjustment frame 123 and the cover 112 respectively. The first telescopic drive mechanism 151 is used to drive the part of the adjustment frame 123 connected to the first telescopic drive mechanism 151 to move horizontally, so as to drive the upper electrode assembly 120 to move horizontally. The telescopic directions of each first telescopic drive mechanism 151 are not parallel.

[0087] In some embodiments, the first telescopic drive mechanism 151 may include a first screw 1511 and a connecting seat 1512. The first screw 1511 is rotatably connected to the connecting seat 1512, the connecting seat 1512 is disposed on the cover 112, and the first screw 1511 is threadedly connected to the adjusting bracket 123. In some embodiments, the number of first telescopic drive mechanisms 151 is two, and the telescopic directions of the two first telescopic drive mechanisms 151 are perpendicular.

[0088] Thus, combined Figure 2 The upper electrode assembly 120 can be driven to move back and forth in the horizontal plane along with the adjustment frame 123 by rotating the first screw 1511, which is set in the front-back direction. The upper electrode assembly 120 can also be driven to move left and right in the horizontal plane along with the adjustment frame 123 by rotating the first screw 1511, which is set in the left-right direction.

[0089] refer to Figure 4 In some embodiments, the semiconductor process equipment may further include a plurality of first displacement sensors 152, each first displacement sensor 152 being used to detect the displacement of the adjustment frame 123 along the extension direction of the corresponding first extension drive mechanism 151.

[0090] Combination Figure 2 The leveling assembly 140 may include at least three second telescopic drive mechanisms 141, each of which is supported between the adjustment frame 123 and the cover 112. The second telescopic drive mechanism 141 is used to drive the portion of the adjustment frame 123 connected to the second telescopic drive mechanism 141 to move closer to or away from the cover 112, so as to adjust the tilt angle of the adjustment frame 123, thereby adjusting the tilt angle of the lower surface of the upper electrode assembly 120 relative to the wafer 200 supported on the lower electrode assembly 130.

[0091] refer to Figure 4 In some embodiments, the semiconductor process equipment 100 may further include a plurality of second displacement sensors 142, each second displacement sensor 142 being used to detect the displacement of the adjustment frame 123 along the extension direction of the corresponding second extension drive mechanism 141.

[0092] This application provides a method for adjusting etching uniformity, applicable to any of the semiconductor process equipment provided in this application, which is used to perform a die edge etching process. (Reference) Figure 6 The etching uniformity adjustment method provided in this application includes:

[0093] Step 310: Determine whether the inner ring etching uniformity parameter of the etched wafer is greater than the first preset value. If the inner ring etching uniformity parameter is greater than the first preset value, change the relative position of the wafer with respect to the upper electrode shield in the horizontal direction so that the inner ring etching uniformity parameter is less than or equal to the first preset value.

[0094] In the embodiments of this application, the wafer 200 can be etched first. Then, the etching rate of each measurement point on the inner ring 230 of the wafer 200 can be determined, and the inner ring etching uniformity parameter can be determined. Further, it can be determined whether the inner ring etching uniformity parameter of the etched wafer 200 is greater than a first preset value. If the inner ring etching uniformity parameter is greater than the first preset value, the relative position of the wafer 200 with respect to the upper electrode shield 121 in the horizontal direction is changed so that the inner ring etching uniformity parameter is less than or equal to the first preset value.

[0095] For example, combined Figure 5 In one embodiment, the etching rates at various measurement points on the inner ring 230 and outer ring 240 of wafer 200 are shown in the table below:

[0096] 40° 85° 130° 175° 220° 265° 310° 355° ER2 (A / min) 11467 12334 12911 11947 11031 10749 11078 11013 ER1 (A / min) 50 25 17 45 70 89 104 101

[0097] It should be noted that, to distinguish the etching rates of the inner and outer rings of the wafer, in the embodiments of this application, ER2 represents the etching rate of the outer ring of wafer 200, and ER1 represents the etching rate of the inner ring of wafer 200. Referring to the table above, for the outer ring 240 of the wafer, the ER is highest at 130° and lowest at 265°, with a uniformity of 9.3%. The ER map generally shows a faster ER in the 10-11 o'clock direction. For the inner ring 230 of wafer 200, the etching rate is highest at 310° and lowest at 130°. The ER map generally shows a faster ER in the 3-5 o'clock direction. The circumferential etching rate trend of the inner ring 230 of wafer 200 differs from that of the outer ring 240, and the inner ring etching uniformity parameter is 70.1%. Therefore, it is not possible to improve the etching uniformity of the inner and outer rings simultaneously simply by changing the relative position of the wafer 200 with respect to the upper electrode shield 121 in the horizontal direction.

[0098] For example, the first preset value can be 30% to 50%. Since the inner ring etching uniformity parameter is 70.1%, it can be concluded that the inner ring etching uniformity parameter is greater than the first preset value. Therefore, the inner ring etching uniformity parameter can be reduced to below the first preset value by changing the horizontal relative position of the wafer 200 with respect to the upper electrode shield 121.

[0099] In some embodiments, step 310, changing the relative position of the wafer with respect to the upper electrode shield in the horizontal direction so that the inner ring etching uniformity parameter is less than or equal to a first preset value, may include:

[0100] Based on the inner ring etching rate of the wafer, a first relative offset parameter of the wafer relative to the upper electrode shield is determined in the horizontal direction; based on the first relative offset parameter, the wafer supported on the lower electrode assembly is translated in the horizontal direction, and / or the upper electrode shield is translated in the horizontal direction, so that the inner ring etching uniformity parameter is less than or equal to a first preset value.

[0101] More specifically, in some embodiments, determining a first relative offset parameter of the wafer relative to the upper electrode shield in the horizontal direction based on the inner edge etching rate of the wafer includes:

[0102] In the etched area of ​​the wafer, multiple first reference points are selected along the circumferential direction of the inner circle of the wafer, and a first average etching rate is determined for the multiple first reference points. Second reference points with the same first average etching rate are determined along the line connecting the center of the inner circle and each of the first reference points. The multiple second reference points are fitted to obtain a first fitted circle. A first center position deviation parameter between the center of the inner circle and the center of the first fitted circle is determined, and a first relative offset parameter is determined based on the first center position deviation parameter.

[0103] For example, refer to Figure 7 Multiple first reference points 231 can be selected along the circumferential direction of the inner ring 230 of the wafer 200 in the etching area, and the first average etching rate of the multiple first reference points 231 can be determined. For example, eight first reference points 231 can be uniformly selected along the circumferential direction of the inner ring 230, and the first average etching rate of the eight first reference points 231 can be determined.

[0104] Furthermore, a second reference point 232, equal to the first average etching rate, can be determined along the line connecting the center of the inner circle 230 and each of the first reference points 231. For example, multiple detection points can be taken in each direction to detect the etching rate at each detection point, and an etching rate curve can be plotted based on the etching rate at each detection point. Thus, the position of the second reference point 232, equal to the first average etching rate, can be determined based on the etching rate curve.

[0105] Furthermore, multiple second reference points 232 are fitted to obtain a first fitted circle 233. For example, the first fitted circle 233 can be obtained through Fourier fitting.

[0106] Furthermore, a first center position deviation parameter is determined between the center of the inner circle 230 and the center of the first fitted circle 233, and a first relative offset parameter is determined based on this first center position deviation parameter. In other words, the difference between the first center of the inner circle 230 and the first fitted circle 233 can be calculated to determine the first center position deviation parameter between them. The first relative offset parameter can then be determined based on this first center position deviation parameter.

[0107] It should be noted that, in the embodiments of this application, the relative position of the wafer 200 with respect to the upper electrode shield 121 in the horizontal direction can be adjusted by using a robotic arm to drive the wafer 200 to move. Alternatively, the relative position of the wafer 200 with respect to the upper electrode shield 121 in the horizontal direction can be adjusted by manipulating the translation component 150 to drive the upper electrode shield 121 to translate horizontally relative to the lower electrode assembly 130.

[0108] After step 310, the etching uniformity adjustment method provided in this application embodiment further includes:

[0109] Step 320: Etch the wafer to determine whether the circumferential etching rate trend of the inner ring of the wafer is the same as that of the outer ring of the wafer. If the circumferential etching rate trends of the inner ring and the outer ring are different, adjust the tilt angle of the upper electrode shield relative to the wafer so that the circumferential etching rate trends of the inner ring and the outer ring are the same.

[0110] In the embodiments of this application, after reducing the inner ring etching uniformity parameter to below a first preset value, the wafer 200 can be placed in the semiconductor process equipment 100 according to the parameters adjusted in step 310, so as to perform etching processing on the wafer 200 using the semiconductor process equipment 100. It should be noted that in step 310, if the inner ring etching uniformity parameter is less than or equal to the first preset value, step 320 can be executed directly.

[0111] It should also be noted that the applicant found through experiments that adjusting the tilt angle of the upper electrode shield 121 relative to the lower electrode assembly 130 has virtually no impact on the etching uniformity of the inner ring 230. Therefore, in the process of adjusting the etching uniformity, the etching uniformity of the inner ring 230 is adjusted first. In this way, during the subsequent adjustment of the tilt angle of the upper electrode shield 121 relative to the lower electrode assembly 130, the etching uniformity of the inner ring 230 will not be significantly altered, thus avoiding the problem of deterioration in the uniformity of the inner ring 230 during the adjustment of the tilt angle of the upper electrode shield 121 relative to the lower electrode assembly 130.

[0112] In the embodiments of this application, after etching the wafer 200, it can be determined whether the circumferential etching rate trend of the inner ring of the etched wafer 200 is the same as the circumferential etching rate trend of the outer ring of the wafer 200. If the circumferential etching rate trends of the inner ring and the outer ring are different, the tilt angle of the upper electrode shielding member 121 relative to the wafer 200 supported by the lower electrode assembly 130 is adjusted so that the circumferential etching rate trends of the inner ring and the outer ring are the same.

[0113] Exemplarily, in some embodiments, step 320, adjusting the tilt angle of the upper electrode shield relative to the wafer to make the inner circumferential etching rate trend the same as the outer circumferential etching rate trend, may include:

[0114] Based on the circumferential etching rate trends of the inner and outer rings, a third relative offset parameter along the vertical direction is determined for multiple fifth reference points on the upper electrode shield. Based on the third relative offset parameter, the spacing between the fifth reference points of the upper electrode shield and the wafer is adjusted to adjust the tilt angle of the upper electrode shield relative to the wafer so that the circumferential etching rate trends of the inner and outer rings are the same.

[0115] More specifically, in some embodiments, based on the inner circumferential etching rate trend and the outer circumferential etching rate trend, a third relative offset parameter in the vertical direction is determined for multiple fifth reference points on the upper electrode shield, including: based on the deviation between the inner circumferential etching rate trend and the outer circumferential etching rate trend, and the displacement to etching rate ratio parameter, the third relative offset parameter in the vertical direction for each fifth reference point is determined.

[0116] It should be noted that, through experiments, the applicant discovered that, taking one of the multiple fifth reference points as the target reference point, the orthographic projection of the target reference point on the wafer 200 supported by the lower electrode assembly 130 coincides with the sixth reference point. The seventh reference point on the wafer 200 is symmetrically distributed with the sixth reference point along the center of the wafer 200. Increasing the distance between the target reference point and the lower electrode assembly 130 reduces the etching rate of the sixth reference point on the wafer 200 and increases the etching rate of the seventh reference point on the wafer 200.

[0117] More simply, increasing the distance between a fifth reference point of the upper electrode shielding member 121 and the wafer 200 will decrease the etching rate of the sixth reference point on the wafer 200 opposite to the fifth reference point, and increase the etching rate of the seventh reference point on the wafer 200 located on the opposite side of the sixth reference point. Based on this, it can be determined whether each of the fifth reference points of the upper electrode shielding member 121 needs to be raised or lowered.

[0118] In some embodiments, the third relative offset parameter can be determined according to the formula: (ER2max-ER2min) / (2V); where ER2max is the maximum etching rate of the outer ring 240, ER2max is the minimum etching rate of the outer ring 240, and V is 18 to 30 angstroms per minute (A / min).

[0119] It should be noted that adjusting the relative tilt angle of the upper electrode shield 121 primarily affects the etching uniformity of the outer ring 240, but has virtually no impact on the etching uniformity of the inner ring 230. Therefore, the third relative offset parameter can be determined based on the maximum and minimum etching rates of the outer ring 240.

[0120] In addition, the applicant discovered through experiments that for every 1 micrometer increase in the fifth reference point of the upper electrode shield 121 relative to the lower electrode assembly 130, the etching rate of the sixth reference point of the wafer 200 relative to the fifth reference point would decrease by 18 to 30 angstroms per minute. Therefore, the value of V was set to 18 to 30 angstroms per minute.

[0121] The following, with a more specific example, illustrates the specific process of making the inner circumferential etching rate trend the same as the outer circumferential etching rate trend by adjusting the tilt angle of the upper electrode shield relative to the wafer.

[0122] For example, combined Figure 5 In one embodiment, after etching the wafer 200, the etching rates at each measurement point on the inner ring 230 and outer ring 240 of the wafer 200 are shown in the table below:

[0123] 40° 85° 130° 175° 220° 265° 310° 355° ER2 (A / min) 11925 13445 14536 13235 11747 10726 10897 10966 ER1 (A / min) 62 47 38 91 92 79 79 90

[0124] Therefore, for the outer ring 240 of wafer 200, the etching rate is highest at 130° and lowest at 265°. The overall trend of the circumferential etching rate in the outer ring shows a faster etching rate between the 10 and 11 o'clock positions, resulting in a worse etching uniformity parameter of 15.6%. For the inner ring 230 of wafer 200, the etching rate is highest at 220° and lowest at 130°. The overall trend of the circumferential etching rate in the inner ring shows a faster etching rate between the 6 and 7 o'clock positions, resulting in an etching uniformity parameter of 37.4%.

[0125] It should be noted that before changing the horizontal relative position of the wafer to the upper electrode shield, the inner ring etching uniformity parameter was 70.1%. After changing the horizontal relative position of the wafer to the upper electrode shield, the inner ring etching uniformity parameter was 37.4%. Therefore, changing the horizontal relative position of the wafer to the upper electrode shield can effectively improve the etching uniformity of the inner ring 230.

[0126] Furthermore, since the overall circumferential etching rate trend of the outer ring shows a faster etching rate in the 10 to 11 o'clock direction and a faster etching rate in the 6 to 7 o'clock direction, it can be seen that the circumferential etching rate trends of the inner ring and the outer ring are different. Therefore, it is necessary to adjust the tilt angle of the upper electrode shielding member 121 relative to the lower electrode assembly 130 to make the circumferential etching rate trends of the inner ring and the outer ring the same.

[0127] The wafer etching rate table shows that ER2max is 14536 A / min and ER2max is 10726 A / min. Calculations based on the formula for the third relative offset parameter show that its value ranges from 63.5 to 105.83 micrometers. In one embodiment of this application, the third relative offset parameter is set to 100 micrometers.

[0128] Combination Figure 8 The etching rate is highest at the measurement points on the outer ring 240 located between 85° and 130°, and relatively high at the measurement points on the inner ring 230 located between 220° and 265°. Therefore, the etching rate of the etched portion on the outer ring 240 located between 85° and 130° can be reduced. Consequently, the second telescopic drive mechanism 141 located between 130° and 175° can be adjusted so that the portion where the upper electrode shield 121 is driven to connect with the second telescopic drive mechanism 141 is raised by 100 micrometers. Furthermore, the second telescopic drive mechanism 141 located between 40° and 85° can be adjusted so that the portion where the upper electrode shield 121 is driven to connect with the second telescopic drive mechanism 141 is raised by 100 micrometers.

[0129] In this manner, using the etching uniformity adjustment method provided in this application embodiment, the etching uniformity of the inner ring 230 can be improved by first changing the relative position of the wafer 200 with respect to the upper electrode shield 121 in the horizontal direction. Furthermore, by adjusting the tilt angle of the upper electrode shield 121 relative to the wafer 200, the circumferential etching rate trend of the inner ring can be made the same as that of the outer ring, thereby improving the etching uniformity of the outer ring 240.

[0130] It should be noted that, for example, before performing edge etching on a batch of wafers using semiconductor process equipment, the semiconductor process equipment can be adjusted to a state where the etching uniformity meets the requirements using the method provided in the embodiments of this application. Referring to the above example, the semiconductor process equipment can be debugged first using a test wafer. The relative position of the test wafer with respect to the upper electrode shield in the horizontal direction can be changed first, and then the tilt angle of the upper electrode shield relative to the test wafer can be adjusted. When the edge etching parameters of the test wafer meet the requirements, the position of the test wafer on the wafer bearing surface of the lower electrode assembly is determined, and the relative position and tilt angle of the upper electrode assembly and the lower electrode assembly are determined. Thus, in the subsequent edge etching process of the wafer, the wafer is etched based on the parameters determined by the test wafer.

[0131] It should also be noted that in some special cases, after performing steps 310 and 320, the etching uniformity of the inner and / or outer rings may still not meet the process requirements. In such cases, the etching uniformity of the inner and / or outer rings can be further adjusted by changing the horizontal relative position of the wafer 200 with respect to the upper electrode shield 121. It is understood that after performing step 320, the circumferential etching rate trends of the inner and outer rings are the same. Therefore, the problem present in related technologies, where changing the horizontal relative position of the wafer with respect to the upper electrode shield to preferentially adjust the etching rate uniformity of one ring (indicating opposite etching trends) inevitably leads to a worse uniformity of the other ring.

[0132] Therefore, in order to better improve the etching uniformity of the inner ring 230 and the outer ring 240, reference is made. Figure 9 Optionally, in some embodiments, after step 320, the etching uniformity adjustment method provided in this application embodiment may further include:

[0133] Step 330: Etch the wafer, determine whether the inner ring etching uniformity parameter of the wafer is greater than a second preset value, determine whether the outer ring etching uniformity parameter of the wafer is greater than a third preset value, and if the inner ring etching uniformity parameter is greater than the second preset value and / or the outer ring etching uniformity parameter is greater than the third preset value, change the relative position of the wafer with respect to the upper electrode shield in the horizontal direction so that the inner ring etching uniformity parameter is less than or equal to the second preset value and the outer ring etching uniformity parameter is less than or equal to the third preset value.

[0134] Exemplarily, in some embodiments, step 330, changing the relative position of the wafer with respect to the upper electrode shield in the horizontal direction so that the inner ring etching uniformity parameter is less than or equal to a second preset value and the outer ring etching uniformity parameter is less than or equal to a third preset value, may include:

[0135] The etching uniformity deviation of the inner ring etching uniformity parameter relative to a second preset value and the etching uniformity deviation of the outer ring etching uniformity parameter relative to a third preset value are determined. Using the larger etching uniformity deviation of the inner and outer rings of the wafer as an offset reference, a second relative offset parameter of the wafer relative to the wafer in the horizontal direction is determined. Based on the second relative offset parameter, the wafer is translated in the horizontal direction, and / or the upper electrode shielding member is translated in the horizontal direction, so that the inner ring etching uniformity parameter is less than or equal to the second preset value and the outer ring etching uniformity parameter is less than or equal to the third preset value.

[0136] Specifically, in some embodiments, the second relative offset parameter of the wafer relative to the wafer in the horizontal direction is determined by using the one with the larger etching uniformity deviation between the inner and outer rings of the wafer as an offset reference. This may include:

[0137] The inner and outer circles with the larger etching uniformity deviation are used as reference circles. In the etching region of the wafer, multiple third reference points are selected along the circumference of the reference circle, and the second average etching rate of the multiple third reference points is determined. Fourth reference points with the same second average etching rate are determined along the line connecting the center of the reference circle and each of the third reference points. The multiple fourth reference points are fitted to obtain a second fitted circle. The second center position deviation parameter between the center of the reference circle and the center of the second fitted circle is determined, and the second relative offset parameter is determined based on the second center position deviation parameter.

[0138] More simply, if the etching uniformity deviation of the inner ring relative to the second preset value is greater than the etching uniformity deviation of the outer ring relative to the third preset value, then the inner ring 230 can be used as a reference circle to determine the second relative offset parameter. Specifically, the second relative offset parameter can be obtained by referring to the calculation method of the first relative offset parameter.

[0139] The following describes, with more specific examples, the specific process of changing the relative position of the wafer with respect to the upper electrode shield in the horizontal direction so that the inner ring etching uniformity parameter is less than or equal to a second preset value and the outer ring etching uniformity parameter is less than or equal to a third preset value.

[0140] For example, combined Figure 5 In one embodiment, after etching the wafer 200, the etching rates at each measurement point on the inner ring 230 and outer ring 240 of the wafer 200 are shown in the table below:

[0141] 40° 85° 130° 175° 220° 265° 310° 355° ER2 (A / min) 11274 11490 12183 12070 12433 12843 13002 12057 ER1 (A / min) 109 80 68 148 159 139 142 168

[0142] Therefore, for the outer ring 240 of wafer 200, the outer ring etching uniformity parameter is 7.1%, and the overall trend of the outer ring circumferential etching rate shows a faster etching rate in the 175° to 355° direction. For the inner ring 230 of wafer 200, the inner ring etching uniformity parameter is 39.6%, and the trend of the outer ring circumferential etching rate does not change much, with the overall trend showing a faster etching rate in the 175° to 355° direction. This indicates that by adjusting the tilt angle of the upper electrode shield relative to the wafer, the circumferential etching rate trends of the inner and outer rings can be made the same.

[0143] Furthermore, the outer ring etching uniformity parameter decreased from 15.6% to 7.1%, indicating that adjusting the tilt angle of the upper electrode shielding component relative to the wafer can also improve the outer ring etching uniformity. Before adjusting the tilt angle of the upper electrode shielding component 121 relative to the wafer 200, the inner ring etching uniformity parameter was 37.4%. After adjusting the tilt angle of the upper electrode shielding component 121 relative to the wafer 200, the inner ring etching uniformity parameter was 39.6%. This shows that adjusting the tilt angle of the upper electrode shielding component 121 relative to the wafer 200 has virtually no impact on the inner ring etching uniformity.

[0144] Furthermore, based on process requirements, it is considered to further improve the etching rate uniformity of the inner ring 230 and the outer ring 240. For example, a second preset value of 30% and a third preset value of 10% can be used. In other words, it is necessary to further adjust and change the relative position of the wafer with respect to the upper electrode shield along the horizontal direction so that the etching uniformity parameter of the inner ring is less than or equal to 30%, and the etching uniformity parameter of the outer ring is less than or equal to 10%.

[0145] After executing step 320, the outer ring etching uniformity parameter is 7.1%, which meets the requirement of less than or equal to 10%. However, the inner ring etching uniformity parameter is 39.6%, which does not meet the requirement of less than or equal to 30%. Furthermore, it can be concluded that the etching uniformity deviation of the inner ring 230 is relatively large. Therefore, referring to the calculation method of the first relative offset parameter, the second relative offset parameter can be determined using the inner ring 230 as a reference circle.

[0146] For example, in other embodiments, if the etching uniformity deviation of the outer ring 240 is large, the second relative offset parameter can be determined by referring to the calculation method of the first relative offset parameter, using the outer ring 240 as a reference circle.

[0147] To verify the effectiveness of the solution, the applicant obtained the etching rates at various measurement points on the inner ring 230 and outer ring 240 of the etched wafer 200. The specific data are shown in the table below:

[0148] 40° 85° 130° 175° 220° 265° 310° 355° ER2 (A / min) 13309 14043 15194 14335 13817 13479 13647 13302 ER1 (A / min) 472 510 482 496 546 431 387 468

[0149] Therefore, the etching uniformity parameter of the outer ring is 6.8%, and that of the inner ring is 16.7%, which meets the etching uniformity requirements for both the inner and outer rings. Moreover, the circumferential etching rate trends of the inner and outer rings remain the same.

[0150] It should be noted that in some extreme cases, when the horizontal deviation between the wafer 200 and the upper electrode shield 121 is too large, the effect of the difference in the tilt angle of the upper electrode shield 121 relative to the wafer 200 on the circumferential etching rate trends of the inner and outer rings can be easily masked and become insignificant. Consequently, the circumferential etching rate trends of the inner and outer rings may become the same, resulting in a situation where the etching uniformity of the inner and outer rings does not meet the requirements.

[0151] For cases where the circumferential etching rate trends of the inner and outer rings are the same, and the etching uniformity of the inner and outer rings does not meet the requirements, refer to... Figure 9 Optionally, in some embodiments, the method for adjusting etching uniformity may further include:

[0152] Step 305: Etch the wafer, determine whether the inner ring etching uniformity parameter of the wafer is greater than the fourth preset value, determine whether the outer ring etching uniformity parameter of the wafer is greater than the fifth preset value, and determine whether the inner ring circumferential etching rate trend and the outer ring circumferential etching rate trend of the wafer are the same. If the inner ring etching uniformity parameter of the wafer is greater than the fourth preset value, the outer ring etching uniformity parameter of the wafer is greater than the fifth preset value, and the inner ring circumferential etching rate trend and the outer ring circumferential etching rate trend of the wafer are the same, change the relative position of the wafer with respect to the upper electrode assembly in the horizontal direction so that the inner ring etching uniformity parameter is less than or equal to the fourth preset value, and / or the outer ring etching uniformity parameter is less than or equal to the fifth preset value, and etch the wafer again.

[0153] In other words, before step 310, the wafer 200 can be etched to determine whether the circumferential etching rate trends of the inner and outer rings are the same, and whether the etching uniformity of the inner and outer rings meets the requirements. If the circumferential etching rate trends of the inner and outer rings are the same, but the etching uniformity of the inner and outer rings does not meet the requirements, it is considered that the deviation between the wafer 200 and the upper electrode shielding component 121 is too large. Therefore, the relative position of the wafer and the upper electrode component can be coarsely adjusted by changing the relative position of the wafer with respect to the upper electrode component in the horizontal direction. After the coarse adjustment ensures that the etching uniformity of the inner and outer rings meets the requirements, step 310 is then executed.

[0154] It should be noted that in step 305, if the circumferential etching rate trends of the inner and outer rings are different, then the relative positions of the wafer and the upper electrode assembly do not need to be coarsely adjusted, and step 310 can be executed directly. It should also be noted that since step 305 is designed to handle extreme cases, such extreme cases generally do not occur if the semiconductor process equipment is well maintained. Therefore, in some embodiments, the method for adjusting etching uniformity may not include step 305.

[0155] This application also provides a semiconductor process apparatus 100, which may include a chamber body 110, an upper electrode assembly 120, and a lower electrode assembly 130. The lower electrode assembly 130 has a support surface for supporting a wafer 200. The upper electrode assembly 120 includes an upper electrode shielding member 121 disposed inside the chamber body 110. The upper electrode shielding member 121 is disposed opposite to the support surface. Any etching uniformity adjustment method provided in this application embodiment is executed in the semiconductor process apparatus of this application embodiment.

[0156] In some embodiments, the semiconductor process equipment 100 further includes a leveling component 140 connected to the upper electrode assembly 120, used to adjust the tilt angle of the upper electrode shield 121 to adjust the tilt angle of the upper electrode shield 121 relative to the wafer 200 supported on the lower electrode assembly 130. Thus, by adjusting the tilt angle of the upper electrode shield 121, the distance between each portion of the upper electrode shield 121 and its corresponding portion on the wafer 200 can be adjusted.

[0157] In some embodiments, the semiconductor process equipment 100 further includes a translation component 150 and / or a transfer device. The translation component 150 is connected to the upper electrode assembly 120 and is used to drive the upper electrode shielding member 121 to translate horizontally relative to the wafer 200. The transfer device is used to move the wafer 200 horizontally relative to the upper electrode shielding member 121. Exemplarily, the transfer device can be a robotic arm. Generally, the semiconductor process equipment 100 can be combined with a robotic arm to transfer the wafer 200, for example, by using a robotic arm to move the wafer 200 to the bearing surface of the lower electrode assembly 130 so that the semiconductor process equipment 100 can etch the wafer 200. After etching, the robotic arm can be used to remove the wafer 200. Therefore, in the embodiments of this application, a robotic arm for transferring the wafer 200 can be used to move the wafer 200 horizontally to change the relative position of the wafer 200 with respect to the upper electrode shielding member 121 in the horizontal direction.

[0158] It should be noted that, in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such process, method, article, or apparatus.

[0159] Although embodiments of this application have been shown and described, it will be understood by those skilled in the art that various changes, modifications, substitutions and variations can be made to these embodiments without departing from the principles and spirit of the embodiments of this application, the scope of which is defined by the appended claims and their equivalents.

Claims

1. A method for adjusting etching uniformity, applied to semiconductor process equipment to perform a crystal edge etching process, characterized in that, The method for adjusting etching uniformity includes: Determine whether the inner ring etching uniformity parameter of the etched wafer is greater than a first preset value. If the inner ring etching uniformity parameter is greater than the first preset value, change the relative position of the wafer with respect to the upper electrode shield in the horizontal direction so that the inner ring etching uniformity parameter is less than or equal to the first preset value. The wafer is etched to determine whether the circumferential etching rate trend of the inner ring of the wafer is the same as that of the outer ring of the wafer. If the circumferential etching rate trends of the inner ring and the outer ring are different, the tilt angle of the upper electrode shield relative to the wafer is adjusted so that the circumferential etching rate trends of the inner ring and the outer ring are the same.

2. The method for adjusting etching uniformity according to claim 1, characterized in that, Changing the relative position of the wafer with respect to the upper electrode shield along the horizontal direction so that the inner ring etching uniformity parameter is less than or equal to the first preset value includes: Based on the inner ring etching rate of the wafer, a first relative offset parameter of the wafer relative to the upper electrode shielding member in the horizontal direction is determined; Based on the first relative offset parameter, the wafer is translated horizontally, and / or the upper electrode shield is translated horizontally, so that the inner ring etching uniformity parameter is less than or equal to the first preset value.

3. The method for adjusting etching uniformity according to claim 2, characterized in that, The determination of a first relative offset parameter of the wafer relative to the upper electrode shielding member in the horizontal direction based on the inner ring etching rate of the wafer includes: In the etching area of ​​the wafer, a plurality of first reference points are selected along the circumferential direction of the inner circle of the wafer, and the first average etching rate of the plurality of first reference points is determined. In the direction of the line connecting the center of the inner circle and each of the first reference points, a second reference point equal to the first average etching rate is determined. The first fitted circle is obtained by fitting multiple second reference points; A first center position deviation parameter is determined between the center of the inner circle and the center of the first fitted circle, and a first relative offset parameter is determined based on the first center position deviation parameter.

4. The method for adjusting etching uniformity according to claim 1, characterized in that, After adjusting the tilt angle of the upper electrode shield relative to the wafer to make the circumferential etching rate trend of the inner ring the same as that of the outer ring, the method for adjusting the etching uniformity further includes: The wafer is etched. Determine whether the inner ring etching uniformity parameter of the wafer is greater than a second preset value, and determine whether the outer ring etching uniformity parameter of the wafer is greater than a third preset value. If the inner ring etching uniformity parameter is greater than the second preset value, and / or the outer ring etching uniformity parameter is greater than the third preset value, the relative position of the wafer with respect to the upper electrode shield in the horizontal direction is changed so that the inner ring etching uniformity parameter is less than or equal to the second preset value, and the outer ring etching uniformity parameter is less than or equal to the third preset value.

5. The method for adjusting etching uniformity according to claim 4, characterized in that, Changing the horizontal relative position of the wafer to the upper electrode shielding member so that the inner ring etching uniformity parameter is less than or equal to the second preset value, and the outer ring etching uniformity parameter is less than or equal to the third preset value, includes: Determine the etching uniformity deviation of the inner ring etching uniformity parameter relative to the second preset value, and the etching uniformity deviation of the outer ring etching uniformity parameter relative to the third preset value; Using the larger etching uniformity deviation between the inner and outer rings of the wafer as an offset reference, a second relative offset parameter of the wafer relative to the wafer in the horizontal direction is determined. Based on the second relative offset parameter, the wafer is translated horizontally, and / or the upper electrode shield is translated horizontally, so that the inner ring etching uniformity parameter is less than or equal to the second preset value, and the outer ring etching uniformity parameter is less than or equal to the third preset value.

6. The method for adjusting etching uniformity according to claim 5, characterized in that, The step of determining a second relative offset parameter of the wafer along the horizontal direction, using the larger of the etching uniformity deviations of the inner and outer rings of the wafer as an offset reference, includes: The inner circle and the outer circle with the larger corresponding etching uniformity deviation are used as the reference circle; In the etched area of ​​the wafer, a plurality of third reference points are selected along the circumferential direction of the reference circle, and the second average etching rate of the plurality of third reference points is determined. A fourth reference point, equal to the second average etching rate, is determined along the line connecting the center of the reference circle and each of the third reference points. The multiple fourth reference points are fitted to obtain a second fitted circle; A second center position deviation parameter is determined between the center of the reference circle and the center of the second fitted circle, and a second relative offset parameter is determined based on the second center position deviation parameter.

7. The method for adjusting etching uniformity according to claim 1, characterized in that, Adjusting the tilt angle of the upper electrode shield relative to the wafer to make the circumferential etching rate trend of the inner ring the same as that of the outer ring includes: Based on the circumferential etching rate trend of the inner ring and the circumferential etching rate trend of the outer ring, a third relative offset parameter along the vertical direction is determined for multiple fifth reference points on the upper electrode shield. The distance between the fifth reference point of the upper electrode shield and the wafer is adjusted based on the third relative offset parameter to adjust the tilt angle of the upper electrode shield relative to the wafer so that the circumferential etching rate trend of the inner ring is the same as that of the outer ring.

8. The method for adjusting etching uniformity according to claim 7, characterized in that, The method for determining multiple fifth reference points on the upper electrode shield based on the circumferential etching rate trends of the inner and outer rings, and the third relative offset parameter along the vertical direction, includes: Based on the deviation between the inner circumferential etching rate trend and the outer circumferential etching rate trend, and the displacement-etching rate ratio parameter, the third relative offset parameter of each of the fifth reference points along the vertical direction is determined.

9. The method for adjusting etching uniformity according to claim 8, characterized in that, The third relative offset parameter is determined according to the formula: (ER2max-ER2min) / (2V); where, ER2max is the maximum etching rate of the outer ring. ER2min is the minimum etching rate of the outer ring. V ranges from 18 to 30 angstroms per minute.

10. The method for adjusting etching uniformity according to claim 8, characterized in that, Using one of the plurality of fifth reference points as the target reference point, the orthographic projection of the target reference point on the wafer coincides with the sixth reference point, and the seventh reference point on the wafer is symmetrically distributed with the sixth reference point along the center of the wafer. Increasing the distance between the target reference point and the wafer reduces the etching rate of the sixth reference point on the wafer and increases the etching rate of the seventh reference point on the wafer.

11. The method for adjusting etching uniformity according to claim 1, characterized in that, Before determining whether the inner ring etching uniformity parameter of the etched wafer is greater than a first preset value, the etching uniformity adjustment method further includes: The wafer is etched. Determine whether the inner ring etching uniformity parameter of the wafer is greater than a fourth preset value, determine whether the outer ring etching uniformity parameter of the wafer is greater than a fifth preset value, and determine whether the inner ring circumferential etching rate trend and the outer ring circumferential etching rate trend of the wafer are the same. When the inner ring etching uniformity parameter of the wafer is greater than the fourth preset value, the outer ring etching uniformity parameter of the wafer is greater than the fifth preset value, and the circumferential etching rate trends of the inner and outer rings of the wafer are the same, the relative position of the wafer with respect to the upper electrode shielding member in the horizontal direction is changed so that the inner ring etching uniformity parameter is less than or equal to the fourth preset value, and / or the outer ring etching uniformity parameter is less than or equal to the fifth preset value. The wafer is then etched again.

12. A semiconductor process apparatus, comprising: The device comprises a chamber body, an upper electrode assembly, and a lower electrode assembly, wherein the lower electrode assembly has a support surface for supporting a wafer, and the upper electrode assembly includes an upper electrode shield disposed inside the chamber body, the upper electrode shield being disposed opposite to the support surface; characterized in that the etching uniformity adjustment method according to any one of claims 1 to 11 is performed in the semiconductor process equipment.

13. The semiconductor process equipment according to claim 12, characterized in that, The semiconductor process equipment also includes: A leveling assembly, connected to the upper electrode assembly, is used to adjust the tilt angle of the upper electrode shielding member, thereby adjusting the tilt angle of the upper electrode shielding member relative to the wafer supported by the lower electrode assembly. A translation component and / or a transmission device, wherein the translation component is connected to the upper electrode component and is used to drive the upper electrode shielding member to translate relative to the wafer in a horizontal direction; and the transmission device is used to drive the wafer to move relative to the upper electrode shielding member in a horizontal direction.

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