Method for testing metal contamination of semiconductor structures

Abstract

This application provides a method for testing metal contamination in semiconductor structures, comprising: providing a semiconductor structure under test and a control semiconductor structure; maintaining constant voltages at the drain, source, and substrate terminals of the semiconductor structure under test and the control semiconductor structure; varying the voltage at the gate terminal of the semiconductor structure under test and the control semiconductor structure from a first preset value to a second preset value, and obtaining the relationship between the voltage at the gate terminal and the current at the drain terminal of the semiconductor structure under test and the control semiconductor structure, respectively; obtaining the transconductance of the semiconductor structure under test and the control semiconductor structure; obtaining the electron mobility of the semiconductor structure under test and the control semiconductor structure, thereby obtaining the metal contamination status of the semiconductor structure under test. The method for testing metal contamination in semiconductor structures provided in this application can qualitatively reflect the metal content at the ppb level and has advantages such as sensitivity, high efficiency, simplicity, and universality.

Description

Technical Field

[0001] This application relates to the field of semiconductor manufacturing, and more particularly to a method for testing metal contamination in semiconductor structures. Background Technology

[0002] In the field of integrated circuit manufacturing, wafer surfaces are extremely sensitive to metal ions because metals increase leakage current, reduce breakdown voltage, and consequently affect the operational lifespan of devices. Conventional methods for detecting metals are usually independent of chip manufacturing, and are costly, time-consuming, and unable to monitor problems in the production process in real time.

[0003] Metal ions in photoresist are currently one of the major sources of contamination on wafers. There are many types of metal ions, but they are generally at the ppb level. Therefore, changes in metal content cannot be detected by conventional electrical tests. Summary of the Invention

[0004] The technical problem to be solved by this application is to provide a method for testing metal contamination in semiconductor structures, which can qualitatively reflect the metal content at the ppb level, and has the advantages of being sensitive, efficient, simple and universal.

[0005] To address the aforementioned technical problems, this application provides a method for testing metal contamination in a semiconductor structure, comprising: providing a semiconductor structure under test and a control semiconductor structure, wherein both the semiconductor structure under test and the control semiconductor structure include a gate terminal, a source terminal, a drain terminal, and a substrate terminal, and the control semiconductor structure has a preset metal content; maintaining the voltages at the drain terminal, source terminal, and substrate terminal of the semiconductor structure under test and the control semiconductor structure unchanged, wherein the voltage at the drain terminal is greater than the voltages at the source terminal and the substrate terminal; varying the voltage at the gate terminal of the semiconductor structure under test and the control semiconductor structure from a first preset value to a second preset value, and obtaining the relationship between the voltage at the gate terminal and the current at the drain terminal of the semiconductor structure under test and the control semiconductor structure, respectively; obtaining the transconductance of the semiconductor structure under test and the control semiconductor structure based on the relationship between the voltage at the gate terminal and the current at the drain terminal; obtaining the electron mobility of the semiconductor structure under test and the control semiconductor structure based on the transconductance of the semiconductor structure under test and the control semiconductor structure, thereby obtaining the metal contamination status of the semiconductor structure under test.

[0006] In this embodiment of the application, the method for obtaining the electron mobility is as follows: Where, μ n G represents the electron mobility of the semiconductor structure under test or the control semiconductor structure. m V represents the transconductance of the semiconductor structure under test or the reference semiconductor structure. dC is the drain voltage of the semiconductor structure under test or the reference semiconductor structure. ox is the gate capacitance of the semiconductor structure under test or the reference semiconductor structure, L is the length of the channel of the semiconductor structure under test or the reference semiconductor structure, and W is the width of the gate of the semiconductor structure under test or the reference semiconductor structure.

[0007] In this embodiment of the application, the method for obtaining the transconductance of the semiconductor structure under test and the reference semiconductor structure includes: differentiating the relationship between the voltage at the gate terminal and the current at the drain terminal of the semiconductor structure under test to obtain the transconductance of the semiconductor structure under test; and differentiating the relationship between the voltage at the gate terminal and the current at the drain terminal of the reference semiconductor structure to obtain the transconductance of the reference semiconductor structure.

[0008] In this embodiment of the application, the preset metal content is the maximum allowable metal content; the method for obtaining the metal contamination status of the semiconductor structure to be tested includes: comparing the electron mobility of the semiconductor structure to be tested and the control semiconductor structure, and confirming that the electron mobility of the semiconductor structure to be tested is greater than or equal to the electron mobility of the control semiconductor structure, then the metal contamination test status of the semiconductor structure to be tested is qualified.

[0009] In this embodiment of the application, if it is confirmed that the electron mobility of the semiconductor structure under test is less than that of the control semiconductor structure, then the metal contamination test of the semiconductor structure under test is considered to be out of standard.

[0010] In this embodiment of the application, the source and substrate ends of both the semiconductor structure under test and the reference semiconductor structure are grounded.

[0011] In this embodiment of the application, the voltage at the gate terminals of the semiconductor structure under test and the control semiconductor structure increases from the first preset value to the second preset value, and the first preset value is 0.

[0012] In this embodiment, the gate terminal is located on the substrate terminal, and the source terminal and the drain terminal are respectively located in the substrate terminals on both sides of the gate terminal. The gate terminal includes a gate oxide layer and a gate located on the gate oxide layer.

[0013] In this embodiment of the application, the semiconductor structure to be tested and the reference semiconductor structure are NMOS or PMOS.

[0014] In this embodiment of the application, the semiconductor structure under test is formed by a front gate process, and the metal contamination is ppb-level metal contamination caused by a photoresist process.

[0015] In this embodiment, the metal contamination refers to metal ion contamination in the channel of the semiconductor structure under test.

[0016] Compared with existing technologies, the method for testing metal contamination in semiconductor structures in this application has the following advantages:

[0017] By keeping the voltages at the drain, source, and substrate of the semiconductor structure under test and the control semiconductor structure constant, with the drain voltage greater than the source and substrate voltages, and changing the gate voltages of the semiconductor structure under test and the control semiconductor structure from a first preset value to a second preset value, the drain current of the semiconductor structure under test and the control semiconductor structure changes. The transconductance of the semiconductor structure under test and the control semiconductor structure is obtained through the relationship between the gate voltage and the drain current. Then, the electron mobility of the semiconductor structure under test and the control semiconductor structure is obtained through the transconductance. Using the electron mobility of the control semiconductor structure as a reference, the metal contamination of the semiconductor structure under test can be obtained. This method can qualitatively reflect the metal content at the ppb level and has high sensitivity, while also being compatible with WAT electrical testing.

[0018] The testing method of this application can perform metal contamination testing on any device with a channel structure. The testing method is simple and universal. Attached Figure Description

[0019] The following accompanying drawings describe in detail the exemplary embodiments disclosed in this application. The same reference numerals denote similar structures in several views of the drawings. Those skilled in the art will understand that these embodiments are non-limiting and exemplary, and the drawings are for illustrative purposes only and are not intended to limit the scope of this application. Other embodiments may similarly fulfill the inventive intent of this application. It should be understood that the drawings are not drawn to scale. Wherein:

[0020] Figure 1 This is a flowchart illustrating a method for testing metal contamination in semiconductor structures according to an embodiment of this application.

[0021] Figure 2 These are schematic diagrams of the semiconductor structure under test and the control semiconductor structure in an embodiment of this application;

[0022] Figure 3 This is a schematic diagram of the circuit structure of the semiconductor structure under test and the control semiconductor structure in an embodiment of this application;

[0023] Figure 4 The graphs show the relationship between the gate voltage and the drain current of the semiconductor structure under test, as well as the transconductance curve, in an embodiment of this application.

[0024] Figure 5 The graph shows the test results for the Jleak and GLK methods.

[0025] Figure 6 This is a diagram showing the test results for metal contamination in a semiconductor structure according to an embodiment of this application. Detailed Implementation

[0026] The following description provides specific application scenarios and requirements for this application, intended to enable those skilled in the art to make and use the content of this application. Various partial modifications to the disclosed embodiments will be apparent to those skilled in the art, and the general principles defined herein can be applied to other embodiments and applications without departing from the spirit and scope of this application. Therefore, this application is not limited to the embodiments shown, but rather to the widest scope consistent with the claims.

[0027] Currently, common methods for detecting metal contamination include chemical detection methods and electrical detection methods. Chemical detection methods include X-ray diffraction, EDX, TXRF, ICP-MS, and Raman spectroscopy, but these methods are independent of product manufacturing and cannot directly assess the impact of metal contamination on the chip. Conventional electrical detection methods monitor parameters such as gate oxide breakdown voltage, leakage current, and junction leakage current, but they are not sensitive or fast enough.

[0028] Based on this, the technical solution of this application provides a new method for detecting metal contamination. By monitoring changes in electron mobility, the influence of metal cations in the device can be reflected. When there are metal impurities in the channel of the semiconductor structure, electrons are attracted by metal cations after the device is turned on, resulting in a decrease in electron mobility. Electron mobility can be calculated by transconductance. Compared with existing detection methods, the detection method of this application is compatible with WAT electrical testing, and is simple, efficient, accurate and sensitive.

[0029] refer to Figure 1 This application provides a method for testing metal contamination in semiconductor structures, comprising:

[0030] Step S1: Provide a semiconductor structure to be tested and a reference semiconductor structure. Both the semiconductor structure to be tested and the reference semiconductor structure include a gate terminal, a source terminal, a drain terminal, and a substrate terminal, and the reference semiconductor structure has a preset metal content.

[0031] Step S2: Keep the voltages at the drain, source, and substrate of the semiconductor structure under test and the reference semiconductor structure constant, and ensure that the voltage at the drain is greater than the voltages at the source and the substrate.

[0032] Step S3: Change the voltage at the gate terminals of the semiconductor structure under test and the control semiconductor structure from a first preset value to a second preset value, and obtain the relationship between the voltage at the gate terminals of the semiconductor structure under test and the control semiconductor structure and the current at the drain terminals, respectively.

[0033] Step S4: Based on the relationship between the voltage at the gate terminal and the current at the drain terminal, obtain the transconductance of the semiconductor structure under test and the control semiconductor structure, respectively.

[0034] Step S5: Based on the transconductance of the semiconductor structure under test and the control semiconductor structure, obtain the electron mobility of the semiconductor structure under test and the control semiconductor structure, and then obtain the metal contamination status of the semiconductor structure under test.

[0035] In step S1, the semiconductor structure under test is formed using a front-gate process, and the photoresist process in the front-gate process creates ppb-level metal contamination in the semiconductor structure under test. Specifically, the metal contamination is metal ion contamination in the channel of the semiconductor structure under test. The semiconductor structure under test and the control semiconductor structure have the same structure and can be any semiconductor device structure with a channel structure. For example, it can be NMOS or PMOS; this embodiment uses NMOS as an example for illustration. The manufacturing processes of the semiconductor structure under test and the control semiconductor structure are the same, the difference being that the metal content in the photoresist used to fabricate the semiconductor structure under test is unknown, while the metal content in the photoresist used to fabricate the control semiconductor structure is preset, and in this embodiment, the preset metal content is the maximum permissible metal content.

[0036] refer to Figure 2 The semiconductor structure under test and the reference semiconductor structure in this application embodiment both include a gate terminal G, a source terminal S, a drain terminal D, and a substrate terminal SUB. The gate terminal G is located on the substrate terminal SUB, and the source terminal S and the drain terminal D are respectively located in the substrate terminals SUB on both sides of the gate terminal G. The gate terminal G may include a gate oxide layer and a gate located on the gate oxide layer. The two sidewalls of the gate terminal G also include sidewalls.

[0037] refer to Figure 3 During the test, the voltages at the drain terminal D, source terminal S, and substrate terminal SUB of the semiconductor structure under test and the control semiconductor structure are kept constant, and the voltage V at the drain terminal D is... D The voltage V greater than that at the source terminal S S and the voltage V at the substrate terminal SUB SUB In some embodiments, the source terminal S and substrate terminal SUB of both the semiconductor structure under test and the reference semiconductor structure are grounded, i.e., the voltage V is... S and the V SUn The value is 0. The voltage V at the drain terminal D is 0. D The size can be determined according to the actual situation, for example, the voltage V at the drain terminal D. D The value is 0.05V.

[0038] During testing, the voltage V at the gate terminal G of the semiconductor structure under test and the control semiconductor structure is increased. G The current at the drain terminal D changes from a first preset value to a second preset value. In this embodiment, the second preset value is greater than the first preset value, that is, the voltage V at the gate terminal G is greater than the first preset value. G The value increases from the first preset value to the second preset value, where the first preset value can be 0. In other embodiments, the second preset value is less than the first preset value, that is, the voltage V at the gate terminal G. G The voltage V at the gate terminal G of the semiconductor structure under test and the control semiconductor structure gradually decreases from large to small. As an example, the voltage V at the gate terminal G of the semiconductor structure under test and the control semiconductor structure are... G The voltage increases from 0 to 100V, with an increment (Step) of 0.05V.

[0039] The voltage V at the gate terminal G of the semiconductor structure under test and the reference semiconductor structure G During the process of changing to the second preset value, the drain current I at the end D of the semiconductor structure under test and the control semiconductor structure are obtained respectively. d This allows for the acquisition of the voltage V at the gate terminal G of the semiconductor structure under test and the control semiconductor structure. G The current I at the drain terminal D d The relationship between the gate terminal G and the voltage V. G The current I at the drain terminal D d The relationship between them can be obtained through curve fitting. As an example, the voltage V at the gate terminal G of the semiconductor structure under test... G and the current I at the drain terminal D d The relationship curve a is as follows Figure 4 As shown.

[0040] The voltage V at the gate terminal G of the semiconductor structure under test G Current I at drain terminal D d Differentiating the relationship between the two, the transconductance G of the semiconductor structure under test is obtained. m And the voltage V at the gate terminal G of the control semiconductor structure. G Current I at drain terminal D d By differentiating the relationship between the two semiconductor structures, the transconductance G of the semiconductor structure under test and the control semiconductor structure can be obtained respectively. m The transconductance G m The voltage V at the gate terminal G G and the current I at the drain terminal D d The relationship between them is as follows: As an example, the transconductance G of the semiconductor structure under test m Curve b, for example Figure 4 As shown.

[0041] Finally, based on the transconductance G of the semiconductor structure to be measured and the control semiconductor structure m , the electron mobility μ of the semiconductor structure to be measured and the control semiconductor structure is obtained n , and then the metal contamination situation of the semiconductor structure to be measured is obtained. The calculation method of the electron mobility μ n is as follows:

[0042]

[0043] where μ n is the electron mobility of the semiconductor structure to be measured or the control semiconductor structure. G m is the transconductance of the semiconductor structure to be measured or the control semiconductor structure, which is obtained by taking the derivative of the relationship between the voltage at the gate terminal and the current at the drain terminal of the semiconductor structure to be measured or the control semiconductor structure. V d is the drain voltage of the semiconductor structure to be measured or the control semiconductor structure. C ox is the gate capacitance of the semiconductor structure to be measured or the control semiconductor structure. L is the length of the channel of the semiconductor structure to be measured or the control semiconductor structure. W is the width of the gate of the semiconductor structure to be measured or the control semiconductor structure. When the structure of the semiconductor structure to be measured or the control semiconductor structure is determined, C ox , L, and W are known values.

[0044] If the channel of the semiconductor structure contains metal impurities (metal cations), when the device is turned on, electrons are attracted by the metal cations, which in turn leads to a decrease in the electron mobility. Therefore, in the embodiments of the present application, the metal contamination situation of the semiconductor structure to be measured can be obtained based on the magnitude of the electron mobility. The specific method may include: comparing the electron mobility μ of the semiconductor structure to be measured and the control semiconductor structure n , if the electron mobility μ of the semiconductor structure to be measured n is greater than or equal to the electron mobility μ of the control semiconductor structure n , then the metal contamination test situation of the semiconductor structure to be measured meets the standard; if the electron mobility μ of the semiconductor structure to be measured n is less than the electron mobility μ of the control semiconductor structure n , then the metal contamination test situation of the semiconductor structure to be measured fails.

[0045] The test effects of the existing detection method and the detection method of the embodiments of the present application are compared below.

[0046] Figure 5 )]] Figure 5The figures show the test results of the Jleak and GLK methods. The Jleak method uses reverse leakage current testing to reflect metal contamination, while the GLK method uses grounded source / drain and substrate terminals, with voltage applied to the gate terminal to test the leakage current between the gate and substrate. In the figures, Normal PR represents the photoresist used in fabricating the semiconductor structure under test, and High Metal PR represents the photoresist used in fabricating the control semiconductor structure. Normal PR has an Fe content of less than 1 ppb, while High Metal PR has an Fe content greater than 6 ppb. As shown in the figures, the detection results obtained using the Jleak and GLK methods for testing the semiconductor structure under test and the control semiconductor structure show little difference. Therefore, the sensitivity of the Jleak and GLK methods for qualitative analysis of metal content is not high.

[0047] Figure 6 This image shows the test results for metal contamination in semiconductor structures according to an embodiment of this application. Compared to the Jleak and GLK methods, the test method of this embodiment can significantly distinguish the data of the semiconductor structure under test and the control semiconductor structure. Therefore, the method for testing metal contamination in semiconductor structures according to this embodiment can qualitatively reflect the metal content at the ppb level and has high sensitivity.

[0048] In summary, after reading this application, those skilled in the art will understand that the foregoing application content is presented by way of example only and is not restrictive. Although not explicitly stated herein, those skilled in the art will understand that this application is intended to encompass various reasonable changes, improvements, and modifications to the embodiments. These changes, improvements, and modifications are all within the spirit and scope of the exemplary embodiments of this application.

[0049] It should be understood that the term "and / or" as used in this embodiment includes any or all combinations of one or more of the associated listed items. When an element such as a layer, region, or substrate is referred to as being "on" another element, it may be directly on the other element, or there may be intermediate elements present. Conversely, the term "directly" indicates the absence of intermediate elements. It should also be understood that the terms "comprising," "including," "including," or "comprises," as used in this application, specify the presence of the described features, integrals, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or groups thereof.

[0050] It should also be understood that although the terms first, second, third, etc., may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. Therefore, without departing from the teachings of this application, a first element in some embodiments may be referred to as a second element in other embodiments. The same reference numerals or the same reference signs denote the same elements throughout the specification.

[0051] Furthermore, this application specification describes exemplary embodiments by referring to idealized exemplary cross-sectional views and / or plan views and / or perspective views. Therefore, differences from the illustrated shapes are foreseeable due to factors such as manufacturing techniques and / or tolerances. Thus, exemplary embodiments should not be construed as limited to the shapes of the regions shown herein, but should include deviations in shape caused, for example, by manufacturing processes. For instance, etched areas shown as rectangular typically have circular or curved features. Therefore, the regions shown in the figures are substantially schematic, and their shapes are not intended to illustrate the actual shape of the regions of the device, nor are they intended to limit the scope of the exemplary embodiments.

Claims

1. A method for testing metal contamination in semiconductor structures, characterized in that, include: A semiconductor structure to be tested and a reference semiconductor structure are provided. Both the semiconductor structure to be tested and the reference semiconductor structure include a gate terminal, a source terminal, a drain terminal and a substrate terminal, and the reference semiconductor structure has a preset metal content. The voltages at the drain, source, and substrate of the semiconductor structure under test and the control semiconductor structure are kept constant, and the voltage at the drain is greater than the voltages at the source and the substrate. The voltage at the gate terminals of the semiconductor structure under test and the control semiconductor structure is changed from a first preset value to a second preset value, and the relationship between the voltage at the gate terminals of the semiconductor structure under test and the control semiconductor structure and the current at the drain terminals is obtained respectively. Based on the relationship between the voltage at the gate terminal and the current at the drain terminal, the transconductance of the semiconductor structure under test and the control semiconductor structure are obtained respectively. Based on the transconductance of the semiconductor structure under test and the control semiconductor structure, the electron mobility of the semiconductor structure under test and the control semiconductor structure is obtained, and then the metal contamination status of the semiconductor structure under test is obtained.

2. The method for testing metal contamination in semiconductor structures according to claim 1, characterized in that, The method for obtaining the electron mobility is as follows: wherein μ n is the electron mobility of the semiconductor structure under test or the control semiconductor structure, G m is the transconductance of the semiconductor structure under test or the control semiconductor structure, V d is the drain voltage of the semiconductor structure under test or the control semiconductor structure, C ox is the gate capacitance of the semiconductor structure under test or the control semiconductor structure, L is the length of the channel of the semiconductor structure under test or the control semiconductor structure, and W is the width of the gate of the semiconductor structure under test or the control semiconductor structure.

3. The method for testing metal contamination in semiconductor structures according to claim 2, characterized in that, The method for obtaining the transconductance of the semiconductor structure under test and the reference semiconductor structure includes: The transconductance of the semiconductor structure under test is obtained by differentiating the relationship between the voltage at the gate terminal and the current at the drain terminal. The transconductance of the reference semiconductor structure is obtained by differentiating the relationship between the voltage at the gate terminal and the current at the drain terminal.

4. The method for testing metal contamination in semiconductor structures according to claim 1, characterized in that, The preset metal content is the maximum permissible metal content; the method for obtaining the metal contamination status of the semiconductor structure under test includes: comparing the electron mobility of the semiconductor structure under test and the control semiconductor structure, and confirming that the electron mobility of the semiconductor structure under test is greater than or equal to the electron mobility of the control semiconductor structure, then the metal contamination test status of the semiconductor structure under test is qualified.

5. The method for testing metal contamination in semiconductor structures according to claim 4, characterized in that, If the electron mobility of the semiconductor structure under test is confirmed to be less than that of the control semiconductor structure, then the metal contamination test of the semiconductor structure under test is considered to be exceeding the standard.

6. The method for testing metal contamination in semiconductor structures according to claim 1, characterized in that, Both the source and substrate ends of the semiconductor structure under test and the control semiconductor structure are grounded.

7. The method for testing metal contamination in semiconductor structures according to claim 1, characterized in that, The voltage at the gate terminals of the semiconductor structure under test and the control semiconductor structure increases from the first preset value to the second preset value, where the first preset value is 0.

8. The method for testing metal contamination in semiconductor structures according to claim 1, characterized in that, The gate terminal is located on the substrate terminal, and the source terminal and the drain terminal are respectively located in the substrate terminals on both sides of the gate terminal. The gate terminal includes a gate oxide layer and a gate located on the gate oxide layer.

9. The method for testing metal contamination in semiconductor structures according to claim 8, characterized in that, The semiconductor structure under test and the reference semiconductor structure are NMOS or PMOS.

10. The method for testing metal contamination in semiconductor structures according to claim 1, characterized in that, The semiconductor structure under test is formed by a front gate process, and the metal contamination is ppb-level metal contamination caused by the photoresist process.

11. The method for testing metal contamination in semiconductor structures according to claim 10, characterized in that, The metal contamination refers to metal ion contamination in the channel of the semiconductor structure under test.

Images