Light emitting diode epitaxial wafer and preparation method thereof, LED

Abstract

This invention discloses a light-emitting diode (LED) epitaxial wafer and its fabrication method. The LED epitaxial wafer includes a substrate and a nucleation layer, an intrinsic GaN layer, an N-type semiconductor layer, a multiple quantum well layer, an electron blocking layer, and a P-type semiconductor layer sequentially stacked on the substrate. The N-type semiconductor layer includes a first SiInGaN layer, a second SiInAlGaN layer, a third SiInAlGaN layer, a fourth SiAlGaN layer, and a fifth SiAlGaN layer sequentially stacked on the intrinsic GaN layer. The LED epitaxial wafer provided by this invention can improve the uniformity of the emission brightness wavelength distribution, release underlying stress, improve the antistatic capability of the LED, and improve luminous efficiency.

Description

Technical Field

[0001] This invention relates to the field of optoelectronic technology, and in particular to a light-emitting diode epitaxial wafer and its preparation method, and LEDs. Background Technology

[0002] Currently, GaN-based light-emitting diodes (LEDs) are widely used in solid-state lighting and display fields, attracting increasing attention. GaN-based LEDs have achieved industrial-scale production and are used in backlights, general lighting, and landscape lighting.

[0003] Existing light-emitting diode epitaxial wafer structures include: a substrate, and a nucleation layer, an intrinsic GaN layer, an N-type semiconductor layer, a multiple quantum well layer, an electron blocking layer, and a P-type semiconductor layer sequentially grown on the substrate. The inventors have discovered the following problems:

[0004] Traditional N-type semiconductor layers have high concentrations of Si doping, requiring relatively high growth temperatures and rotation speeds. Furthermore, due to the warpage and stress accumulated during the growth of the preceding nucleation and intrinsic GaN layers, the warpage stress during N-type semiconductor layer growth is significant, leading to uneven Si doping distribution, poor lattice quality, and consequently, uneven operating voltage distribution and poor electrostatic discharge immunity. Moreover, the accumulation of defects and stress in the multi-quantum-well region can become non-radiative recombination centers, affecting luminescence efficiency.

[0005] Furthermore, the excessively fast movement speed of electrons and their poor expansion ability, coupled with the relatively slow movement speed of holes, leads to uneven voltage distribution, poor antistatic properties, and affects the luminous efficiency and uniformity of luminous brightness. It also makes electron overflow problems more likely to occur. Summary of the Invention

[0006] The technical problem to be solved by the present invention is to provide a light-emitting diode epitaxial wafer that can overcome the shortcomings of the above-mentioned related technologies.

[0007] The technical problem to be solved by the present invention is to provide a method for preparing an epitaxial wafer of a light-emitting diode, which has a simple process and can stably produce an epitaxial wafer of a light-emitting diode with good luminous efficiency.

[0008] To solve the above-mentioned technical problems, the present invention provides a light-emitting diode epitaxial wafer, comprising a substrate and a nucleation layer, an intrinsic GaN layer, an N-type semiconductor layer, a multiple quantum well layer, an electron blocking layer, and a P-type semiconductor layer sequentially stacked on the substrate.

[0009] The N-type semiconductor layer includes a first SiInGaN layer, a second SiInAlGaN layer, a third SiInAlGaN layer, a fourth SiAlGaN layer, and a fifth SiAlGaN layer, which are sequentially stacked on the intrinsic GaN layer.

[0010] In one embodiment, the Si doping concentration of the first SiInGaN layer > the Si doping concentration of the second SiInAlGaN layer > the Si doping concentration of the third SiInAlGaN layer > the Si doping concentration of the fourth SiAlGaN layer > the Si doping concentration of the fifth SiAlGaN layer;

[0011] The In doping concentration of the first SiInGaN layer is greater than the In doping concentration of the second SiInAlGaN layer, which is greater than the In doping concentration of the third SiInAlGaN layer.

[0012] The Al doping concentration of the second SiInAlGaN layer is less than the Al doping concentration of the third SiInAlGaN layer, which is less than the Al doping concentration of the fourth SiAlGaN layer, which is less than the Al doping concentration of the fifth SiAlGaN layer.

[0013] Preferably, the Si doping concentration of the first SiInGaN layer is 1×10⁻⁶. 20 atoms / cm 3 -1×10 21 atoms / cm 3 ;

[0014] The Si doping concentration of the second SiInAlGaN layer is 1×10⁻⁶. 19 atoms / cm 3 -1×10 20 atoms / cm 3 ;

[0015] The Si doping concentration of the third SiInAlGaN layer is 1×10⁻⁶. 18 atoms / cm 3 -1×10 19 atoms / cm 3 ;

[0016] The Si doping concentration of the fourth SiAlGaN layer is 1×10⁻⁶. 17 atoms / cm 3 -1×10 18 atoms / cm 3 ;

[0017] The Si doping concentration of the fifth SiAlGaN layer is 1×10⁻⁶. 16 atoms / cm 3 -1×10 17 atoms / cm 3 .

[0018] Preferably, the In doping concentration of the first SiInGaN layer is 1×10⁻⁶.2 atoms / cm 3 -5×10 2 atoms / cm 3 ;

[0019] The In doping concentration of the second SiInAlGaN layer is 5 × 10 atoms / cm 3 -1×10 2 atoms / cm 3 ;

[0020] The In doping concentration of the third SiInAlGaN layer is 1×10 atoms / cm 3 -5×10 atoms / cm 3 .

[0021] Preferably, the Al doping concentration of the second SiInAlGaN layer is 1×10⁻⁶. 2 atoms / cm 3 -1×10 3 atoms / cm 3 ;

[0022] The Al doping concentration of the third SiInAlGaN layer is 1×10⁻⁶. 3 atoms / cm 3 -1×10 4 atoms / cm 3 ;

[0023] The Al doping concentration of the fourth SiAlGaN layer is 1×10⁻⁶. 4 atoms / cm 3 -1×10 5 atoms / cm 3 ;

[0024] The Al doping concentration of the fifth SiAlGaN layer is 1×10⁻⁶. 5 atoms / cm 3 -1×10 6 atoms / cm 3 .

[0025] To address the above problems, this invention provides a method for fabricating a light-emitting diode epitaxial wafer, comprising the following steps:

[0026] S1. Prepare the substrate;

[0027] S2. Sequentially deposit a nucleation layer, an intrinsic GaN layer, an N-type semiconductor layer, a multiple quantum well layer, an electron blocking layer, and a P-type semiconductor layer on the substrate;

[0028] Depositing an N-type semiconductor layer on the intrinsic GaN layer includes:

[0029] A first SiInGaN layer, a second SiInAlGaN layer, a third SiInAlGaN layer, a fourth SiAlGaN layer, and a fifth SiAlGaN layer are sequentially deposited on the intrinsic GaN layer to obtain the N-type semiconductor layer.

[0030] In one embodiment, the growth temperature of the first SiInGaN layer is < the growth temperature of the second SiInAlGaN layer < the growth temperature of the third SiInAlGaN layer < the growth temperature of the fourth SiAlGaN layer < the growth temperature of the fifth SiAlGaN layer.

[0031] The growth pressure of the first SiInGaN layer is greater than the growth pressure of the second SiInAlGaN layer, the third SiInAlGaN layer, the fourth SiAlGaN layer, or the fifth SiAlGaN layer.

[0032] Preferably, the growth temperature of the first SiInGaN layer is 1000℃-1050℃;

[0033] The growth temperature of the second SiInAlGaN layer, the third SiInAlGaN layer, or the fourth SiAlGaN layer is 1050℃-1100℃;

[0034] The growth temperature of the fifth SiAlGaN layer is 1100℃-1150℃.

[0035] Preferably, the growth pressure of the first SiInGaN layer is 200 torr-250 torr;

[0036] The growth pressure of the second, third, fourth, or fifth SiInAlGaN layer is 100 torr-200 torr.

[0037] Accordingly, the present invention also provides an LED, which includes the above-described light-emitting diode epitaxial wafer.

[0038] Implementing this invention has the following beneficial effects:

[0039] The light-emitting diode epitaxial wafer provided by this invention comprises a first SiInGaN layer, a second SiInAlGaN layer, a third SiInAlGaN layer, a fourth SiAlGaN layer, and a fifth SiAlGaN layer in its N-type semiconductor layer. The N-type semiconductor layer can slow down the current flow rate and ensure uniform current transmission through variations in barrier height and N-type doping concentration. This also facilitates the expansion of charge carriers, thereby reducing the diode's operating voltage, lowering energy consumption, effectively mitigating poor electrostatic discharge (ESD) performance caused by uneven charge carrier distribution, improving the ESD capability of the light-emitting diode, and effectively addressing the problem of uneven luminous brightness and wavelength caused by poor electron expansion into the multi-quantum-well layer, thus improving the uniformity of luminous brightness and wavelength distribution. Furthermore, it releases underlying stress, improves the lattice quality of the underlying layer, enhances the ESD capability of the light-emitting diode, and increases luminous efficiency. Attached Figure Description

[0040] Figure 1 This is a schematic diagram of the structure of the light-emitting diode epitaxial wafer provided by the present invention.

[0041] The structure consists of: substrate 1, nucleation layer 2, intrinsic GaN layer 3, N-type semiconductor layer 4, multiple quantum well layer 5, electron blocking layer 6, P-type semiconductor layer 7, first SiInGaN layer 41, second SiInAlGaN layer 42, third SiInAlGaN layer 43, fourth SiAlGaN layer 44, and fifth SiAlGaN layer 45. Detailed Implementation

[0042] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be described in further detail below.

[0043] Unless otherwise stated or in case of contradiction, the terms or phrases used herein shall have the following meanings:

[0044] In this invention, "preferred" is merely a description of a more effective implementation method or embodiment, and should be understood as not constituting a limitation on the scope of protection of this invention.

[0045] In this invention, the technical features described in an open-ended manner include both closed-ended technical solutions composed of the listed features and open-ended technical solutions that include the listed features.

[0046] In this invention, numerical ranges are involved, and unless otherwise specified, they include the two endpoints of the numerical range.

[0047] To address the above problems, the present invention provides a light-emitting diode epitaxial wafer, such as... Figure 1As shown, it includes a substrate 1 and a nucleation layer 2, an intrinsic GaN layer 3, an N-type semiconductor layer 4, a multiple quantum well layer 5, an electron blocking layer 6, and a P-type semiconductor layer 7 sequentially stacked on the substrate 1.

[0048] The N-type semiconductor layer 4 includes a first SiInGaN layer 41, a second SiInAlGaN layer 42, a third SiInAlGaN layer 43, a fourth SiAlGaN layer 44, and a fifth SiAlGaN layer 45, which are sequentially stacked on the intrinsic GaN layer 3.

[0049] In one embodiment, the Si doping concentration of the first SiInGaN layer 41 is greater than the Si doping concentration of the second SiInAlGaN layer 42, which is greater than the Si doping concentration of the third SiInAlGaN layer 43, which is greater than the Si doping concentration of the fourth SiAlGaN layer 44, which is greater than the Si doping concentration of the fifth SiAlGaN layer 45. Preferably, the Si doping concentration of the first SiInGaN layer 41 is 1 × 10⁻⁶. 20 atoms / cm 3 -1×10 21 atoms / cm 3 The Si doping concentration of the second SiInAlGaN layer 42 is 1×10⁻⁶. 19 atoms / cm 3 -1×10 20 atoms / cm 3 The Si doping concentration of the third SiInAlGaN layer 43 is 1×10⁻⁶. 18 atoms / cm 3 -1×10 19 atoms / cm 3 The Si doping concentration of the fourth SiAlGaN layer 44 is 1×10⁻⁶. 17 atoms / cm 3 -1×10 18 atoms / cm 3 The Si doping concentration of the fifth SiAlGaN layer 45 is 1×10⁻⁶. 16 atoms / cm 3 -1×10 17 atoms / cm 3 .

[0050] In one embodiment, the In doping concentration of the first SiInGaN layer 41 is greater than the In doping concentration of the second SiInAlGaN layer 42, which is greater than the In doping concentration of the third SiInAlGaN layer 43; preferably, the In doping concentration of the first SiInGaN layer 41 is 1×10⁻⁶. 2 atoms / cm3 -5×10 2 atoms / cm 3 The In doping concentration of the second SiInAlGaN layer 42 is 5 × 10 atoms / cm. 3 -1×10 2 atoms / cm 3 The In doping concentration of the third SiInAlGaN layer 43 is 1 × 10 atoms / cm. 3 -5×10 atoms / cm 3 .

[0051] In one embodiment, the Al doping concentration of the second SiInAlGaN layer 42 is less than the Al doping concentration of the third SiInAlGaN layer 43, which is less than the Al doping concentration of the fourth SiAlGaN layer 44, which is less than the Al doping concentration of the fifth SiAlGaN layer 45. Preferably, the Al doping concentration of the second SiInAlGaN layer 42 is 1 × 10⁻⁶. 2 atoms / cm 3 -1×10 3 atoms / cm 3 The Al doping concentration of the third SiInAlGaN layer 43 is 1×10⁻⁶. 3 atoms / cm 3 -1×10 4 atoms / cm 3 The Al doping concentration of the fourth SiAlGaN layer 44 is 1×10⁻⁶. 4 atoms / cm 3 -1×10 5 atoms / cm 3 The Al doping concentration of the fifth SiAlGaN layer 45 is 1×10⁻⁶. 5 atoms / cm 3 -1×10 6 atoms / cm 3 .

[0052] It should be noted that the potential barrier gradient of the five sub-layers of the N-type peninsula layer proposed in this invention increases. The sub-layers closer to the multi-quantum well layer 5 have higher Al content and lower In content, resulting in a higher barrier; conversely, the sub-layers farther from the multi-quantum well layer 5 have lower Al content and higher In content, resulting in a lower barrier. This gradient barrier change allows electrons to migrate from the low barrier layer to the high barrier layer, slowing down the current mobility and ensuring uniform current transmission. Charge carriers also spread more easily, thereby reducing the diode's operating voltage, lowering energy consumption, effectively mitigating the poor antistatic capability caused by uneven charge carrier distribution, improving the antistatic capability of the LED device, and effectively improving the problem of uneven luminous brightness and wavelength caused by poor electron expansion into the multi-quantum well layer 5, thus enhancing the uniformity of luminous brightness and wavelength distribution. Furthermore, the reduced Si concentration gradient also facilitates electron expansion.

[0053] Furthermore, in sublayers with higher Si doping concentrations, the In content is relatively higher, and the In atoms are larger, which can provide tensile stress, alleviate bottom layer warpage, and avoid uneven Si distribution caused by excessive warpage of the N-type semiconductor layer 4. The closer the sublayer is to the multi-quantum-well layer 5, the higher the Al content, the smaller the lattice constant of Al atoms, and the stronger the covalent bonds between Al and N atoms is compared to the Ga and N atoms. This maintains the integrity of the GaN lattice and reduces defect generation, resulting in better lattice quality in sublayers closer to the multi-quantum-well layer 5. Dislocation defects generated in the early growth stages are gradually annihilated and distorted as the lattice size decreases layer by layer.

[0054] In addition to the doping gradient characteristics, the N-type semiconductor layer 4 provided by the present invention also has the following characteristics:

[0055] Preferably, the nucleation layer 2 has a thickness of 20nm-100nm; the intrinsic GaN layer 3 has a thickness of 300nm-800nm; the N-type semiconductor layer 4 has a thickness of 1μm-3μm; the multi-quantum-well layer 5 is a periodic composite structure composed of quantum well layers and quantum barrier layers, wherein the thickness of a single quantum well layer is 2nm-5nm, and the thickness of a single quantum barrier layer is 6nm-15nm; the electron blocking layer 6 is Al a Ga 1-a N and In b Ga 1-b The structure consists of alternating N and Mg phases, with a value ranging from 0.05 to 0.2 and b value ranging from 0.1 to 0.5. The electron blocking layer 6 has a thickness of 20 nm to 100 nm, the P-type semiconductor layer 7 has a thickness of 200 nm to 300 nm, and the Mg doping concentration is 5 × 10⁻⁶. 17 atoms / cm 3 -1×10 20atoms / cm 3 .

[0056] In summary, the N-type semiconductor layer 4 provided by this invention can slow down the current flow rate and ensure uniform current transmission by changing the barrier height and N-type doping concentration. This also facilitates the expansion of charge carriers, thereby reducing the operating voltage of the diode, lowering energy consumption, effectively mitigating the poor antistatic capability caused by uneven charge carrier distribution, improving the antistatic capability of the light-emitting diode, effectively improving the problem of uneven luminous brightness and wavelength caused by poor electron expansion into the multi-quantum-well layer 5, and enhancing the uniformity of luminous brightness and wavelength distribution. Furthermore, it releases the underlying stress, improves the lattice quality of the underlying layer, enhances the antistatic capability of the light-emitting diode, and improves luminous efficiency.

[0057] Accordingly, the present invention provides a method for fabricating a light-emitting diode epitaxial wafer, comprising the following steps:

[0058] S1. Prepare substrate 1;

[0059] In one embodiment, the substrate 1 is selected as a sapphire substrate 1; the reaction chamber temperature is controlled at 1000℃-1200℃, the reaction chamber pressure is controlled at 200 torr-600 torr, and the substrate 1 is subjected to high-temperature annealing for 5 min-8 min in an H2 atmosphere. The above operation cleans the particles and oxides on the surface of the substrate 1.

[0060] S2. On the substrate 1, a nucleation layer 2, an intrinsic GaN layer 3, an N-type semiconductor layer 4, a multiple quantum well layer 5, an electron blocking layer 6, and a P-type semiconductor layer 7 are deposited sequentially.

[0061] In one implementation, step S2 includes the following steps:

[0062] S21. A nucleation layer 2 is grown on substrate 1.

[0063] Preferably, the nucleation layer 2 is made of AlGaN or AlN. This layer is mainly used to provide seed crystals, alleviate the lattice mismatch between the substrate 1 and the epitaxial layer, and improve the lattice quality of the epitaxial wafer; the reaction chamber temperature is controlled at 500℃-700℃, the reaction chamber pressure is controlled at 200 torr-400 torr, NH3 is introduced to provide the N source, N2 and H2 are used as carrier gases, TMGa is introduced as the Ga source, TMAl is introduced as the Al source, and AlGaN is grown as the nucleation layer 2.

[0064] S22. An intrinsic GaN layer 3 is grown on nucleation layer 2.

[0065] Preferably, the temperature of the reaction chamber is controlled at 1100℃-1150℃ and the pressure is 100 torr-500 torr; NH3 is introduced as the N source, N2 and H2 are used as carrier gases, and TMGa is introduced as the Ga source to grow the intrinsic GaN layer 3.

[0066] S23. Deposit an N-type semiconductor layer 4 on the intrinsic GaN layer 3, including:

[0067] The N-type semiconductor layer 4 is obtained by sequentially depositing a first SiInGaN layer 41, a second SiInAlGaN layer 42, a third SiInAlGaN layer 43, a fourth SiAlGaN layer 44, and a fifth SiAlGaN layer 45 on the intrinsic GaN layer 3.

[0068] In one embodiment, the growth temperature of the first SiInGaN layer 41 is less than the growth temperature of the second SiInAlGaN layer 42, which is less than the growth temperature of the third SiInAlGaN layer 43, which is less than the growth temperature of the fourth SiAlGaN layer 44, which is less than the growth temperature of the fifth SiAlGaN layer 45; and the growth pressure of the first SiInGaN layer 41 is greater than the growth pressure of the second SiInAlGaN layer 42, the third SiInAlGaN layer 43, the fourth SiAlGaN layer 44, or the fifth SiAlGaN layer 45. Preferably, the growth temperature of the first SiInGaN layer 41 is 1000℃-1050℃; the growth temperature of the second SiInAlGaN layer 42, the third SiInAlGaN layer 43, or the fourth SiAlGaN layer 44 is 1050℃-1100℃; and the growth temperature of the fifth SiAlGaN layer 45 is 1100℃-1150℃. Preferably, the growth pressure of the first SiInGaN layer 41 is 200 torr-250 torr; the growth pressure of the second SiInAlGaN layer 42, the third SiInAlGaN layer 43, the fourth SiAlGaN layer 44, or the fifth SiAlGaN layer 45 is 100 torr-200 torr.

[0069] It should be noted that among the five sub-layers of the N-type semiconductor layer 4, the sub-layers closer to the multi-quantum-well layer 5 have higher growth temperatures and lower growth pressures. Furthermore, the sub-layers closer to the multi-quantum-well layer 5 have relatively higher Al content and lower growth pressures. The lower pressure can reduce the pre-reaction of Al, ensure stable reactions between Al and N elements, improve the lattice quality of the N-type semiconductor layer 4, enhance the anti-static capability of the light-emitting diode, and reduce the entry of defects into the multi-quantum-well region, which can become non-radiative recombination centers and affect luminous efficiency.

[0070] More preferably, the above five sublayers are prepared by the following method:

[0071] (1) Growth of the first SiInGaN layer 41: The reaction chamber temperature was controlled at 1060℃, the growth pressure was controlled at 200Torr, NH3 was introduced as the N source, N2 and H2 were introduced as the carrier gas, TMGa was introduced as the Ga source, TMIn was introduced as the In source, and SiH4 was introduced as the Si source to grow the first SiInGaN layer 41 with a thickness of 0.6μm.

[0072] (2) Growth of the second SiInAlGaN layer 42: The reaction chamber temperature was controlled at 1080℃, the growth pressure was controlled at 100Torr, NH3 was introduced as the N source, N2 and H2 were introduced as the carrier gas, TMGa was introduced as the Ga source, TMIn was introduced as the In source, TMAl was introduced as the Al source, and SiH4 was introduced as the Si source to grow the second SiInAlGaN layer 42 with a thickness of 0.6μm.

[0073] (3) Growth of the third SiInAlGaN layer 43: The reaction chamber temperature was controlled at 1100℃, the growth pressure was controlled at 100Torr, NH3 was introduced as the N source, N2 and H2 were introduced as the carrier gas, TMGa was introduced as the Ga source, TMIn was introduced as the In source, TMAl was introduced as the Al source, and SiH4 was introduced as the Si source to grow a third SiInAlGaN layer 43 with a thickness of 0.6μm.

[0074] (4) Growth of the fourth SiAlGaN layer 44: The reaction chamber temperature was controlled at 1120℃, the growth pressure was controlled at 100Torr, NH3 was introduced as the N source, N2 and H2 were introduced as the carrier gas, TMGa was introduced as the Ga source, TMAl was introduced as the Al source, and SiH4 was introduced as the Si source to grow the fourth SiAlGaN layer 44 with a thickness of 0.6μm.

[0075] (5) Growth of the fifth SiAlGaN layer 45: The reaction chamber temperature was controlled at 1140℃, the growth pressure was controlled at 100Torr, NH3 was introduced as the N source, N2 and H2 were introduced as the carrier gas, TMGa was introduced as the Ga source, TMAl was introduced as the Al source, and SiH4 was introduced as the Si source to grow the fifth SiAlGaN layer 45 with a thickness of 0.6μm.

[0076] S24, a multi-quantum well layer 5 grown on an N-type semiconductor layer 4.

[0077] The multiple quantum well layer 5 is the core structure for light emission in a light-emitting diode. Preferably, the multiple quantum well layer 5 is a periodic structure consisting of alternating InGaN quantum well layers and GaN quantum barrier layers, and the number of periods in the multiple quantum well layer 5 is 3-15.

[0078] During the growth of the multi-quantum well layer 5, the reaction chamber pressure is controlled at 100 torr-500 torr; the quantum well layer is grown first, with the reaction chamber temperature controlled at 700℃-800℃, N2 as the carrier gas, H2 shut off, NH3 providing the N source, TEGa introduced as the Ga source, and TMIn introduced as the In source; the quantum barrier layer is then grown, with the reaction chamber temperature controlled at 800℃-900℃, the In source shut off, H2 and N2 used as carrier gases, and TEGa introduced as the Ga source; the quantum well layer and quantum barrier layer are repeatedly stacked and grown periodically.

[0079] S25. An electron blocking layer 6 is grown on the multi-quantum well layer 5.

[0080] Preferably, the electron blocking layer 6 is Al. a Ga 1-a N and In b Ga 1-b The periodic structure of alternating N values, where a ranges from 0.05 to 0.2, b ranges from 0.1 to 0.5, and the number of periods is 3 to 15.

[0081] First, the growth temperature in the reaction chamber is controlled at 900℃-1000℃, and the pressure at 100 torr-500 torr. The N source is NH3, the Ga source can be TMGa, and the Al source can be TMAl. Al is then deposited. a Ga 1-a N layers; then, turn off the Al source, continue to introduce the Ga source, turn on the In source, and deposit In. b Ga 1-b N layer; Al a Ga 1-a N layers and In b Ga 1-b N-layer repeated stacking growth.

[0082] S26. Grow a P-type semiconductor layer 7 on the electron blocking layer 6.

[0083] Preferably, the growth temperature of the Mg-doped P-type semiconductor layer 7 is 800℃-1000℃, the growth pressure is 100 torr-300 torr, NH3 is introduced as the N source, the Ga source can be TMGa, and CP2Mg is introduced as the P-type dopant to grow a Mg-doped GaN layer.

[0084] Accordingly, the present invention also provides an LED comprising the aforementioned light-emitting diode epitaxial wafer. The photoelectric efficiency of the LED is effectively improved, and other electrical properties are also excellent.

[0085] The present invention is further illustrated below with specific embodiments:

[0086] Example 1

[0087] This embodiment provides a light-emitting diode epitaxial wafer, including a substrate and a nucleation layer, an intrinsic GaN layer, an N-type semiconductor layer, a multiple quantum well layer, an electron blocking layer, and a P-type semiconductor layer sequentially stacked on the substrate;

[0088] The N-type semiconductor layer includes a first SiInGaN layer, a second SiInAlGaN layer, a third SiInAlGaN layer, a fourth SiAlGaN layer, and a fifth SiAlGaN layer, which are sequentially stacked on the intrinsic GaN layer.

[0089] The Si doping concentration of the first SiInGaN layer is 5 × 10⁻⁶. 20 atoms / cm 3 The In doping concentration is 3×10 2 atoms / cm 3 The growth temperature is 1060℃; the growth pressure is 200 torr.

[0090] The Si doping concentration of the second SiInAlGaN layer is 5 × 10⁻⁶. 19 atoms / cm 3 The In doping concentration is 8 × 10 atoms / cm 3 The Al doping concentration is 5 × 10⁻⁶. 2 atoms / cm 3 The growth temperature is 1080℃; the growth pressure is 100 torr.

[0091] The Si doping concentration of the third SiInAlGaN layer is 5 × 10⁻⁶. 18 atoms / cm 3 The In doping concentration is 3 × 10 atoms / cm 3 The Al doping concentration is 5 × 10⁻⁶. 3 atoms / cm 3 The growth temperature is 1100℃; the growth pressure is 100 torr.

[0092] The Si doping concentration of the fourth SiAlGaN layer is 5 × 10⁻⁶. 17 atoms / cm 3 The Al doping concentration is 5 × 10⁻⁶. 4 atoms / cm 3 The growth temperature is 1120℃; the growth pressure is 100 torr.

[0093] The Si doping concentration of the fifth SiAlGaN layer is 5 × 10⁻⁶. 16 atoms / cm 3 The Al doping concentration is 5 × 10⁻⁶. 5 atoms / cm3 The growth temperature is 1140℃; the growth pressure is 100 torr.

[0094] Example 2

[0095] This embodiment provides a light-emitting diode epitaxial wafer, including a substrate and a nucleation layer, an intrinsic GaN layer, an N-type semiconductor layer, a multiple quantum well layer, an electron blocking layer, and a P-type semiconductor layer sequentially stacked on the substrate;

[0096] The N-type semiconductor layer includes a first SiInGaN layer, a second SiInAlGaN layer, a third SiInAlGaN layer, a fourth SiAlGaN layer, and a fifth SiAlGaN layer, which are sequentially stacked on the intrinsic GaN layer.

[0097] The Si doping concentration of the first SiInGaN layer is 1×10⁻⁶. 20 atoms / cm 3 The In doping concentration is 1×10 2 atoms / cm 3 The growth temperature is 1060℃; the growth pressure is 200 torr.

[0098] The Si doping concentration of the second SiInAlGaN layer is 1×10⁻⁶. 19 atoms / cm 3 The In doping concentration is 1×10 atoms / cm 3 The Al doping concentration is 1×10 2 atoms / cm 3 The growth temperature is 1080℃; the growth pressure is 100 torr.

[0099] The Si doping concentration of the third SiInAlGaN layer is 1×10⁻⁶. 18 atoms / cm 3 The In doping concentration is 1×10 atoms / cm 3 The Al doping concentration is 1×10 3 atoms / cm 3 The growth temperature is 1100℃; the growth pressure is 100 torr.

[0100] The Si doping concentration of the fourth SiAlGaN layer is 1×10⁻⁶. 17 atoms / cm 3 The Al doping concentration is 1×10 4 atoms / cm 3 The growth temperature is 1120℃; the growth pressure is 100 torr.

[0101] The Si doping concentration of the fifth SiAlGaN layer is 1×10⁻⁶. 16 atoms / cm 3 The Al doping concentration is 1×10 5 atoms / cm 3 The growth temperature is 1140℃; the growth pressure is 100 torr.

[0102] Example 3

[0103] This embodiment provides a light-emitting diode epitaxial wafer, including a substrate and a nucleation layer, an intrinsic GaN layer, an N-type semiconductor layer, a multiple quantum well layer, an electron blocking layer, and a P-type semiconductor layer sequentially stacked on the substrate;

[0104] The N-type semiconductor layer includes a first SiInGaN layer, a second SiInAlGaN layer, a third SiInAlGaN layer, a fourth SiAlGaN layer, and a fifth SiAlGaN layer, which are sequentially stacked on the intrinsic GaN layer.

[0105] The Si doping concentration of the first SiInGaN layer is 1×10⁻⁶. 21 atoms / cm 3 The In doping concentration is 5×10⁻⁶. 2 atoms / cm 3 The growth temperature is 1060℃; the growth pressure is 200 torr.

[0106] The Si doping concentration of the second SiInAlGaN layer is 1×10⁻⁶. 20 atoms / cm 3 The In doping concentration is 100 atoms / cm. 3 The Al doping concentration is 1×10 3 atoms / cm 3 The growth temperature is 1080℃; the growth pressure is 100 torr.

[0107] The Si doping concentration of the third SiInAlGaN layer is 1×10⁻⁶. 19 atoms / cm 3 The In doping concentration is 5 × 10 atoms / cm 3 The Al doping concentration is 1×10 4 atoms / cm 3 The growth temperature is 1100℃; the growth pressure is 100 torr.

[0108] The Si doping concentration of the fourth SiAlGaN layer is 1×10⁻⁶. 18 atoms / cm 3 The Al doping concentration is 1×105 atoms / cm 3 The growth temperature is 1120℃; the growth pressure is 100 torr.

[0109] The Si doping concentration of the fifth SiAlGaN layer is 1×10⁻⁶. 17 atoms / cm 3 The Al doping concentration is 1×10 6 atoms / cm 3 The growth temperature is 1140℃; the growth pressure is 100 torr.

[0110] Comparative Example 1

[0111] This embodiment provides a light-emitting diode epitaxial wafer, which differs from Embodiment 1 in that the N-type semiconductor layer does not have a first SiInGaN layer. All other aspects are the same as in Embodiment 1.

[0112] Comparative Example 2

[0113] This embodiment provides a light-emitting diode epitaxial wafer, which differs from Embodiment 1 in that the N-type semiconductor layer does not have a second SiInAlGaN layer. All other aspects are the same as in Embodiment 1.

[0114] Comparative Example 3

[0115] This embodiment provides a light-emitting diode epitaxial wafer, which differs from Embodiment 1 in that the N-type semiconductor layer does not have a third SiInAlGaN layer. All other aspects are the same as in Embodiment 1.

[0116] Comparative Example 4

[0117] This embodiment provides a light-emitting diode epitaxial wafer, which differs from Embodiment 1 in that the N-type semiconductor layer does not have a fourth SiAlGaN layer. All other aspects are the same as in Embodiment 1.

[0118] Comparative Example 5

[0119] This embodiment provides a light-emitting diode epitaxial wafer, which differs from Embodiment 1 in that the N-type semiconductor layer does not have a fifth SiAlGaN layer. All other aspects are the same as in Embodiment 1.

[0120] Comparative Example 6

[0121] This embodiment provides a light-emitting diode epitaxial wafer, including a substrate and a nucleation layer, an intrinsic GaN layer, an N-type semiconductor layer, a multiple quantum well layer, an electron blocking layer, and a P-type semiconductor layer sequentially stacked on the substrate; the N-type semiconductor layer is a Mg-doped GaN layer.

[0122] The light-emitting diode epitaxial wafers prepared in Examples 1-3 and Comparative Examples 1-6 were fabricated into 10*24mil chips using the same chip process conditions. 300 LED chips were randomly selected from each example, and the photoelectric performance of the chips was tested. The specific test results are shown in Table 1.

[0123] Table 1 shows the performance test results of the LEDs prepared in Examples 1-3 and Comparative Examples 1-6.

[0124]

[0125]

[0126] The results above show that the luminous efficiency, operating voltage, antistatic capability, and voltage and brightness distribution uniformity of the light-emitting diode (LED) fabricated using the epitaxial structure proposed in this invention are significantly better than those of the comparative example. The LED epitaxial wafer provided by this invention comprises a first SiInGaN layer, a second SiInAlGaN layer, a third SiInAlGaN layer, a fourth SiAlGaN layer, and a fifth SiAlGaN layer in its N-type semiconductor layer. The N-type semiconductor layer can slow down the current flow rate and ensure uniform current transmission through variations in barrier height and N-type doping concentration. This also facilitates the expansion of charge carriers, thereby reducing the diode's operating voltage, lowering energy consumption, effectively mitigating poor antistatic capability caused by uneven charge carrier distribution, improving the antistatic capability of the LED, effectively addressing the problem of uneven luminous brightness and wavelength caused by poor electron expansion into the multi-quantum-well layer, and improving the uniformity of luminous brightness and wavelength distribution. Furthermore, it releases underlying stress, improves the lattice quality of the underlying layer, enhances the antistatic capability of the LED, and increases luminous efficiency.

[0127] The above description is a preferred embodiment of the invention. It should be noted that, for those skilled in the art, several improvements and modifications can be made without departing from the principle of the invention, and these improvements and modifications are also considered to be within the scope of protection of the invention.

Claims

1. A light-emitting diode epitaxial wafer, characterized in that, It includes a substrate and a nucleation layer, an intrinsic GaN layer, an N-type semiconductor layer, a multiple quantum well layer, an electron blocking layer, and a P-type semiconductor layer sequentially stacked on the substrate; The N-type semiconductor layer includes a first SiInGaN layer, a second SiInAlGaN layer, a third SiInAlGaN layer, a fourth SiAlGaN layer, and a fifth SiAlGaN layer, which are sequentially stacked on the intrinsic GaN layer. The Si doping concentration of the first SiInGaN layer > the Si doping concentration of the second SiInAlGaN layer > the Si doping concentration of the third SiInAlGaN layer > the Si doping concentration of the fourth SiAlGaN layer > the Si doping concentration of the fifth SiAlGaN layer; The In doping concentration of the first SiInGaN layer is greater than the In doping concentration of the second SiInAlGaN layer, which is greater than the In doping concentration of the third SiInAlGaN layer. The Al doping concentration of the second SiInAlGaN layer is less than the Al doping concentration of the third SiInAlGaN layer, which is less than the Al doping concentration of the fourth SiAlGaN layer, which is less than the Al doping concentration of the fifth SiAlGaN layer.

2. The light-emitting diode epitaxial wafer as described in claim 1, characterized in that, The Si doping concentration of the first SiInGaN layer is 1×10⁻⁶. 20 atoms / cm 3 -1×10 21 atoms / cm 3 ; The Si doping concentration of the second SiInAlGaN layer is 1×10⁻⁶. 19 atoms / cm 3 -1×10 20 atoms / cm 3 ; The Si doping concentration of the third SiInAlGaN layer is 1×10⁻⁶. 18 atoms / cm 3 -1×10 19 atoms / cm 3 ; The Si doping concentration of the fourth SiAlGaN layer is 1×10⁻⁶. 17 atoms / cm 3 -1×10 18 atoms / cm 3 ; The Si doping concentration of the fifth SiAlGaN layer is 1×10⁻⁶. 16 atoms / cm 3 -1×10 17 atoms / cm 3 .

3. The light-emitting diode epitaxial wafer as described in claim 1, characterized in that, The In doping concentration of the first SiInGaN layer is 1×10⁻⁶. 2 atoms / cm 3 -5×10 2 atoms / cm 3 ; The In doping concentration of the second SiInAlGaN layer is 5 × 10 atoms / cm 3 -1×10 2 atoms / cm 3 ; The In doping concentration of the third SiInAlGaN layer is 1×10 atoms / cm 3 -5×10 atoms / cm 3 .

4. The light-emitting diode epitaxial wafer as described in claim 1, characterized in that, The Al doping concentration of the second SiInAlGaN layer is 1×10⁻⁶. 2 atoms / cm 3 -1×10 3 atoms / cm 3 ; The Al doping concentration of the third SiInAlGaN layer is 1×10⁻⁶. 3 atoms / cm 3 -1×10 4 atoms / cm 3 ; The Al doping concentration of the fourth SiAlGaN layer is 1×10⁻⁶. 4 atoms / cm 3 -1×10 5 atoms / cm 3 ; The Al doping concentration of the fifth SiAlGaN layer is 1×10⁻⁶. 5 atoms / cm 3 -1×10 6 atoms / cm 3 .

5. A method for fabricating a light-emitting diode epitaxial wafer as described in any one of claims 1-4, characterized in that, Includes the following steps: S1. Prepare the substrate; S2. Sequentially deposit a nucleation layer, an intrinsic GaN layer, an N-type semiconductor layer, a multiple quantum well layer, an electron blocking layer, and a P-type semiconductor layer on the substrate; Depositing an N-type semiconductor layer on the intrinsic GaN layer includes: A first SiInGaN layer, a second SiInAlGaN layer, a third SiInAlGaN layer, a fourth SiAlGaN layer, and a fifth SiAlGaN layer are sequentially deposited on the intrinsic GaN layer to obtain the N-type semiconductor layer.

6. The method for fabricating a light-emitting diode epitaxial wafer as described in claim 5, characterized in that, The growth temperature of the first SiInGaN layer < the growth temperature of the second SiInAlGaN layer < the growth temperature of the third SiInAlGaN layer < the growth temperature of the fourth SiAlGaN layer < the growth temperature of the fifth SiAlGaN layer; The growth pressure of the first SiInGaN layer is greater than the growth pressure of the second SiInAlGaN layer, the third SiInAlGaN layer, the fourth SiAlGaN layer, or the fifth SiAlGaN layer.

7. The method for fabricating a light-emitting diode epitaxial wafer as described in claim 6, characterized in that, The growth temperature of the first SiInGaN layer is 1000℃-1050℃; The growth temperature of the second SiInAlGaN layer, the third SiInAlGaN layer, or the fourth SiAlGaN layer is 1050℃-1100℃; The growth temperature of the fifth SiAlGaN layer is 1100℃-1150℃.

8. The method for fabricating a light-emitting diode epitaxial wafer as described in claim 6, characterized in that, The growth pressure of the first SiInGaN layer is 200 torr-250 torr; The growth pressure of the second, third, fourth, or fifth SiInAlGaN layer is 100 torr-200 torr.

9. An LED, characterized in that, The LED includes a light-emitting diode epitaxial wafer as described in any one of claims 1-4.

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