Comparator with high potential feedback

Abstract

The application provides a high potential feedback comparator, comprising a preamplification stage circuit for amplifying first and second input signals; a comparator circuit for receiving the first and second input signals for voltage comparison, thereby outputting first and second output signals; a feedback module for receiving disturbance signals of the first and second output signals, generating first and second feedback signals to feedback to the first and second output signals, so that the potential of the first and second output signals originally in H or X state is raised. The comparator of the application inputs the differential output of the high potential feedback comparator into the feedback module and outputs high potential feedback to the differential output end of the high potential feedback comparator. When there is a large enough positive or negative voltage disturbance, the feedback module will generate an output response and raise the potential of the differential output end originally in X or H state, thereby stabilizing the state of the comparator.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of semiconductor technology, in particular to a high potential feedback comparator. BACKGROUND

[0002] The comparator is an important component in modern electronic systems, and is a basic conversion unit of analog signals and digital signals, which can be used as a 1-bit analog-to-digital converter. It is mostly operated in an open-loop state, and internal positive feedback is often used to obtain greater gain or hysteresis effect.

[0003] The comparator is widely used in the conversion process of analog signals to digital signals, and POR, VDT, ADC and other circuits often cannot do without the comparator. In the power management module, the power supply voltage is generally sampled, and the sampled signal and the reference voltage are input to the differential input end of the comparator for comparison to determine the state of the current circuit, and then the power management of the entire circuit is performed. However, when the comparator is disturbed by environmental noise, it is very likely to produce an incorrect output, which is particularly evident in high-precision applications, which may reset the entire circuit system.

[0004] Figure 1 and Figure 2 is a high-gain open-loop comparator structure of P-type and N-type differential pairs. High-precision comparators are often composed of 2-4 stages of high-gain open-loop comparators. Due to the differential input and differential output structure, external noise input to the comparator will be suppressed and will not cause incorrect output. However, the interference of the external environment on the internal nodes of the comparator cannot be ignored, and in Figure 1 and Figure 2 , any node of A and B is disturbed, which may cause incorrect response of the comparator. In the entire high-precision comparator, the first stage of high-gain open-loop comparators is most susceptible to external noise and is most likely to produce incorrect response.

[0005] Figure 3 is a structure diagram of a high-precision comparator composed of three stages of high-gain open-loop comparators. Figure 4 is Figure 3 the response diagram of the input INP, INN and the output VOUTP, VOUTN of stage1 (the first stage comparator) and the final output VOUT of the high-precision comparator in normal operation in

[0006] When the comparator is operating normally, the smaller of VOUTN and VOUTP at the stable time is defined as the L state, and the larger one is defined as the H state, and under the non-stable state, it is defined as the X state. When the comparator is operating normally, the following states may occur: ① VOUTN is in the H state, and VOUTP is in the X or L state; ② VOUTN is in the L state, and VOUTP is in the X or H state; ③ VOUTN and VOUTP are both in the X state;

[0007] Figure 3 In the prior art, only a small OD=INP-INN is needed to obtain the response of VOUT, but the differential output of the high-gain open-loop comparator of stage 1 is small, and is particularly susceptible to external interference to generate false responses.

[0008] Figure 5 In the prior art, VOUTN is subjected to a large positive voltage interference at t1, resulting in a false response of VOUT for a time Terror.

[0009] Figure 6 In the prior art, VOUTP is subjected to a large negative voltage interference at t1, resulting in a false response of VOUT for a time Terror.

[0010] To solve the above problems, a new high-potential feedback comparator needs to be proposed. SUMMARY

[0011] In view of the above-mentioned shortcomings of the prior art, the purpose of the present application is to provide a high-potential feedback comparator for solving the problem that in the prior art, when the comparator is working normally, the smaller of VOUTN and VOUTP at the stable time is defined as the L state, and the larger one is defined as the H state, and under non-stable conditions, it is defined as the X state. When the comparator is working normally, the differential output of the high-gain open-loop comparator of the first stage is small, and is particularly susceptible to external interference to generate false responses.

[0012] To achieve the above-mentioned purpose and other related purposes, the present application provides a high-potential feedback comparator, comprising:

[0013] A preamplification stage circuit, which is used to amplify the first and second input signals;

[0014] Preferably, the preamplification stage circuit is a differential amplification circuit.

[0015] A comparator circuit, which is used to receive the first and second input signals for voltage comparison, thereby outputting the first and second output signals;

[0016] A feedback module, which is used to receive the disturbance signals of the first and second output signals, and the disturbance signals usually include positive voltage disturbance and negative voltage disturbance, and the feedback module generates the first and second feedback signals to feedback to the first and second output signals, so that the potential of the first and second output signals originally in the H or X state is raised.

[0017] Preferably, the comparator is a P-type differential pair, which is used for the positive voltage disturbance and the negative voltage disturbance.

[0018] Preferably, the comparator is a P-type differential pair for the positive voltage perturbation or the negative voltage perturbation.

[0019] Preferably, the pre-amplification stage circuit comprises a first PMOS, a second PMOS, a third PMOS, a fourth NMOS and a fifth NMOS;

[0020] The comparator circuit comprises a sixth NMOS and a seventh NMOS; wherein the source of the first PMOS is connected to a power voltage, the gate of the first PMOS is connected to a bias voltage, the gate of the second PMOS is connected to a first input signal, the gate of the third PMOS is connected to a second input signal, the drain of the first PMOS is connected to the source of the second PMOS and the source of the third PMOS respectively, the drain of the second PMOS is connected to the drain of the fourth NMOS, and the drain of the third PMOS is connected to the drain of the fifth NMOS;

[0021] The drain of the fourth NMOS is short-circuited to the gate of the fourth NMOS, the gate of the fourth NMOS is connected to the gate of the sixth NMOS, the drain of the fifth NMOS is short-circuited to the gate of the fifth NMOS, the gate of the fifth NMOS is connected to the gate of the seventh NMOS, and the sources of the fourth NMOS, the fifth NMOS, the sixth NMOS and the seventh NMOS are connected in sequence and connected to a power ground;

[0022] The drain of the sixth NMOS is connected to the drain of the fifth NMOS, the drain of the third PMOS and a second input end of a feedback module respectively, the second output end of the feedback module is connected to the drain of the fifth NMOS and the drain of the third PMOS respectively; the drain of the seventh NMOS is connected to the drain of the fourth NMOS, the drain of the second PMOS and a first input end of the feedback module respectively, and the first output end of the feedback module is connected to the drain of the fourth NMOS and the drain of the second PMOS respectively.

[0023] Preferably, the feedback module comprises an eighth PMOS, a ninth PMOS, a tenth PMOS, an eleventh NMOS, a twelfth NMOS, a thirteenth NMOS, a fourteenth NMOS and a logic module; wherein,

[0024] The source of the eighth PMOS, the drain of the thirteenth NMOS and the drain of the fourteenth NMOS are all connected to a power voltage;

[0025] The gate of the eighth PMOS is short-circuited to the drain of the eighth PMOS, the drain of the eighth PMOS is connected to a bias current, the gate of the eighth PMOS is connected to the gate of the first PMOS, and the gates of the ninth PMOS and the tenth PMOS are both connected to a bias voltage;

[0026] The drain of the ninth PMOS is connected to the drain of the eleventh NMOS, and the drain of the tenth PMOS is connected to the drain of the twelfth NMOS;

[0027] The source of the eleventh NMOS and the source of the twelfth NMOS are connected to a power ground;

[0028] The gate of the eleventh NMOS is connected to the drain of a second PMOS and the drain of a fourth NMOS, and the gate of the twelfth NMOS is connected to the drain of a third PMOS and the drain of a fifth NMOS; a first input end of the logic module is connected to the drain of a ninth PMOS and the drain of the eleventh NMOS, a first output end of the logic module is connected to the gate of a thirteenth NMOS, and the drain of the thirteenth NMOS is connected to an output end of a first output signal; a second input end of the logic module is connected to the drain of a tenth PMOS and the drain of the twelfth NMOS, a second output end of the logic module is connected to the gate of a fourteenth NMOS, and the drain of the fourteenth NMOS is connected to an output end of a second output signal.

[0029] Preferably, the preamplification stage circuit includes a first PMOS, a second PMOS, a third PMOS, a fourth NMOS, and a fifth NMOS;

[0030] The comparator circuit includes a sixth NMOS and a seventh NMOS; wherein,

[0031] The source of the first PMOS is connected to a power voltage, the gate of the first PMOS is connected to a bias voltage, the gate of the second PMOS is connected to a first input signal, the gate of the third PMOS is connected to a second input signal, the drain of the first PMOS is connected to the source of the second PMOS and the source of the third PMOS, the drain of the second PMOS is connected to the drain of the fourth NMOS, and the drain of the third PMOS is connected to the drain of the fifth NMOS;

[0032] The drain of the fourth NMOS is short-circuited to the gate of the fourth NMOS, the gate of the fourth NMOS is connected to the gate of the sixth NMOS, the drain of the fifth NMOS is short-circuited to the gate of the fifth NMOS, the gate of the fifth NMOS is connected to the gate of the seventh NMOS, and the source of the fourth NMOS, the source of the fifth NMOS, the source of the sixth NMOS, and the source of the seventh NMOS are sequentially connected and connected to a power ground;

[0033] The drain of the sixth NMOS is connected to the drain of the fifth NMOS, the drain of the third PMOS, and a second input end of a feedback module, the second output end of the feedback module is connected to the drain of the fifth NMOS and the drain of the third PMOS; the drain of the seventh NMOS is connected to the drain of the fourth NMOS, the drain of the second PMOS, and a first input end of the feedback module, and the first output end of the feedback module is connected to the drain of the fourth NMOS and the drain of the second PMOS.

[0034] Preferably, the feedback module comprises an eighth PMOS, a ninth PMOS, a tenth PMOS, an eleventh NMOS, a twelfth NMOS, a thirteenth NMOS, a fourteenth NMOS, a fifteenth NMOS, a sixteenth NMOS, and a first and a second logic module; wherein,

[0035] The first and the second logic module are used for different types of voltage disturbance.

[0036] The sources of the eighth PMOS, the ninth PMOS, and the tenth PMOS are connected to a power supply voltage; the drains of the thirteenth NMOS, the fourteenth NMOS, the fifteenth NMOS, and the sixteenth NMOS are connected to a power supply voltage.

[0037] The gate of the eighth PMOS is shorted to the drain of the eighth PMOS, the drain of the eighth PMOS is connected to a bias current, the gate of the eighth PMOS is connected to the gate of the first PMOS, the gates of the ninth PMOS and the tenth PMOS are connected to a bias voltage.

[0038] The drain of the ninth PMOS is connected to the drain of the eleventh NMOS, and the drain of the tenth PMOS is connected to the drain of the twelfth NMOS.

[0039] The sources of the eleventh NMOS and the twelfth NMOS are connected to a power supply ground.

[0040] The gate of the eleventh NMOS is connected to the drain of the second PMOS and the drain of the fourth NMOS, and the gate of the twelfth NMOS is connected to the drain of the third PMOS and the drain of the fifth NMOS.

[0041] The first input of the first and the second logic module is connected between the drain of the ninth PMOS and the drain of the eleventh NMOS, respectively; the second input of the first and the second logic module is connected between the drain of the tenth PMOS and the drain of the twelfth NMOS, respectively; the sources of the thirteenth NMOS and the fifteenth NMOS are connected to the output of the first output signal; and the sources of the fourteenth NMOS and the sixteenth NMOS are connected to the output of the second output signal.

[0042] Preferably, the feedback module is an N-type differential pair, which is used for positive voltage disturbance or negative voltage disturbance.

[0043] Preferably, the preamplifier stage circuit comprises a seventh NMOS, a fifth NMOS, a sixth NMOS, a first PMOS, and a second PMOS; the comparator circuit comprises a third PMOS and a fourth PMOS; wherein,

[0044] The source of the seventh NMOS is connected to a power ground, the gate of the seventh NMOS is connected to a bias voltage, the gate of the fifth NMOS is connected to a first input signal, the gate of the sixth NMOS is connected to a second input signal, the drain of the seventh NMOS is connected to the source of the fifth NMOS and the source of the sixth NMOS respectively, the drain of the fifth NMOS is connected to the drain of the first PMOS, and the drain of the sixth NMOS is connected to the drain of the second PMOS;

[0045] The drain of the first PMOS is shorted to the gate of the first PMOS, the gate of the first PMOS is connected to the gate of the third PMOS, the drain of the second PMOS is shorted to the gate of the second PMOS, the gate of the second PMOS is connected to the gate of the fourth PMOS, and the source of the first PMOS, the source of the second PMOS, the source of the third PMOS and the source of the fourth PMOS are connected in sequence and connected to a power voltage;

[0046] The drain of the third PMOS is connected to the drain of the second PMOS, the drain of the sixth NMOS and a second input end of a feedback module respectively, the second output end of the feedback module is connected to the drain of the second PMOS and the drain of the sixth NMOS respectively, the drain of the fourth PMOS is connected to the drain of the first PMOS, the drain of the fifth NMOS and a first input end of the feedback module respectively, and the first output end of the feedback module is connected to the drain of the first PMOS and the drain of the fifth NMOS respectively.

[0047] Preferably, the feedback module comprises an eighth NMOS, a ninth NMOS, a tenth NMOS, an eleventh PMOS, a twelfth PMOS, a thirteenth NMOS, a fourteenth NMOS and a logic module; wherein,

[0048] The source of the eighth NMOS, the source of the ninth NMOS and the source of the tenth NMOS are connected to a power ground;

[0049] The gate of the eighth NMOS is shorted to the drain of the eighth NMOS, the drain of the eighth NMOS is connected to a bias current, the gate of the eighth NMOS is connected to the gate of the seventh NMOS, the gate of the ninth NMOS and the gate of the tenth NMOS are connected to a bias voltage;

[0050] The drain of the ninth NMOS is connected to the drain of the eleventh PMOS, and the drain of the tenth NMOS is connected to the drain of the twelfth PMOS;

[0051] The source of the eleventh PMOS and the source of the twelfth PMOS are connected to a power voltage, and the drain of the thirteenth NMOS and the drain of the fourteenth NMOS are connected to a power voltage;

[0052] The gate of the eleventh PMOS is connected to the drain of the fifth NMOS and the drain of the first PMOS, and the gate of the twelfth PMOS is connected to the drain of the sixth NMOS and the drain of the second PMOS;

[0053] The first input end of the logic module is connected with the drain of the ninth NMOS and the eleventh PMOS, the first output end of the logic module is connected with the gate of the thirteenth NMOS, and the source of the thirteenth NMOS is connected with the output end of the first output signal; the second input end of the logic module is connected with the drain of the tenth NMOS and the twelfth PMOS, the second output end of the logic module is connected with the gate of the fourteenth NMOS, and the source of the fourteenth NMOS is connected with the output end of the second output signal.

[0054] Preferably, the comparator is an N-type differential pair for the positive voltage perturbation and the negative voltage perturbation.

[0055] Preferably, the logic module for the positive voltage perturbation comprises a first inverter, a second inverter, a third inverter, a fourth inverter, a first NAND gate, a fifth inverter, a sixth inverter, a seventh inverter, a first NOR gate, a second NOR gate, a second NAND gate, a third NAND gate; wherein,

[0056] The input end of the first inverter is the second input end of the logic module, the output end of the first inverter is connected with the input end of the third inverter, the output end of the third inverter is connected with the input end of the sixth inverter, the output end of the sixth inverter is connected with the first input end of the first NAND gate, and the output end of the first NAND gate is connected with the second input end of the second NOR gate;

[0057] The input end of the second inverter is the first input end of the module, the output end of the second inverter is connected with the input end of the fourth inverter, the output end of the fourth inverter is connected with the input end of the seventh inverter, the output end of the seventh inverter is connected with the second input end of the second NAND gate, and the output end of the second NAND gate is connected with the first input end of the third NAND gate;

[0058] The first input end of the first NAND gate is connected with the output end of the third inverter, the second input end of the first NAND gate is connected with the output end of the fourth inverter, the output end of the first NAND gate is connected with the input end of the fifth inverter, the output end of the fifth inverter is connected with the first input end of the second NOR gate and the second input end of the third NAND gate respectively, the second input end of the first NAND gate is connected between the output end of the second NAND gate and the first input end of the third NAND gate, and the first input end of the second NAND gate is connected between the output end of the first NAND gate and the second input end of the second NOR gate;

[0059] The output end of the third NAND gate is the first output end of the logic module, and the output end of the second NOR gate is the second output end of the logic module.

[0060] Preferably, the logic module for the negative voltage disturbance comprises a first inverter, a second inverter, a third inverter, a fourth inverter, a first NAND gate, a second NAND gate, a third NAND gate, a first NOR gate, a second NOR gate; wherein,

[0061] The input end of the first inverter is a first input end of the logic module, the output end of the first inverter is connected with the input end of the third inverter, the output end of the third inverter is connected with the input end of the second NAND gate, and the output end of the second NAND gate is connected with the second input end of the first NOR gate;

[0062] The input end of the second inverter is a second input end of the logic module, the output end of the second inverter is connected with the input end of the fourth inverter, the output end of the fourth inverter is connected with the input end of the third NAND gate, and the output end of the third NAND gate is connected with the first input end of the second NOR gate;

[0063] The first input end of the first NAND gate is connected between the output end of the third inverter and the first input end of the second NAND gate, the second input end of the first NAND gate is connected between the output end of the fourth inverter and the second input end of the third NAND gate, and the output end of the first NAND gate is connected with the first input end of the first NOR gate and the second input end of the second NOR gate respectively;

[0064] The second input end of the second NAND gate is connected between the output end of the third NAND gate and the first input end of the second NOR gate, and the first input end of the third NAND gate is connected between the output end of the second NAND gate and the second input end of the first NOR gate;

[0065] The output end of the first NOR gate is a first output end of the logic module, and the output end of the second NOR gate is a second output end of the logic module.

[0066] As described above, the comparator with high potential feedback of the present application has the following beneficial effects:

[0067] The comparator of the present application inputs the differential output of the comparator with high potential feedback into the feedback module and outputs high potential feedback to the differential output end of the comparator with high potential feedback. When there is a large enough positive or negative voltage disturbance, the feedback module will generate an output response and raise the potential of the differential output end in the original state X or H, stabilizing the state of the comparator. This high-reliability design method increases a small amount of cost, but can effectively avoid the false response of the high-precision comparator caused by the external positive and negative voltage interference, so that the high-precision comparator can be applied in a more complex working environment, improving the reliability of the entire circuit system. BRIEF DESCRIPTION OF DRAWINGS

[0068] Figure 1The diagram shows a high-gain open-loop comparator for a P-type differential pair in the prior art.

[0069] Figure 2 The diagram shows a high-gain open-loop comparator for N-type differential pairs in the prior art.

[0070] Figure 3 The diagram shows a high-precision comparator structure using a three-stage high-gain open-loop comparator, which is an application of existing technology.

[0071] Figure 4 The diagram shows the response of a high-precision comparator in the prior art operating normally.

[0072] Figure 5 Displayed as existing technology Figure 3 A schematic diagram of the first-stage high-gain open-loop comparator subjected to a forward voltage disturbance;

[0073] Figure 6 Displayed as existing technology Figure 3 A schematic diagram of the first-stage high-gain open-loop comparator subjected to a negative voltage disturbance;

[0074] Figure 7 The diagram shows a comparator structure for high-potential feedback of a P-type differential pair for positive or negative voltage disturbances according to the present invention.

[0075] Figure 8 The diagram shows a comparator structure for high-potential feedback of an N-type differential pair for positive or negative voltage perturbation according to the present invention.

[0076] Figure 9 The diagram shows a detailed structural schematic of the comparator with high-potential feedback for the P-type differential pair of the present invention.

[0077] Figure 10 The diagram shows a detailed structural schematic of the comparator with high-potential feedback for the N-type differential pair of the present invention.

[0078] Figure 11 The diagram shown is a schematic diagram of a logic module of the present invention;

[0079] Figure 12 This is a schematic diagram of another logic module of the present invention;

[0080] Figure 13 The diagram shows a comparator structure for high-potential feedback of a P-type differential pair used for both positive and negative voltage disturbances according to the present invention.

[0081] Figure 14 Displayed as Figure 9 The diagram shows the first-stage high-gain comparator subjected to a forward voltage disturbance.

[0082] Figure 15 Displayed asFigure 9 A first stage high gain comparator shown in a negative voltage disturbance schematic. DETAILED DESCRIPTION

[0083] Other advantages and benefits of the present application will become apparent to those skilled in the art upon consideration of the disclosure, or can be learned by practice of the application. The advantages and benefits of the present application can be realized and attained by means of the instrumentalities particularly pointed out in the specification and claims of the present application. Modifications and changes can be made by those skilled in the art in light of the above detailed description and claims.

[0084] Embodiment One

[0085] Referring to Figure 7 The present application provides a high potential feedback comparator, the comparator is a P-type differential pair, which is used for positive voltage disturbance or negative voltage disturbance, comprising:

[0086] A preamplifier stage circuit, the preamplifier stage circuit is used for amplifying the first and second input signals;

[0087] In the embodiment of the present application, the preamplifier stage circuit is a differential amplifier circuit.

[0088] A comparator circuit, the comparator circuit is used for receiving the first and second input signals to perform voltage comparison, thereby outputting the first and second output signals;

[0089] In the embodiment of the present application, the preamplifier stage circuit comprises a first PMOS PM1, a second PMOS PM2, a third PMOS PM3, a fourth NMOS PM4 and a fifth NMOS PM5.

[0090] The comparator circuit comprises a sixth NMOS NM6 and a seventh NMOS NM7; wherein,

[0091] The source of the first PMOS PM1 is connected to a power supply voltage VDD, the gate of the first PMOS PM1 is connected to a bias voltage, the gate of the second PMOS PM2 is connected to the first input signal, the gate of the third PMOS PM3 is connected to the second input signal, the drain of the first PMOS PM1 is connected to the source of the second PMOS PM2 and the source of the third PMOS PM3 respectively, the drain of the second PMOS PM2 is connected to the drain of the fourth NMOS NM4, and the drain of the third PMOS PM3 is connected to the drain of the fifth NMOS NM5.

[0092] The drain of the fourth NMOS NM4 is short-circuited with the gate of the fourth NMOS NM4, the gate of the fourth NMOS NM4 is connected with the gate of the sixth NMOS NM6, the drain of the fifth NMOS NM5 is short-circuited with the gate of the fifth NMOS NM5, the gate of the fifth NMOS NM5 is connected with the gate of the seventh NMOS NM7; the source of the fourth NMOS NM4, the fifth NMOS NM5, the sixth NMOS NM6 and the seventh NMOS NM7 are connected in sequence and connected with the power ground GND;

[0093] The drain of the sixth NMOS NM6 is connected with the drain of the fifth NMOS NM5, the drain of the third PMOS PM3 and the second input end of the feedback module Reliable respectively, the second output end of the feedback module Reliable is connected with the drain of the fifth NMOS NM5 and the drain of the third PMOS PM3 respectively; the drain of the seventh NMOS NM7 is connected with the drain of the fourth NMOS NM4, the drain of the second PMOS PM2 and the first input end of the feedback module Reliable respectively, the first output end of the feedback module Reliable is connected with the drain of the fourth NMOS NM4 and the drain of the second PMOS PM2 respectively.

[0094] The feedback module Reliable is used for receiving a disturbance signal of the first and second output signals, the disturbance signal usually includes a positive voltage disturbance and a negative voltage disturbance, the feedback module Reliable generates the first and second feedback signals to feed back to the first and second output signals, so that the potential of the first and second output signals originally in H or X state is lifted.

[0095] Specifically, when the first output signal VOUTN or the second output signal VOUTP of the comparator is interfered by a positive voltage, and the first output signal VOUTN or the second output signal VOUTP changes from L or X state to X or H state, the disturbance is input from the first and second input ends of the feedback module Reliable and high potential is output from the first or second output end to the first or second output signal, so that the potential of the first or second output signal originally in H or X state is lifted, thereby stabilizing the working state of the comparator.

[0096] Specifically, when the first output signal VOUTN or the second output signal VOUTP of the comparator is interfered by a negative voltage, and the first output signal VOUTN or the second output signal VOUTP changes from H or X state to X or L state, the disturbance is input from the first and second input ends of the feedback module Reliable and low potential is output from the first or second output end to the first or second output signal, so that the potential of the first or second output signal originally in H or X state is lifted, thereby stabilizing the working state of the comparator.

[0097] In the embodiments of the present application, please refer to Figure 9The feedback module Reliable comprises an eighth PMOS PM8, a ninth PMOS PM9, a tenth PMOS PM10, an eleventh NMOS NM11, a twelfth NMOS NM12, a thirteenth NMOS NM13, a fourteenth NMOS NM14 and a logic module Logic; wherein,

[0098] The drain of the eighth PMOS PM8, the thirteenth NMOS NM13 and the fourteenth NMOS NM14 are connected to a power supply voltage VDD.

[0099] The gate of the eighth PMOS PM8 is shorted with the drain, the drain of the eighth PMOS PM8 is connected to a bias current, the gate of the eighth PMOS PM8 is connected to the gate of the first PMOS, the gates of the ninth PMOS PM9 and the tenth PMOS PM10 are connected to a bias voltage.

[0100] The drain of the ninth PMOS PM9 is connected to the drain of the eleventh NMOS NM11, and the drain of the tenth PMOS PM10 is connected to the drain of the twelfth NMOS NM12.

[0101] The sources of the eleventh NMOS NM11 and the twelfth NMOS NM12 are connected to a ground GND.

[0102] The gate of the eleventh NMOS NM11 is connected to the drain of the second PMOS PM2 and the fourth NMOS NM4, and the gate of the twelfth NMOS NM12 is connected to the drain of the third PMOS PM3 and the fifth NMOS NM5.

[0103] The first input of the logic module Logic is connected to the drains of the ninth PMOS PM9 and the eleventh NMOS NM11, the first output of the logic module Logic is connected to the gate of the thirteenth NMOS NM13, the drain of the thirteenth NMOS NM13 is connected to the output of the first output signal VOUTN, and the output of the first output signal VOUT is between the second PMOS PM2 and the fourth NMOS NM4; the second input of the logic module Logic is connected to the drains of the tenth PMOS PM10 and the twelfth NMOS NM12, the second output of the logic module Logic is connected to the gate of the fourteenth NMOS NM14, the drain of the fourteenth NMOS NM14 is connected to the output of the second output signal VOUTP, and the output of the second output signal VOUTP is between the drain of the third PMOS PM3 and the fifth NMOS NM5.

[0104] In the embodiment of the present application, please refer to Figure 11, the logic module Logic is used for forward voltage disturbance, it includes first inverter I1, second inverter I2, third inverter I3, fourth inverter I4, first NAND gate I5, fifth inverter I6, sixth inverter I7, seventh inverter I8, first NAND gate I9, second NAND gate I10, second NOR gate I11, third NOR gate I12;Wherein, the input end of first inverter I1 as the second input end of logic module Logic, it is used to obtain the second output signal VOUTP' after amplification, the output end of first inverter I1 is connected with the input end of third inverter I3, the output end of third inverter I3 is connected with the input end of sixth inverter I7, the output end of sixth inverter I7 is connected with the first input end of first NAND gate I9, the output end of first NAND gate I9 is connected with the second input end of second NOR gate I11;

[0105] The input end of second inverter I2 as the first input end of logic module Logic, it is used to obtain the first output signal VOUTN' after amplification, the output end of second inverter I2 is connected with the input end of fourth inverter I4, the output end of fourth inverter I4 is connected with the input end of seventh inverter I8, the output end of seventh inverter I8 is connected with the second input end of second NAND gate I10, the output end of second NAND gate I10 is connected with the first input end of third NOR gate I12;

[0106] The first input end of first NOR gate I5 is connected with the output end of third inverter I3, the second input end of first NOR gate I5 is connected with the output end of fourth inverter I4, the output end of first NOR gate I5 is connected with the input end of fifth inverter I6, the output end of fifth inverter I6 is connected with the first input end of second NOR gate I11, the second input end of third NOR gate I12 respectively, the second input end of second NOR gate I11 is connected between the output end of second NAND gate I10 and the first input end of third NOR gate I12, the first input end of second NAND gate I10 is connected between the output end of first NAND gate I9 and the second input end of second NOR gate I11.

[0107] The output end of third NOR gate I12 as the first output end of logic module Logic, the output end of second NOR gate I11 as the second output end of logic module Logic.

[0108] In the embodiment of the application, please refer to Figure 12 , the logic module Logic is used for negative voltage disturbance, it includes first inverter I1, second inverter I2, third inverter I3, fourth inverter I4, first NAND gate I5, second NAND gate I6, third NAND gate I7, first NOR gate I8, second NOR gate I9;Wherein,

[0109] The input end of the first inverter I1 is the second input end of the logic module Logic, the output end of the first inverter I1 is connected with the input end of the third inverter I3, the output end of the third inverter I3 is connected with the first input end of the second NAND gate I6, and the output end of the second NAND gate I6 is connected with the second input end of the first NOR gate I8;

[0110] The input end of the second inverter I2 is the first input end of the logic module Logic, the output end of the second inverter I2 is connected with the input end of the fourth inverter I4, the output end of the fourth inverter I4 is connected with the first input end of the third NAND gate I7, and the output end of the third NAND gate I7 is connected with the first input end of the second NOR gate I9;

[0111] The first input end of the first NAND gate I5 is connected between the output end of the third inverter I3 and the first input end of the second NAND gate I6, the second input end of the first NAND gate I5 is connected between the output end of the fourth inverter I4 and the second input end of the third NAND gate I7, and the output end of the first NAND gate I5 is connected with the first input end of the first NOR gate I8 and the second input end of the second NOR gate I9 respectively;

[0112] The second input end of the second NAND gate I6 is connected between the output end of the third NAND gate I7 and the first input end of the second NOR gate I9, and the first input end of the third NAND gate I7 is connected between the output end of the second NAND gate I6 and the second input end of the first NOR gate I8;

[0113] The output end of the first NOR gate I8 is the first output end of the logic module Logic, and the output end of the second NOR gate I9 is the second output end of the logic module Logic.

[0114] Specifically, the differential output of the comparator passes through the common-source amplification stage of the eleventh NMOS NM11 and the twelfth NMOS NM12 to obtain large signals VOUTN' and VOUTP', and then passes through the push-pull amplifier of the first inverter I1 and the second inverter I2 in the logic module Logic to be converted into a digital signal of 0-VDD, and finally passes through subsequent logic processing to obtain the required control signal to control the turn-on and turn-off of the thirteenth NMOS NM13 and the fourteenth NMOS NM14, thereby raising the voltage of VOUTN or VOUTP and stabilizing the state of the comparator.

[0115] In the embodiments of the application, Figure 14 and Figure 15 are respectively Figure 9 The response schematic diagram of VOUTN under the positive voltage interference at t1 and VOUTP under the negative voltage interference at t1 in the example is shown in the following figure:

[0116] Figure 14 andFigure 15 t2-t1 is the response time of the feedback module Reliable. It starts to respond at t2 and stops responding at t3;

[0117] Figure 14 and Figure 15 The high potential feedback output by the feedback module Reliable between t2 and t3 when the comparator of the first stage of high gain of the high-reliability design is suddenly disturbed by a positive or negative voltage pulse, i.e. the potential of VOUTP in the original H state is raised, the original comparator state is quickly restored, and false responses are avoided.

[0118] Embodiment Two

[0119] This embodiment is compared with Embodiment One. The comparator is a P-type differential pair, which is used for positive voltage disturbance and negative voltage disturbance (for example Figure 13 The comparator circuit shown in the figure).

[0120] In the embodiment of the application, the preamplifier stage circuit includes a first PMOS, a second PMOS, a third PMOS, a fourth NMOS, and a fifth NMOS;

[0121] The comparator circuit includes a sixth NMOS NM6 and a seventh NMOS NM7; wherein,

[0122] The source of the first PMOS is connected to a power supply voltage VDD, the gate of the first PMOS is connected to a bias voltage, the gate of the second PMOS is connected to a first input signal, the gate of the third PMOS is connected to a second input signal, the drain of the first PMOS is connected to the source of the second PMOS and the source of the third PMOS respectively, the drain of the second PMOS is connected to the drain of the fourth NMOS, and the drain of the third PMOS is connected to the drain of the fifth NMOS;

[0123] The drain of the fourth NMOS NM4 is shorted to the gate, the gate of the fourth NMOS NM4 is connected to the gate of the sixth NMOS NM6, the drain of the fifth NMOS NM5 is shorted to the gate, the gate of the fifth NMOS NM5 is connected to the gate of the seventh NMOS NM7; the sources of the fourth NMOS NM4, the fifth NMOS NM5, the sixth NMOS NM6, and the seventh NMOS NM7 are connected in sequence and connected to a power ground GND;

[0124] The drain of the sixth NMOS NM6 is connected with the drain of the fifth NMOS NM5, the drain of the third PMOS PM3 and the second input end of the feedback module Reliable respectively, the second output end of the feedback module Reliable is connected with the drain of the fifth NMOS NM5 and the drain of the third PMOS PM3 respectively; the drain of the seventh NMOS NM7 is connected with the drain of the fourth NMOS NM4, the drain of the second PMOS PM2 and the first input end of the feedback module Reliable respectively, the first output end of the feedback module Reliable is connected with the drain of the fourth NMOS NM4 and the drain of the second PMOS PM2 respectively.

[0125] In the embodiment of the application, the feedback module Reliable comprises an eighth PMOS PM8, a ninth PMOS PM9, a tenth PMOS PM10, an eleventh NMOS NM11, a twelfth NMOS NM12, a thirteenth NMOS NM13, a fourteenth NMOS NM14, a fifteenth NMOS NM15, a sixteenth NMOS NM16 and first and second logic modules (Logic1, Logic2); wherein,

[0126] The first and second logic modules (Logic1, Logic2) are used for different types of voltage disturbance.

[0127] The sources of the eighth PMOS PM8, the ninth PMOS PM9 and the tenth PMOS PM10 are connected with the power supply voltage VDD; the drains of the thirteenth NMOS NM13, the fourteenth NMOS NM14, the fifteenth NMOS NM15 and the sixteenth NMOS NM16 are connected with the power supply ground GND.

[0128] The gate of the eighth PMOS PM8 is short-circuited with the drain, the drain of the eighth PMOS PM8 is connected with the bias current, the gate of the eighth PMOS PM8 is connected with the gate of the first PMOS, the gates of the ninth PMOS PM9 and the tenth PMOS PM10 are connected with the bias voltage.

[0129] The drain of the ninth PMOS PM9 is connected with the drain of the eleventh NMOS NM11, the drain of the tenth PMOS PM10 is connected with the drain of the twelfth NMOS NM12.

[0130] The sources of the eleventh NMOS NM11 and the twelfth NMOS NM12 are connected with the power supply ground GND.

[0131] The gate of the eleventh NMOS NM11 is connected with the drain of the second PMOS PM2 and the fourth NMOS NM4, and the gate of the twelfth NMOS NM12 is connected with the drain of the third PMOS PM3 and the fifth NMOS NM5;

[0132] The first input end of the first and second logic modules (Logic1, Logic2) is connected between the drain of the ninth PMOS PM9 and the drain of the eleventh NMOS NM11 respectively, and the second input end of the first and second logic modules (Logic1, Logic2) is connected between the drain of the tenth PMOS PM10 and the drain of the twelfth NMOS NM12 respectively; the source of the thirteenth NMOS NM13 and the fifteenth NMOS NM15 is connected with the output end of the first output signal OUTN, and the source of the fourteenth NMOS NM14 and the sixteenth NMOS NM16 is connected with the output end of the second output signal OUTP.

[0133] In the embodiment of the application, please refer to Figure 11 , the logic module Logic is used for forward voltage disturbance, which comprises a first inverter I1, a second inverter I2, a third inverter I3, a fourth inverter I4, a first NOR gate I5, a fifth inverter I6, a sixth inverter I7, a seventh inverter I8, a first NAND gate I9, a second NAND gate I10, a second NOR gate I11, and a third NOR gate I12; wherein,

[0134] The input end of the first inverter I1 is used as the second input end of the logic module Logic, which is used for obtaining the amplified second output signal VOUTP', the output end of the first inverter I1 is connected with the input end of the third inverter I3, the output end of the third inverter I3 is connected with the input end of the sixth inverter I7, the output end of the sixth inverter I7 is connected with the first input end of the first NAND gate I9, and the output end of the first NAND gate I9 is connected with the second input end of the second NOR gate I11;

[0135] The input end of the second inverter I2 is used as the first input end of the logic module, which is used for obtaining the amplified first output signal VOUTN', the output end of the second inverter I2 is connected with the input end of the fourth inverter I4, the output end of the fourth inverter I4 is connected with the input end of the seventh inverter I8, the output end of the seventh inverter I8 is connected with the second input end of the second NAND gate I10, and the output end of the second NAND gate I10 is connected with the first input end of the third NOR gate I12;

[0136] The first input end of the first NOR gate I5 is connected with the output end of the third inverter I3, the second input end of the first NOR gate I5 is connected with the output end of the fourth inverter I4, the output end of the first NOR gate I5 is connected with the input end of the fifth inverter I6, the output end of the fifth inverter I6 is respectively connected with the first input end of the second NOR gate I11 and the second input end of the third NOR gate I12, the second input end of the first NAND gate I9 is connected between the output end of the second NAND gate I10 and the first input end of the third NOR gate I12, and the first input end of the second NAND gate I10 is connected between the output end of the first NAND gate I9 and the second input end of the second NOR gate I11.

[0137] The output end of the third NOR gate I12 is the first output end of the logic module Logic, and the output end of the second NOR gate I11 is the second output end of the logic module Logic.

[0138] In the embodiment of the present application, referring to Figure 12 , the logic module Logic is used for negative voltage disturbance, which comprises a first inverter I1, a second inverter I2, a third inverter I3, a fourth inverter I4, a first NAND gate I5, a second NAND gate I6, a third NAND gate I7, a first NOR gate I8 and a second NOR gate I9; wherein,

[0139] The input end of the first inverter I1 is the first input end of the logic module Logic, the output end of the first inverter I1 is connected with the input end of the third inverter I3, the output end of the third inverter I3 is connected with the input end of the second NAND gate I6, and the output end of the second NAND gate I6 is connected with the second input end of the first NOR gate I8;

[0140] The input end of the second inverter I2 is the second input end of the logic module Logic, the output end of the second inverter I2 is connected with the input end of the fourth inverter I4, the output end of the fourth inverter I4 is connected with the input end of the third NAND gate I7, and the output end of the third NAND gate I7 is connected with the first input end of the second NOR gate I9;

[0141] The first input end of the first NAND gate I5 is connected between the output end of the third inverter I3 and the first input end of the second NAND gate I6, the second input end of the first NAND gate I5 is connected between the output end of the fourth inverter I4 and the second input end of the third NAND gate I7, and the output end of the first NAND gate I5 is respectively connected with the first input end of the first NOR gate I8 and the second input end of the second NOR gate I9;

[0142] The second input end of the second NAND gate I6 is connected between the output end of the third NAND gate I7 and the first input end of the second NOR gate I9, and the first input end of the third NAND gate I7 is connected between the output end of the second NAND gate I6 and the second input end of the first NOR gate I8.

[0143] The output end of the first NOR gate I8 is the first output end of the logic module Logic, and the output end of the second NOR gate I9 is the second output end of the logic module Logic.

[0144] Embodiment three

[0145] Please refer to Figure 8 The feedback module Reliable is a N-type differential pair, and the feedback module Reliable is used for positive voltage disturbance or negative voltage disturbance.

[0146] The feedback module Reliable is used for receiving a disturbance signal of the first and second output signals, and the disturbance signal usually includes positive voltage disturbance and negative voltage disturbance. The feedback module Reliable generates first and second feedback signals to feed back to the first and second output signals, so that the potential of the first and second output signals originally in the H or X state is raised.

[0147] Specifically, when the first output signal VOUTN or the second output signal VOUTP of the comparator is disturbed by positive voltage and changes from the L or X state to the X or H state, the disturbance is input from the first and second input ends of the feedback module Reliable and output from the first or second output end to the first or second output signal with a low potential feedback, so as to lower the potential of the first or second output signal originally in the L or X state, thereby stabilizing the working state of the comparator.

[0148] Specifically, when the first output signal VOUTN or the second output signal VOUTP of the comparator is disturbed by negative voltage and changes from the H or X state to the X or L state, the disturbance is input from the first and second input ends of the feedback module Reliable and output from the first or second output end to the first or second output signal with a low potential feedback, so as to lower the potential of the first or second output signal originally in the L or X state, thereby stabilizing the working state of the comparator.

[0149] In the embodiment of the application, the preamplifier stage circuit includes a seventh NMOS NM7, a fifth NMOS NM5, a sixth NMOS NM6, a first PMOS PM1, and a second PMOS PM2.

[0150] The comparator circuit includes a third PMOS PM3 and a fourth PMOS PM4; wherein,

[0151] The source electrode of the seventh NMOS NM7 is connected to the power supply ground GND, the gate electrode of the seventh NMOS NM7 is connected to a bias voltage, the gate electrode of the fifth NMOS NM5 is connected to a first input signal, the gate electrode of the sixth NMOS NM6 is connected to a second input signal, the drain electrode of the seventh NMOS NM7 is connected to the source electrode of the fifth NMOS NM5 and the source electrode of the sixth NMOS NM6 respectively, the drain electrode of the fifth NMOS NM5 is connected to the drain electrode of the first PMOS PM1, and the drain electrode of the sixth NMOS NM6 is connected to the drain electrode of the second PMOS PM2.

[0152] The drain electrode and the gate electrode of the first PMOS PM1 are short-circuited, the gate electrode of the first PMOS PM1 is connected to the gate electrode of the third PMOS PM3, the drain electrode and the gate electrode of the second PMOS PM2 are short-circuited, the gate electrode of the second PMOS PM2 is connected to the gate electrode of the fourth PMOS PM4, and the source electrodes of the first PMOS PM1, the second PMOS PM2, the third PMOS PM3 and the fourth PMOS PM4 are connected in sequence and connected to a power supply voltage VDD.

[0153] The drain electrode of the third PMOS PM3 is connected to the drain electrode of the second PMOS PM2, the drain electrode of the sixth NMOS NM6 and the second input end of the feedback module Reliable respectively, the second output end of the feedback module Reliable is connected to the drain electrode of the second PMOS PM2 and the drain electrode of the sixth NMOS NM6 respectively, the drain electrode of the fourth PMOS PM4 is connected to the drain electrode of the first PMOS PM1, the drain electrode of the fifth NMOS NM5 and the first input end of the feedback module Reliable respectively, and the first output end of the feedback module Reliable is connected to the drain electrode of the first PMOS PM1 and the drain electrode of the fifth NMOS NM5 respectively.

[0154] In the embodiment of the application, the feedback module Reliable comprises an eighth NMOS NM8, a ninth NMOS NM9, a tenth NMOS NM10, an eleventh PMOS PM11, a twelfth PMOS PM12, a thirteenth NMOS NM13, a fourteenth NMOS NM14 and a logic module Logic.

[0155] The source electrodes of the eighth NMOS NM8, the ninth NMOS NM9 and the tenth NMOS NM10 are connected to the power supply ground GND.

[0156] The gate electrode and the drain electrode of the eighth NMOS NM8 are short-circuited, the drain electrode of the eighth NMOS NM8 is connected to a bias current, the gate electrode of the eighth NMOS NM8 is connected to the gate electrode of the seventh NMOS NM7, and the gate electrodes of the ninth NMOS NM9 and the tenth NMOS NM10 are connected to a bias voltage.

[0157] The drain of the ninth NMOS NM9 is connected with the drain of the eleventh PMOS PM11, and the drain of the tenth NMOS NM10 is connected with the drain of the twelfth PMOS PM12;

[0158] The source of the eleventh PMOS PM11 and the source of the twelfth PMOS PM12 are connected with the power supply voltage VDD; the drain of the thirteenth NMOS NM13 and the drain of the fourteenth NMOS NM14 are connected with the power supply voltage VDD;

[0159] The gate of the eleventh PMOS PM11 is connected with the drain of the fifth NMOS NM5 and the drain of the first PMOS PM1, and the gate of the twelfth PMOS PM12 is connected with the drain of the sixth NMOS NM6 and the drain of the second PMOS PM2;

[0160] The first input end of the logic module Logic is connected with the drain of the ninth NMOS NM9 and the drain of the eleventh PMOS PM11, the first output end of the logic module Logic is connected with the gate of the thirteenth NMOS NM13, and the source of the thirteenth NMOS NM13 is connected with the output end of the first output signal VOUTN; the second input end of the logic module Logic is connected with the drain of the tenth NMOS NM10 and the drain of the twelfth PMOS PM12, the second output end of the logic module Logic is connected with the gate of the fourteenth NMOS NM14, and the source of the fourteenth NMOS NM14 is connected with the output end of the second output signal VOUTP.

[0161] In the embodiment of the present application, please refer to Figure 11 The logic module Logic is used for forward voltage disturbance, which comprises a first inverter I1, a second inverter I2, a third inverter I3, a fourth inverter I4, a first NOR gate I5, a fifth inverter I6, a sixth inverter I7, a seventh inverter I8, a first NAND gate I9, a second NAND gate I10, a second NOR gate I11 and a third NOR gate I12; wherein,

[0162] The input end of the first inverter I1 is used as the second input end of the logic module Logic, which is used for acquiring the amplified second output signal VOUTP', the output end of the first inverter I1 is connected with the input end of the third inverter I3, the output end of the third inverter I3 is connected with the input end of the sixth inverter I7, the output end of the sixth inverter I7 is connected with the first input end of the first NAND gate I9, and the output end of the first NAND gate I9 is connected with the second input end of the second NOR gate I11;

[0163] The input end of the second inverter I2 is the first input end of the module, which is used to obtain the amplified first output signal VOUTN', the output end of the second inverter I2 is connected with the input end of the fourth inverter I4, the output end of the fourth inverter I4 is connected with the input end of the seventh inverter I8, the output end of the seventh inverter I8 is connected with the second input end of the second NAND gate I10, and the output end of the second NAND gate I10 is connected with the first input end of the third NOR gate I12;

[0164] The first input end of the first NOR gate I5 is connected with the output end of the third inverter I3, the second input end of the first NOR gate I5 is connected with the output end of the fourth inverter I4, the output end of the first NOR gate I5 is connected with the input end of the fifth inverter I6, the output end of the fifth inverter I6 is connected with the first input end of the second NOR gate I11 and the second input end of the third NOR gate I12 respectively, the second input end of the first NAND gate I9 is connected between the output end of the second NAND gate I10 and the first input end of the third NOR gate I12, and the first input end of the second NAND gate I10 is connected between the output end of the first NAND gate I9 and the second input end of the second NOR gate I11.

[0165] The output end of the third NOR gate I12 is the first output end of the logic module Logic, and the output end of the second NOR gate I11 is the second output end of the logic module Logic.

[0166] In the embodiment of the application, referring to Figure 12 , the logic module Logic is used for negative voltage disturbance, and comprises a first inverter I1, a second inverter I2, a third inverter I3, a fourth inverter I4, a first NAND gate I5, a second NAND gate I6, a third NAND gate I7, a first NOR gate I8 and a second NOR gate I9; wherein,

[0167] The input end of the first inverter I1 is the first input end of the logic module Logic, the output end of the first inverter I1 is connected with the input end of the third inverter I3, the output end of the third inverter I3 is connected with the input end of the second NAND gate I6, and the output end of the second NAND gate I6 is connected with the second input end of the first NOR gate I8;

[0168] The input end of the second inverter I2 is the second input end of the logic module Logic, the output end of the second inverter I2 is connected with the input end of the fourth inverter I4, the output end of the fourth inverter I4 is connected with the input end of the third NAND gate I7, and the output end of the third NAND gate I7 is connected with the first input end of the second NOR gate I9;

[0169] The first input end of the first NAND gate I5 is connected between the output end of the third inverter I3 and the first input end of the second NAND gate I6, the second input end of the first NAND gate I5 is connected between the output end of the fourth inverter I4 and the second input end of the third NAND gate I7, and the output end of the first NAND gate I5 is connected with the first input end of the first NOR gate I8 and the second input end of the second NOR gate I9 respectively;

[0170] The second input end of the second NAND gate I6 is connected between the output end of the third NAND gate I7 and the first input end of the second NOR gate I9, and the first input end of the third NAND gate I7 is connected between the output end of the second NAND gate I6 and the second input end of the first NOR gate I8.

[0171] The output end of the first NOR gate I8 is the first output end of the logic module Logic, and the output end of the second NOR gate I9 is the second output end of the logic module Logic. Specifically, the differential output of the comparator passes through the common source amplification stage of the eleventh NMOS NM11 and the twelfth NMOS NM12 to obtain large signals VOUTN' and VOUTP', and then passes through the push-pull amplifier of the first inverter and the second inverter in the logic module Logic to be converted into a digital signal of 0-VDD, and finally passes through subsequent logic processing to obtain the required control signal to control the turn-on and turn-off of the thirteenth NMOS NM13 and the fourteenth NMOS NM14, thereby pulling down the voltage of VOUTN or VOUTP to stabilize the state of the comparator.

[0172] Embodiment Four

[0173] In the embodiments of the present application, the comparator is an N-type differential pair, which is used for positive voltage disturbance and negative voltage disturbance. Its structure is similar to that of a P-type differential pair used for positive voltage disturbance and negative voltage disturbance, which is not described here.

[0174] It should be noted that the diagrams provided in the embodiments only illustrate the basic concept of the present application in a schematic manner, and only the components related to the present application are shown in the diagrams, not the number, shape and size of the components when actually implemented. The actual implementation of each component may be a random change in type, number and proportion, and the layout pattern of the components may be more complex.

[0175] In summary, the comparator of the present application inputs the differential output of the high potential feedback comparator into the feedback module and outputs the high potential feedback to the differential output of the high potential feedback comparator. When there is a large enough positive or negative voltage disturbance, the feedback module will generate an output response and pull up the potential of the differential output in the original state X or H, stabilizing the state of the comparator. This highly reliable design method increases a small amount of cost, but can effectively avoid the false response of the high-precision comparator caused by the positive and negative voltage interference from the outside world, so that the high-precision comparator can be applied in a more complex working environment, and the reliability of the entire circuit system is improved. Therefore, the present application effectively overcomes the various shortcomings in the prior art and has a high industrial utilization value.

[0176] The above embodiments only exemplarily illustrate the principles and effects of the present application, and are not intended to limit the present application. Any person skilled in the art can modify or change the above embodiments without departing from the spirit and scope of the present application. Therefore, all equivalent modifications or changes made by those skilled in the art without departing from the spirit and technical idea disclosed by the present application should be covered by the claims of the present application.

Claims

1. A high potential feedback comparator, characterized by, include: A preamplifier stage circuit, wherein the preamplifier stage circuit is used to amplify the first and second input signals; A comparator circuit is used to receive first and second input signals, compare their voltages, and then output first and second output signals. The feedback module is used to receive disturbance signals of the first and second output signals, generate the first and second feedback signals and feed them back to the first and second output signals, so that the potential of the first and second output signals, which were originally in the H or X state, is raised. Wherein, when the comparator is a P-type differential pair, the feedback module includes an eighth PMOS, a ninth PMOS, a tenth PMOS, an eleventh NMOS, a twelfth NMOS, a thirteenth NMOS, a fourteenth NMOS, and a logic module; The drain of the ninth PMOS is connected to the drain of the eleventh NMOS, and the drain of the tenth PMOS is connected to the drain of the twelfth NMOS. The gate of the eleventh NMOS is connected to the first output terminal of the comparator circuit, and the gate of the twelfth NMOS is connected to the second output terminal of the comparator circuit. The first input terminal and the second input terminal of the logic module are respectively connected to the drains of the ninth PMOS and the eleventh NMOS, the tenth PMOS and the twelfth NMOS, and the first output terminal and the second output terminal of the logic module are respectively connected to the gate of the thirteenth NMOS and the gate of the fourteenth NMOS. The drain of the thirteenth NMOS is connected to the first output terminal of the comparator circuit, and the drain of the fourteenth NMOS is connected to the second output terminal of the comparator circuit. Alternatively, when the comparator is an N-type differential pair, the feedback module includes an eighth NMOS, a ninth NMOS, a tenth NMOS, an eleventh PMOS, a twelfth PMOS, a thirteenth NMOS, a fourteenth NMOS, and a logic module; The drain of the ninth NMOS is connected to the drain of the eleventh PMOS, and the drain of the tenth NMOS is connected to the drain of the twelfth PMOS; the gate of the eleventh PMOS is connected to the first output terminal of the comparator circuit, and the gate of the twelfth PMOS is connected to the second output terminal of the comparator circuit. The first and second input terminals of the logic module are connected to the drains of the ninth and eleventh PMOS, the tenth PMOS, and the twelfth PMOS, respectively. The first and second output terminals of the logic module are connected to the gates of the thirteenth and fourteenth NMOS, respectively. The source of the thirteenth NMOS is connected to the first output terminal of the comparator circuit, and the source of the fourteenth NMOS is connected to the second output terminal of the comparator circuit.

2. The high potential feedback comparator of claim 1, wherein: The preamplifier stage circuit is a differential amplifier circuit.

3. The high potential feedback comparator of claim 1, wherein: The disturbance signal includes positive voltage disturbance and negative voltage disturbance.

4. The high potential feedback comparator of claim 3, wherein: The comparator is a P-type differential pair, and the feedback module is used for the positive or negative voltage disturbance.

5. The comparator with high-potential feedback according to claim 4, characterized in that: The pre-amplification stage circuit comprises a first PMOS, a second PMOS, a third PMOS, a fourth NMOS and a fifth NMOS; The comparator circuit comprises a sixth NMOS and a seventh NMOS; wherein, The source of the first PMOS is connected to a power supply voltage, the gate of the first PMOS is connected to a bias voltage, the gate of the second PMOS is connected to a first input signal, the gate of the third PMOS is connected to a second input signal, the drain of the first PMOS is connected to the source of the second PMOS and the source of the third PMOS, the drain of the second PMOS is connected to the drain of the fourth NMOS, and the drain of the third PMOS is connected to the drain of the fifth NMOS; The drain of the fourth NMOS is short-circuited to the gate of the fourth NMOS, the gate of the fourth NMOS is connected to the gate of the sixth NMOS, the drain of the fifth NMOS is short-circuited to the gate of the fifth NMOS, the gate of the fifth NMOS is connected to the gate of the seventh NMOS, and the sources of the fourth NMOS, the fifth NMOS, the sixth NMOS and the seventh NMOS are sequentially connected and connected to a power supply ground; The drain of the sixth NMOS is connected to the drain of the fifth NMOS, the drain of the third PMOS and a second input end of a feedback module, the second output end of the feedback module is connected to the drain of the fifth NMOS and the drain of the third PMOS, the drain of the seventh NMOS is connected to the drain of the fourth NMOS, the drain of the second PMOS and a first input end of the feedback module, and the first output end of the feedback module is connected to the drain of the fourth NMOS and the drain of the second PMOS.

6. The high potential feedback comparator of claim 5, wherein: The feedback module comprises an eighth PMOS, a ninth PMOS, a tenth PMOS, an eleventh NMOS, a twelfth NMOS, a thirteenth NMOS, a fourteenth NMOS and a logic module; wherein, The source of the eighth PMOS, the drain of the thirteenth NMOS and the drain of the fourteenth NMOS are all connected to a power supply voltage; The gate of the eighth PMOS is short-circuited to the drain of the eighth PMOS, the drain of the eighth PMOS is connected to a bias current, the gate of the eighth PMOS is connected to the gate of the first PMOS, the gates of the ninth PMOS and the tenth PMOS are both connected to a bias voltage; The drain of the ninth PMOS is connected to the drain of the eleventh NMOS, and the drain of the tenth PMOS is connected to the drain of the twelfth NMOS; The sources of the eleventh NMOS and the twelfth NMOS are both connected to a power supply ground; The gate of the eleventh NMOS is connected to the drain of the second PMOS and the drain of the fourth NMOS, the gate of the twelfth NMOS is connected to the drain of the third PMOS and the drain of the fifth NMOS, the first input end of the logic module is connected to the drain of the ninth PMOS and the drain of the eleventh NMOS, the first output end of the logic module is connected to the gate of the thirteenth NMOS, the drain of the thirteenth NMOS is connected to the output end of a first output signal, the second input end of the logic module is connected to the drain of the tenth PMOS and the drain of the twelfth NMOS, the second output end of the logic module is connected to the gate of the fourteenth NMOS, and the drain of the fourteenth NMOS is connected to the output end of a second output signal.

7. The high potential feedback comparator of claim 3, wherein: The comparator is a P-type differential pair, and the feedback module is used for the positive voltage disturbance and the negative voltage disturbance.

8. The high potential feedback comparator of claim 7, wherein: The pre-amplification stage circuit comprises a first PMOS, a second PMOS, a third PMOS, a fourth NMOS and a fifth NMOS; The source of the first PMOS is connected to a power supply voltage, the gate of the first PMOS is connected to a bias voltage, the gate of the second PMOS is connected to a first input signal, the gate of the third PMOS is connected to a second input signal, the drain of the first PMOS is connected to the source of the second PMOS and the source of the third PMOS respectively, the drain of the second PMOS is connected to the drain of the fourth NMOS, and the drain of the third PMOS is connected to the drain of the fifth NMOS.

9. The high potential feedback comparator of claim 1, wherein: The feedback module comprises an eighth PMOS, a ninth PMOS, a tenth PMOS, an eleventh NMOS, a twelfth NMOS, a thirteenth NMOS, a fourteenth NMOS, a fifteenth NMOS and a sixteenth NMOS, and the logic module comprises a first logic module and a second logic module; The first logic module and the second logic module are used for different types of voltage disturbances; The sources of the eighth PMOS, the ninth PMOS and the tenth PMOS are all connected to a power supply voltage, and the drains of the thirteenth NMOS, the fourteenth NMOS, the fifteenth NMOS and the sixteenth NMOS are all connected to a power supply voltage; The gate of the eleventh NMOS is connected to the drains of the second PMOS and the fourth NMOS, and the gate of the twelfth NMOS is connected to the drains of the third PMOS and the fifth NMOS; The first input end of the first logic module and the first input end of the second logic module are connected between the drain of the ninth PMOS and the drain of the eleventh NMOS respectively, the second input end of the first logic module and the second input end of the second logic module are connected between the drain of the tenth PMOS and the drain of the twelfth NMOS respectively, and the sources of the thirteenth NMOS and the fifteenth NMOS are connected to the output end of a first output signal; The sources of the fourteenth NMOS and the sixteenth NMOS are connected to the output end of a second output signal.

10. The high potential feedback comparator of claim 3, wherein: The comparator is an N-type differential pair, and the feedback module is used for the positive voltage disturbance or the negative voltage disturbance.

11. The high potential feedback comparator of claim 10, wherein: The pre-amplification stage circuit comprises a seventh NMOS, a fifth NMOS, a sixth NMOS, a first PMOS and a second PMOS; The comparator circuit comprises a third PMOS and a fourth PMOS; wherein The source of the seventh NMOS is connected to a power supply ground, the gate of the seventh NMOS is connected to a bias voltage, the gate of the fifth NMOS is connected to a first input signal, the gate of the sixth NMOS is connected to a second input signal, the drain of the seventh NMOS is connected to the source of the fifth NMOS and the source of the sixth NMOS respectively, the drain of the fifth NMOS is connected to the drain of the first PMOS, and the drain of the sixth NMOS is connected to the drain of the second PMOS; The drain and the gate of the first PMOS are short-circuited, the gate of the first PMOS is connected to the gate of the third PMOS, the drain and the gate of the second PMOS are short-circuited, the gate of the second PMOS is connected to the gate of the fourth PMOS, and the sources of the first PMOS, the second PMOS, the third PMOS and the fourth PMOS are sequentially connected and connected to a power supply voltage. The drain of the third PMOS is connected with the drain of the second PMOS, the drain of the sixth NMOS and the second input end of the feedback module respectively, and the second output end of the feedback module is connected with the drain of the second PMOS and the drain of the sixth NMOS respectively; the drain of the fourth PMOS is connected with the drain of the first PMOS, the drain of the fifth NMOS and the first input end of the feedback module respectively, and the first output end of the feedback module is connected with the drain of the first PMOS and the drain of the fifth NMOS respectively.

12. The high potential feedback comparator of claim 11, wherein: The feedback module comprises an eighth NMOS, a ninth NMOS, a tenth NMOS, an eleventh PMOS, a twelfth PMOS, a thirteenth NMOS, a fourteenth NMOS and a logic module; wherein, The source of the eighth NMOS, the ninth NMOS and the tenth NMOS is connected with the power supply ground; The gate of the eighth NMOS is short-circuited with the drain, the drain of the eighth NMOS is connected with the bias current, the gate of the eighth NMOS is connected with the gate of the seventh NMOS, and the gate of the ninth NMOS and the gate of the tenth NMOS are connected with the bias voltage; The drain of the ninth NMOS is connected with the drain of the eleventh PMOS, and the drain of the tenth NMOS is connected with the drain of the twelfth PMOS; The source of the eleventh PMOS and the twelfth PMOS is connected with the power supply voltage, and the drain of the thirteenth NMOS and the fourteenth NMOS is connected with the power supply voltage; The gate of the eleventh PMOS is connected with the drain of the fifth NMOS and the first PMOS, and the gate of the twelfth PMOS is connected with the drain of the sixth NMOS and the second PMOS; The first input end of the logic module is connected with the drain of the ninth NMOS and the eleventh PMOS, the first output end of the logic module is connected with the gate of the thirteenth NMOS, the source of the thirteenth NMOS is connected with the output end of the first output signal, the second input end of the logic module is connected with the drain of the tenth NMOS and the twelfth PMOS, the second output end of the logic module is connected with the gate of the fourteenth NMOS, and the source of the fourteenth NMOS is connected with the output end of the second output signal.

13. The high potential feedback comparator of claim 3, wherein: The comparator is an N-type differential pair, and the feedback module is used for the positive voltage disturbance and the negative voltage disturbance.

14. The high potential feedback comparator of claim 6 or 9 or 12 or 13, wherein: The logic module is used for the positive voltage disturbance, and comprises a first inverter, a second inverter, a third inverter, a fourth inverter, a first NOR gate, a fifth inverter, a sixth inverter, a seventh inverter, a first NAND gate, a second NAND gate, a second NOR gate and a third NOR gate; wherein, The input end of the first inverter is used as the second input end of the logic module, the output end of the first inverter is connected with the input end of the third inverter, the output end of the third inverter is connected with the input end of the sixth inverter, the output end of the sixth inverter is connected with the first input end of the first NAND gate, and the output end of the first NAND gate is connected with the second input end of the second NOR gate. The input end of the second inverter is the first input end of the module, the output end of the second inverter is connected with the input end of the fourth inverter, the output end of the fourth inverter is connected with the input end of the seventh inverter, the output end of the seventh inverter is connected with the second input end of the second NAND gate, and the output end of the second NAND gate is connected with the first input end of the third NOR gate; The first input end of the first NOR gate is connected with the output end of the third inverter, the second input end of the first NOR gate is connected with the output end of the fourth inverter, the output end of the first NOR gate is connected with the input end of the fifth inverter, the output end of the fifth inverter is connected with the first input end of the second NOR gate and the second input end of the third NOR gate respectively, the second input end of the first NAND gate is connected between the output end of the second NAND gate and the first input end of the third NOR gate, and the first input end of the second NAND gate is connected between the output end of the first NAND gate and the second input end of the second NOR gate; The output end of the third NOR gate is the first output end of the logic module, and the output end of the second NOR gate is the second output end of the logic module.

15. The high potential feedback comparator of claim 6 or 9 or 12 or 13, wherein: The logic module is used for negative voltage disturbance, and comprises a first inverter, a second inverter, a third inverter, a fourth inverter, a first NAND gate, a second NAND gate, a third NAND gate, a first NOR gate and a second NOR gate. The input end of the first inverter is the second input end of the logic module, the output end of the first inverter is connected with the input end of the third inverter, the output end of the third inverter is connected with the input end of the second NAND gate, and the output end of the second NAND gate is connected with the second input end of the first NOR gate; The input end of the second inverter is the first input end of the logic module, the output end of the second inverter is connected with the input end of the fourth inverter, the output end of the fourth inverter is connected with the input end of the third NAND gate, and the output end of the third NAND gate is connected with the first input end of the second NOR gate; The first input end of the first NAND gate is connected between the output end of the third inverter and the first input end of the second NAND gate, the second input end of the first NAND gate is connected between the output end of the fourth inverter and the second input end of the third NAND gate, and the output end of the first NAND gate is connected with the first input end of the first NOR gate and the second input end of the second NOR gate respectively; The second input end of the second NAND gate is connected between the output end of the third NAND gate and the first input end of the second NOR gate, and the first input end of the third NAND gate is connected between the output end of the second NAND gate and the second input end of the first NOR gate; The output end of the first NOR gate is the first output end of the logic module, and the output end of the second NOR gate is the second output end of the logic module.

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