Gate drive circuits for cascaded power devices, integrated semiconductor power devices

Abstract

The present invention discloses a gate drive circuit for a cascade power device and an integrated semiconductor power device. The gate drive circuit includes: a current-type drive unit; a current detection unit for detecting the current of the drain of the cascade enhancement-type transistor; a self-power supply unit for outputting a first power supply signal and charging through the drain of the cascade depletion-type transistor after a second level is input to the input end of the current-type drive; a voltage adjustment unit for adjusting the first power supply signal to a second power supply signal; a protection unit for outputting an overvoltage protection signal when the first power supply signal exceeds a first preset voltage and outputting an undervoltage protection signal when the second power supply signal is less than a second preset voltage; a gate logic unit for outputting a reset signal; and a trigger unit for outputting a pulse width modulation signal to the input end of the current-type drive unit and resetting according to the reset signal. The present invention can reduce the probability of damage and failure of gallium nitride devices in a cascade power structure.

Description

Technical Field

[0001] The embodiments of the present invention relate to the field of power electronics technology, and in particular to a gate drive circuit of a cascade power device and an integrated semiconductor power device. Background Art

[0002] Compared with silicon-based power MOSFETs, silicon-based gallium nitride (GaN) devices have more superior performance, such as higher operating frequency, better temperature resistance and higher power density in power supply applications. Therefore, GaN devices are increasingly used in the field of modern power electronics technology.

[0003] Gallium nitride power transistors can be divided into two categories: depletion mode (d-type) and enhancement mode (e-type). Among them, e-type GaN power transistors are driven by a positive threshold voltage, similar to driving a normally-off n-channel MOSFET, but there are many challenges, including: low threshold voltage, narrow gate drive voltage range, dv / dt and di / dt problems caused by high-speed power switching processes, etc. On the other hand, d-type GaN transistors usually require a negative gate-source voltage to be reliably turned off. However, providing negative voltage levels is uncommon and impractical in practical applications, and power supply switching during operation may cause serious safety issues in normally-on circuits. Therefore, using d-type GaN power transistors in a cascade structure is a recognized and effective use case. However, the high probability of damage and failure of GaN devices in existing cascade structures limits the application of GaN devices. Summary of the Invention

[0004] The present invention provides a gate drive circuit for a cascade power device and an integrated semiconductor power device, so as to reduce the probability of damage and failure of gallium nitride devices in a cascade power structure.

[0005] In a first aspect, an embodiment of the present invention provides a gate drive circuit for a cascade power device, wherein the cascade power device includes a cascade depletion-mode transistor and a cascade enhancement-mode transistor, and the gate drive circuit includes:

[0006] a current-type driving unit, configured to convert a first electrical level at its input terminal into a current signal and output the current signal to the gate of the cascade enhancement-mode transistor via its current output terminal;

[0007] a current detection unit, configured to detect a drain current of the cascade enhancement mode transistor;

[0008] a self-powered unit, configured to output a first power supply signal and charge the first power supply signal through the drain of the cascaded depletion-mode transistor after a second level is input to the input terminal of the current-mode driver; the first level and the second level have opposite polarities;

[0009] a protection unit, configured to output an overvoltage protection signal when the first power supply signal exceeds a first preset voltage, output an undervoltage protection signal when the second power supply signal is less than a second preset voltage, and output an overcurrent protection signal when the drain current of the cascade enhancement mode transistor exceeds a preset current;

[0010] a gate logic unit, configured to output a reset signal when at least one of the undervoltage protection signal and the overcurrent protection signal is inputted into an input terminal thereof;

[0011] a trigger unit, configured to output a pulse width modulation signal to an input terminal of the current-mode driving unit and reset the current-mode driving unit according to the reset signal;

[0012] A voltage regulating unit is used to regulate the first power supply signal into the second power supply signal and then supply power to the current-type driving unit, the protection unit, the gate logic unit and the trigger unit.

[0013] Optionally, the gate drive circuit further includes a delay unit;

[0014] The input end of the delay unit is electrically connected to the voltage output end of the current-type driving unit, and the output end of the delay unit is electrically connected to the state switching end of the current detection unit and the state switching end of the self-power supply unit. The delay unit is used to delay the signal of the voltage output end of the current-type driving unit for a preset time and then output it to the state switching end of the current detection unit and the state switching end of the self-power supply unit; wherein, the current-type driving unit is used to invert the signal of its input end and output it from its voltage output end.

[0015] Optionally, the current detection unit includes: a sensing transistor, a sensing resistor, a first detection NMOS transistor and a second detection NMOS transistor;

[0016] The drain of the sensing transistor is electrically connected to the drain of the cascade enhancement mode transistor, the gate of the sensing transistor serves as the state switching terminal of the current detection unit and is electrically connected to the output terminal of the delay unit, and the source of the sensing transistor is electrically connected to the drain of the first detection NMOS transistor;

[0017] The gate of the first detection NMOS transistor is electrically connected to the output end of the delay unit, and the source of the first detection NMOS transistor is electrically connected to the first end of the sensing resistor;

[0018] The first end of the sensing resistor is electrically connected to the protection unit, and the second end of the sensing resistor is used to be externally connected to a reference ground or an external resistor;

[0019] The drain of the second detection NMOS tube is electrically connected to the source of the sensing transistor, the source of the second detection NMOS tube is electrically connected to the second end of the sensing resistor, and the gate of the second detection NMOS tube serves as the mode selection end of the current detection unit.

[0020] Optionally, the self-power supply unit includes: a pull-up resistor, a pull-up anti-backflow diode, a third NOMS transistor, a fourth NMOS transistor and an energy storage capacitor;

[0021] The first end of the pull-up resistor is electrically connected to the drain of the cascade depletion-mode transistor, and the second end of the pull-up resistor is electrically connected to the drain of the third NMOS transistor; the gate of the third NMOS transistor serves as the state switching end of the self-power supply unit, and the source of the third NMOS transistor is grounded;

[0022] The anode of the pull-up anti-backflow diode is electrically connected to the drain of the cascade depletion-mode transistor, and the cathode of the pull-up anti-backflow diode is electrically connected to the drain of the fourth NMOS transistor;

[0023] The gate of the fourth NMOS transistor is electrically connected to the second end of the pull-up resistor, the source of the fourth NMOS transistor is electrically connected to the first end of the energy storage capacitor, the second end of the energy storage capacitor is grounded, and the first end of the energy storage capacitor is used to output the first supply voltage.

[0024] Optionally, the delay unit includes: a first delay PMOS tube, a second delay PMOS tube, a first delay NMOS tube, a second delay NMOS tube, a first delay resistor, a second delay resistor and a delay capacitor;

[0025] The source of the first delay PMOS transistor and the source of the second delay PMOS transistor are connected to serve as the power supply end of the delay unit, the drain of the first delay PMOS transistor is electrically connected to the first end of the first delay resistor, and the gate of the first delay PMOS transistor and the gate of the first delay NMOS transistor are connected to serve as the input end of the delay unit;

[0026] The drain of the first delay NMOS transistor is electrically connected to the first end of the second delay resistor, and the source of the first delay NMOS transistor is grounded;

[0027] The drain of the second delay PMOS transistor is connected to the drain of the second delay NMOS transistor and serves as the output end of the delay unit, and the gate of the second delay PMOS transistor is electrically connected to the second end of the first delay resistor;

[0028] The gate of the second delay NMOS tube is electrically connected to the second end of the second delay resistor, the second end of the first delay resistor and the first end of the delay capacitor. The source of the second delay NMOS tube is grounded; the second end of the delay capacitor is grounded.

[0029] Optionally, the current-mode driving unit includes an inverter and a current mirror;

[0030] The input end of the inverter serves as the input end of the current-mode driving unit, and the output end of the inverter serves as the voltage output end of the current-mode driving unit;

[0031] The input end of the current mirror is electrically connected to the output end of the inverter, and the output end of the current mirror serves as the current output end of the current-type driving unit.

[0032] Optionally, the inverter includes a first driving PMOS transistor and a first driving NMOS transistor;

[0033] The source of the first driving PMOS transistor serves as the power supply terminal of the current-mode driving unit, the gate of the first driving PMOS transistor is connected to the gate of the first driving NMOS transistor and serves as the input terminal of the inverter, the drain of the first driving PMOS transistor is connected to the drain of the first driving NMOS transistor and serves as the output terminal of the inverter, and the source of the first driving NMOS transistor is grounded;

[0034] The current mirror includes a second driving PMOS transistor, a third driving PMOS transistor, a fourth driving PMOS transistor, a fifth driving PMOS transistor and a reference resistor;

[0035] The source of the second driving PMOS transistor is connected to the source of the fourth driving PMOS transistor and serves as the input end of the current mirror, the gate of the second driving PMOS transistor is electrically connected to the gate of the fourth driving PMOS transistor, and the drain of the second driving PMOS transistor is electrically connected to the drain of the third driving PMOS transistor and the gate of the second driving PMOS transistor;

[0036] The gate of the third driving PMOS transistor is electrically connected to the gate of the fifth driving PMOS transistor, and the source of the third driving PMOS transistor is electrically connected to the gate of the third driving PMOS transistor and the first end of the reference resistor;

[0037] The second end of the reference resistor is grounded, the source of the fifth driving PMOS transistor is electrically connected to the drain of the fourth driving PMOS transistor, and the drain of the fifth driving PMOS transistor serves as the output end of the current mirror.

[0038] Optionally, the gate drive circuit further includes a blanking unit, which is used to filter the undervoltage protection signal and the overcurrent protection signal and output them to the gate logic unit, and filter the overvoltage protection signal and output it to the outside of the gate drive circuit.

[0039] In a second aspect, an embodiment of the present invention provides an integrated semiconductor power device, which includes a cascade power device and the gate drive circuit of the cascade power device described in the first aspect, wherein the source of the cascade depletion-mode transistor is electrically connected to the drain of the cascade enhancement-mode transistor, and the gate of the cascade depletion-mode transistor is electrically connected to the source of the cascade enhancement-mode transistor.

[0040] Optionally, the cascaded depletion-mode power device is integrated into a first integrated unit, and the gate drive circuit and the cascaded enhancement-mode transistor are integrated into a second integrated unit.

[0041] Optionally, the gate drive circuit further includes a delay unit;

[0042] The input end of the delay unit is electrically connected to the voltage output end of the current-type driving unit, and the output end of the delay unit is electrically connected to the state switching end of the current detection unit and the state switching end of the self-power supply unit. The delay unit is used to delay the signal of the voltage output end of the current-type driving unit for a preset time and then output it to the state switching end of the current detection unit and the state switching end of the self-power supply unit; wherein, the current-type driving unit is used to invert the signal of its input end and output it from its voltage output end;

[0043] The current detection unit includes: a sensing transistor, a sensing resistor, a first detection NMOS tube and a second detection NMOS tube;

[0044] The drain of the sensing transistor is electrically connected to the drain of the cascade enhancement mode transistor, the gate of the sensing transistor serves as the state switching terminal of the current detection unit and is electrically connected to the output terminal of the delay unit, and the source of the sensing transistor is electrically connected to the drain of the first detection NMOS transistor;

[0045] The gate of the first detection NMOS transistor is electrically connected to the output end of the delay unit, and the source of the first detection NMOS transistor is electrically connected to the first end of the sensing resistor;

[0046] The first end of the sensing resistor is electrically connected to the protection unit, and the second end of the sensing resistor is used to be externally connected to a reference ground or an external resistor;

[0047] The drain of the second detection NMOS transistor is electrically connected to the source of the sensing transistor, the source of the second detection NMOS transistor is electrically connected to the second end of the sensing resistor, and the gate of the second detection NMOS transistor serves as a mode selection terminal of the current detection unit;

[0048] The sensing transistor and the cascade enhancement mode transistor are same-cell devices.

[0049] The technical solution of this embodiment uses a gate drive circuit that can not only control the cascade power device to perform power conversion, but also detect and protect the voltage and current of the cascade power device during operation, thereby reducing the probability of damage and failure of the gallium nitride device in the cascade power device. In addition, since the gate drive circuit integrates a voltage regulation unit and a self-power supply unit, it can flexibly select whether to draw power from the internal circuit or connect it externally, thereby improving the circuit's integration, reducing the volume, and reducing the difficulty of subsequent applications. BRIEF DESCRIPTION OF THE DRAWINGS

[0050] Figure 1 A schematic diagram of the circuit structure of a cascade power device provided in an embodiment of the present invention;

[0051] Figure 2 A schematic diagram of the circuit structure of a gate drive circuit of a cascade power device provided by an embodiment of the present invention;

[0052] Figure 3 A schematic diagram of a circuit structure when a gate drive circuit of a cascade power device is connected to a cascade power device according to an embodiment of the present invention;

[0053] Figure 4 A schematic diagram of the circuit structure of a gate drive circuit of another cascade power device provided by an embodiment of the present invention;

[0054] Figure 5 A schematic diagram of the circuit structure of a current detection unit provided in an embodiment of the present invention;

[0055] Figure 6 A schematic diagram of the circuit structure of a self-powered unit provided in an embodiment of the present invention;

[0056] Figure 7 A schematic diagram of the circuit structure of a delay unit provided in an embodiment of the present invention;

[0057] Figure 8 A schematic diagram of the circuit structure of a current-mode driving unit provided in an embodiment of the present invention;

[0058] Figure 9 A schematic diagram of the circuit structure of an integrated power semiconductor device provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0059] The present invention will be further described in detail below with reference to the accompanying drawings and examples. It will be understood that the specific embodiments described herein are intended only to illustrate the present invention and are not intended to limit the present invention. It should also be noted that, for ease of description, the accompanying drawings only illustrate portions relevant to the present invention, not all structures.

[0060] Figure 1 A schematic diagram of a circuit structure of a cascade power device provided by an embodiment of the present invention, referring to Figure 1 The cascade power device includes a cascade depletion-mode transistor 121 and a cascade enhancement-mode transistor 122. The cascade depletion-mode transistor 121 is a gallium nitride device, while the cascade enhancement-mode transistor 122 is not a gallium nitride device, but a traditional silicon device. The drain Drain1 of the cascade depletion-mode transistor 121 serves as the drain of the cascade power device, the source Source1 of the cascade depletion-mode transistor 121 is electrically connected to the drain Drain2 of the cascade enhancement-mode transistor 122, the gate Gate1 of the cascade depletion-mode transistor 121 is electrically connected to the source Source2 of the cascade enhancement-mode transistor 122, the gate Gate2 of the cascade enhancement-mode transistor 122 serves as the gate of the cascade power device, and the source Source of the cascade enhancement-mode transistor 122 serves as the source of the cascade power device, and can be used as the ground terminal GND, for example. The working principle of the cascade power device is as follows: when its gate voltage is a high voltage greater than the threshold voltage of the cascade depletion-mode transistor 121, the cascade enhancement-mode transistor 122 is in a saturated conduction state, the source-drain voltage Vds122 of the cascade enhancement-mode transistor 122 is ≈0, the gate-source voltage Vgs121 of the cascade depletion-mode transistor 121 is =Vds11 ≈0, the cascade depletion-mode transistor 121 is turned on, at this time the cascade power device is in the on state, and the reverse high voltage Vds=(Vds121+Vds122) ≈0; when its gate voltage is small ... gate-source voltage Vgs121 of the cascade enhancement-mode transistor 121 is =Vds11 ≈0, the gate-source voltage Vgs121 of the cascade enhancement-mode transistor 12 When the threshold voltage of the cascode depletion-mode transistor 121 is below the threshold voltage, the cascode enhancement-mode transistor 122 is in the off state, the source-drain voltage Vds122 of the cascode enhancement-mode transistor 122 is greater than zero, and the gate-source voltage Vgs121 of the cascode depletion-mode transistor 121 is equal to -Vds122. If Vgs121 is lower than the threshold voltage of the cascode depletion-mode transistor 121, the cascode depletion-mode transistor 121 is also in the off state. At this time, the cascode power device is in the off state, and most of the reverse high voltage Vds is borne by the cascode depletion-mode transistor 121.

[0061] Figure 2 A schematic diagram of a gate drive circuit for a cascaded power device according to an embodiment of the present invention is provided. Figure 2 , Figure 3A schematic diagram of a circuit structure when a gate drive circuit of a cascade power device is connected to a cascade power device according to an embodiment of the present invention, combined with Figure 2 and Figure 3 The gate drive circuit 101 includes: a current-type driving unit 1011, which is used to convert the first level of its input terminal into a current signal and then output it to the gate of the cascade enhancement-mode transistor 122 through its current output terminal Vg1; a current detection unit 1012, which is used to detect the current of the drain Drain2 of the cascade enhancement-mode transistor 122; a self-power supply unit 1013, which is used to output a first power supply signal and charge the drain Drain1 of the cascade depletion-mode transistor 121 after inputting a second level at the input terminal of the current-type driving unit 1011, wherein the first level and the second level have opposite polarities; a protection unit, which is used to output an overvoltage protection signal when the first power supply signal exceeds a first preset voltage. signal, outputting an undervoltage protection signal when the second power supply signal is less than a second preset voltage, and outputting an overcurrent protection signal when the current of the drain of the cascade enhancement mode transistor 122 exceeds a preset current; a gate logic unit 1017, outputting a reset signal when at least one of the undervoltage protection signal and the overcurrent protection signal is inputted at its input terminal; a trigger unit 1018, outputting a pulse width modulation signal to the input terminal of the current mode drive unit, and resetting according to the reset signal; a voltage regulating unit 1014, supplying power to the current mode drive unit 1011, the protection unit, the gate logic unit 1017 and the trigger unit 1018 after regulating the first power supply signal to the second power supply signal.

[0062] Specifically, when a pulse width control signal is input to the gate of a cascade power device, a signal can be output to the load between its source and drain. When the pulse width modulation signal is different (such as duty cycle, frequency, etc.), the output signal between the source and drain of the cascade power device is also different. Therefore, the power conversion function can be achieved by inputting a suitable pulse width modulation signal.The current-mode driving unit 1011 can convert the first level into a driving current output to the gate of the cascade power device when the first level is input to the input terminal thereof, thereby controlling the conduction of the cascade power device. The first level can be, for example, a low level, and the second level is a high level at this time. That is to say, when the input terminal of the current-mode driving unit inputs a low level, the current output terminal Vg1 of the current-mode driving unit outputs a driving current. When the input terminal of the current-mode driving unit inputs a high level, the current output terminal Vg1 of the current-mode driving unit has no output. When the cascade power device is working, the current output terminal Vg1 of the current-mode driving unit 1011 outputs a driving current, and at this time there is a large voltage on the drain Drain1 of the cascade depletion transistor 121. , the voltage can be provided to the self-power supply unit 1013, the self-power supply unit 1013 can store energy, thereby outputting a first power supply signal, when the input end of the current-mode driving unit 1011 is connected to the first level and the drain Drain1 of the cascade depletion-mode transistor 121 is connected to the operating voltage, the cascade power device is turned on, and the self-power supply unit only outputs the first power supply signal without charging, so that it is regulated by the voltage regulating unit and used by each unit in the gate driving circuit, thereby ensuring the stability of the power supply, thereby ensuring that the cascade power device can work stably; when the input end of the current-mode driving unit 1011 is connected to the second level and the drain Drain1 of the cascade depletion-mode transistor 121 is connected to the operating voltage, the cascade power device is not turned on, and the self-power supply unit On the one hand, the self-power supply unit 1013 can be charged through the drain of the cascade depletion-mode transistor 121, and on the other hand, it can output a first power supply signal; it should be noted that the self-power supply unit 1013 can lead to an external terminal Cp, and the power supply output terminal Cp can be used to connect other energy storage units, thereby increasing the ability of the self-power supply unit 1013 to store electrical energy; since the cascade power device is a power device, its operating voltage is generally large, and thus the first power supply signal output by the self-power supply unit 1013 is generally large, and cannot be directly used for powering the various units in the gate drive circuit. The first power supply signal can be adjusted to a second power supply signal through the voltage adjustment unit 1014, and specifically, the first power supply signal can be stepped down to a second power supply signal by stepping down the voltage. signal, thereby powering the units that need power in the gate drive circuit (current type drive unit 1011 and protection unit, and may also include gate logic unit 1017, trigger unit 1018 and current detection unit 1012). It should be noted that, in addition to outputting the second power supply signal, the output terminal VDD of the voltage regulating unit 1014 can also lead out a port to the outside of the gate drive circuit. When the self-power supply unit 1013 cannot output the first power supply signal, the voltage regulating unit 1014 cannot output the second power supply signal. At this time, a voltage signal can be connected through the external port led out from the output terminal of the voltage regulating unit 1014, thereby powering each unit in the gate drive circuit and ensuring the normal operation of each unit in the gate drive circuit.The current detection unit 1012 can detect the current flowing through the drain Drain2 of the cascade enhancement-mode transistor 122 in real time under working conditions. The protection unit may specifically include a current protection unit 1015 and a voltage protection unit 1016. Both the current protection unit 1015 and the voltage protection unit 1016 can be composed of comparators. When the current of the drain Drain2 of the cascade enhancement-mode transistor 122 is too large (exceeding a preset current), the cascade power device is likely to burn out. This may be due to excessive driving current. The current protection unit 1015 can generate an overcurrent protection signal. When the first power supply signal is large, it may be due to excessive voltage applied to the drain of the cascade depletion-mode transistor 121, which may also burn out the cascade depletion-mode transistor 121. In this case, the voltage protection unit 1016 can generate an overvoltage control signal. When the second power supply signal is small, each module in the gate drive circuit 101 is in an undervoltage state, which may cause the cascade power device to output an error. In this case, the voltage protection unit 1016 can output an undervoltage protection signal. When an overcurrent protection signal and an undervoltage protection signal are generated, it indicates that the cascade power device is operating in an abnormal state. Therefore, a reset signal can be output through the gate logic unit 1017 to control the reset of the trigger unit 1018, thereby shutting down the output of the current-type driving unit 1011 to prevent damage to the cascade power device; when an overvoltage protection signal is generated, it indicates that the external voltage of the cascade power device is too large. Therefore, an overvoltage output terminal Vov can be set on the gate drive circuit. The overvoltage output terminal Vov is used to output the overvoltage protection signal to the outside (such as an external controller), so that the external controller is informed that the external voltage of the cascade power device is too large, and can adjust the external voltage in time to prevent damage to the cascade power device.

[0063] Both the undervoltage protection signal and the overcurrent protection signal can be low. In this case, the gate logic unit 1017 can be, for example, an AND gate, one of whose two input terminals receives the undervoltage protection signal and the other receives the overcurrent protection signal, and the output terminal outputs a reset signal. The trigger unit 1018 can be, for example, a T-type inverter, including a power supply terminal VD, a reset terminal RST, an input terminal, and an output terminal Q. When the reset terminal RST is high, it indicates that the protection unit has neither output the overcurrent protection signal nor the undervoltage protection signal. In this case, the output signal of the output terminal Q of the trigger unit 1018 is consistent with the signal of its input terminal. When the reset terminal RST is low, it indicates that the protection unit has output at least one of the overcurrent protection signal and the undervoltage protection signal. The trigger unit 1018 is reset at this time. The reset can, for example, lock the trigger unit 1018 to prevent its output terminal Q from outputting a signal, that is, to prevent the input terminal of the current-type driving unit 1011 from inputting the first level, thereby shutting down the cascade power device. The input terminal of the trigger unit 1018 can be used as a driving signal input terminal PWM of the gate driving circuit for inputting a pulse width modulation signal, thereby controlling the cascade power device to perform power conversion.

[0064] The technical solution of this embodiment uses a gate drive circuit that can not only control the cascade power device to perform power conversion, but also detect and protect the voltage and current of the cascade power device during operation, thereby reducing the probability of damage and failure of the gallium nitride device in the cascade power device. In addition, since the gate drive circuit integrates a voltage regulation unit and a self-power supply unit, it can flexibly select whether to draw power from the internal circuit or connect it externally, thereby improving the circuit's integration, reducing the volume, and reducing the difficulty of subsequent applications.

[0065] Optionally, continue to refer to Figures 1 to 3 The gate drive circuit 101 further includes a delay unit 1010; the delay unit 1010 is used to delay the signal of the voltage output terminal Vg1' of the current-type drive unit 1011 for a preset time and then output it to the state switching terminal of the current detection unit 1012 and the state switching terminal of the self-power supply unit 1013; wherein, the current-type drive unit 1011 is used to invert the signal of its input terminal and output it from its voltage output terminal Vg1'.

[0066] Specifically, when the conduction state of the cascade power device is switched, such as from the conduction state to the off state, the state of the current detection unit needs to be switched from detecting current to not detecting current, and the self-power supply unit needs to be switched from outputting the first power supply signal to outputting the first power supply signal and charging; when the cascade power device is switched from the off state to the conduction state, the state of the current detection unit needs to be switched from not detecting current to detecting current, and the state of the self-power supply unit also needs to be switched, from only outputting the first power supply signal to both outputting the first power supply signal and charging to only outputting the first power supply signal; in this embodiment, the current detection unit 1013 includes a state switching end, and the current detection unit 1013 can only detect when a valid signal is input to its state switching end, thereby detecting the current flowing through the drain of the cascade enhancement transistor 122; the self-power supply unit 1013 includes a state switching end, when When a valid signal is input to its state switching end, the self-power supply unit 1013 is in a state of not charging through the drain of the cascade depletion-type transistor 121 and only outputting the first power supply signal. When an invalid signal is input to the charging control end of the self-power supply unit 1013, the self-power supply unit 1013 is in a state of both charging through the drain of the cascade depletion-type transistor 121 and outputting the first power supply signal. The valid signal is, for example, a high level, and the invalid signal is correspondingly a low level. By setting the delay unit 1010, when the signal at the input end of the current-type driving unit 1011 changes, the signal at its current output end changes immediately, that is, the conduction state of the cascade power device changes immediately, but the signal at the output end of the delay unit 1010 changes only after a preset time, thereby controlling the state of the current detection unit 1012 and controlling the state of the self-power supply unit 1013 to switch. That is, by setting the delay unit 1010, the state switching of the cascade power device can be performed first, and the current detection of the current detection unit and the state switching of the self-power supply unit can be performed later, thereby avoiding the high voltage that may occur when the current detection unit and the self-power supply unit are turned on transiently and burn out the self-power supply unit and the current detection unit.

[0067] Optionally, Figure 4 A circuit structure diagram of a gate drive circuit of another cascade type power device provided in an embodiment of the present invention, with reference to Figure 4 The gate drive circuit also includes a blanking unit 1019, which is used to filter the undervoltage protection signal and the overcurrent protection signal and output them to the gate logic unit 1017, and filter the overvoltage protection signal and output it to the outside of the gate drive circuit.

[0068] Specifically, blanking unit 1019 may include, for example, a potential safety time control circuit and a blanking filter circuit. During the switching process of cascaded power devices, parasitic parameters and high switching speeds may generate varying degrees of oscillation, leading to missampling of the feedback voltage and, consequently, inaccurate detection results for voltage and current protection. Blanking unit 1019 can generate filtered overcurrent protection signals, overvoltage protection signals, and undervoltage protection signals, thereby improving protection accuracy.

[0069] Optionally, Figure 5 A schematic diagram of the circuit structure of a current detection unit provided by an embodiment of the present invention, combined with Figure 4 and Figure 5 The current detection unit 1012 includes: a sensing transistor M0, a sensing resistor Rsense, a first detection NMOS transistor M1, and a second detection NMOS transistor M2; the drain of the sensing transistor M0 is electrically connected to the drain Drain2 of the cascade enhancement transistor, the gate of the sensing transistor M0 serves as the state switching end of the current detection unit 1012, and is electrically connected to the output end Vg2 of the delay unit 1010, the source of the sensing transistor M0 is electrically connected to the drain of the first detection NMOS transistor M1; the gate of the first detection NMOS transistor M1 is electrically connected to the output end Vg2 of the delay unit 1010 The source of the first detection NMOS tube M1 is electrically connected to the first end of the sensing resistor Rsense; the first end Ic of the sensing resistor Rsense is electrically connected to the protection unit, and the second end Isense of the sensing resistor Rsense is used to be externally connected to a reference ground or an external resistor; the drain of the second detection NMOS tube M2 is electrically connected to the source of the sensing transistor M0, the source of the second detection NMOS tube M2 is electrically connected to the second end Isense of the sensing resistor Rsense, and the gate of the second detection NMOS tube serves as the mode selection terminal Ictl of the current detection unit 1012.

[0070] Specifically, each transistor comprising the current sensing unit 1012 is a conventional silicon device, not a gallium nitride device. The mode selection terminal Ictl of the current sensing unit 1012 controls the current sampling mode of the current sensing unit 1012. When the mode selection terminal Ictl inputs a low level, the second sensing NMOS transistor M2 is turned off. When the output terminal Vg2 of the delay unit outputs a high level, the first sensing NMOS transistor M1 is turned on. The sense resistor Rsense is then responsible for detecting the output current. At this point, the second terminal Isense of the sense resistor Rsense can be connected to ground. When the mode selection terminal Ictl inputs a high level, the second sensing NMOS transistor M2 is turned on, short-circuiting the first sensing NMOS transistor M1 and the sense resistor Rsense. At this point, the second terminal Isense of the sense resistor Rsense can be connected to any other sampling resistor or circuit, thereby achieving controllable current sampling. The first terminal Ic of the sense resistor Rsense outputs the drain current of the cascade enhancement-mode transistor at a fixed sampling ratio to the current protection unit 1015, thereby determining whether the current is abnormal. When the output terminal Vg2 of the delay unit 1010 outputs a high level, the sensing transistor M0 is turned on, thereby controlling the current detection unit 1012 to enter a state of detecting current, and when the output terminal Vg2 of the delay unit 1010 outputs a low level, the sensing transistor M0 is turned off, thereby controlling the current detection unit 1012 to enter a state of not detecting current.

[0071] Optionally, Figure 6 A schematic diagram of the circuit structure of a self-powered unit provided in an embodiment of the present invention, with reference to Figure 6 The self-power supply unit 1013 includes: a pull-up resistor Rup, a pull-up anti-backflow diode Dup, a third NMOS transistor, a fourth NMOS transistor M4 and an energy storage capacitor Cbp; a first end of the pull-up resistor Rup is electrically connected to the drain Drain1 of the cascade depletion-type transistor, and a second end of the pull-up resistor Rup is electrically connected to the drain of the third NMOS transistor M3; the gate of the third NMOS transistor M3 serves as a state switching end of the self-power supply unit 1013, and the source of the third NMOS transistor M3 is grounded; an anode of the pull-up anti-backflow diode Dup is electrically connected to the drain Drain1 of the cascade depletion-type transistor, and a cathode of the pull-up anti-backflow diode Dup is electrically connected to the drain of the fourth NMOS transistor M4; a gate of the fourth NMOS transistor M4 is electrically connected to the second end of the pull-up resistor Rup, a source of the fourth NMOS transistor M4 is electrically connected to the first end of the energy storage capacitor Cbp, a second end of the energy storage capacitor Cbp is grounded, and the first end of the energy storage capacitor Cbp is used to output a first supply voltage.

[0072] Specifically, if Figure 6As shown in FIG, when the output terminal Vg2 of the delay unit 1010 outputs a high level, the third NMOS transistor M3 is turned on, so that the gate of the fourth NMOS transistor M4 is grounded, and the fourth NMOS transistor M4 is turned off, thereby disconnecting the energy storage capacitor Cbp from the drain Drain1 of the cascade depletion transistor, and the energy storage capacitor Cbp cannot be charged. That is, when the input terminal of the current-type driving unit inputs a low level and the cascade power device is turned on, the self-power supply unit 1013 outputs the first power supply signal only through the energy storage capacitor Cbp; when the output terminal Vg2 of the delay unit 1010 outputs a low level, the third NMOS transistor M3 is turned off, so that the fourth The gate potential of the NMOS tube M4 is pulled up by the pull-up resistor Rup, and the fourth NMOS tube M4 is turned on, so that the energy storage capacitor Cbp is charged through the drain Drain1 of the cascade depletion-type transistor and outputs the first power supply signal to the outside; the pull-up anti-backflow diode Dup is used to prevent the energy storage capacitor Cbp from charging the drain Drain1 of the cascade depletion-type transistor; the external terminal Cp of the self-power supply unit 1013 is the first end of the energy storage capacitor Cbp, and a larger power energy storage capacitor can be achieved by connecting a capacitor in parallel to the external terminal Cp, or the external terminal Cp can also be connected to a circuit with a voltage regulation function to achieve a more stable power supply voltage.

[0073] Optionally, Figure 7 A circuit diagram of a delay unit provided in an embodiment of the present invention is provided. Figure 7 The delay unit 1010 includes: a first delay PMOS transistor Md1, a second delay PMOS transistor Md3, a first delay NMOS transistor Md2, a second delay NMOS transistor, a first delay resistor Rd1, a second delay resistor Rd2 and a delay capacitor Cd1; the source of the first delay PMOS transistor Md1 is connected to the source of the second delay PMOS transistor Md3 and serves as the power supply end of the delay unit, the drain of the first delay PMOS transistor Md1 is electrically connected to the first end of the first delay resistor Rd1, and the gate of the first delay PMOS transistor Md1 is connected to the gate of the first delay NMOS transistor Md2 and serves as the input end of the delay unit; the first delay The drain of the NMOS transistor Md2 is electrically connected to the first end of the second delay resistor Rd2, and the source of the first delay NMOS transistor Md2 is grounded; the drain of the second delay PMOS transistor Md3 is connected to the drain of the second delay NMOS transistor Md4 and serves as the output end of the delay unit, and the gate of the second delay PMOS transistor Md3 is electrically connected to the second end of the first delay resistor Rd1; the gate of the second delay NMOS transistor Md4 is electrically connected to the second end of the second delay resistor Rd2, the second end of the first delay resistor Rd1, and the first end of the delay capacitor Cd1, and the source of the second delay NMOS transistor Md4 is grounded; the second end of the delay capacitor Cd1 is grounded.

[0074] Specifically, the power supply end of the delay unit 1010 is electrically connected to the output end VDD of the voltage regulating unit 1014. When the voltage output end Vg1' of the current-mode driving unit 1011 outputs a low level to the input end of the delay unit 1010, the first delay PMOS tube Md1 is turned on, the first delay NMOS tube Md2 is turned off, and the delay capacitor Cd1 is slowly charged through the first delay resistor Rd1. When the terminal voltage of the delay capacitor Cd1 reaches the threshold voltage of the second delay NMOS tube Md4, the second delay NMOS tube Md4 is turned on, and the output end Vg2 of the delay unit 1010 is a low-level signal after the delay; when ... delay unit When the input end of the element 1010 outputs a high level, the first delay PMOS transistor Md1 is turned off, the first delay NMOS transistor Md2 is turned on, and the delay capacitor Cd1 is slowly discharged through the second delay resistor Rd2. When the terminal voltage of the delay capacitor Cd1 reaches the threshold voltage of the second delay PMOS transistor Md3, the second delay PMOS transistor Md3 is turned on, and the output end Vg2 of the delay unit 1010 is a high-level signal after the delay. The delay time of the low-level signal can be adjusted by configuring at least one of the resistance value of the first delay resistor Rd1 and the delay capacitor Cd1, and the delay time of the high-level signal can be adjusted by configuring at least one of the resistance value of the second delay resistor Rd2 and the delay capacitor Cd1.

[0075] Optionally, Figure 8 A schematic diagram of a circuit structure of a current-type driving unit provided by an embodiment of the present invention, with reference to Figure 8 The current-type driving unit includes an inverter and a current mirror; the input end of the inverter serves as the input end Vq of the current-type driving unit, and the output end of the inverter serves as the voltage output end Vgl' of the current-type driving unit; the input end of the current mirror is electrically connected to the output end of the inverter, and the output end of the current mirror serves as the current output end Vg1 of the current-type driving unit.

[0076] For example, Figure 8As shown, the inverter includes a first driving PMOS transistor Mdrv1 and a first driving NMOS transistor Mdrv2. The source of the first driving PMOS transistor Mdrv1 serves as the power supply terminal of the current-type driving unit. The gate of the first driving PMOS transistor Mdrv1 is connected to the gate of the first driving NMOS transistor Mdrv2 and serves as the input terminal of the inverter. The drain of the first driving PMOS transistor Mdrv1 is connected to the drain of the first driving NMOS transistor Mdrv2 and serves as the output terminal of the inverter. The source of the first driving NMOS transistor Mdrv2 is grounded. When a low level is input to the input terminal of the inverter, the first driving NMOS transistor Mdrv2 is turned off and the first driving PMOS transistor Mdrv1 is turned on, so that the output terminal of the inverter outputs the signal of its power supply terminal, that is, outputs a high level. When the output terminal of the inverter outputs a high level, the first driving NMOS transistor Mdrv2 is turned on and the first driving PMOS transistor Mdrv1 is turned off, so that the output terminal of the inverter outputs a ground signal, that is, outputs a low level.

[0077] The current mirror includes a second driving PMOS transistor Mdrv3, a third driving PMOS transistor Mdrv4, a fourth driving PMOS transistor Mdrv5, a fifth driving PMOS transistor Mdrv6 and a reference resistor Rref; the source of the second driving PMOS transistor Mdrv3 is connected to the source of the fourth driving PMOS transistor Mdrv5 and serves as the input end of the current mirror, the gate of the second driving PMOS transistor Mdrv3 is electrically connected to the gate of the fourth driving PMOS transistor Mdrv5, and the drain of the second driving PMOS transistor Mdrv3 is electrically connected to the drain of the third driving PMOS transistor Mdrv4. The gate of the third driving PMOS transistor Mdrv4 is electrically connected to the gate of the fifth driving PMOS transistor Mdrv6, the source of the third driving PMOS transistor Mdrv4 is electrically connected to the gate of the third driving PMOS transistor Mdrv4 and the first end of the reference resistor Rref; the second end of the reference resistor Rref is grounded, the source of the fifth driving PMOS transistor Mdrv6 is electrically connected to the drain of the fourth driving PMOS transistor Mdrv5, and the drain of the fifth driving PMOS transistor Mdrv6 serves as the output end of the current mirror.

[0078] Specifically, when the output terminal of the inverter outputs a low level, the fourth driver PMOS transistor Mdrv5 and the fifth driver PMOS transistor Mdrv6 are turned off, and the gate of the cascade enhancement-mode transistor releases charge through the body diodes of the fourth driver PMOS transistor Mdrv5 and the fifth driver PMOS transistor Mdrv6. When the output terminal of the inverter outputs a high level, that is, when the input terminal of the current-type driving unit inputs a low level, the second driver PMOS transistor Mdrv3, the third driver PMOS transistor Mdrv4, the fourth driver PMOS transistor Mdrv5, and the fifth driver PMOS transistor Mdrv6 are all turned on, and the gate of the cascade enhancement-mode transistor is charged through the fourth driver PMOS transistor Mdrv5 and the fifth driver PMOS transistor Mdrv6. At the same time, the magnitude of the charging current can be controlled by controlling the current of the second driver PMOS transistor Mdrv3, the third driver PMOS transistor Mdrv4, and the reference resistor Rref branch.

[0079] Figure 9 A schematic diagram of a circuit structure of an integrated power semiconductor device provided by an embodiment of the present invention, with reference to Figure 9 The integrated power semiconductor device 10 includes a cascade power device and a gate drive circuit of the cascade power device provided by any embodiment of the present invention, the source of the cascade depletion-mode transistor 121 is electrically connected to the drain of the cascade enhancement-mode transistor 122, and the gate of the cascade depletion-mode transistor 121 is electrically connected to the source of the cascade enhancement-mode transistor 122.

[0080] The integrated power semiconductor device 10 integrates and packages a cascade power device and a gate drive circuit. The ports of the integrated power semiconductor device 10 include the drain Drain1 of the cascade depletion-mode transistor, the port GND after the gate of the cascade depletion-mode transistor is connected to the source of the cascade enhancement-mode transistor 122, and Drain1 and GND serve as output ports of the cascade power device, which can be used to output a power signal to the load; the ports of the integrated power semiconductor device 10 also include the external connection terminal Cp of the self-power supply circuit in the gate drive circuit, the output terminal VDD of the voltage regulation unit, the second terminal Isense of the sensing resistor, the mode selection terminal Ictl of the current detection unit, the drive signal input terminal PWM and the overvoltage output terminal Vov. Since it includes the gate drive circuit provided by any embodiment of the present invention, it also has the same beneficial effects and will not be repeated here.

[0081] Alternatively, as Figure 9 As shown, the cascode depletion-mode transistor 121 is integrated into the first integrated unit 102 , and the gate driving circuit 101 and the cascode enhancement-mode transistor 122 are integrated into the second integrated unit.

[0082] Specifically, the cascaded depletion-mode transistors in the first integrated unit 102 are gallium nitride devices, while the transistors in the second integrated unit 101 are all traditional silicon devices. They can be manufactured separately during production, and then the first integrated unit 102 and the second integrated unit 101 are integrated and packaged into an integrated power semiconductor device 10, thereby greatly improving the integration of the device, reducing the required PCB space and parasitic parameters, and reducing design difficulty.

[0083] Optionally, the gate drive circuit further includes a delay unit; the input end of the delay unit is electrically connected to the voltage output end of the current-type drive unit, the output end of the delay unit is electrically connected to the state switching end of the current detection unit and the state switching end of the self-power supply unit, and the delay unit is used to delay the signal of the voltage output end of the current-type drive unit for a preset time and then output it to the state switching end of the current detection unit and the state switching end of the self-power supply unit; wherein the current-type drive unit is used to invert the signal of its input end and then output it from its voltage output end; the current detection unit includes: a sensing transistor, a sensing resistor, a first detection NMOS tube and a second detection NMOS tube; the drain of the sensing transistor is electrically connected to the drain of the cascade enhancement transistor, and the sensing transistor The gate serves as the state switching end of the current detection unit and is electrically connected to the output end of the delay unit. The source of the sensing transistor is electrically connected to the drain of the first detection NMOS tube. The gate of the first detection NMOS tube is electrically connected to the output end of the delay unit, and the source of the first detection NMOS tube is electrically connected to the first end of the sensing resistor. The first end of the sensing resistor is electrically connected to the protection unit, and the second end of the sensing resistor is used for an external reference ground or an external resistor. The drain of the second detection NMOS tube is electrically connected to the source of the sensing transistor, and the source of the second detection NMOS tube is electrically connected to the second end of the sensing resistor. The gate of the second detection NMOS tube serves as the mode selection end of the current detection unit. The sensing transistor and the cascade enhancement transistor are homocellular devices.

[0084] Specifically, combined Figure 5 and Figure 9 The sensing transistor M0 and the cascade enhancement transistor 122 are homocell devices, that is, the cascade enhancement transistor 122 and the sensing transistor M0 are formed on the same substrate, but have different gate widths. As a result, when the gate-source voltage of the cascade enhancement transistor 122 is consistent with the gate-source voltage of the sensing transistor M0, the current flowing through the cascade enhancement transistor 122 is different from the current flowing through the sensing transistor M0. The gate widths of the two can be set to make the current flowing through the sensing transistor M0 smaller than the current flowing through the cascade enhancement transistor 122. Since only a small portion of the current is used for current sensing, the source current of the Liu Jing cascade power device is close to equal to the load current. The sensing transistor M0 fully utilizes the advantage of close matching between the on-resistances of the units manufactured on the same die to ensure consistent accuracy and temperature stability.

[0085] Note that the above are only preferred embodiments of the present invention and the technical principles employed. Those skilled in the art will understand that the present invention is not limited to the specific embodiments described herein, and that various obvious changes, readjustments, and substitutions can be made by those skilled in the art without departing from the scope of protection of the present invention. Therefore, although the present invention has been described in detail through the above embodiments, the present invention is not limited to the above embodiments and may include many other equivalent embodiments without departing from the concept of the present invention. The scope of the present invention is determined by the scope of the appended claims.

Claims

1. A gate drive circuit for a cascaded power device, wherein the cascaded power device comprises a cascaded depletion-mode transistor and a cascaded enhancement-mode transistor, characterized in that: The gate drive circuit includes: a current-type driving unit, configured to convert a first electrical level at its input terminal into a current signal and output the current signal to the gate of the cascade enhancement-mode transistor via its current output terminal; a current detection unit, configured to detect a drain current of the cascade enhancement mode transistor; a self-powered unit, configured to output a first power supply signal and charge the first power supply signal through the drain of the cascaded depletion-mode transistor after a second level is input to the input terminal of the current-mode driver; the first level and the second level have opposite polarities; a protection unit, configured to output an overvoltage protection signal when the first power supply signal exceeds a first preset voltage, output an undervoltage protection signal when the second power supply signal is less than a second preset voltage, and output an overcurrent protection signal when the drain current of the cascade enhancement mode transistor exceeds a preset current; a gate logic unit, configured to output a reset signal when at least one of the undervoltage protection signal and the overcurrent protection signal is inputted into an input terminal thereof; a trigger unit, configured to output a pulse width modulation signal to an input terminal of the current-mode driving unit and reset the current-mode driving unit according to the reset signal; A voltage regulating unit is used to regulate the first power supply signal into the second power supply signal and then supply power to the current-type driving unit, the protection unit, the gate logic unit and the trigger unit.

2. The gate drive circuit of the cascade power device according to claim 1, characterized in that: The gate drive circuit further includes a delay unit; The input end of the delay unit is electrically connected to the voltage output end of the current-type driving unit, and the output end of the delay unit is electrically connected to the state switching end of the current detection unit and the state switching end of the self-power supply unit. The delay unit is used to delay the signal of the voltage output end of the current-type driving unit for a preset time and then output it to the state switching end of the current detection unit and the state switching end of the self-power supply unit; wherein, the current-type driving unit is used to invert the signal of its input end and output it from its voltage output end.

3. The gate drive circuit of the cascade power device according to claim 2, characterized in that: The current detection unit includes: a sensing transistor, a sensing resistor, a first detection NMOS tube and a second detection NMOS tube; The drain of the sensing transistor is electrically connected to the drain of the cascade enhancement mode transistor, the gate of the sensing transistor serves as the state switching terminal of the current detection unit and is electrically connected to the output terminal of the delay unit, and the source of the sensing transistor is electrically connected to the drain of the first detection NMOS transistor; The gate of the first detection NMOS transistor is electrically connected to the output end of the delay unit, and the source of the first detection NMOS transistor is electrically connected to the first end of the sensing resistor; The first end of the sensing resistor is electrically connected to the protection unit, and the second end of the sensing resistor is used to be externally connected to a reference ground or an external resistor; The drain of the second detection NMOS tube is electrically connected to the source of the sensing transistor, the source of the second detection NMOS tube is electrically connected to the second end of the sensing resistor, and the gate of the second detection NMOS tube serves as the mode selection end of the current detection unit.

4. The gate drive circuit of the cascade power device according to claim 2, wherein: The self-power supply unit includes: a pull-up resistor, a pull-up anti-backflow diode, a third NMOS transistor, a fourth NMOS transistor and an energy storage capacitor; The first end of the pull-up resistor is electrically connected to the drain of the cascade depletion-mode transistor, and the second end of the pull-up resistor is electrically connected to the drain of the third NMOS transistor; the gate of the third NMOS transistor serves as the state switching end of the self-power supply unit, and the source of the third NMOS transistor is grounded; The anode of the pull-up anti-backflow diode is electrically connected to the drain of the cascade depletion-mode transistor, and the cathode of the pull-up anti-backflow diode is electrically connected to the drain of the fourth NMOS transistor; The gate of the fourth NMOS transistor is electrically connected to the second end of the pull-up resistor, the source of the fourth NMOS transistor is electrically connected to the first end of the energy storage capacitor, the second end of the energy storage capacitor is grounded, and the first end of the energy storage capacitor is used to output the first power supply signal.

5. The gate drive circuit of the cascade power device according to claim 2, wherein: The delay unit includes: a first delay PMOS tube, a second delay PMOS tube, a first delay NMOS tube, a second delay NMOS tube, a first delay resistor, a second delay resistor and a delay capacitor; The source of the first delay PMOS transistor and the source of the second delay PMOS transistor are connected to serve as the power supply end of the delay unit, the drain of the first delay PMOS transistor is electrically connected to the first end of the first delay resistor, and the gate of the first delay PMOS transistor and the gate of the first delay NMOS transistor are connected to serve as the input end of the delay unit; The drain of the first delay NMOS transistor is electrically connected to the first end of the second delay resistor, and the source of the first delay NMOS transistor is grounded; The drain of the second delay PMOS transistor is connected to the drain of the second delay NMOS transistor and serves as the output end of the delay unit, and the gate of the second delay PMOS transistor is electrically connected to the second end of the first delay resistor; The gate of the second delay NMOS tube is electrically connected to the second end of the second delay resistor, the second end of the first delay resistor and the first end of the delay capacitor. The source of the second delay NMOS tube is grounded; the second end of the delay capacitor is grounded.

6. The gate drive circuit of the cascade power device according to claim 2, characterized in that: The current-mode driving unit includes an inverter and a current mirror; The input end of the inverter serves as the input end of the current-mode driving unit, and the output end of the inverter serves as the voltage output end of the current-mode driving unit; The input end of the current mirror is electrically connected to the output end of the inverter, and the output end of the current mirror serves as the current output end of the current-type driving unit.

7. The gate drive circuit of the cascade power device according to claim 6, characterized in that: The inverter includes a first driving PMOS tube and a first driving NMOS tube; The source of the first driving PMOS transistor serves as the power supply terminal of the current-mode driving unit, the gate of the first driving PMOS transistor is connected to the gate of the first driving NMOS transistor and serves as the input terminal of the inverter, the drain of the first driving PMOS transistor is connected to the drain of the first driving NMOS transistor and serves as the output terminal of the inverter, and the source of the first driving NMOS transistor is grounded; The current mirror includes a second driving PMOS transistor, a third driving PMOS transistor, a fourth driving PMOS transistor, a fifth driving PMOS transistor and a reference resistor; The source of the second driving PMOS transistor is connected to the source of the fourth driving PMOS transistor and serves as the input end of the current mirror, the gate of the second driving PMOS transistor is electrically connected to the gate of the fourth driving PMOS transistor, and the drain of the second driving PMOS transistor is electrically connected to the drain of the third driving PMOS transistor and the gate of the second driving PMOS transistor; The gate of the third driving PMOS transistor is electrically connected to the gate of the fifth driving PMOS transistor, and the source of the third driving PMOS transistor is electrically connected to the gate of the third driving PMOS transistor and the first end of the reference resistor; The second end of the reference resistor is grounded, the source of the fifth driving PMOS transistor is electrically connected to the drain of the fourth driving PMOS transistor, and the drain of the fifth driving PMOS transistor serves as the output end of the current mirror.

8. The gate drive circuit of the cascade power device according to claim 1, characterized in that: The gate drive circuit further includes a blanking unit, which is used to filter the undervoltage protection signal and the overcurrent protection signal and output them to the gate logic unit, and filter the overvoltage protection signal and output it to the outside of the gate drive circuit.

9. An integrated semiconductor power device, characterized in that: The integrated semiconductor power device includes a cascade power device and a gate drive circuit of the cascade power device according to any one of claims 1 to 8, the source of the cascade depletion-mode transistor is electrically connected to the drain of the cascade enhancement-mode transistor, and the gate of the cascade depletion-mode transistor is electrically connected to the source of the cascade enhancement-mode transistor.

10. The integrated semiconductor power device according to claim 9, characterized in that: The cascade depletion-mode power device is integrated into a first integrated unit, and the gate drive circuit and the cascade enhancement-mode transistor are integrated into a second integrated unit.

11. The integrated semiconductor power device according to claim 10, characterized in that: The gate drive circuit further includes a delay unit; The input end of the delay unit is electrically connected to the voltage output end of the current-type driving unit, and the output end of the delay unit is electrically connected to the state switching end of the current detection unit and the state switching end of the self-power supply unit. The delay unit is used to delay the signal of the voltage output end of the current-type driving unit for a preset time and then output it to the state switching end of the current detection unit and the state switching end of the self-power supply unit; wherein, the current-type driving unit is used to invert the signal of its input end and output it from its voltage output end; The current detection unit includes: a sensing transistor, a sensing resistor, a first detection NMOS tube and a second detection NMOS tube; The drain of the sensing transistor is electrically connected to the drain of the cascade enhancement mode transistor, the gate of the sensing transistor serves as the state switching terminal of the current detection unit and is electrically connected to the output terminal of the delay unit, and the source of the sensing transistor is electrically connected to the drain of the first detection NMOS transistor; The gate of the first detection NMOS transistor is electrically connected to the output end of the delay unit, and the source of the first detection NMOS transistor is electrically connected to the first end of the sensing resistor; The first end of the sensing resistor is electrically connected to the protection unit, and the second end of the sensing resistor is used to be externally connected to a reference ground or an external resistor; The drain of the second detection NMOS transistor is electrically connected to the source of the sensing transistor, the source of the second detection NMOS transistor is electrically connected to the second end of the sensing resistor, and the gate of the second detection NMOS transistor serves as a mode selection terminal of the current detection unit; The sensing transistor and the cascade enhancement mode transistor are same-cell devices.

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