Transparent display device

Abstract

A transparent display device is provided in which reflection visibility between a display region and a non-display region is improved. The transparent display device includes a substrate provided with a display region in which a plurality of pixels having a transmissive portion and a plurality of sub-pixels are provided, and a non-display region adjacent to the display region, having a pad region; a line portion provided above the substrate in the non-display region, having a plurality of lines connected to the pad region; and a circuit portion having a plurality of circuits connected to the plurality of lines in the non-display region, wherein the line portion is provided separately from the circuit portion.

Description

TECHNICAL FIELD

[0001] The disclosure relates to a transparent display apparatus. BACKGROUND

[0002] With the progress of the information age, the demand for display apparatuses for displaying images has increased in various forms. Accordingly, various types of display apparatuses, such as liquid crystal display (LCD) apparatuses, plasma display panel (PDP) apparatuses, organic light emitting display (OLED) apparatuses, and quantum dot light emitting display (QLED) apparatuses, have recently been used.

[0003] Recently, research into a transparent display apparatus in which a user can view an object or an image located at an opposite side by passing through the display apparatus is actively being conducted.

[0004] The transparent display apparatus includes a display area displaying an image and a non-display area including a bezel area, wherein the display area can include a transmissive area capable of transmitting external light and a non-transmissive area. SUMMARY

[0005] In the related art, a plurality of circuits and a plurality of lines for driving pixels of the display area are disposed in the non-display area, and a plurality of pixels are disposed in the display area to display an image. Accordingly, since the structures of the display area and the non-display area are different from each other, a problem of a difference in reflection visibility of external light occurs. This problem related to reflection visibility can be more serious in a case where the plurality of lines and the plurality of circuits are alternately disposed in the non-display area.

[0006] The disclosure has been made in view of the above problems, and it is an object of the disclosure to provide a transparent display apparatus that improves reflection visibility between a display area and a non-display area.

[0007] In addition to the above object of the disclosure as described above, additional objects and features of the disclosure will be clearly understood by those skilled in the art from the following description of the disclosure.

[0008] According to one aspect of the disclosure, the above and other objects can be achieved by providing a transparent display apparatus including a substrate provided with a display area in which a plurality of pixels having a transmissive portion and a plurality of sub-pixels are disposed, and a non-display area adjacent to the display area having a pad area, a line portion disposed in the non-display area above the substrate having a plurality of lines connected to the pad area, and a circuit portion having a plurality of circuits connected to the plurality of lines in the non-display area, wherein the line portion is disposed to be separated from the circuit portion.

[0009] According to another aspect of the present disclosure, the above and other objects can be achieved by providing a transparent display apparatus including a substrate provided with a display area in which a plurality of pixels having a transmissive portion and a plurality of sub-pixels are disposed, and a non-display area adjacent to the display area, having a pad area; a line portion disposed above the substrate in the non-display area, having a plurality of lines connected to the pad area; and a circuit portion having a plurality of circuits connected to the plurality of lines in the non-display area, wherein the circuit portion is disposed between the line portion and the display area.

[0010] Other systems, methods, features and advantages will be, or will become apparent to one with skill in the art upon examination of the following figures and detailed description. It is intended that all such additional systems, methods, features and advantages be included within this description, be within the scope of the present disclosure, and be protected by the following claims. Nothing in this section should be taken as a limitation on those claims. Additional aspects and advantages are discussed below in conjunction with the detailed description. BRIEF DESCRIPTION OF DRAWINGS

[0011] The above and other objects, features and other advantages of the present disclosure will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0012] Figure 1 is a plan view illustrating a transparent display apparatus according to an embodiment of the present disclosure;

[0013] Figure 2A is a plan view illustrating Figure 1 is a schematic enlarged view illustrating a connection relationship between a plurality of clock lines, a ground line, and a buffer portion in part A of

[0014] Figure 2B is a schematic enlarged view illustrating a connection relationship between a plurality of signal lines, a common controller, and a buffer portion in part A of Figure 1

[0015] Figure 3A is a comparative example illustrating reflection visibility in a case where lines and circuits are alternately disposed;

[0016] Figure 3B is a graph illustrating reflection visibility in a case where a plurality of lines and a plurality of circuits are separately disposed in a transparent display apparatus according to an embodiment of the present disclosure;

[0017] Figure 4 is a schematic cross-sectional view taken along line I-I' shown in Figure 2A ​​

[0018] Figure 5 is a diagram illustrating an example of portion B of Figure 2B

[0019] Figure 6 is a diagram illustrating another example of portion B of Figure 5

[0020] Figure 7 is a diagram illustrating another example of portion B of Figure 2B

[0021] Throughout the drawings and detailed description, unless otherwise described, the same drawing references can be understood to refer to the same elements, features and structures. The relative size and depiction of these elements can be exaggerated for clarity, illustration and convenience. DETAILED DESCRIPTION

[0022] Reference will now be made in detail embodiments of the present disclosure, examples of which are illustrated in the accompanying drawings. Whenever possible, the same reference numerals will be used throughout the drawings to refer to the same or like parts.

[0023] Advantages and features of the present disclosure and methods of accomplishing the same can be understood more readily by reference to the following embodiments described in detail in connection with the drawings. The present disclosure may, however, be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete and fully convey the scope of the present disclosure to those skilled in the art.

[0024] The shapes, sizes, proportions, angles, and numbers disclosed in the accompanying drawings for describing the embodiments of the present disclosure are merely examples, and thus the present disclosure is not limited to the illustrated details.

[0025] Like reference numerals refer to like elements throughout. In the following description, detailed descriptions of functions or constructions known in the related art can be omitted when it is determined that such detailed description obscures the gist of the present disclosure.

[0026] In the case of using "include", "have", and "contain" described in the present specification, other parts can be added unless "only" is used. Unless otherwise specified, a singular form can include a plural form.

[0027] In interpreting elements, although not explicitly described, the elements are interpreted to include an error range.

[0028] ​​​In describing positional relationships, for example, when the positional relationship between two parts is described as "on", "above", "below", and "close to", unless "only" or "directly" is used, one or more other parts can be disposed between the two parts.

[0029] In describing temporal relationships, for example, when the temporal order is described as "after", "subsequently", "next", and "before", unless "immediately" or "directly" is used, discontinuous cases can be included.

[0030] It will be understood that, although the terms "first", "second", etc. can be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, a first element could be termed a second element, and, similarly, a second element could be termed a first element, without departing from the scope of the present disclosure.

[0031] The "X-axis direction", "Y-axis direction", "Z-axis direction" should not be interpreted as a geometric relationship of mutual perpendicularity only, but can have a wider directionality within the range in which the elements of the present disclosure can functionally act.

[0032] The term "at least one of" should be understood to include any all combinations of one or more of the listed items. For example, the meaning of "at least one of a first item, a second item, and a third item" is that all combinations of two or more items from among the first item, the second item, and the third item are included, as well as the first item, the second item, or the third item.

[0033] As a person of ordinary skill in the art can fully understand, the features of various embodiments of the present disclosure can be partially or entirely coupled or combined with each other, and can be interoperable and technically driven in various ways with each other. Embodiments of the present disclosure can be implemented independently of each other, or can be implemented together in a dependent relationship.

[0034] Hereinafter, preferred embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0035] Figure 1 is a plan view illustrating a transparent display apparatus according to one embodiment of the present disclosure, Figure 2A is a plan view illustrating Figure 1 is a schematic enlarged view of a connection relationship between a plurality of clock lines, a ground line, and a buffer part in part A of Figure 2B is a schematic enlarged view of a connection relationship between a plurality of clock lines, a ground line, and a buffer part in part A of Figure 1 is a schematic enlarged view of a connection relationship between a plurality of signal lines, a common controller, and a buffer part in part A of Figure 3A is a comparative example illustrating reflection visibility in a case where lines and circuits are alternately disposed, Figure 3Bis a graph illustrating reflection visibility in a case where a plurality of lines and a plurality of circuits are separately disposed in a transparent display apparatus according to one embodiment of the present disclosure, and Figure 4 is a schematic cross-sectional view taken along Figure 2A line I-I' as indicated.

[0036] Hereinafter, the following description will be based on the transparent display apparatus 100 according to one embodiment of the present disclosure being an organic light emitting display apparatus, but is not limited thereto. That is, the transparent display apparatus according to one embodiment of the present disclosure can be implemented as any one of a liquid crystal display apparatus, a field emission display apparatus, a quantum dot light emitting diode apparatus, an electrophoretic display apparatus, and an organic light emitting display apparatus.

[0037] Referring to Figures 1-4 , the transparent display apparatus 100 according to one embodiment of the present disclosure can include a display panel including a gate driver GD having a line portion LNP and a circuit portion GIP, a source driving integrated circuit (hereinafter referred to as "IC") 130, a flexible film 140, a circuit board 150, and a timing controller 160.

[0038] The line portion LNP can include a plurality of lines LN. The circuit portion GIP can include a plurality of circuits GTR. The line portion LNP and the circuit portion GIP can be disposed to be separated from each other. Accordingly, in the transparent display apparatus 100 according to one embodiment of the present disclosure, the plurality of lines can be disposed to be concentrated on one side of the circuit portion GIP, and the plurality of circuits GTR can be disposed to be concentrated on the other side of the line portion LNP. Accordingly, in the transparent display apparatus 100 according to one embodiment of the present disclosure, a difference in reflection visibility for external light can be reduced as compared with a case where the plurality of lines and the plurality of circuits are alternately disposed. This will be described in detail later.

[0039] The display panel can include a substrate 110 and a counter substrate 120 bonded to each other (as shown in Figure 4 ).

[0040] The substrate 110 can include a thin film transistor, and can be a transistor array substrate, a lower substrate, a base substrate, or a first substrate. The substrate 110 can be a transparent glass substrate or a transparent plastic substrate. For example, the substrate 110 can be a transparent glass substrate. Hereinafter, the substrate 110 will be defined as a first substrate.

[0041] The facing substrate 120 can be bonded to the first substrate 110 via a transparent bonding member (not shown). For example, the facing substrate 120 can have a size smaller than that of the first substrate 110, and can be bonded to a remaining portion of the first substrate 110 except for the pad area. The transparent bonding member can be an adhesive member (or a transparent adhesive). The facing substrate 120 can be an upper substrate, a second substrate, or a package substrate. The facing substrate 120 can be bonded to the first surface of the first substrate 110 by a substrate bonding process using an adhesive member. Hereinafter, the facing substrate 120 will be defined as a second substrate.

[0042] The first substrate 110 according to an example can include a display area DA and a non-display area NDA.

[0043] The display area DA is an area in which an image is displayed, and can be a pixel array area, an active area, a pixel array unit, a display unit, or a screen. For example, the display area DA can be disposed at a central portion of the display panel DP.

[0044] The display area DA according to an example can include a gate line, a data line, a pixel driving power line, and a plurality of pixels P (as shown in Figure 2A and Figure 2B Each of the plurality of pixels P can include a plurality of sub-pixels SP that can be defined by the gate line and the data line, and a transmissive portion TR1 disposed adjacent to some or all of the plurality of sub-pixels SP. The transmissive portion TR1 is an area disposed to allow light to pass through the front surface and the rear surface of the display panel. Accordingly, a user located in a front surface direction of the display panel can view an image or a background located in a rear surface direction of the display panel through the transmissive portion TR1.

[0045] Each of the plurality of sub-pixels SP can be defined as a minimum unit area that actually emits light.

[0046] According to an example, at least four sub-pixels disposed adjacent to each other among the plurality of sub-pixels SP and one transmissive portion TR1 constitute one unit pixel P. One transmissive portion TR1 included in the unit pixel can be divided into a plurality of portions. One unit pixel can include, but is not limited to, a red sub-pixel, a green sub-pixel, a blue sub-pixel, a white sub-pixel, and a transmissive portion TR1. As an example, one unit pixel can include at least one red sub-pixel, at least one green sub-pixel, at least one blue sub-pixel, at least one white sub-pixel, and at least one transmissive portion TR1.

[0047] According to another example, three sub-pixels disposed adjacent to each other among the plurality of sub-pixels SP and one transmissive portion TR1 constitute one unit pixel. One unit pixel can include, but is not limited to, at least one red sub-pixel, at least one green sub-pixel, at least one blue sub-pixel, and at least one transmissive portion TR1.

[0048] Each of the plurality of sub-pixels SP includes a thin film transistor and a light emitting portion connected to the thin film transistor. The light emitting portion can include a light emitting element layer (or an organic light emitting layer) interposed between a first electrode and a second electrode.

[0049] The light emitting element layers respectively provided in the plurality of sub-pixels SP can individually emit their respective colors of light different from each other, or collectively emit white light. According to an example, when the light emitting element layers of the plurality of sub-pixels SP collectively emit white light, each of red, green, and blue sub-pixels can include a color filter (or a wavelength conversion member) for converting the white light into its respective different color of light. In this case, a white sub-pixel according to the example can not include the color filter. In the transparent display apparatus 100 according to an embodiment of the disclosure, the white sub-pixel can be the first sub-pixel SP1, the red sub-pixel can be the second sub-pixel SP2, the green sub-pixel can be the third sub-pixel SP3, and the blue sub-pixel can be the fourth sub-pixel SP4.

[0050] When a gate-on signal is input from a gate line by using the thin film transistor, each sub-pixel SP provides a predetermined current to the organic light emitting element according to a data voltage of a data line. To this end, the light emitting portion of each sub-pixel can emit light having a predetermined brightness according to the predetermined current. The structure of each sub-pixel SP will be described later with reference to FIGS. 2A and 2B. Figure 4

[0051] The non-display area NDA can be an area in which an image is not displayed, and can be a peripheral circuit area, a signal supply area, a non-active area, or a bezel area. The non-display area NDA can be configured to surround the display area DA. That is, the non-display area NDA can be disposed to surround the display area DA.

[0052] In the transparent display apparatus 100 according to an embodiment of the disclosure, a pad area PA can be disposed in the non-display area NDA. The pad area PA can provide a power source and / or a signal for outputting an image to the pixels P disposed in the display area DA. Hereinafter, the non-display area NDA in which the pad area PA is disposed will be defined as a pad non-display area PNDA.

[0053] The gate driver GD provides a gate-on signal to the gate line according to a gate control signal input from the timing controller 160. The gate driver GD can be formed at one side of the display area DA of the display panel, or in a manner as illustrated in FIG. 1B. Figure 1 ​The illustrated gate-in-panel (GIP) method is formed over the non-display area NDA outside both sides of the display area DA. Alternatively, the gate driver GD can be manufactured as a driving chip, packaged in a flexible film, and attached to the non-display area NDA outside one side or both sides of the display area DA of the display panel DP by a tape automated bonding (TAB) method. The gate driver GD according to one example can include a plurality of circuits and a plurality of lines. The plurality of circuits can be gate driving circuits (or GIP circuits). The plurality of GIP lines can be a plurality of clock lines CLK, a plurality of ground lines, and a plurality of signal lines SL.

[0054] The plurality of gate drivers GD can be disposed at the left side (i.e., the first non-display area) of the display area DA and the right side (i.e., the second non-display area) of the display area DA. According to one example, the plurality of gate drivers GD can be connected to the plurality of pixels P and a plurality of first signal lines for supplying signals to the plurality of pixels P, respectively. The plurality of first signal lines includes at least one signal line LS for supplying a signal for driving the pixels P. The plurality of first signal lines can extend in a first direction (X-axis direction). The first direction (X-axis direction) can refer to a direction parallel to the scan lines.

[0055] The plurality of second signal lines can extend in a second direction (Y-axis direction). The plurality of second signal lines can cross the plurality of first signal lines. The plurality of signal lines can include a pixel power line VDD for supplying a data voltage to the pixels P and at least one data line. Each of the second signal lines can be connected to at least one of a plurality of pads, a pixel power shorting bar, or a common power shorting bar. The pixel power shorting bar and the common power shorting bar can be disposed in a third non-display area disposed to face the pad area PA based on the display area DA. The second direction (Y-axis direction) can be a direction parallel to the data lines.

[0056] The pixels P can be disposed to overlap at least one of the first signal lines or the second signal lines to emit predetermined light, thereby displaying an image. The light emission area EA can correspond to an area in which light is emitted in the pixels P.

[0057] Each of the pixels P can include at least one of a first sub-pixel SP1, a second sub-pixel SP2, a third sub-pixel SP3, or a fourth sub-pixel SP4. The first sub-pixel SP1 can be provided to include a first emission area EA1 for emitting white light, the second sub-pixel SP2 can be provided to include a second emission area EA2 for emitting red light, the third sub-pixel SP3 can be provided to include a third emission area EA3 for emitting green light, and the fourth sub-pixel SP4 can be provided to include a fourth emission area EA4 for emitting blue light, but they are not limited thereto. Each of the pixels P can include a sub-pixel that emits light of a color other than red, green, blue, and white. In addition, various modifications can be made to the arrangement order of the sub-pixels SP1, SP2, SP3, and SP4.

[0058] Hereinafter, for convenience of description, the first sub-pixel SP1 is a white sub-pixel for emitting white light, the second sub-pixel SP2 is a red sub-pixel for emitting red light, the third sub-pixel SP3 is a green sub-pixel for emitting green light, and the fourth sub-pixel SP4 is a blue sub-pixel for emitting blue light.

[0059] In the transparent display device 100 according to one embodiment of the disclosure, since the organic light emitting element is provided to emit white light, the first sub-pixel SP1, which is a white sub-pixel, can not include a color filter, as shown in Figure 2A and Figure 4 On the other hand, the second sub-pixel SP2 can include a red color filter CF1 to emit red light, the third sub-pixel SP3 can include a green color filter CF2 to emit green light, and the fourth sub-pixel SP4 can include a blue color filter CF3 to emit blue light.

[0060] As shown in Figure 2A , the first sub-pixel SP1 can be provided in a first direction (X-axis direction). The second sub-pixel SP2, the third sub-pixel SP3, and the fourth sub-pixel SP4 can be adjacent to the first sub-pixel SP1 and can be provided in a second direction (Y-axis direction). The second sub-pixel SP2 according to one example can be provided to face the third sub-pixel SP3 and the fourth sub-pixel SP4, and the first signal line LS is interposed therebetween. Each of the plurality of pixels P can include a first transmission part TR1 provided adjacent to the first sub-pixel SP1 and the second sub-pixel SP2, and another first transmission part TR1 provided adjacent to the first sub-pixel SP1 and the third sub-pixel SP3. That is, each of the plurality of pixels P can include four sub-pixels SP1, SP2, SP3, and SP4 and two transmission parts TR1, as shown in Figure 2A The plurality of pixels P can be divided in the first direction (X-axis direction) based on the second signal line VDDL.

[0061] The first sub-pixel SP1 is disposed between the transmissive portions TR1, while being adjacent to the second to fourth sub-pixels SP2 to SP4, such that the first sub-pixel SP1 can overlap at least a portion of the first signal line LS. As described above, since the first sub-pixel SP1 is a white sub-pixel disposed to emit white light, the first sub-pixel SP1 does not include a color filter as the other sub-pixels do. Thus, when external light is reflected toward the first signal line LS, the first sub-pixel SP1 can have greater reflectivity of visibility than the other sub-pixels provided with the color filter. In the transparent display apparatus 100 according to one embodiment of the present disclosure, the non-display area NDA can have the same or similar structure as that of the display area DA to reduce a difference in visibility between the display area DA and the non-display area NDA. For example, the GIP portion GP can include the same or similar number of color filters as the pixels P disposed in the display area DA. This will be described later with reference to FIGS. 6A and 6B. Figure 2A and Figure 5 described in detail.

[0062] Hereinafter, a pixel P of the transparent display apparatus 100 according to one embodiment of the present disclosure will be described with reference to Figure 1 , Figure 2A and Figure 4 .

[0063] Referring to Figure 1 , Figure 2A and Figure 4 , the pixel P disposed in the display area DA can include a plurality of sub-pixels SP and a transmissive portion TR1. As Figure 2A indicated, the transmissive portion TR1 can be disposed adjacent to at least a portion of the plurality of sub-pixels SP. Referring to Figure 4 , each of the plurality of sub-pixels SP can include a buffer layer BL disposed over the first substrate 110 to prevent moisture from penetrating the thin film transistor 112.

[0064] Further, each sub-pixel SP according to one embodiment of the present disclosure can include an inorganic layer 111 (which includes a gate insulating layer 111a, an interlayer insulating layer 111b, and a passivation layer 111c) disposed over an upper surface of the buffer layer BL, a planarization layer 113 disposed over the inorganic layer 111, a first electrode 114 disposed over the planarization layer 113, a bank 115, an organic light emitting layer 116, a second electrode 117, a capping layer 118, and an encapsulation layer 119.

[0065] The thin film transistor 112 for driving the sub-pixel SP can be disposed in the inorganic layer 111. The inorganic layer 111 can be referred to as a term of a circuit element layer. The buffer layer BL can be included in the inorganic layer 111 together with the gate insulating layer 111a, the interlayer insulating layer 111b, and the passivation layer 111c. The first electrode 114, the organic light emitting layer 116, and the second electrode 117 can be included in the light emitting element.

[0066] The buffer layer BL can be formed between the first substrate 110 and the gate insulating layer 111a to protect the thin film transistor 112. The buffer layer BL can be disposed entirely over one surface (or a front surface) of the first substrate 110. The buffer layer BL can be used to prevent materials contained in the first substrate 110 from diffusing into the transistor layer during a high-temperature process of a manufacturing process of the thin film transistor. Alternatively, the buffer layer BL can be omitted as circumstances warrant.

[0067] The thin film transistor 112 according to an example can include an active layer 112a, a gate 112b, a source 112c, and a drain 112d.

[0068] The active layer 112a can include a channel region, a drain region, and a source region formed in a thin film transistor region of a circuit region of the pixel P. The drain region and the source region can be spaced apart from each other, and the channel region is interposed therebetween.

[0069] The active layer 112a can be formed of a semiconductor material based on any one of amorphous silicon, polycrystalline silicon, oxide, and organic material.

[0070] The gate insulating layer 111a can be formed over the channel region of the active layer 112a. As an example, the gate insulating layer 111a can be formed in an island shape only over the channel region of the active layer 112a, or can be formed over the entire front surface of the first substrate 110 including the active layer 112a or the buffer layer BL.

[0071] At least a portion of the gate 112b can be formed over the gate insulating layer 111a to overlap the channel region of the active layer 112a.

[0072] The interlayer insulating layer 111b can be formed over the gate 112b and the drain region and the source region of the active layer 112a. The interlayer insulating layer 111b can be formed in the circuit region and the entire light emitting region that emits light to the pixel P. For example, the interlayer insulating layer 111b can be made of an inorganic material, but is not necessarily limited thereto.

[0073] The source 112c can be electrically connected to the source region of the active layer 112a through a source contact hole disposed in the interlayer insulating layer 111b overlapping at least a portion of the source region of the active layer 112a.

[0074] The drain 112d can be electrically connected to the drain region of the active layer 112a through a drain contact hole provided in an interlayer insulating layer 111b that overlaps with at least a portion of the drain region of the active layer 112a.

[0075] The drain 112d and the source 112c can be made of the same metallic material. For example, each of the drain 112d and the source 112c can be made of a single metal layer, a single layer of alloy, or a multilayer of two or more layers, which may be made of the same or different material as the gate.

[0076] Additionally, the circuit region may also include a first switching thin-film transistor and a second switching thin-film transistor disposed together with the thin-film transistor 112, as well as a capacitor. Since each of the first and second switching thin-film transistors is disposed above the circuit region of pixel P to have the same structure as the thin-film transistor 112, their description will be omitted. The capacitor may be disposed in the overlapping region between the gate 112b and the source 112c of the thin-film transistor 112, with the gate 112b and the source 112c of the thin-film transistor 112 overlapping each other and an interlayer insulating layer 111b placed between them.

[0077] Additionally, to prevent the threshold voltage of the thin-film transistors disposed in the pixel region from shifting due to light, the display panel or the first substrate 110 may further include a light-shielding layer (not shown) disposed below the active layer 112a of at least one of the thin-film transistors 112, the first switching thin-film transistor, or the second switching thin-film transistor. The light-shielding layer may be disposed between the first substrate 110 and the active layer 112a to block light incident on the active layer 112a through the first substrate 110, thereby minimizing the change in the threshold voltage of the transistor due to external light.

[0078] A protective layer 111c may be disposed above the first substrate 110 to cover the pixel area. The protective layer 111c covers the drain 112d and source 112c of the thin-film transistor 112, as well as the interlayer insulating layer 111b. The protective layer 111c may be formed entirely within the circuit area and the light-emitting area. For example, the protective layer 111c may be represented as a passivation layer. The protective layer 111c may be omitted.

[0079] The planarization layer 113 can be formed over the first substrate 110 to cover the protective layer 111c. When the protective layer 111c is omitted, the planarization layer 113 can be disposed over the first substrate 110 to cover the circuit region. The planarization layer 113 can be entirely formed in the circuit region and the light emitting region. Also, the planarization layer 113 can be formed on other regions except for the pad region PA (or the pad portion PA) and the entire display region DA in the non-display region NDA. For example, the planarization layer 113 can include an extension portion (or an enlarged portion) extending or enlarged from the display region DA to other non-display region NDA except for the pad region PA. Accordingly, the planarization layer 113 can have a relatively wider size than that of the display region DA.

[0080] The planarization layer 113 according to an example can be formed to be relatively thick, and thus can provide a flat surface over the display region DA and the non-display region NDA. For example, the planarization layer 113 can be made of an organic material such as photopolymer, benzocyclobutene, polyimide, and fluororesin.

[0081] The first electrode 114 of the sub-pixel SP can be formed over the planarization layer 113. The first electrode 114 is connected to the drain or the source of the thin film transistor 112 through a contact hole passing through the planarization layer 113 and the protective layer 111c.

[0082] The first electrode 114 can be made of at least one of a transparent metal material, a semi-transmissive metal material, or a metal material having high reflectivity.

[0083] When the transparent display apparatus 100 is set to a top emission mode, the first electrode 114 can be formed of a metal material having high reflectivity or a stacked structure of a metal material having high reflectivity and a transparent metal material. For example, the first electrode 114 can be formed of a metal material having high reflectivity such as a stacked structure of aluminum and titanium (Ti / Al / Ti), a stacked structure of aluminum and ITO (ITO / Al / ITO), an Ag alloy, a stacked structure of an Ag alloy and ITO (ITO / Ag alloy / ITO). The Ag alloy can be an alloy such as silver (Ag), palladium (Pd), and copper (Cu).

[0084] When the transparent display apparatus 100 is set to a bottom emission mode, the first electrode 114 can be formed of a transparent conductive material (TCO) such as ITO and IZO, which is transmissive to light, or a semi-transmissive conductive material such as magnesium (Mg), silver (Ag), or an alloy of magnesium (Mg) and silver (Ag).

[0085] Also, the material constituting the first electrode 114 can include MoTi. The first electrode 114 can be an anode electrode or a pixel electrode.

[0086] The bank 115 is a non-light emitting area that does not emit light, and can be provided to surround each light emitting area (or light emitting portion) of the plurality of sub-pixels SP. That is, the bank 115 can separate (or define) the respective light emitting areas (or light emitting portions).

[0087] The bank 115 can be formed above the planarization layer 113 to cover edges of the first electrode 114, thereby separating (or defining) the light emitting areas (or light emitting portions) of the plurality of sub-pixels SP.

[0088] The bank 115 can be formed to cover edges of the first electrode 114 of each sub-pixel SP and expose a portion of each first electrode 114. Accordingly, a current is concentrated at an end portion of each first electrode 114 to avoid a problem of reduced light emission efficiency. The exposed portion of the first electrode 114 that is not covered by the bank 115 can be a light emitting area (or light emitting portion).

[0089] The bank 115 can be formed of an organic layer such as an acrylic resin, an epoxy resin, a phenol resin, a polyamide resin, and a polyimide resin, but is not limited thereto.

[0090] The organic light emitting layer 116 is formed above the first electrode 114 and the bank 115. When a voltage is applied to the first electrode 114 and the second electrode 117, holes and electrons move to the organic light emitting layer 116, respectively, and recombine with each other in the organic light emitting layer 116 to emit light.

[0091] The organic light emitting layer 116 can be formed of the plurality of sub-pixels SP and a common layer provided above the bank 115. In this case, the organic light emitting layer 116 can be provided in a cascade structure in which a plurality of light emitting layers (for example, a yellow-green light emitting layer and a blue light emitting layer) are stacked, and can emit white light when an electric field is formed between the first electrode 114 and the second electrode 117.

[0092] Color filters suitable for colors of the corresponding sub-pixels SP can be formed above the second substrate 120. For example, a red color filter CF1 can be provided in a red sub-pixel, a green color filter CF2 can be provided in a green sub-pixel, and a blue color filter CF3 can be provided in a blue sub-pixel. A white sub-pixel can not include a color filter because the organic light emitting layer 116 emits white light.

[0093] The second electrode 117 is formed above the organic light emitting layer 116. The second electrode 117 can be a common layer commonly formed in the sub-pixels SP. The second electrode 117 can be made of a transparent metal material, a semi-transmissive metal material, or a metal material having high reflectivity.

[0094] When the transparent display apparatus 100 is set to the top emission mode, the second electrode 117 can be formed of a transparent conductive material (TCO) such as ITO and IZO, which can transmit light, or a semi-transmissive conductive material such as magnesium (Mg), silver (Ag), or an alloy of magnesium (Mg) and silver (Ag).

[0095] When the transparent display apparatus 100 is set to the bottom emission mode, the second electrode 117 can be formed of a metal material having high reflectivity such as a stacked structure of aluminum and titanium (Ti / Al / Ti), a stacked structure of aluminum and ITO (ITO / Al / ITO), an Ag alloy, and a stacked structure of an Ag alloy and ITO (ITO / Ag alloy / ITO). The Ag alloy can be an alloy of silver (Ag), palladium (Pd), copper (Cu), or the like. The second electrode 117 can be a counter electrode or a cathode electrode.

[0096] A capping layer 118 can be formed on the second electrode 117, but can be omitted. When the capping layer 118 is formed, the capping layer 118 can be formed entirely in the display area DA. Also, the capping layer 118 can be disposed up to the non-display area NDA, as shown. Figure 6

[0097] An encapsulation layer 119 is formed above the capping layer 118. The encapsulation layer 119 serves to prevent oxygen or water from permeating into the organic light emitting layer 116 and the second electrode 117. To this end, the encapsulation layer 119 can include at least one inorganic layer.

[0098] In the transparent display apparatus 100 according to one embodiment of the disclosure, the encapsulation layer 119 can be disposed in the non-display area NDA as well as the display area DA. The encapsulation layer 119 according to one example can be disposed between the capping layer 118 and the second substrate 120.

[0099] Since the encapsulation layer 119 is disposed in the display area DA and extends to reach the non-display area NDA, the encapsulation layer 119 can come into contact with a dam portion (not shown) at the outside of the display panel. Accordingly, the transparent display apparatus 100 according to one embodiment of the disclosure can effectively prevent moisture from permeating into the display area DA.

[0100] Referring back to Figure 4 , a color filter and a black matrix BM can be disposed between the encapsulation layer 119 and the second substrate 120. As described above, the white sub-pixel (i.e., the first sub-pixel SP1) can not include a color filter, since the organic light emitting layer 116 emits white light. On the other hand, in the second sub-pixel SP2, which is a red sub-pixel, a first color filter CF1 can be disposed between the encapsulation layer 119 and the second substrate 120.

[0101] As Figure 4 ​As shown, a black background BM can be disposed between the first sub-pixel SP1 and the second sub-pixel SP2 to prevent color mixing between sub-pixels. The black background BM can be made of a black base material and can be disposed in the non-light-emitting area NEA. According to one example, the black background BM is formed above the second substrate 120 such that at least a portion of it overlaps with the embankment 115, thereby reducing the cell gap between the organic light-emitting layer 116 and the second substrate 120 to prevent color mixing between sub-pixels.

[0102] like Figure 2A As shown, the first sub-pixel SP1 can overlap with at least a portion of the first signal line LS. Figure 4 As shown, the first signal line LS can be disposed in the first sub-pixel SP1 between the buffer layer BL and the first substrate 110. Therefore, at least a portion of the first signal line LS in the first sub-pixel SP1 can overlap with each of the gate 112b, source 112c, and drain 112d of the thin-film transistor 112. That is, the first signal line LS, the gate 112b, and the source 112c and drain 112d can partially overlap each other below the planarization layer 113 of the first sub-pixel SP1. The first signal line LS, the gate 112b, and the source 112c and drain 112d disposed in the first sub-pixel SP1 are disposed in the display area DA, and therefore can be referred to as the pixel metal layer.

[0103] Reference Figure 1 and Figure 2A According to one embodiment of the present disclosure, a transparent display device 100 may include a line portion LNP having multiple lines LN connected to a pad region PA, and a circuit portion GIP having multiple circuits GTR connected to the multiple lines LN in a non-display area NDA. The line portion LNP and the circuit portion GIP may be disposed in the non-display area NDA, more specifically, in a gate driver GD. In the transparent display device 100 according to one embodiment of the present disclosure, since the line portion LNP and the circuit portion GIP are disposed separately from each other in the gate driver GD, the difference in reflectivity of the lines and circuits to external light can be reduced. That is, in the transparent display device 100 according to one embodiment of the present disclosure, the multiple lines LN are disposed concentrated on one side of the circuit portion GIP, and the multiple circuits GTR are disposed concentrated on one side of the line portion LNP, so that compared to the case where the multiple lines and multiple circuits are disposed sequentially (alternatingly), the difference in reflectivity of external light can be reduced.

[0104] For more details, see [link to relevant documentation]. Figure 1 , Figure 2A and Figure 2BAccording to one example, the line portion LNP can be disposed between the end of the first substrate 110 and the circuit portion GIP. According to one example, the circuit portion GIP can be disposed between the line portion LNP and the display area DA. For example... Figure 2A and Figure 2B As shown, the multiple lines LN in the online section LNP can include multiple clock lines CLK, multiple ground lines, and multiple signal lines SL. For ease of description, Figure 2A Only multiple clock lines CLK and the first ground line GVSS0 are shown, while Figure 2B Only multiple signal lines SL, a second ground line GVSS1, and a third ground line GVSS2 are shown. Therefore, in a transparent display device 100 according to one embodiment of this disclosure, the line portion LNP may include... Figure 2A The multiple clock lines CLK and the first ground line GVSS0 shown are as follows: Figure 2B The diagram shows the complete structure of the multiple signal lines SL, the second ground line GVSS1, and the third ground line GVSS2.

[0105] According to an example, a circuit section GIP includes a common control section CUP and a buffer section BP. Multiple circuits GTRs disposed within the circuit section GIP may include multiple common transistors CTR disposed in the common control section CUP and multiple sub-buffers SBP disposed in the buffer section BP. In this case, the multiple sub-buffers SBP may refer to the buffers TR disposed in the buffer section BP.

[0106] Multiple clock lines CLK can be connected to pad area PA to receive image signals for driving pixels P in display area DA. Each of the multiple clock lines CLK can be directly connected via a first connection line CL1 to each of the multiple sub-buffers SBP disposed in buffer section BP to transmit the received image signal to each of the multiple sub-buffers.

[0107] Each of the multiple sub-buffers SBP can generate an image output signal for driving pixel P based on image signals received from multiple clock lines CLK. Each of the multiple sub-buffers SBP can apply the generated image output signal to multiple pixels P through multiple signal lines LS connected to the display area DA. However, each of the multiple sub-buffers SBP can ultimately receive the generation signal (or timing signal) of the common transistor CTR located in the common control section CUP, and apply the image output signal to multiple pixels P.

[0108] A portion of multiple ground lines (e.g., the first ground line GVSS0) can be connected to all of the multiple sub-buffers via the first connection line CL1. One side of the first ground line GVSS0 can be connected to the pad area PA, and can be connected to each of the multiple sub-buffers SBP via the first connection line CL1. The first ground line GVSS0 can receive an image output stop signal from the pad area PA to prevent the multiple sub-buffers from generating an image output signal, and can transmit the image output stop signal to each of the multiple sub-buffers SBP. As a result, the multiple sub-buffers SBP can receive image signals through multiple clock lines CLK and the first ground line GVSS0 to generate an image output signal for driving pixel P or to stop the image output signal.

[0109] like Figure 2A As shown, according to one example, multiple sub-buffers SBP may include a first sub-buffer SBP1, a second sub-buffer SBP2, a third sub-buffer SBP3, a fourth sub-buffer SBP4, a fifth sub-buffer SBP5, a sixth sub-buffer SBP6, a seventh sub-buffer SBP7, and an eighth sub-buffer SBP8. These sub-buffers SBP1, SBP2, SBP3, SBP4, SBP5, SBP6, SBP7, and SBP8 can be configured to be spaced apart from each other along a second direction (Y-axis direction) between the common control section CUP and the display area DA. According to one example, multiple clock lines CLK may include a first clock line CLK1, a second clock line CLK2, a third clock line CLK3, a fourth clock line CLK4, a fifth clock line CLK5, a sixth clock line CLK6, a seventh clock line CLK7, and an eighth clock line CLK8. The first clock line CLK1, the second clock line CLK2, the third clock line CLK3, the fourth clock line CLK4, the fifth clock line CLK5, the sixth clock line CLK6, the seventh clock line CLK7, and the eighth clock line CLK8 can be spaced apart from each other in the first direction (X-axis direction) and extend in the second direction (Y-axis direction). Figure 2A In the diagram, each of the multiple sub-buffer SBPs is shown as a quadrilateral, but each sub-buffer SBP can have a structure including multiple buffer transistors TR and GIP transmission sections. For example, as... Figure 5 As shown, each sub-buffer SBP can be configured to cover multiple buffer TRs with different color filters without overlapping with the GIP transmission section.

[0110] The first clock line CLK1 can be directly connected to the first sub-buffer SBP1 provided in the buffer portion BP through the first connection line CL1. The second clock line CLK2 can be directly connected to the second sub-buffer SBP2 provided in the buffer portion BP through the first connection line CL1. The third clock line CLK3 can be directly connected to the third sub-buffer SBP3 provided in the buffer portion BP through the first connection line CL1. The fourth clock line CLK4 can be directly connected to the fourth sub-buffer SBP4 provided in the buffer portion BP through the first connection line CL1. The fifth clock line CLK5 can be directly connected to the fifth sub-buffer SBP5 provided in the buffer portion BP through the first connection line CL1. The sixth clock line CLK6 can be directly connected to the sixth sub-buffer SBP6 provided in the buffer portion BP through the first connection line CL1. The seventh clock line CLK7 can be directly connected to the seventh sub-buffer SBP7 provided in the buffer portion BP through the first connection line CL1. The eighth clock line CLK8 can be directly connected to the eighth sub-buffer SBP8 provided in the buffer portion BP through the first connection line CL1.

[0111] As shown in Figure 2A , the plurality of clock lines CLK and the first ground line GVSS0 can be directly connected to each of the plurality of sub-buffers through the first connection line CL1. Accordingly, the first connection line CL1 can be provided to cross the common control portion CUP provided between the line portion LNP and the buffer portion BP without being connected to the common control portion CUP.

[0112] Referring to Figure 2A , the plurality of clock lines CLK and the first ground line GVSS0 can be provided to be concentrated on one side of the common control portion CUP (or the plurality of signal lines SL) and thereby spaced apart from each other in the pad non-display area PNDA. That is, in the pad non-display area PNDA, the plurality of clock lines CLK and the first ground line GVSS0 can be provided at regular intervals without being overlapped or twisted with each other. Accordingly, since the plurality of clock lines CLK and the first ground line GVSS0 are not twisted at the upper portion of the gate driver GD (more specifically, in the pad non-display area PNDA), a parasitic capacitance generated between the lines when the lines are twisted can be reduced or can not be generated.

[0113] Referring to Figure 2BMultiple signal lines SL can be connected to pad areas PA to receive pixel power supplies and control signals such as timing control signals applied from the pad areas PA. Each of the multiple signal lines SL can be connected via a second connection line CL2 to each of the multiple common transistors CTR located in the common control section CUP to transmit the received timing control signals to the multiple common transistors CTR. The multiple common transistors CTR can be connected via a buffer line BLN to multiple sub-buffers SBP of the buffer section BP. The multiple common transistors CTR can select the sub-buffer from the multiple sub-buffers SBP to generate the image output signal based on the timing control signals received from the multiple signal lines SL, and apply a generation signal for generating the image output signal to the selected sub-buffer. Therefore, the multiple sub-buffers can receive the generation signal from the common control section CUP to generate the image output signal based on the image signal applied from the clock line CLK, and apply the output signal to multiple pixels P.

[0114] like Figure 2B As shown, multiple signal lines LN can be connected to the first ground line GVSS0 (e.g., Figure 2A The part shown (PA) and the common control section CUP extend further in the second direction (Y-axis direction) and can be arranged parallel to each other while being spaced apart in the first direction (X-axis direction). Multiple signal lines LN may include a pixel power line VDD, a signal start line Vst, a reset line Reset, a second ground line GVSS1, and a third ground line GVSS2. The pixel power line VDD is connected to the pad area PA to apply pixel power to the common transistor CTR for driving pixel P. The signal start line Vst is connected to the pad area PA to apply a start signal to the common transistor CTR to allow pixel P to output an image. The reset line Reset is connected to the pad area PA to apply a reset signal to the common transistor CTR to reset the image output by pixel P. The second ground line GVSS1 and the third ground line GVSS2 are connected to the pad area PA to apply an image output stop signal to the common transistor CTR. Signals applied to the common control section CUP via each of the pixel power line VDD, signal start line Vst, reset line Reset, second ground line GVSS1, and third ground line GVSS2 can be transmitted to any one of the multiple common transistors CTR. A common transistor CTR can generate a control signal based on the received signal. The generated control signal can be applied to any one of the multiple sub-buffers SBP via the buffer line BLN. The sub-buffer that has received the control signal can generate an image output signal, and the generated image output signal can be transmitted to the pixel P located in the display area DA via the signal line LS.

[0115] In addition, refer toFigure 2B The plurality of signal lines SL (i.e., the pixel power line VDD, the signal start line Vst, the reset line Reset, the second ground line GVSS1, and the third ground line GVSS2) can be spaced apart from each other between the clock line CLK (or the first ground line GVSS0) and the common control portion CUP. The plurality of signal lines SL (i.e., the pixel power line VDD, the signal start line Vst, the reset line Reset, the second ground line GVSS1, and the third ground line GVSS2) can be disposed to be spaced apart from each other in the pad non-display area PNDA. Accordingly, in the pad non-display area PNDA, the pixel power line VDD, the signal start line Vst, the reset line Reset, the second ground line GVSS1, and the third ground line GVSS2 can be disposed to be regularly spaced apart from each other without being twisted or intertwined. Accordingly, at the upper portion of the gate driver GD (more specifically, in the pad non-display area PNDA), the pixel power line VDD, the signal start line Vst, the reset line Reset, the second ground line GVSS1, and the third ground line GVSS2 are not twisted, so that a parasitic capacitance generated between the lines when the lines are twisted can be reduced, or the parasitic capacitance can not be generated.

[0116] As a result, in the transparent display device 100 according to one embodiment of the disclosure, the plurality of lines LN can be disposed to be concentrated on one side of the circuit portion GIP, and the plurality of circuits GTR can be disposed to be concentrated on the other side of the line portion LNP, so that the lines in the pad non-display area PNDA can be prevented from being twisted or overlapped with each other, thereby the parasitic capacitance between the lines can be reduced or can not be generated.

[0117] Referring back to Figure 2BThe common control section CUP may include multiple common lines CUL. These multiple common lines CUL can connect multiple common transistors CTR in the common control section CUP to each other. Therefore, the multiple common transistors CTR can share power and / or timing control signals applied from multiple signal lines SL. This can be represented as each signal line in the multiple signal lines SL sharing multiple common transistors CTR. In a transparent display device 100 according to one embodiment of the present disclosure, since the multiple signal lines SL are configured to share multiple common transistors CTR, the number of second connection lines CL2 connecting each of the multiple signal lines SL to the multiple common transistors CTR can be reduced. Therefore, compared to the case where multiple lines and multiple circuits are alternately arranged, in a transparent display device 100 according to one embodiment of the present disclosure, the number of first connection lines CL1 and second connection lines CL2 crossing the common control section CUP can be reduced, i.e., the number of first connection lines CL1 and second connection lines CL2 passing through the GIP transmissive portions TR2 disposed in the non-display area NDA. Therefore, in a transparent display device 100 according to one embodiment of the present disclosure, since the first connecting line CL1 and the second connecting line CL2 do not cover the GIP transmissive portion TR2 compared to the case where multiple lines and multiple circuits are alternately arranged, the transmittance in the non-display area NDA can be improved.

[0118] The buffer section BP can be connected to the common control section CUP via buffer lines BLN. Buffer lines BLN can include a main buffer line BLN1 and multiple branch buffer lines BLN2. The main buffer line BLN1 can be connected to at least one of the multiple circuits (i.e., multiple common transistors CTR) included in the common control section CUP. The multiple branch buffer lines BLN2 can be connected to the main buffer line BLN1 and each of the multiple sub-buffers (i.e., first sub-buffer SBP1 to eighth sub-buffer SBP8). The multiple branch buffer lines BLN2 can be lines connecting the multiple sub-buffers SBP in the buffer section BP to each other. Therefore, as... Figure 2B As shown, only one main buffer line BLN1 can be set between the common control section CUP and the buffer section BP, and multiple branch buffer lines BLN2 can be set in the buffer section BP. Since the multiple sub-buffers SBP are connected to each other in the buffer section BP through multiple branch buffer lines BLN2, the signal of the common control section CUP applied through the main buffer line BLN1 can be applied to any of the multiple sub-buffers SBP.

[0119] As a result, in the transparent display device 100 according to one embodiment of the present disclosure, the plurality of common transistors CTR can be connected to each other in the common control portion CUP, and the plurality of sub-buffers SBP can be connected to each other in the buffer portion BP, so that a signal applied from each of the plurality of signal lines SL can be applied to any one of the plurality of common transistors CTR connected to each other, and a control signal generated by any one of the common transistors CTR can be applied to any one of the plurality of sub-buffers SBP connected to each other to generate an output signal. Accordingly, in the transparent display device 100 according to one embodiment of the present disclosure, the plurality of common transistors CTR provided in the common control portion CUP can be shared, and thus the number of the second connection lines CL2 connecting the line portion LNP to the common control portion CUP can be reduced. Further, in the transparent display device 100 according to one embodiment of the present disclosure, the plurality of sub-buffers SBP provided inside the buffer portion BP can be shared, and thus the number of the main buffer lines BLN1 connecting the common control portion CUP to the buffer portion BP can be reduced.

[0120] Accordingly, in the transparent display device 100 according to one embodiment of the present disclosure, since the number of each of the first connection lines CL1, the second connection lines CL2, and the buffer lines BLN can be minimized, the minimum number of the first connection lines CL1, the second connection lines CL2, and the buffer lines BLN can be provided between the GIP transmission portions TR2 provided in the non-display area NDA. Accordingly, in the transparent display device 100 according to one embodiment of the present disclosure, the plurality of lines LN can be provided to be concentrated on one side of the circuit portion GIP, and the plurality of circuits GTR can be provided to be concentrated on the other side of the line portion LNP. That is, the plurality of lines LN and the plurality of circuits GTR can be provided to be separated from each other.

[0121] As described above, since the plurality of lines LN and the plurality of circuits GTR are provided to be separated from each other, the lines in the pad non-display area PNDA can be prevented from being twisted or overlapped with each other, so that a parasitic capacitance can be reduced or can not be generated. Further, in the transparent display device 100 according to one embodiment of the present disclosure, since the plurality of lines LN and the plurality of circuits GTR are provided to be separated from each other, a reflection visibility difference caused by external light can be improved compared to a case in which the plurality of lines and the plurality of circuits are provided in sequence (i.e., alternately).

[0122] Referring to Figure 3A and Figure 3B , Figure 3A The comparative example in which the plurality of lines and the plurality of circuits are alternately arranged is illustrated, and is a graph (or a photograph) illustrating a reflection visibility caused by external light. Figure 3Bis a diagram (or a photograph) illustrating reflection visibility caused by external light when a line portion LNP including a plurality of lines LN and a circuit portion GIP including a plurality of circuits GTR are separated from each other in the transparent display device 100 according to one embodiment of the present disclosure. In Figure 3A , a black stripe is a line L and a bright stripe is a circuit G. As shown in Figure 3A , since a plurality of lines L and a plurality of circuits G are alternately arranged in the gate driver GD, the black and bright stripes alternately arranged due to the external light can be more noticeable to a user than the display area DA.

[0123] In contrast, in the transparent display device 100 according to one embodiment of the present disclosure, as shown in Figure 3B , the line portion LNP having a plurality of lines and the circuit portion GIP having the common control portion CUP and the buffer portion BP can be separated from each other such that the line portion LNP can be seen by a user in the form of a bright area with respect to external light and the circuit portion GIP can be seen by a user in the form of a slightly darker area than the line portion LNP. Thus, since the transparent display device 100 according to one embodiment of the present disclosure can be seen by a user in the form of a gradual change in luminance gradually decreasing from the line portion LNP to the display area DA as shown in Figure 3B , the line and the circuit can not be clearly seen by a user compared to the comparative example of Figure 3A . Thus, in the transparent display device 100 according to one embodiment of the present disclosure, the difference in reflection visibility between the line portion LNP and the circuit portion GIP due to external light can be reduced in the non-display area NDA compared to the comparative example of Figure 3A , and in addition, the difference in reflection visibility between the circuit portion GIP of the non-display area NDA and the display area DA can be reduced as shown in Figure 3B .

[0124] In the transparent display device 100 according to one embodiment of the present disclosure, a plurality of signal lines SL arranged in the line portion LNP are arranged to share a plurality of circuits, i.e., a plurality of common transistors CTR, arranged in the common control portion CUP such that the number of the plurality of circuits arranged in the common control portion CUP can be reduced. Thus, as shown in Figure 2B , since a space margin can occur in the common control portion CUP, the degree of freedom in arrangement of the common transistors CTR arranged in the common control portion CUP can be improved. Since the arrangement of the common transistors CTR can be freely implemented in the common control portion CUP, the width of the common control portion CUP can be designed to be minimized and thus a narrow bezel can be implemented.

[0125] Figure 5 is a diagram illustrating Figure 2Ba diagram of an example of part B of FIG. 1, while Figure 6 is a schematic cross-sectional view taken along Figure 5 line II-II' shown in FIG. 1.

[0126] Referring to Figures 4-6 , in the transparent display apparatus 100 according to the embodiment of the disclosure, since the common transistor CTR disposed in the common control portion CUP can be freely disposed as described above, the common transistor CTR disposed in the common control portion CUP can be disposed similarly to the structure of the pixel P of the display area DA. In Figure 2B , the arrangement of the common transistor CTR freely disposed in the common control portion CUP is described as an example, while Figure 5 another example in which the common transistor CTR and the GIP transmission portion TR2 disposed in the common control portion CUP are disposed similarly to the structure of the pixel P of Figure 1 is illustrated.

[0127] As shown in Figure 5 , the common transistor CTR and the GIP transmission portion TR2 disposed in the common control portion CUP are disposed similarly to the structure of the pixel P of Figure 1 , so that the difference in visibility between the display area DA and the non-display area NDA for a user can be reduced.

[0128] More specifically, the common control portion CUP can include a GIP portion GP similar to the structure of the pixel P of the display area DA. The GIP portion GP according to one example can include a first block portion BLK1, a second block portion BLK2, and a GIP transmission portion TR2. The first block portion BLK1 and the second block portion BLK2 can be disposed in a non-transmission portion NTA of the non-display area NDA. The non-transmission portion NTA can be a region in the non-display area NDA that does not overlap the GIP transmission portion TR2.

[0129] As shown in Figure 2A and Figure 2B , the GIP transmission portion TR2 can be disposed between a plurality of lines LN and / or a plurality of circuits GTR. That is, a plurality of GIP transmission portions TR2 can be disposed in the non-display area NDA. Since a plurality of GIP transmission portions TR2 are disposed in the non-display area NDA, a visual difference with the display area DA can be reduced, and the overall transmittance of the transparent display apparatus can be improved.

[0130] The first block portion BLK1 can refer to a region in the non-display area NDA (or the common control portion CUP) that does not include a color filter and does not overlap the GIP transmission portion TR2. That is, the first block portion BLK1 can refer to a region in which no color filter is disposed in the non-transmission portion NTA. The first block portion BLK1 according to one example can be disposed at a position corresponding to the first sub-pixel SP1 in the non-transmission portion NTA. The first block portion BLK1 can be referred to as a white block portion. The second block portion BLK2 can refer to a region in the non-display area NDA (or the common control portion CUP) that is disposed adjacent to the first block portion BLK1 and is disposed with a color filter. The second block portion BLK2 can be disposed in the non-transmission portion NTA that does not overlap the GIP transmission portion TR2 to improve transmittance. The second block portion BLK2 can include a red block portion BLK2-1, a green block portion BLK2-2, and a blue block portion BLK2-3. The red block portion BLK2-1 can refer to a region in the common control portion CUP that is disposed with a first color filter CF1. The first color filter CF1 can be a red color filter and can overlap a portion of the first common transistor CTR1. The red block portion BLK2-1 can be disposed at a position corresponding to the second sub-pixel SP2. The green block portion BLK2-2 can refer to a region in the common control portion CUP that is disposed with a second color filter CF2. The second color filter CF2 can be a green color filter and can overlap a portion of the first common transistor CTR1 that does not overlap the first color filter CF1. The green block portion BLK2-2 can be disposed at a position corresponding to the third sub-pixel SP3. The blue block portion BLK2-3 can refer to a region in the common control portion CUP that is disposed with a third color filter CF3. The third color filter CF3 can be a blue color filter and can overlap a portion of the first common transistor CTR1 that does not overlap the first color filter CF1 and the second color filter CF2. The blue block portion BLK2-3 can be disposed at a position corresponding to the fourth sub-pixel SP4. The GIP transmission portion TR2 of the non-display area NDA can be disposed at a position corresponding to the transmission portion TR1 of the display area DA. Accordingly, the GIP transmission portion TR2 can be disposed adjacent to each of the first block portion BLK1 and the red block portion BLK2-1 and each of the first block portion BLK1 and the green block portion BLK2-2.

[0131] If the first block portion BLK1, the second block portion BLK2, and the GIP transmission portion TR2 included in the GIP portion GP have the same or similar visibility as each of the first to fourth sub-pixels SP1 to SP4 and the transmission portion TR1 of the pixel P, they can not necessarily correspond to the first to fourth sub-pixels SP1 to SP4 and the transmission portion TR1.

[0132] The red block portion BLK2-1, the green block portion BLK2-2, and the blue block portion BLK2-3 of the other GIP portion can be disposed at adjacent positions based on the first block portion BLK1. That is, as shown in Figure 5 The first block portion BLK1 can be disposed between a plurality of common transistors CTR. For example, the first block portion BLK1 can be disposed between a first common transistor CTR1 and a second common transistor CTR2. A red color filter CF1 can be disposed in the red block portion BLK2-1 of the other GIP portion to overlap a portion of the second common transistor CTR2. A green color filter CF2 can be disposed in the green block portion BLK2-2 of the other GIP portion to overlap a portion of the second common transistor CTR2 that does not overlap the red color filter CF1. A blue color filter CF3 can be disposed in the blue block portion BLK2-3 of the other GIP portion to overlap a portion of the second common transistor CTR2 that does not overlap the red color filter CF1 and the green color filter CF2.

[0133] For convenience of description, only the plurality of GIP transmission portions TR2 (or GIP portions) disposed in the plurality of GIP portions in the non-display area NDA (or the gate driver GD) are illustrated in Figure 2A and Figure 2B The plurality of GIP portions GP including the plurality of GIP transmission portions TR2 can be substantially disposed in the non-display area NDA (or the gate driver GD) of the transparent display apparatus 100 according to an embodiment of the present disclosure. However, since Figure 5 The GIP portions GP are illustrated as being disposed in the common control portion CUP, and thus color filters of different colors can cover the common transistors CTR. In contrast, color filters of different colors can be disposed to cover the plurality of lines LN in the line portion LNP.

[0134] As shown in Figure 5 The GIP portions GP of the common control portion CUP can be disposed to be the same as or similar to the pixels P of the display area DA. Accordingly, in the transparent display apparatus 100 according to an embodiment of the present disclosure, a visibility difference between the display area DA and the non-display area NDA can be reduced.

[0135] The first block portion BLK1 disposed in the common control portion CUP can not include a color filter. This is because the first sub-pixel SP1 disposed in the display area DA is disposed to emit white light, and thus a color filter is not disposed. Since the first block portion BLK1 does not have a color filter disposed therein, a reflection visibility can be greatly generated when external light is emitted. Accordingly, the transparent display apparatus 100 according to an embodiment of the present disclosure can have a structure in which the first block portion BLK1 is disposed to be the same as or similar to the first sub-pixel SP1, thereby reducing a reflection visibility difference with respect to external light.

[0136] The first block portion BLK1 according to one example can include at least three metal layers, such as the first sub-pixel SP1, which overlap each other. The at least three metal layers provided in the first block portion BLK1 are provided in the non-display area NDA, and thus can be referred to as a term of non-pixel metal layers.

[0137] Referring to Figure 5 , the first block portion BLK1 can be provided between the second block portions BLK2. In more detail, the first block portion BLK1 can be provided to be longer in a first direction (X-axis direction), and can be provided between adjacent second block portions BLK2. In this case, the second block portion BLK2 can refer to the second block portion BLK2 of two adjacent GIP portions GP. The second block portion BLK2 can be provided to be longer in a second direction (Y-axis direction) crossing the first direction (X-axis direction). Accordingly, the first block portion BLK1 can be provided in a bridging form between the second block portions BLK2. As a result, the first block portion BLK1 and the second block portion BLK2 of the non-display area NDA can be provided to be the same as or similar to each of the first sub-pixel SP1, and the second sub-pixel SP2 to the fourth sub-pixel SP4 of the display area DA, whereby a visibility difference with the display area DA can be reduced.

[0138] Referring to Figure 5 and Figure 6 , the first block portion BLK1 can include a dummy pattern DMP provided to be the same as or similar to the first sub-pixel SP1. The dummy pattern DMP according to one example can be provided between a plurality of circuits (i.e., common transistor CTR). The dummy pattern DMP can be provided by stacking a plurality of metal layers (or non-pixel metal layers). Since the first block portion BLK1 does not provide a color filter, the first block portion BLK1 is provided to be the same as or similar to a structure of a pixel metal layer provided in the first sub-pixel SP1 to reduce a reflection visibility difference due to external light. For example, the first block portion BLK1 can be provided to have a step difference the same as a step difference of the pixel metal layer provided in the first sub-pixel SP1, thereby reducing the reflection visibility difference due to external light.

[0139] The dummy pattern DMP according to one example can include a first metal layer DMP1 provided above the substrate 110, a second metal layer DMP2 provided above the first metal layer DMP1, and a third metal layer DMP3 provided above the second metal layer DMP2. In this case, the first metal layer DMP1 can be provided such that at least a portion thereof overlaps the second metal layer DMP2 and the third metal layer DMP3. Accordingly, as Figure 6As shown, at least a portion of each dummy pattern DMP can be disposed to overlap three metal layers (i.e., the first metal layer DMP1 to the third metal layer DMP3) under the planarization layer 113, and thus can be disposed to overlap each other with at least a portion of each of the signal line LS, the gate 112b, and the source 112c (or the drain 112d) (as shown in FIG. 1B). Figure 4 The first metal layer DMP1 can be disposed on the same layer as the signal line LS disposed above the substrate 110. The signal line LS can refer to a signal line disposed above the first substrate 110 and disposed in the same layer as a common voltage line (not shown) for supplying a common voltage to the pixel P. When the common voltage line is formed in the display area DA, the first metal layer DMP1 can be formed in the non-display area NDA by the same material as that of the non-display area NDA (or the common control portion CPU). Thus, the first metal layer DMP1 disposed in the common control portion CPU can be disposed on the same layer as the common voltage line of the display area DA. For example, the first metal layer DMP1 can be disposed between the first substrate 110 and the buffer layer BL.

[0140] The second metal layer DMP2 can be disposed on the same layer as the gate 112b of the plurality of sub-pixels SP (more specifically, the first sub-pixel SP1). When the gate 112b is formed in the display area DA, the second metal layer DMP2 can be formed in the common control portion CPU by the same material as that of the common control portion CPU. Thus, the second metal layer DMP2 disposed in the common control portion CPU can be disposed on the same layer as the gate 112b of the display area DA. For example, the second metal layer DMP2 can be disposed between the interlayer insulating layer 111b and the buffer layer BL, but is not limited thereto. When at least a portion of the second metal layer DMP2 can overlap the first metal layer DMP1 and the third metal layer DMP3, the second metal layer DMP2 can be disposed between the interlayer insulating layer 111b and the gate insulating layer 111a.

[0140]

[0140] Referring to Figure 4 and Figure 6 , the first metal layer DMP1 can be disposed on the same layer as the signal line LS disposed above the substrate 110. The signal line LS can refer to a signal line disposed above the first substrate 110 and disposed in the same layer as a common voltage line (not shown) for supplying a common voltage to the pixel P. When the common voltage line is formed in the display area DA, the first metal layer DMP1 can be formed in the non-display area NDA by the same material as that of the non-display area NDA (or the common control portion CPU). Thus, the first metal layer DMP1 disposed in the common control portion CPU can be disposed on the same layer as the common voltage line of the display area DA. For example, the first metal layer DMP1 can be disposed between the first substrate 110 and the buffer layer BL.

[0141] The second metal layer DMP2 can be disposed on the same layer as the gate 112b of the plurality of sub-pixels SP (more specifically, the first sub-pixel SP1). When the gate 112b is formed in the display area DA, the second metal layer DMP2 can be formed in the common control portion CPU by the same material as that of the common control portion CPU. Thus, the second metal layer DMP2 disposed in the common control portion CPU can be disposed on the same layer as the gate 112b of the display area DA. For example, the second metal layer DMP2 can be disposed between the interlayer insulating layer 111b and the buffer layer BL, but is not limited thereto. When at least a portion of the second metal layer DMP2 can overlap the first metal layer DMP1 and the third metal layer DMP3, the second metal layer DMP2 can be disposed between the interlayer insulating layer 111b and the gate insulating layer 111a.

[0142] The third metal layer DMP3 can be provided on the same layer as the source electrode 112c provided on the gate electrode 112b in the first sub-pixel SP1. The third metal layer DMP3 can be formed of the same material as that of the common control portion CPU when the source electrode 112c is formed in the display area DA. Thus, the third metal layer DMP3 provided in the common control portion CPU can be formed on the same layer as the source electrode 112c of the display area DA. For example, the third metal layer DMP3 can be provided between the passivation layer 111c and the interlayer insulating layer 111b. The third metal layer DMP3 provided in the common control portion CPU can be provided on the same layer as the drain electrode 112d of the display area DA.

[0143] Thus, in the transparent display device 100 according to one embodiment of the present disclosure, the at least three non-pixel metal layers provided on the same layer as the at least three pixel metal layers of the first sub-pixel SP1 are provided to overlap with each other in the first block portion BLK1, so that the difference in reflection visibility due to external light between the first sub-pixel SP1 and the first block portion BLK1 can be reduced. The red block portion BLK2-1, the green block portion BLK2-2, and the blue block portion BLK2-3 can be provided to be the same as or similar to the second to fourth sub-pixels SP2 to SP4, respectively, and specifically, include the color filters having the same color as the color filters of the second to fourth sub-pixels SP2 to SP4, respectively, so that the difference in reflection visibility due to external light can be reduced.

[0144] Although Figure 6 The first metal layer DMP1, the second metal layer DMP2, and the third metal layer DMP3 are shown to have the same width in a flat shape, but the first metal layer DMP1, the second metal layer DMP2, and the third metal layer DMP3 can have the same structure as that of the signal line LS, the gate electrode 112b, and the source electrode 112c (or the drain electrode 112d) of the first sub-pixel SP1. Figure 4

[0145] The first block portion BLK1 can further include the planarization layer 113, the dummy electrode DE, the dummy bank DB, the cap layer 118, and the encapsulation layer 119.

[0146] In the first block portion BLK1, the planarization layer 113 can be provided above the passivation layer 111c. The planarization layer 113 of the first block portion BLK1 can be formed of the same material as that of the planarization layer 113 of the first sub-pixel SP1 together with the planarization layer 113 of the first sub-pixel SP1, and thus can be provided to have the same thickness as that of the planarization layer 113 of the first sub-pixel SP1.

[0147] As Figure 5 ​As shown, since the GIP-transmissive portion TR2 is provided in the second direction (Y-axis direction) of the first block portion BLK1, both sides of the planarization layer 113 provided in the first block portion BLK1 can be provided adjacent to the GIP-transmissive portion TR2.

[0148] A dummy electrode DE can be provided above the planarization layer 113 of the first block portion BLK1. The dummy electrode DE can be provided in the same or similar structure as the structure of the first sub-pixel SP1 and thereby formed in the common control portion CPU to reduce a visibility difference. The dummy electrode DE can be formed of the same material as the first electrode 114 provided in the sub-pixel together with the first electrode 114. The dummy electrode DE according to one example can overlap at least a portion of each of the first metal layer DMP1, the second metal layer DMP2, and the third metal layer DMP3.

[0149] In Figure 6 Since the first metal layer DMP1, the second metal layer DMP2, and the third metal layer DMP3 are provided in a flat shape, a lower surface profile of the planarization layer 113 covering the third metal layer DMP3 can be provided in a flat shape. However, when the first metal layer DMP1 to the third metal layer DMP3 are provided in the same form as the signal line LS, the gate 112b, and the source 112c of Figure 4 the dummy electrode DE and the third metal layer DMP3, such that an upper surface of the planarization layer 113 can be provided in a flat shape. Since the dummy electrode DE is provided above the planarized upper surface of the planarization layer 113, the dummy electrode DE can also be provided in a flat shape. Since at least a portion of the dummy electrode DE provided in a flat shape is provided to overlap the metal layer provided thereunder in a non-flat shape, a diffuse reflection of external light can be reduced or prevented by the metal layer in a non-flat shape. Accordingly, the dummy electrode DE provided in the first block portion BLK1 can reduce or prevent a diffuse reflection of external light with respect to the dummy pattern DMP.

[0150] Furthermore, since the non-display area NDA (or the common control section CPU) does not emit light, power (or voltage) need not be supplied to the dummy electrode DE. Therefore, the dummy electrode DE can be configured as a floating element and not electrically connected to the third metal layer DMP3. Similarly, the first metal layer DMP1, the second metal layer DMP2, and the third metal layer DMP3 are configured to reduce the difference in reflective visibility with the display area DA, and therefore do not need to be electrically connected to the driving circuit of the pad area PA. Therefore, in the transparent display device 100 according to one embodiment of the present disclosure, the dummy pattern DP (i.e., the first metal layer DMP1, the second metal layer DMP2, and the third metal layer DMP3) can be configured as an island.

[0151] The dummy embankment DB can be configured to cover the edge of the dummy electrode DE above the planarization layer 113. The dummy embankment DB can be configured to have the same structure as the embankment 115 disposed in the display area DA, thereby reducing the visibility difference with the display area DA. According to one example, the dummy embankment DB can be formed together with the embankment 115 from the same material as the embankment 115 of the display area DA.

[0152] Return to reference Figure 6 Since the non-display area NDA does not emit light, the organic light-emitting layer 116 and the second electrode 117 are not required. Therefore, as... Figure 6 As shown, the capping layer 118 may cover the upper surface of the passivation layer 111c exposed to the GIP transmission portion TR2, the side surface of the planarization layer 113, the upper surface and side surface of the dummy embankment DB, and the upper surface of the dummy electrode DE exposed between the dummy embankments DB, but is not limited thereto. The organic light-emitting layer 116 and the second electrode 117 may be disposed above the dummy electrode DE to reduce the visibility difference with the display area DA. Even if the organic light-emitting layer 116 and the second electrode 117 are disposed above the dummy electrode DE, no power (or voltage) is supplied to the dummy electrode DE, so that the organic light-emitting layer 116 may not emit light.

[0153] The encapsulation layer 119 can be configured to cover the capping layer 118 disposed in the first block portion BLK1 and the capping layer 118 disposed in the GIP transmissive portion TR2 adjacent to the first block portion BLK1. The encapsulation layer 119 disposed in the non-display area NDA can include at least one inorganic layer and at least one organic layer. Therefore, the encapsulation layer 119 disposed in the non-display area NDA (or common control portion CPU) can prevent moisture from penetrating from the outside of the substrate 110 toward the display area DA.

[0154] Further, the first block portion BLK1 can not include a color filter to reduce a visibility difference with the first sub-pixel SP1. Accordingly, the second substrate 120 can be disposed over the encapsulation layer 119 of the first block portion BLK1 so that the second substrate 120 can be in direct contact with the encapsulation layer 119 of the first block portion BLK1.

[0155] Accordingly, in the transparent display apparatus 100 according to one embodiment of the disclosure, the structure of the GIP portion GP of the non-display area NDA is the same as or similar to that of the pixel P of the display area DA so that a visibility difference between the display area DA and the non-display area NDA for a user can be reduced, and a reflection visibility difference due to external light can be reduced.

[0156] In more detail, in the first block portion BLK1, there is no color filter, and at least a portion of each of the three non-pixel metal layers is disposed under the planarization layer 113 to overlap each other so that the non-pixel metal layers are disposed to be the same as or similar to the first sub-pixel SP1, whereby a reflection visibility difference can be reduced. Since the red block portion BLK2-1 of the second block portion BLK2 includes a red color filter CF1, a visibility difference and a reflection visibility with the second sub-pixel SP2 can be reduced. Since the green block portion BLK2-2 of the second block portion BLK2 includes a green color filter CF2, a visibility difference and a reflection visibility with the third sub-pixel SP3 can be reduced. Since the blue block portion BLK2-3 of the second block portion BLK2 includes a blue color filter CF3, a visibility difference and a reflection visibility with the fourth sub-pixel SP4 can be reduced.

[0157] Figure 7 is a diagram illustrating another example of the portion B of Figure 2B

[0158] In the case of Figure 5 , the dummy pattern DMP disposed in the common control portion CUP can be disposed in the form of an island to reduce a reflection visibility difference with the display area DA.

[0159] In contrast, in another example of Figure 7 , the dummy pattern DMP disposed in the common control portion CUP can be disposed to connect a plurality of circuits, i.e., a plurality of common transistors CTR in the common control portion CUP. In more detail, in Figure 7 ​In this case, the dummy pattern DMP can be connected to the plurality of common transistors CTR through the sub-common lines SCUL in the common control part CUP. In this case, the dummy pattern DMP can serve as a connection electrode or a connection line connecting the plurality of common transistors CTR. Since each of the first metal layer DMP1, the second metal layer DMP2, and the third metal layer DMP3 having the dummy pattern DMP is made of the same metal material as that of the common power line, the gate 112b, and the source 112c, at least one of the first metal layer DMP1, the second metal layer DMP2, or the third metal layer DMP3 can serve as a connection electrode (or a connection line) connected to the sub-common line SCUL to transmit a signal between the plurality of common transistors CTR, but the present disclosure is not limited thereto. At least one of the first metal layer DMP1, the second metal layer DMP2, or the third metal layer DMP3 can serve as a connection electrode (or a connection line) for applying a power source to the plurality of common transistors CTR.

[0160] As described above, since the common transistor CTR can be freely disposed inside the common control part CUP, a plurality of first block parts BLK1 can be disposed between the common transistors CTR. That is, a plurality of dummy patterns DMP consisting of at least three non-pixel metal layers can be disposed at different positions between the common transistors CTR. Since the dummy patterns DMP disposed at different positions serve as connection electrodes (or connection lines) for applying a signal or a power source, the number of sub-common lines SCUL can be reduced compared to a case in which the dummy pattern DMP is not used electrically, whereby the width of the common control part CUP can be further reduced. In addition, since the non-pixel metal layers disposed in the dummy pattern DMP are larger in width and area than general signal lines or power lines, problems such as signal reduction or voltage drop can be solved.

[0161] Accordingly, the transparent display apparatus 100 according to another embodiment of the present disclosure is disposed such that at least one of the first metal layer DMP1, the second metal layer DMP2, or the third metal layer DMP3 of the first block part BLK1 serves as a connection electrode (or a connection line) connecting the common transistor CTR, whereby the bezel width can be reduced, and problems such as signal reduction or voltage drop can be solved.

[0162] According to the present disclosure, the following advantageous effects can be obtained.

[0163] In the present disclosure, since the plurality of lines and the plurality of circuits disposed in the non-display area are disposed to be separated from each other, a reflection visibility difference between the display area and the non-display area can be reduced.

[0164] Further, in the present disclosure, the plurality of lines disposed in the non-display area are disposed to be concentrated on one side of the circuit portion, so that the plurality of lines can be prevented from being twisted in the non-display area, thereby the parasitic capacitance can be prevented from being generated between the lines.

[0165] Further, in the present disclosure, since the plurality of circuits disposed in the non-display area are disposed to be concentrated on the other side of the line portion, the plurality of circuits can be shared, so that the number of circuits can be reduced, thereby the degree of freedom in the buffer, etc. can be improved.

[0166] Further, in the present disclosure, since the number of circuits disposed in the non-display area is reduced, the dummy pattern can be disposed in the space between the circuits, so that the difference in reflectance visibility between the display area and the non-display area due to external light can be further reduced.

[0167] It will be apparent to those skilled in the art that the above-described disclosure is not limited by the above-described embodiments and drawings, and various substitutions, modifications and variations of the disclosure can be made without departing from the spirit or scope of the disclosure. Therefore, the disclosure intends that all variations or modifications derived from the meaning, scope and equivalent concepts of the claims fall within the scope of the disclosure.

[0168] Cross Reference to Related Applications

[0169] This application claims priority to Korean Patent Application No. 10-2021-0186145, filed on December 23, 2021, which is incorporated by reference herein as if fully set forth in its entirety in the present document.

Claims

1. A transparent display device, the transparent display device comprising: A substrate having a display area and a non-display area, wherein the display area has a plurality of pixels having a transmissive portion and a plurality of sub-pixels, and the non-display area is configured to surround the display area and have a pad area. The line portion, which is disposed above the substrate in the non-display area, has multiple lines connected to the pad area; as well as The circuit section, located in the non-display area, has multiple circuits connected to the multiple lines. The line portion is configured to be separate from the circuit portion. The transparent display device further includes a GIP (Glass Inlet Propagation) transmissive portion disposed between the plurality of lines and the plurality of circuits, and The circuit portion includes: a common control section comprising multiple circuits; and a buffer section disposed between the common control section and the display area. The line portion also includes multiple signal lines respectively connected to the plurality of circuits of the common control portion, and The common control section includes multiple common lines that connect the multiple circuits to each other.

2. The transparent display device according to claim 1, wherein, The non-display area includes a non-display area of ​​the pads in which the pad area is disposed, and The multiple lines are spaced apart from each other in the non-display area of ​​the pads.

3. The transparent display device according to claim 2, wherein, The plurality of lines are arranged to be concentrated on one side of the circuit portion, and the plurality of circuits are arranged to be concentrated on one side of the line portion.

4. The transparent display device according to claim 1, wherein, The buffer section includes multiple sub-buffers, and The multiple sub-buffers are connected to the common control section via buffer lines.

5. The transparent display device according to claim 4, wherein, The buffer line includes a main buffer line connected to at least one of the plurality of circuits included in the common control section, and a plurality of branch buffer lines connecting the main buffer line to each of the plurality of sub-buffers.

6. The transparent display device according to claim 1, wherein, The buffer section includes multiple sub-buffers, and The line portion includes multiple clock lines connected to the sub-buffers and all ground lines connected to the multiple sub-buffers.

7. The transparent display device according to claim 6, wherein, The multiple signal lines are arranged in parallel between the grounding wire and the buffer section.

8. The transparent display device according to claim 7, wherein, Each of the multiple signal lines shares the multiple circuits of the common control section.

9. The transparent display device according to claim 1, wherein, The common control section also includes a dummy pattern disposed among the plurality of circuits.

10. The transparent display device according to claim 9, wherein, The virtual pattern includes: A first metal layer is disposed above the substrate; A second metal layer is disposed above the first metal layer; and A third metal layer is disposed above the second metal layer, and The first metal layer overlaps at least partially with the second metal layer and the third metal layer.

11. The transparent display device according to claim 10, wherein, The first metal layer is disposed on the same layer as the common voltage line disposed above the substrate. The second metal layer is disposed on the same layer as the gates disposed in the plurality of sub-pixels, and The third metal layer is disposed on the same layer as the source electrode disposed above the gate.

12. The transparent display device according to claim 10, wherein, At least one of the first metal layer, the second metal layer, or the third metal layer is connected to the plurality of circuits in the common control section.

13. A transparent display device, the transparent display device comprising: A substrate having a display area and a non-display area, wherein the display area has a plurality of pixels having a transmissive portion and a plurality of sub-pixels, and the non-display area is configured to surround the display area and has a pad area; The line portion, which is disposed above the substrate in the non-display area, has multiple lines connected to the pad area; as well as The circuit section, located in the non-display area, has multiple circuits connected to the multiple lines. The circuit portion is disposed between the line portion and the display area. The transparent display device further includes a GIP (Glass Inlet Propagation) transmissive portion disposed between the plurality of lines and the plurality of circuits, and The circuit portion includes: a common control section comprising multiple circuits; and a buffer section disposed between the common control section and the display area. The common control section includes multiple common lines that connect the multiple circuits to each other.

14. The transparent display device according to claim 13, wherein, The non-display area includes a non-display area of ​​the pads in which the pad area is disposed, and The multiple lines do not overlap with each other in the non-display area of ​​the pads.

15. The transparent display device according to claim 13, wherein, The line portion includes multiple signal lines respectively connected to the plurality of circuits of the common control portion, and Each of the multiple signal lines shares the multiple circuits of the common control section.

16. The transparent display device according to claim 13, wherein, The common control section also includes a dummy pattern disposed among the plurality of circuits.

17. The transparent display device according to claim 16, wherein, The virtual pattern includes: A first metal layer is disposed above the substrate; A second metal layer is disposed above the first metal layer; and A third metal layer is disposed above the second metal layer, and The first metal layer overlaps at least partially with the second metal layer and the third metal layer.

18. The transparent display device according to claim 17, wherein, At least one of the first metal layer, the second metal layer, and the third metal layer serves as a connection electrode connected to a sub-common line in the common control section to transmit signals between multiple common transistors in the common control section.

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