A Simulation Modeling Method for Substrate Bias Effect of Silicon-Based GaN HEMT Devices

Abstract

The present invention relates to the technical field of semiconductor devices, and particularly relates to a simulation modeling method for the substrate bias effect of a silicon-based GaN HEMT device. Based on the Schrödinger-Poisson equation, the present invention takes into account the threshold voltage drift and dynamic on-resistance degradation caused by the field effect when the GaN HEMT device is under substrate bias, and constructs the substrate bias voltage applied to the device as being linearly related to the first order of the device threshold drift amount. Based on the trapping and releasing effects of trap centers on channel carriers and the positive charge storage effect of the GaN Buffer layer, using SRH statistics, a non-linear exponential relationship between the magnitudes of different pulsed substrate bias voltages and the threshold voltage and mobility of the GaN HEMT is constructed. Finally, the change amount of the model parameters caused by the substrate bias voltage is input into the analytical model of the core drain current of the GaN HEMT, and is applied to the large-signal simulation and circuit design of the GaN HEMT device. The effectiveness of the model in simulating the substrate bias effect is verified through test data and circuit simulation.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor devices, and particularly relates to a simulation modeling method for substrate bias effect of a silicon-based GaN HEMT device. Background Art

[0002] With the high-performance power management requirements proposed by the development of civilian fields such as smart phones and new energy vehicles, as well as the requirements of military fields such as radars, aerospace in terms of power density, operating frequency, etc., the first-generation semiconductors represented by Si-based devices and the second-generation semiconductors represented by GaAs often cannot meet the requirements of multiple aspects in modern applications at the same time. The third-generation semiconductors represented by GaN have material characteristics such as wide bandgap, high thermal conductivity, and stable chemical properties. Therefore, compared with the first two generations of semiconductor devices, they have higher breakdown voltage and operating temperature, as well as better radiation resistance. And GaN crystals can be grown on low-cost, large-diameter silicon wafers without high cost. Therefore, GaN devices can not only meet the requirements of the civilian field for miniaturization of power management modules, but also meet the requirements of the military field for high operating frequency, high power density, and high stability in harsh environments.

[0003] The high switching frequency characteristics of GaN HEMT power devices enable significant reduction in the weight and volume of power electronic systems such as power converters fabricated using them. However, the parasitic effects from interconnecting wires have become a bottleneck for the high-frequency applications of GaN HEMT power devices. The gate drive loop formed by the separation of the power drive, power switch, and protection circuits has obvious parasitic effects, and the gate ringing also limits the switching frequency. Selecting to monolithically integrate the GaN HEMT half-bridge circuit can significantly reduce the parasitic inductance in the power loop and improve the operating frequency and stability of the power conversion circuit. However, at the same time, the high-side and low-side GaN HEMTs in the fully integrated GaN bridge circuit share a conductive silicon substrate, so they share a substrate potential. Depending on the different substrate connection methods, the upper and lower transistors will be subject to different substrate biases, resulting in changes in electrical characteristics such as different threshold voltages, on-resistances, and saturation currents. Currently, the mainstream GaN models do not fully characterize the substrate bias effect, which hinders the design of GaN full integrated circuits. Summary of the Invention

[0004] In view of this, the purpose of the present invention is to establish an easy-to-use, completely physics-based substrate bias effect model for GaN HEMT devices, solve the problem that the current mainstream models cannot accurately predict the threshold voltage drift and current collapse phenomena of silicon-based GaN HEMT devices under substrate bias in a circuit simulation platform, and improve the prediction accuracy of the model for the threshold voltage and drain current. To achieve the above purpose.

[0005] The present invention adopts the following technical solutions:

[0006] A simulation modeling method for the substrate bias effect of a silicon-based GaN HEMT device, characterized by comprising:

[0007] In the first step, the relationship between the two-dimensional electron gas concentration in the channel and the DC substrate bias voltage is obtained by solving the Schrödinger-Poisson equation, and based on the field effect, a first-order linear threshold voltage drift model and an effective mobility degradation model are established as:

[0008]

[0009]

[0010]

[0011] where V bs is the device substrate bias voltage, ΔV off,n is the change in the threshold voltage caused by the field effect, μ eff is the effective mobility, C g , C b are the barrier layer and substrate capacitances per unit area respectively, E y,eff is the effective vertical electric field, U0 is the low-field mobility, UA is the first-order effective mobility degradation factor, UB is the second-order effective mobility degradation factor, ε AlGaN , ε GaN are the relative dielectric constants of the barrier layer and GaN, is the average value of the drain potential and the source potential, V g0 =V g -V off , V g is the gate voltage of the device, and k1 and k2 are the first-order fitting coefficients related to the substrate bias field effect;

[0012] In the second step, based on the SRH statistics of the trap effect, a non-linear threshold voltage drift model and an effective mobility degradation model caused by the pulsed substrate bias stress are established as:

[0013]

[0014]

[0015]

[0016] where, ΔV off,p and ΔUA are respectively the change in the threshold voltage and the first-order effective mobility degradation factor caused by the trap effect, α, A, B, D are coefficients related to the trap energy level and the number of traps, and a and b are fitting factors; based on the charge storage effect of the silicon-based GaN HEMT buffer layer, the normalized trap control potential is corrected to:

[0017]

[0018] Among them, γ, E, F, and G are correlation coefficients related to the charge storage effect;

[0019] In the third step, combining the models of the first and second steps, an analytical model of the drain current is established as:

[0020]

[0021] Among them, I ds is the drain current of the device, W is the gate width of the device, L is the gate length of the device, N f is the device exponent, λ is the channel length modulation parameter, V th is the thermal voltage, θ sat is the carrier saturation velocity parameter, V off,eff is the corrected threshold voltage, V g is the gate voltage, is the difference in surface potential between the drain and source, V ds is the drain-source voltage;

[0022] In the fourth step, the transfer characteristics and output characteristics of the silicon-based GaN HEMT device under substrate bias stress are tested, and model parameter extraction is performed based on the test data;

[0023] In the fifth step, based on the complete model after parameter extraction, circuit simulation verification is carried out, and some model parameters are readjusted according to the simulation results until the accuracy requirements are met.

[0024] Furthermore, according to the I-V test under the static negative substrate bias in the off state of the device, the first-order fitting coefficients of the k1 and k2 parameters in the model are extracted by using the linear fitting method.

[0025] Furthermore, the extraction of the buffer layer trap model parameters is based on the pulsed substrate bias I-V test in the off state of the device, and the trap-related and charge storage effect-related fitting coefficients are extracted by using the curve fitting method.

[0026] Using the gallium nitride device characteristic characterization instrument, the changes in the transfer characteristics and output characteristics of the GaN HEMT device under different substrate biases are measured. Using the substrate bias effect model of the GaN HEMT device in this model to fit the measured transfer characteristics and device output characteristic curves of the gallium nitride device, the first-order fitting coefficients k1, k2 of the substrate bias-related field effect and the coefficients α, γ, A, B, D, E, F, G related to the trap energy level and trap number, as well as the fitting factors a, b, and the carrier saturation drift velocity parameter θ are extracted sat, the low-field mobility U0, the mobility degradation coefficients UA and UB, which can accurately predict the threshold voltage drift and current collapse phenomena of GaN HEMT devices under different substrate biases.

[0027] The beneficial effects of the present invention are as follows. Based on the Schrödinger-Poisson equation, considering the threshold voltage drift and dynamic on-resistance degradation caused by the field effect when the GaN HEMT device is under substrate bias, the substrate bias applied to the device is constructed to be linearly related to the first order of the device threshold drift amount. Based on the trapping and releasing effects of trap centers on channel carriers and the positive charge storage effect of the GaN Buffer layer, using SRH statistics, a non-linear exponential relationship between the magnitudes of different pulsed substrate biases and the threshold voltage and mobility of GaNHEMT is constructed. Finally, the change amount of the substrate bias on the model parameters is input into the analytical model of the core drain current of the GaNHEMT device and applied to the large-signal simulation and circuit design of the GaN HEMT device. The effectiveness of the model in simulating the substrate bias effect is verified through test data and circuit simulation. The substrate bias effect model of the silicon-based GaN HEMT device of the present invention solves the defect that the current mainstream models cannot predict the threshold voltage drift and current collapse phenomena of GaN HEMT devices when there is a substrate bias voltage in the circuit simulation platform, improves the characterization ability of the silicon-based GaN HEMT device model for the substrate bias effect of the device, improves the complete simulation ability of the model for GaN HEMT devices, and provides a solution for the simulation design of GaN full integrated circuits. Brief Description of the Drawings

[0028] Figure 1 It is a schematic cross-sectional structure diagram of the device based on which the substrate bias effect model of the present invention is established;

[0029] Figure 2 It is a schematic flow chart of establishing the substrate bias effect model of the present invention;

[0030] Figure 3 It is a schematic circuit model diagram established by the present invention based on the trap energy level capturing electrons and the GaN Buffer charge storage effect;

[0031] Figure 4 It is a schematic diagram of the DC substrate bias stress test of the gallium nitride HEMT device of the present invention;

[0032] Figure 5 It is a schematic diagram of the pulsed substrate bias stress test of the gallium nitride HEMT device of the present invention;

[0033] Figure 6 It is a comparison relationship diagram of the predicted threshold voltage and the device threshold voltage of the substrate bias effect model of the present invention under DC substrate bias stress, where the solid line is the model prediction result and the symbol is the device measurement result;

[0034] Figure 7 This is a comparison graph of the model-predicted threshold voltage and the device threshold voltage under pulsed substrate stress for the substrate bias effect model of the present invention. The solid line represents the model prediction result, and the symbols represent the device measurement results;

[0035] Figure 8 This is a comparison graph of the model-predicted output characteristics and the device output characteristics under DC substrate bias stress for the present invention. The solid line represents the model prediction result, and the symbols represent the device measurement results;

[0036] Figure 9 This is a comparison graph of the model-predicted output characteristics and the device output characteristics under pulsed substrate stress for the present invention. The solid line represents the model prediction result, and the symbols represent the device measurement results. Detailed implementation manners

[0037] The technical solution of the present invention will be described in detail below with reference to the accompanying drawings:

[0038] The present invention is based on Figure 1 to elaborate on the principle of the substrate bias effect and the theoretical basis for modeling of silicon-based GaN HEMT devices. The substrate bias effect specifically means that when the potential of the silicon substrate of the device is not equal to that of the source electrode, there will be a vertical potential difference. The vertical electric field generated by this potential difference will theoretically have the following effects on the device:

[0039] 1. This vertical electric field will change the electron energy band at the AlGaN / GaN interface through the field effect to change the two-dimensional electron gas concentration.

[0040] 2. This vertical electric field will induce electrons to be injected from the channel and the substrate into the GaN buffer layer traps, partially depleting the two-dimensional electron gas.

[0041] The change in the two-dimensional electron gas concentration caused by the above effects may lead to:

[0042] 1. Threshold voltage drift.

[0043] 2. Change in on-resistance.

[0044] 3. Decrease in saturation current.

[0045] Based on the above theory, this technical solution takes the substrate bias voltage to characterize the threshold voltage drift amount and the on-resistance change amount of the device as the core of the model, and accordingly obtains the calculation formula for the drain-source current of the device.

[0046] Use such as Figure 2Schematic diagram of the threshold voltage and drain current model establishment process shown, based on the Schrödinger-Poisson equation and Fermi-Dirac statistics, considering the threshold voltage drift, dynamic on-resistance degradation, and saturation current degradation of the GaN HEMT device under the influence of the substrate bias voltage. Based on the direct influence of the back-gate field effect on the 2-DEG concentration, the trapping and release effect of trap centers on channel carriers, and the positive charge storage effect in the GaN Buffer layer caused by the substrate bias, the device threshold voltage and the first-order effective mobility decay coefficient model are constructed to be related to the substrate bias voltage of the device. Combining and finally constructing a model applicable to calculating the threshold voltage and drain current of gallium nitride high electron mobility transistors under different substrate bias voltages, the specific calculation method is as follows:

[0047] Combined with the Schrödinger-Poisson equation, the 2-DEG concentration n in the triangular quantum well under the gate of the GaN HEMT s and the Fermi level E f The complex relationship is Equation (1)

[0048]

[0049] where γ0, γ1 are constants usually determined in experiments, E f is the Fermi level expressed in volts, V th is the thermal voltage kT / q. Assuming that the AlGaN barrier layer is fully ionized, n s can be expressed as (2)

[0050]

[0051] where V go =V g -V off , V g is the gate voltage of the device, V off is the threshold voltage of the device; d is the thickness of the AlGaN, ε is the relative dielectric constant of the AlGaN, and q is the electric charge of the electron. The channel potential V x and the surface potential of the gallium nitride HEMT device The relationship is (3)

[0052]

[0053] Combining Equations (1), (2), and (3), n s (4)

[0054]

[0055] According to the drift-diffusion model and applying the gradual channel approximation, the drain current I at any point x in the channel d can be expressed as (5)

[0056]

[0057] where μ eff is the effective carrier mobility, and this value is from the effective mobility degradation model. W is the device channel width; Q ch has the following expression

[0058]

[0059] Considering the optical phonon scattering caused by the increase in the transverse electric field, which leads to carrier velocity saturation, and integrating Equation (5) along the x-direction (transverse), the corrected I can be obtained ds

[0060]

[0061] where θ sat is the saturation velocity related model parameter, has the following expression

[0062]

[0063] where and are the surface potentials at the drain end and the source end calculated using Equation (3), respectively.

[0064] When there is a substrate bias voltage in the device, the channel surface potential is corrected using the principle of capacitive coupling. It is stipulated that C g is the potential barrier layer capacitance per unit area, and C b is the GaN buffer layer capacitance per unit area, that is:

[0065]

[0066]

[0067] Substituting (9) and (10) into (4) gives

[0068] qn s = C g (V g0 - E f ) (11)

[0069] qn sb = C b (V bs - E f ) (12)

[0070] Adding the right sides of (11) and (12) gives

[0071]

[0072] Among them, C eff =(C g +C bs ), V geff =αV g0 +βV bs . Since d AlGaN <<d GaN , so C b <<C g . Substituting this relationship into V geff we can get:

[0073]

[0074] Substituting the corrected V geff into the normalized n s and the core current expression, the expression of I ds including the influence of substrate bias can be obtained.

[0075] Considering the change in the vertical electric field strength caused by the substrate bias, which will change the relative position of the channel carriers and the AlGaN / GaN interface as well as the carrier density. Therefore, due to the interface roughness and carrier-carrier scattering, the carrier mobility will decrease. The expression of the effective mobility μ eff is

[0076]

[0077] According to Gauss's theorem, the effective vertical electric field E y,eff is expressed as

[0078] E y,eff =Q ch / ε AlGaN (16)

[0079] Taking into account the substrate bias, the additional vertical electric field strength generated at this time can be expressed as

[0080] E y,b =Q b / ε GaN (17)

[0081]

[0082] From this, it can be obtained that the changed total electric field strength is

[0083] E y =E y,eff +E y,b =βE y.eff (19)

[0084] It can be simplified to obtain

[0085]

[0086] where α is the constant term, and then the first-order effective mobility decay coefficient UA is corrected to:

[0087] UA → β·UA (21)

[0088] The simulation of the trap effect caused by the substrate bias in this model is based on the Shockley-Read-Hall (SRH) statistics of the trap process, and a single-level trap center is introduced. Let the net capture rates of electrons and holes at the trap center energy level E x be U n and U p

[0089] U n = e n [p x exp(φ n ) - n x (22)

[0090] U p = e p [n x exp(φ p ) - p x (23)

[0091] where φ n ≡ (F n - E x ) / kT, φ p ≡ (E x - F p ) / kT. F n and F p are the quasi-Fermi levels of electrons and holes.

[0092] Meanwhile, the concentrations of electrons and holes that can be trapped by the trap center can be expressed as

[0093]

[0094]

[0095] where are the concentrations of electrons and holes in the conduction band when F n and F p drop to the trap center energy level E x respectively. From the above formula, it can be seen that φ n and φ pIt is the control potential of the net electron capture rate at the trap center and the control potential of the charge concentration that can be captured, so it is collectively called the control potential of the trap center.

[0096] The present invention establishes a circuit model by capturing electrons at the trap energy level as shown in Figure 3 . This model represents the trap effect as the charging and discharging process of a controlled current source controlled by the control potential for the trap capacitor C x . It can be seen from the figure that the relationship between the electron concentration at the trap center and the trap potential v x is:

[0097] C x = (-q)n x / v x (26)

[0098] Figure 3 In cn , i en , i cp , i ep are defined as the currents of electron and hole capture and emission, then the total electron capture current can be expressed as:

[0099] i = (i cn - i en ) - (i cp - i ep ) (27)

[0100] Where

[0101] i cn = C x e n (V x - v x )exp(φ n ) (28)

[0102] i en = C x e n v x (29)

[0103] i cp = C x e p v x exp(φ p ) (30)

[0104] i ep = C x e p (V x - v x ) (31)

[0105] In the above formula, V x ≡ (-qN​​​​​​​​​​​​​​​​​​​​​​​​​​​​​x ) / C x is the electric potential when the trap is completely occupied by electrons, N x is the trap center energy level E x at the concentration of the trap center. For a steady-state situation, the total electron capture current i should be 0. Therefore, from Equation (27), we can obtain

[0106]

[0107] where η≡e n / e p , ε≡ln(η), is v under steady-state conditions x . According to the device mechanism and test results of GaN HEMT (E-mode), the main trap effect in GaN HEMT is electron capture. If it is assumed that the inside of the device is all electron capture trap centers, that is, e p =0, then the above equation can be simplified to:

[0108]

[0109] The quasi-Fermi level of electrons can be corrected under external bias conditions as

[0110] F n =F n0 +(V stress *q / θ) (34)

[0111] Substituting Equation (34) into (33) and making certain modifications and simplifications, we can obtain

[0112]

[0113] where A, B, and D are model correction parameters to achieve first-order calibration of the trap center. Actual tests show that when the GaN HEMT device is subjected to a pulsed positive substrate bias stress below a certain magnitude, both the threshold voltage and the on-resistance decrease. It is speculated that this is due to the storage phenomenon of positive charges in the GaN Buffer layer. Applying the description of the electron trap effect in Equation (35), further correction is made by adding a hole charging term. Let then

[0114]

[0115] A, B, D, E, F, G, α, γ are coefficients related to trap energy levels and trap numbers, and the device threshold voltage and the first-order effective mobility decay coefficient are corrected according to Equation (36)

[0116]

[0117]

[0118] The expression of the drain-source current of the final compact physical model that can simulate the substrate bias of GaN HEMT is as follows

[0119]

[0120]

[0121] Based on the Schrödinger-Poisson equation and Fermi-Dirac statistics, the present invention considers the threshold voltage drift and on-resistance degradation caused by the substrate bias effect in the silicon-based GaN HEMT device in the fully integrated half-bridge, the field effect based on the negative back-gate, and the capture and release effects of the trap centers on the channel carriers caused by the positive pulse back-gate. The device threshold voltage and on-resistance degradation models are constructed to be related to the device substrate bias voltage, and based on this, a substrate bias effect model applicable to gallium nitride high electron mobility transistors under different substrate bias voltages is constructed. The calculation model established by the present invention is completely physical and easy to use, providing a more comprehensive simulation model for the design of gallium nitride full integrated circuits.

[0122] To verify the effectiveness and accuracy of the threshold voltage and drain current models of the present invention, use Figure 4 and Figure 5 The test scheme of applies stress to the gallium nitride HEMT device, and then measures the transfer and output characteristics of the gallium nitride device.

[0123] Using this model to fit the model and extract parameters for the transfer and output characteristic curves of the gallium nitride device substrate bias model. The comparison between the threshold voltage and output characteristics of the gallium nitride device predicted by the calculation model and the actual measured characteristics of the device under different DC substrate bias voltages is as Figure 6 、 8 shown; The comparison between the threshold voltage and output characteristics of the gallium nitride device predicted by the calculation model and the actual measured characteristics of the device under different pulse substrate bias voltages is as Figure 7 、 9 shown. In practical applications, the present invention can obtain relevant results quickly and accurately according to the model establishment process of Figure 2 for substrate bias voltages of different polarities and magnitudes.

[0124] Figure 6 、 7 、8, 9 The extracted model parameters are as follows: gate width W = 1mm, gate length L = 1um, exponent N f = 80, low-field mobility U0 = 0.068m 2 / (V*s), mobility degradation coefficient UA = 3.2E-09V -1 , UB = 1E-18V -2 , saturation drift velocity θsat = 1.1E+05 m / s, the fitting coefficient β of the field-induced mobility degradation is 1.156, the fitting coefficients α, γ, A, B, D, E, F, and G related to traps and charge storage are 0.87, -0.04, 0.185, -3.81, -0.03605, 1.142, -2.2, and -0.337 respectively.

Claims

1. A simulation modeling method for the substrate bias effect of a silicon-based GaN HEMT device, characterized in that, Including: First step: Obtain the relationship between the two-dimensional electron gas concentration in the channel and the DC substrate bias voltage by solving the Schrödinger-Poisson equation, and based on the field effect, establish the first-order linear threshold voltage drift model and the effective mobility degradation model as follows: where V bs is the device substrate bias voltage, ΔV off,n is the change in threshold voltage caused by the field effect, μ eff is the effective mobility, C g , C b are the barrier layer and substrate capacitances per unit area respectively, E y,eff is the effective vertical electric field, U0 is the low-field mobility, UA is the first-order effective mobility degradation factor, UB is the second-order effective mobility degradation factor, ε AlGaN , ε GaN are the relative dielectric constants of the barrier layer and GaN, is the average of the drain potential and the source potential, V g0 = V g - V off , V g is the gate voltage of the device, and k1 and k2 are the first-order fitting coefficients related to the substrate bias field effect; Second step: Based on the SRH statistics of the trap effect, establish the nonlinear threshold voltage drift model and the effective mobility degradation model caused by the pulsed substrate bias stress as follows: where, ΔV off,p and ΔUA are the threshold voltage caused by the trap effect and the change amount of the first-order effective mobility degradation factor respectively, α, A, B, and D are correlation coefficients related to the trap energy level and the number of traps, and a and b are fitting factors; based on the charge storage effect of the silicon-based GaN HEMT buffer layer, the normalized trap control potential is corrected to: where γ, E, F, and G are the correlation coefficients related to the charge storage effect; Third step: Combine the models of the first and second steps to establish the drain current analytical model as follows: Wherein, I ds is the device drain current, W is the device gate width, L is the device gate length, N f is the device exponent, λ is the channel length modulation parameter, V th is the thermal voltage, θ sat is the carrier saturation velocity parameter, V off,eff is the corrected threshold voltage, V g is the gate voltage, is the drain-source surface potential difference, V ds is the drain-source voltage; Fourth step: Test the transfer characteristics and output characteristics of the silicon-based GaN HEMT device under the substrate bias stress, and extract the model parameters based on the test data; Fifth step: Based on the complete model after parameter extraction, conduct the verification of the circuit simulation, and readjust some model parameters according to the simulation results until the accuracy requirement is met.

2. The simulation modeling method for the substrate bias effect of a silicon-based GaN HEMT device according to claim 1, characterized in that, Based on the I-V test under the static negative substrate bias in the off state of the device, extract the first-order fitting coefficients of the k1 and k2 parameters in the model by using the linear fitting method.

3. The simulation modeling method for the substrate bias effect of a silicon-based GaN HEMT device according to claim 1, characterized in that, The extraction of the buffer layer trap model parameters is based on the pulsed substrate bias I-V test in the off state of the device, and the trap-related and charge storage effect-related fitting coefficients are extracted by using the curve fitting method.

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