Method of forming a semiconductor structure

Abstract

A method for forming a semiconductor structure includes: providing a substrate, the substrate including a base and a layer to be etched, the layer to be etched including a first region and a second region, the first region having a plurality of first initial mask structures thereon, and the second region having a plurality of second mask structures thereon; forming a sacrificial layer on the second region; performing etching processing on the first initial mask structures to form first mask structures; forming a protective layer on sidewalls and top surfaces of the first mask structures and on sidewalls and top surfaces of the second mask structures based on a first advanced process control technology; and etching the layer to be etched to form a plurality of patterned structures on the base. The first advanced process control technology can compensate feature sizes of the first mask structures and the second mask structures at the same time, and thus the feature sizes of the second mask structures also conform to preset feature sizes, thereby ensuring accuracy of subsequent pattern transfer and improving wafer production yield and reliability.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing technology, and in particular to a method for forming a semiconductor structure. Background Technology

[0002] The purpose of Advanced Process Control (APC) research in semiconductor manufacturing is to effectively monitor the process and equipment in order to improve yield and overall equipment efficiency.

[0003] As semiconductor process nodes continue to shrink, the process window for semiconductor device fabrication becomes increasingly narrow. This places more stringent requirements on integrated circuit equipment and testing equipment for process control. Traditional statistical process control (SPC) and methods that control only a single parameter are no longer adequate for current process technology requirements. Therefore, analog-to-digital (APC) technology has become one of the key technologies in semiconductor manufacturing. APC technology, as a primary solution, has gradually gained acceptance from semiconductor equipment suppliers, measurement equipment suppliers, and manufacturers, and is currently being increasingly applied in processes such as chemical mechanical polishing, chemical vapor deposition, photolithography, and etching.

[0004] The goal of APC technology is to address the drift in average results caused by fluctuations in various parameters and performance indicators during the process between different wafers. It can effectively shorten measurement time and allow for timely adjustments to process variables. Its implementation helps improve productivity, reduce energy consumption, improve product quality and continuity, and enhance process safety. It also enables process equipment to achieve more stringent process windows, meeting the requirements of continuously shrinking semiconductor process nodes. To address the uniformity issue on a single wafer, different temperature units can be applied to different regions of the wafer to improve uniformity, such as the Hydra function provided by Lam Semiconductor.

[0005] Although existing technologies employ APC technology to control the etching process, they still suffer from low wafer production yield and low reliability. Summary of the Invention

[0006] The technical problem solved by this invention is to provide a method for forming a semiconductor structure, which uses a first advanced process control technology to uniformly control the key dimensions and uniformity of patterns in regions with huge differences in characteristics, thereby improving wafer production yield and reliability.

[0007] To address the aforementioned problems, the present invention provides a method for forming a semiconductor structure, comprising: providing a substrate, the substrate including a base and an etchable layer located on the base, the etchable layer including a first region and a second region, the first region having a plurality of mutually discrete first initial mask structures, the first initial mask structures having a first width dimension, and the second region having a plurality of mutually discrete second mask structures; forming a sacrificial layer on the etchable layer and the second mask structures, the sacrificial layer exposing the first region and the first initial mask structures; etching the first initial mask structures to form a first mask structure, the first mask structure having a second width dimension, the second width dimension being smaller than the first width dimension; forming a protective layer on the sidewalls and top surface of the first mask structure and on the sidewalls and top surface of the second mask structure based on a first advanced process control technology; and etching the etchable layer using the first mask structure, the second mask structure, and the protective layer as masks to form a plurality of patterned structures on the substrate.

[0008] Optionally, the method for forming the first initial mask structure and the second mask structure includes: forming a mask material layer on the layer to be etched; forming a patterned layer on the mask material layer, the patterned layer exposing a portion of the top surface of the mask material layer; etching the mask material layer using the patterned layer as a mask until the top surface of the layer to be etched is exposed, thereby forming the first initial mask structure and the second mask structure.

[0009] Optionally, during the process of etching the mask material layer using the patterned layer as a mask, a first Hydra technique is used to etch the mask material layer located on the first region.

[0010] Optionally, the process of etching the mask material layer using the patterned layer as a mask includes: a dry etching process.

[0011] Optionally, the material of the mask material layer includes silicon oxide or silicon nitride.

[0012] Optionally, the protective layer is also located on the top surface of the layer to be etched.

[0013] Optionally, the protective layer is formed using an atomic layer deposition process.

[0014] Optionally, the material of the protective layer includes silicon oxide.

[0015] Optionally, the etching process for the first initial mask structure includes a dry etching process.

[0016] Optionally, the process of etching the layer to be etched using the first mask structure, the second mask structure, and the protective layer as masks includes: a plasma dry etching process.

[0017] Optionally, during the etching process of the layer to be etched, a second advanced process control technology and a second Hydra technology are used to etch the layer to be etched.

[0018] Optionally, the material of the layer to be etched includes: a semiconductor material; the semiconductor material includes: silicon or silicon germanium.

[0019] Optionally, the graphical structure includes a fin.

[0020] Compared with the prior art, the technical solution of the present invention has the following advantages:

[0021] In the semiconductor structure formation method of this invention, a first initial mask structure is first etched using a conventional etching process to form a first mask structure. After forming the first mask structure, a protective layer is formed on the sidewalls and top surface of the first mask structure, and on the sidewalls and top surface of the second mask structure, based on a first advanced process control technology. This allows the first advanced process control technology to simultaneously compensate for the feature dimensions of both the first and second mask structures, thereby ensuring that the feature dimensions of the second mask structure also conform to a preset feature dimension. This guarantees the accuracy of subsequent pattern transfer, thereby improving wafer production yield and reliability. Attached Figure Description

[0022] Figure 1 and 2 This is a schematic diagram of the steps involved in forming a semiconductor structure.

[0023] Figures 3 to 8 This is a schematic diagram of the steps in the method for forming a semiconductor structure in an embodiment of the present invention. Detailed Implementation

[0024] As described in the background section, although existing technologies employ APC technology to control the etching process, they still suffer from low wafer production yield and low reliability. This will be explained in detail below with reference to the accompanying drawings.

[0025] Please refer to Figure 1A substrate is provided, the substrate including a base 100 and an etchable layer 101 located on the base 100, the etchable layer 101 including a first region I and a second region II; a plurality of mutually discrete first initial mask structures (not shown) are formed on the first region I, and a plurality of mutually discrete second mask structures 102 are formed on the second region II, the first initial mask structures having a first width dimension; a sacrificial layer 103 is formed on the etchable layer 101, the sacrificial layer 103 exposing the first region I; based on advanced process control technology, the first initial mask structures are etched to form a first mask structure 104, the first mask structure 104 having a second width dimension, the second width dimension being smaller than the first width dimension.

[0026] Please refer to Figure 2 A protective layer 105 is formed on the sidewalls and top surface of the first mask structure 104 and on the sidewalls and top surface of the second mask structure 102. After the protective layer 105 is formed, the layer to be etched 101 is etched using the first mask structure 102, the second mask structure 104 and the protective layer 105 as masks, and a plurality of patterned structures 106 are formed on the substrate 100.

[0027] In this embodiment, during the formation of the first initial mask structure and the second mask structure 104, some deviations in feature dimensions occur due to process fluctuations. Because advanced process control technology is used when etching and adjusting the first initial mask structure, the feature dimensions of the formed first mask structure 104 conform to the preset feature dimensions. However, during the etching and adjustment of the first initial mask structure, the second mask structure 102 is covered by the sacrificial layer 103. Therefore, the advanced process control technology cannot compensate for the feature dimensions of the second mask structure 102, resulting in a persistent feature dimension deviation. Subsequent etching of the layer 101 using the second mask structure 102 as a mask also leads to deviations in the feature dimensions of the final formed patterned structure 106, resulting in lower wafer production yield and reliability.

[0028] Based on this, the present invention provides a method for forming a semiconductor structure, employing a first advanced process control technology to form protective layers on the sidewalls and top surfaces of the first mask structure and the second mask structure. This allows the first advanced process control technology to simultaneously compensate for the feature dimensions of both the first and second mask structures, thereby ensuring that the feature dimensions of the second mask structure also conform to a preset feature dimension. This guarantees the accuracy of subsequent patterning transfer, thereby improving wafer production yield and reliability.

[0029] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0030] Figures 3 to 8 This is a schematic diagram of the steps in the method for forming a semiconductor structure in an embodiment of the present invention.

[0031] Please refer to Figure 3 A substrate is provided, the substrate including a base 200 and an etchable layer 201 located on the base 200, the etchable layer 201 including a first region I and a second region II.

[0032] In this embodiment, the substrate 200 is made of silicon. In other embodiments, the substrate may also be made of germanium, silicon germanide, silicon carbide, gallium arsenide, or indium gallium ionide.

[0033] In this embodiment, the material of the layer 201 to be etched is a semiconductor material; the semiconductor material is silicon. In other embodiments, the semiconductor material may also be silicon-germanium.

[0034] In other embodiments, the material of the layer to be etched may also be a metal.

[0035] In this embodiment, the first region I is used to form a plurality of first fins in the future, and the second region II is used to form a plurality of second fins in the future. The first fins have a smaller width in the design requirements and a larger spacing between adjacent first fins, while the second fins have a larger width in the design requirements and a smaller spacing between adjacent second fins.

[0036] Please refer to Figure 4 A plurality of mutually independent first initial mask structures 202 are formed on the first region I, and a plurality of mutually independent second mask structures 203 are formed on the second region II. The first initial mask structures 202 have a first width dimension d1.

[0037] In this embodiment, the method for forming the first initial mask structure 202 and the second mask structure 203 includes: forming a mask material layer (not shown) on the layer to be etched 201; forming a patterned layer (not shown) on the mask material layer, wherein the patterned layer exposes a portion of the top surface of the mask material layer; etching the mask material layer using the patterned layer as a mask until the top surface of the layer to be etched 201 is exposed, thereby forming the first initial mask structure 202 and the second mask structure 203.

[0038] In this embodiment, since the width of the first fin is relatively small, the corresponding mask structure requires more precise dimensions. Therefore, during the etching of the mask material layer using the patterned layer as a mask, the first Hydra technique is employed to etch the mask material layer located on the first region I.

[0039] In this embodiment, the process of etching the mask material layer using the patterned layer as a mask adopts a dry etching process.

[0040] In this embodiment, the mask material layer is made of silicon oxide; in other embodiments, the mask material layer may also be made of silicon nitride.

[0041] Please refer to Figure 5 A sacrificial layer 204 is formed on the layer to be etched 201 and the second mask structure 203, the sacrificial layer 204 exposing the first region I and the first initial mask structure 202.

[0042] It should be noted that, in order to reduce process costs, the first initial mask structure 202 and the second mask structure 203 are formed using the same photomask. However, since the first fin and the second fin have different feature sizes, the feature sizes of the second mask structure 203 and the subsequently formed first mask structure also need to be different. However, due to the limitations of photolithography, the first initial mask structure 202 and the second mask structure 203 formed from a single photomask cannot simultaneously meet the corresponding feature size requirements. Therefore, the first initial mask structure 202 needs to be further adjusted to further reduce the critical dimensions, so that the first mask structure and the second mask structure 203 can meet the corresponding feature size requirements.

[0043] In this embodiment, when adjusting the first initial mask structure 202, in order to avoid affecting the second mask structure 203, the sacrificial layer 204 is used to cover the second mask structure 203.

[0044] In this embodiment, the material of the sacrificial layer 204 is photoresist.

[0045] Please refer to Figure 6 The first initial mask structure 202 is etched to form a first mask structure 205. The first mask structure 205 has a second width dimension d2, which is smaller than the first width dimension d1.

[0046] In this embodiment, the etching process for the first initial mask structure 202 is a dry etching process.

[0047] In this embodiment, the first fin is formed by pattern transfer from the first mask structure 205, and the second fin is formed by pattern transfer from the second mask structure 203. Therefore, the feature size of the first mask structure 205 is consistent with the feature size of the first fin, and the feature size of the second mask structure 203 is consistent with the feature size of the second fin.

[0048] Please refer to Figure 7 Based on the first advanced process control technology, a protective layer 206 is formed on the sidewalls and top surface of the first mask structure 205 and on the sidewalls and top surface of the second mask structure 203.

[0049] In this embodiment, the first initial mask structure 202 is first etched using a conventional etching process to form a first mask structure 205. After forming the first mask structure 205, a protective layer 206 is formed on the sidewalls and top surface of the first mask structure 205 and on the sidewalls and top surface of the second mask structure 203, based on a first advanced process control technology. This allows the first advanced process control technology to simultaneously compensate for the feature dimensions of both the first mask structure 205 and the second mask structure 203, thereby ensuring that the feature dimensions of the second mask structure 203 also conform to a preset feature dimension. This ensures the accuracy of subsequent pattern transfer, thereby improving wafer production yield and reliability.

[0050] In this embodiment, the protective layer 206 serves to reduce the impact of lateral etching on the width dimensions of the first mask structure 205 and the second mask structure 203 during the subsequent patterning process, so as to ensure that the first fin and the second fin formed after patterning are consistent with the preset feature dimensions.

[0051] In this embodiment, the protective layer 206 is also located on the top surface of the layer to be etched 201.

[0052] In this embodiment, the protective layer 206 is formed using atomic layer deposition (ALD).

[0053] In this embodiment, the protective layer 206 is made of silicon oxide.

[0054] It should be noted that although the protective layer 206 is still located on the top surface of the layer to be etched 201, its thickness is very thin. During the subsequent patterning process, the plasma etching process can directly bombard and etch away the protective layer 206 located on the top surface of the layer to be etched 201. Therefore, after the protective layer 206 is formed by atomic layer deposition, no further processing is required even if the protective layer 206 is still located on the top surface of the layer to be etched 201.

[0055] Please refer to Figure 8 After the protective layer 206 is formed, the layer to be etched 201 is etched using the first mask structure 205, the second mask structure 203 and the protective layer 206 as masks, forming a plurality of patterned structures on the substrate 200.

[0056] In this embodiment, the process of etching the layer 201 to be etched using the first mask structure 205, the second mask structure 203, and the protective layer 206 as masks adopts a plasma dry etching process.

[0057] In this embodiment, during the etching process of the layer 201 to be etched, a second advanced process control technology and a second Hydra technology are used to etch the layer 201. The second advanced process control technology and the second Hydra technology can effectively improve the accuracy of pattern transfer, thereby ensuring that the feature size of the patterned structure remains consistent with the preset feature size.

[0058] In this embodiment, the graphical structure is a fin, namely the first fin 207 and the second fin 208.

[0059] In other embodiments, when the material of the layer to be etched is a metal, the patterned structure may also be a conductive layer.

[0060] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A method for forming a semiconductor structure, characterized in that, include: A substrate is provided, the substrate including a base and an etchable layer located on the base, the etchable layer including a first region and a second region, the first region having a plurality of mutually discrete first initial mask structures, the first initial mask structures having a first width dimension, and the second region having a plurality of mutually discrete second mask structures. A sacrificial layer is formed on the layer to be etched and on the second mask structure, the sacrificial layer exposing the first region and the first initial mask structure; The first initial mask structure is etched to form a first mask structure, the first mask structure having a second width dimension, the second width dimension being smaller than the first width dimension; Based on the first advanced process control technology, a protective layer is formed on the sidewall and top surface of the first mask structure and on the sidewall and top surface of the second mask structure; The layer to be etched is etched using the first mask structure, the second mask structure, and the protective layer as masks, forming several patterned structures on the substrate.

2. The method for forming a semiconductor structure as described in claim 1, characterized in that, The method for forming the first initial mask structure and the second mask structure includes: forming a mask material layer on the layer to be etched; forming a patterned layer on the mask material layer, wherein the patterned layer exposes a portion of the top surface of the mask material layer; and etching the mask material layer using the patterned layer as a mask until the top surface of the layer to be etched is exposed, thereby forming the first initial mask structure and the second mask structure.

3. The method for forming a semiconductor structure as described in claim 2, characterized in that, During the etching of the mask material layer using the patterned layer as a mask, the first Hydra technique is used to etch the mask material layer located on the first region.

4. The method for forming a semiconductor structure as described in claim 2, characterized in that, The process of etching the mask material layer using the patterned layer as a mask includes: a dry etching process.

5. The method for forming a semiconductor structure as described in claim 2, characterized in that, The material of the mask material layer includes silicon oxide or silicon nitride.

6. The method for forming a semiconductor structure as described in claim 1, characterized in that, The protective layer is also located on the top surface of the layer to be etched.

7. The method for forming a semiconductor structure as described in claim 6, characterized in that, The process for forming the protective layer includes atomic layer deposition.

8. The method for forming a semiconductor structure as described in claim 1, characterized in that, The material of the protective layer includes silicon oxide.

9. The method for forming a semiconductor structure as described in claim 1, characterized in that, The etching process for the first initial mask structure includes: dry etching process.

10. The method for forming a semiconductor structure as described in claim 1, characterized in that, The process of etching the layer to be etched using the first mask structure, the second mask structure, and the protective layer as masks includes: a plasma dry etching process.

11. The method for forming a semiconductor structure as described in claim 1, characterized in that, During the etching process of the layer to be etched, the second advanced process control technology and the second Hydra technology are used to etch the layer to be etched.

12. The method for forming a semiconductor structure as described in claim 1, characterized in that, The material of the layer to be etched includes: semiconductor material; the semiconductor material includes: silicon or silicon germanium.

13. The method for forming a semiconductor structure as described in claim 12, characterized in that, The graphical structure includes: fins.

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