A COT control circuit, driver chip and electronic equipment

Abstract

The present invention provides a COT control circuit, comprising: a first circuit module, a second circuit module, and a third circuit module connected in sequence; wherein the first circuit module is configured to generate a first control signal based on a received first input signal and a second input signal, and transmit the signal to the second circuit module; the second circuit module is configured to receive a first external input signal, adjust the pulse width of the first external input signal based on the received first control signal, and generate a first processed signal, which is then transmitted to the third circuit module; and the third circuit module is configured to generate a first controlled signal based on the received first processed signal; the first controlled signal is controlled by the first processed signal; and the falling edge of the first controlled signal is related to the pulse width of the first processed signal. The technical solution provided by the present invention solves the problem of how to obtain an output signal with a falling edge controlled.

Description

Technical Field

[0001] The present invention belongs to the technical field of integrated circuits, and in particular relates to a COT control circuit, a driver chip and an electronic device. Background Art

[0002] In power supply systems, COT control has been widely used in DC-DC converters due to its superior transient response. Compared to peak current control and average current control, COT-controlled power supply systems have variable switching frequencies and are difficult to control. In some applications, a VOUT signal with a controlled falling edge is required. To address various issues in the prior art, this application proposes a COT control circuit with a controlled falling edge. Summary of the Invention

[0003] The present invention provides a COT control circuit, a driving chip and an electronic device to solve the problem of how to obtain an output signal with a controlled falling edge.

[0004] According to a first aspect of the present invention, a COT control circuit is provided, comprising: a first circuit module, a second circuit module, and a third circuit module; a first end of the first circuit module is connected to a first end of the second circuit module, a second end of the second circuit module is connected to a first end of the third circuit module, the second end of the first circuit module is used to input a first input signal and a second input signal; and a second end of the third circuit module is used to output a first controlled signal.

[0005] The first circuit module is configured to generate a first control signal according to the received first input signal and the second input signal, and send the first control signal to the second circuit module;

[0006] The second circuit module is configured to receive a first external input signal, adjust a pulse width of the first external input signal according to the received first control signal, generate a first processed signal, and send the first processed signal to the third circuit module;

[0007] The third circuit module is used to generate a first controlled signal according to the received first processing signal; the first controlled signal is controlled by the first processing signal; wherein the falling edge of the first controlled signal is related to the pulse width of the first processing signal.

[0008] Optionally, the first circuit module includes: a first operational amplifier unit, a first inverting unit, a first delay unit and a first NAND gate unit;

[0009] The first input terminal and the second input terminal of the first operational amplifier unit are respectively used to input the first input signal and the second input signal; the output terminal of the first operational amplifier unit is connected to the first terminal of the first inverting unit and the first terminal of the first delay unit; and is used to generate a first COT_INPUT signal according to the first input signal and the second input signal; and send the first COT_INPUT signal to the first inverting unit and the first delay unit respectively;

[0010] The second end of the first inverting unit is connected to the first input end of the first NAND gate unit; the first inverting unit is used to obtain a first inverted pulse signal according to the received first COT_INPUT signal, and output the first pulse inverted signal to the first NAND gate unit;

[0011] The second end of the first delay unit is connected to the second input end of the first NAND gate unit; the first delay unit is used to generate a first delayed pulse signal according to the received first COT_INPUT signal, and send the first delayed pulse signal to the first NAND gate unit;

[0012] The first NAND gate unit is used to generate a first control signal according to the received first inverted pulse signal and the first delayed pulse signal; the output end of the first NAND gate unit is used to output the first control signal to the second circuit module.

[0013] Optionally, the second circuit module includes: a first NOT gate unit, a second delay unit, and a first DFFR unit;

[0014] The first NOT gate unit; the first input end of the first NOT gate unit is used to receive the first VIN_PLUSE input signal; the second input end of the first NOT gate unit is connected to the output end of the first NAND gate unit, for receiving the first control signal; the first NOT gate unit is used to generate a first voltage signal according to the received first VIN_PLUSE input signal and the first control signal; the output end of the first NOT gate unit is connected to the first input end of the first DFFR unit, and the output end of the first NOT gate unit is used to output the first voltage signal to the first DFFR unit;

[0015] The first end of the second delay unit is used to receive the first VIN_PLUSE input signal; the second delay unit is used to generate a second voltage signal according to the first VIN_PLUSE input signal; the second end of the second delay unit is connected to the second input end of the first DFFR unit; the second end of the second delay unit is used to output the second voltage signal to the first DFFR unit;

[0016] The first DFFR unit is used to generate a first processing signal according to the received first voltage signal and the second voltage signal; the output end of the first DFFR unit is used to output the first processing signal to the third circuit module;

[0017] The rising edge of the first processing signal is controlled by the second voltage signal; and the falling edge of the first processing signal is controlled by the first voltage signal.

[0018] Optionally, the third circuit module includes: a second NOT gate unit and a first control unit;

[0019] The first input end of the second NOT gate unit is connected to the output end of the first DFFR unit,

[0020] The first end of the first control unit is connected to the output end of the first DFFR unit; the second end of the first control unit is connected to the second input end of the second NOT gate unit; the first control unit receives the first processing signal through the first end of the first control unit, generates a second control signal based on the received first processing signal, and sends the second control signal to the second NOT gate unit;

[0021] The second NOT gate unit is used to generate the first controlled signal according to the received first processing signal and the second control signal, and output the first controlled signal through the output end of the second NOT gate unit;

[0022] The first control unit is configured to generate a second control signal according to the received first processed signal, specifically comprising:

[0023] A first VN signal is generated according to the first processing signal, and a first VP signal is received; the second control signal is generated according to the first VP signal and the first VN signal; wherein, when the first VN signal is greater than the first VP signal, the rising edge of the first controlled signal is adapted to the rising edge of the first processing signal, and the falling edge of the first controlled signal is adapted to the falling edge of the second control signal; when the first VP signal is greater than the first VN signal, the rising edge of the first controlled signal is adapted to the rising edge of the first processing signal; and the falling edge of the first controlled signal is controlled by the falling edge of the first processing signal.

[0024] Optionally, the first control unit specifically includes: a first control subunit and a second control subunit;

[0025] The first end of the first control subunit is connected to the output end of the first DFFR unit; the second end of the first control subunit is connected to the first input end of the second control subunit; the first control subunit is used to generate a first VN signal according to the received first processed signal, and send the first VN signal to the second control subunit;

[0026] The second input end of the second control subunit is used to input the first VP signal; the output end of the second control subunit is connected to the second input end of the second NOT gate unit; the second control subunit is used to generate a second control signal according to the first VN signal and the first VP signal, and send the second control signal to the second NOT gate unit through the output end of the second control subunit.

[0027] Optionally, the first control unit includes: a first operational amplifier, a first bia-current-ref device, a first inverter, a second inverter, a first resistor, a second resistor, a third resistor, a first transistor, and a first capacitor;

[0028] The first end of the first inverter is connected to the output end of the first DFFR unit; the second end of the first inverter is connected to the gate of the first transistor and the first end of the second inverter; the drain of the first transistor is connected to the first end of the third resistor;

[0029] The first end of the first resistor is connected to the first end of the first bia-current-ref device; the first end of the second resistor is connected to the first end of the first bia-current-ref device; the first end of the first resistor is connected to the first end of the second resistor;

[0030] The second end of the first bia-current-ref device is connected to the first input end of the second control subunit and the second end of the third resistor;

[0031] The first end of the first capacitor is connected between the second end of the third resistor and the first input end of the second control subunit.

[0032] Optionally, the second control unit includes: a second operational amplifier and a fourth resistor;

[0033] The first end of the fourth resistor is connected to the second input end of the second operational amplifier; the second end of the fourth resistor is connected to the output end of the second operational amplifier; the first input end of the second operational amplifier is used to receive the first VN signal; the second control signal generated by the second control unit is sent to the second NOT gate unit through the output end of the second operational amplifier.

[0034] Optionally, the first NOT gate unit is a NOT gate circuit, the second delay unit is a delay circuit, and the first DFFR unit is a DFFR circuit; the first operational amplifier unit is an operational amplifier, the first inverting unit is an inverter, the first delay unit is a delay circuit, and the first NAND gate unit is a NAND gate circuit.

[0035] According to a second aspect of the present invention, a driver chip is provided, comprising the COT control circuit according to any one of the first aspects of the present invention.

[0036] According to a third aspect of the present invention, an electronic device is provided, comprising the driver chip according to the second aspect of the present invention.

[0037] The present invention provides a COT control circuit, which is cleverly designed by combining a first circuit module, a second circuit module, and a third circuit module; the first circuit module generates a first control signal based on the first input signal and the second input signal received; the second circuit module receives a first external input signal, adjusts the pulse width of the first external input signal based on the received first control signal, and generates a first processed signal; the third circuit module generates a first controlled signal based on the received first processed signal; the first controlled signal is controlled by the first processed signal; wherein the falling edge of the first controlled signal is related to the pulse width of the first processed signal; thus, using the technical solution provided by the present invention, a first controlled signal with a controlled falling edge can be obtained. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] Figure 1 A schematic diagram of a module of a COT control circuit provided in one embodiment of the present invention;

[0039] Figure 2 A schematic structural diagram of a first circuit module of a COT control circuit provided in one embodiment of the present invention;

[0040] Figure 3 A schematic structural diagram of a second circuit module of a COT control circuit provided in one embodiment of the present invention;

[0041] Figure 4 A schematic structural diagram of a third circuit module of a COT control circuit provided in one embodiment of the present invention;

[0042] Figure 5 A pulse signal waveform diagram of a first circuit module provided in one embodiment of the present invention;

[0043] Figure 6 A pulse signal waveform diagram of a second circuit module provided in one embodiment of the present invention;

[0044] Figure 7A pulse signal waveform diagram of the second circuit module after the period of the first control signal is adjusted according to an embodiment of the present invention;

[0045] Figure 8 A pulse signal waveform diagram of the third circuit module when the first VN signal is greater than the first VP signal provided in one embodiment of the present invention;

[0046] Figure 9 A pulse signal waveform diagram of the third circuit module when the first VP signal is greater than the first VN signal provided in one embodiment of the present invention;

[0047] Figure 10 The pulse signal waveform of the COT control circuit provided by one embodiment of the present invention Figure 1 ;

[0048] Figure 11 The pulse signal waveform of the COT control circuit provided by one embodiment of the present invention Figure 2 ;

[0049] Description of reference numerals:

[0050] 101-first circuit module;

[0051] 102-second circuit module;

[0052] 103-third circuit module;

[0053] 1031-second NOT gate unit;

[0054] 1032 - first control unit;

[0055] 10321-first control subunit;

[0056] 10322-second control subunit;

[0057] R1-first resistor;

[0058] R2-second resistor;

[0059] R3-the third resistor;

[0060] R4-fourth resistor;

[0061] M1 - first transistor. DETAILED DESCRIPTION

[0062] The COT control circuit of the present invention will be described in more detail below with reference to a schematic diagram, which illustrates a preferred embodiment of the present invention. It should be understood that those skilled in the art may modify the present invention as described herein while still achieving the advantageous effects of the present invention. Therefore, the following description should be understood as a general guideline for those skilled in the art and not as a limitation of the present invention.

[0063] The present invention is described in more detail in the following paragraphs by way of example with reference to the accompanying drawings. The advantages and features of the present invention will become more apparent from the following description and claims. It should be noted that the drawings are greatly simplified and not to exact scale, and are provided solely for the purpose of assisting in the description of the embodiments of the present invention.

[0064] Please refer to Figures 1-11 According to an embodiment of the present invention, a COT control circuit is provided, comprising: a first circuit module, a second circuit module, and a third circuit module; a first end of the first circuit module is connected to a first end of the second circuit module, a second end of the second circuit module is connected to a first end of the third circuit module, the second end of the first circuit module is used to input a first input signal and a second input signal; and a second end of the third circuit module is used to output a first controlled signal;

[0065] The first circuit module is configured to generate a first control signal according to the received first input signal and the second input signal, and send the first control signal to the second circuit module;

[0066] The second circuit module is configured to receive a first external input signal, adjust a pulse width of the first external input signal according to the received first control signal, generate a first processed signal, and send the first processed signal to the third circuit module;

[0067] The third circuit module is configured to generate a first controlled signal according to the received first processed signal; the first controlled signal is controlled by the first processed signal; wherein the falling edge of the first controlled signal is related to the pulse width of the first processed signal, such as Figure 1 shown.

[0068] The present invention provides a COT control circuit, which includes a first circuit module for generating a first control signal based on the received first input signal and the second input signal; a second circuit module for receiving a first external input signal, adjusting the pulse width of the first external input signal based on the received first control signal, and generating a first processed signal; and a third circuit module for generating a first controlled signal based on the received first processed signal; the first controlled signal is controlled by the first processed signal; wherein the falling edge of the first controlled signal is related to the pulse width of the first processed signal; thereby, using the technical solution provided by the present invention, a first controlled signal with a controlled falling edge can be obtained.

[0069] In one embodiment, the first circuit module includes: a first operational amplifier unit, a first inverting unit, a first delay unit, and a first NAND gate unit;

[0070] The first input terminal and the second input terminal of the first operational amplifier unit are respectively used to input the first input signal and the second input signal; the output terminal of the first operational amplifier unit is connected to the first terminal of the first inverting unit and the first terminal of the first delay unit; and is used to generate a first COT_INPUT signal according to the first input signal and the second input signal; and send the first COT_INPUT signal to the first inverting unit and the first delay unit respectively;

[0071] The second end of the first inverting unit is connected to the first input end of the first NAND gate unit; the first inverting unit is used to obtain a first inverted pulse signal according to the received first COT_INPUT signal, and output the first pulse inverted signal to the first NAND gate unit;

[0072] The second end of the first delay unit is connected to the second input end of the first NAND gate unit; the first delay unit is used to generate a first delayed pulse signal according to the received first COT_INPUT signal, and send the first delayed pulse signal to the first NAND gate unit;

[0073] The first NAND gate unit is used to generate a first control signal according to the received first inverted pulse signal and the first delayed pulse signal; the output end of the first NAND gate unit is used to output the first control signal to the second circuit module. In a specific embodiment, the specific structure of the first circuit module is as follows Figure 2 shown.

[0074] In a specific embodiment, the first operational amplifier unit is an operational amplifier, the first inverting unit is an inverter, the first delay unit is a delay circuit, and the first NAND gate unit is a NAND gate circuit.

[0075] Among them, the first circuit module is used to input VSIN_REF (first input signal) and VSIN (second input signal) to generate and output COT_CONTROLL signal (first control signal); wherein, COT_CONTROLL signal is a high-low-high low pulse narrow signal used to control the lower-level circuit.

[0076] The input signals VSIN and VSIN_REF pass through folded_cascode_compa_1 (operational amplifier) ​​to generate the first COT_INPUT signal. The first COT_INPUT signal is inverted (inverter) to obtain net043 (first inverted pulse signal). The first COT_INPUT signal passes through the first delay unit to obtain net069 (first delayed pulse signal). Net043 (first inverted pulse signal) and net069 (first delayed pulse signal) pass through the NAND gate circuit to obtain COT_CONTROLL (narrow pulse signal-first control signal). The pulse signal diagram is as follows: Figure 5 shown.

[0077] In one embodiment, the second circuit module includes: a first NOT gate unit, a second delay unit, and a first DFFR unit;

[0078] The first NOT gate unit; the first input end of the first NOT gate unit is used to receive the first VIN_PLUSE input signal; the second input end of the first NOT gate unit is connected to the output end of the first NAND gate unit, for receiving the first control signal; the first NOT gate unit is used to generate a first voltage signal according to the received first VIN_PLUSE input signal and the first control signal; the output end of the first NOT gate unit is connected to the first input end of the first DFFR unit, and the output end of the first NOT gate unit is used to output the first voltage signal to the first DFFR unit;

[0079] The first end of the second delay unit is used to receive the first VIN_PLUSE input signal; the second delay unit is used to generate a second voltage signal according to the first VIN_PLUSE input signal; the second end of the second delay unit is connected to the second input end of the first DFFR unit; the second end of the second delay unit is used to output the second voltage signal to the first DFFR unit;

[0080] The first DFFR unit is used to generate a first processing signal according to the received first voltage signal and the second voltage signal; the output end of the first DFFR unit is used to output the first processing signal to the third circuit module;

[0081] Wherein, the rising edge of the first processing signal is controlled by the second voltage signal; the falling edge of the first processing signal is controlled by the first voltage signal. In a specific embodiment, the structure of the second circuit module is as follows: Figure 3 shown.

[0082] In a specific embodiment, the first NOT gate unit is a NOT gate circuit, the second delay unit is a delay circuit, and the first DFFR unit is a DFFR circuit.

[0083] The second circuit module uses the COT_CONTROLL signal to adjust the pulse width of the external input VIN_PULSE (1:1). COT_CONTROLL is a (high-low-high) low-level narrow pulse signal, and the low-level narrow pulse is inside the high-level pulse of VIN_PULSE.

[0084] Specifically, COT_CONTROLL and the input signal VIN_PLUSE (first VIN_PLUSE input signal) are used to obtain V2 (first voltage signal), VIN_PLUSE is delayed to obtain V1 (second voltage signal), and V1 and V2 are passed through the DFFR circuit to obtain VIN_PLUSE_INPUT (first processed signal); wherein, the rising edge of VIN_PLUSE_INPUT is controlled by V1, and the falling edge is controlled by V2; the pulse signal diagram is shown in FIG. Figure 6 As shown; modify the pulse period of COT_CONTROLL to obtain the pulse signal as shown in the figure Figure 7 shown.

[0085] In one embodiment, the third circuit module includes: a second NOT gate unit and a first control unit; the first input end of the second NOT gate unit is connected to the output end of the first DFFR unit,

[0086] The first end of the first control unit is connected to the output end of the first DFFR unit; the second end of the first control unit is connected to the second input end of the second NOT gate unit; the first control unit receives the first processing signal through the first end of the first control unit, generates a second control signal based on the received first processing signal, and sends the second control signal to the second NOT gate unit;

[0087] The second NOT gate unit is used to generate the first controlled signal according to the received first processing signal and the second control signal, and output the first controlled signal through the output end of the second NOT gate unit;

[0088] The first control unit is configured to generate a second control signal according to the received first processed signal, specifically comprising:

[0089] A first VN signal is generated according to the first processing signal, and a first VP signal is received; the second control signal is generated according to the first VP signal and the first VN signal; wherein, when the first VN signal is greater than the first VP signal, the rising edge of the first controlled signal is adapted to the rising edge of the first processing signal, and the falling edge of the first controlled signal is adapted to the falling edge of the second control signal; when the first VP signal is greater than the first VN signal, the rising edge of the first controlled signal is adapted to the rising edge of the first processing signal; the falling edge of the first controlled signal is controlled by the falling edge of the first processing signal. In a specific embodiment, the specific structure of the third circuit module is as follows Figure 4 shown.

[0090] The third circuit module is configured to receive the input signal VIN_PULSE_INPUT and output the signal VOUT (a first controlled signal), wherein the falling edge of VOUT is controlled. VIN_PLUSE_INPUT and A control (a second control signal) ultimately output VOUT. When the pulse width of VIN_PLUSE_INPUT is sufficiently wide (the first VN signal is greater than the first VP signal), the rising edge of VOUT is controlled by VIN_PLUSE_INPUT, while the falling edge is controlled by the falling edge of A control. When the pulse width of VIN_PLUSE_INPUT is relatively short (the first VN signal is less than the first VP signal), the rising edge of VOUT is controlled by VIN_PLUSE_INPUT, while the falling edge is controlled by the falling edge of VIN_PLUSE_INPUT. This means that the rising edge of the output signal VOUT coincides with the rising edge of the input signal VIN_PULSE_INPUT. The falling edge of the output signal VOUT is related to the pulse width of VIN_PULSE_INPUT.

[0091] When the pulse width of VIN_PULSE_INPUT is wide enough (wide enough to allow the charging voltage VN to exceed VP, A can obtain a high-low-high pulse signal), the falling edge of A controls the falling edge of VOUT.

[0092] Charge and discharge: Charging starts at the rising edge of VIN_PULSE_INPUT, and discharging starts at the falling edge.

[0093] When the pulse width of VIN_PULSE_INPUT is not wide enough (the charging voltage VN cannot be higher than VP, A is always high), A does not control VOUT, and the falling edge of VOUT is consistent with VIN_PULSE_INPUT. The input signal of VIN_PULSE_INPUT is as follows: Figure 9 shown.

[0094] In one embodiment, the first control unit specifically includes: a first control subunit and a second control subunit; a first end of the first control subunit is connected to an output end of the first DFFR unit; a second end of the first control subunit is connected to a first input end of the second control subunit; the first control subunit is configured to generate a first VN signal based on the received first processed signal and send the first VN signal to the second control subunit;

[0095] The second input end of the second control subunit is used to input the first VP signal; the output end of the second control subunit is connected to the second input end of the second NOT gate unit; the second control subunit is used to generate a second control signal according to the first VN signal and the first VP signal, and send the second control signal to the second NOT gate unit through the output end of the second control subunit.

[0096] In one embodiment, the first control unit includes: a first operational amplifier, a first bia-current-ref device, a first inverter, a second inverter, a first resistor, a second resistor, a third resistor, a first transistor, and a first capacitor;

[0097] The first end of the first inverter is connected to the output end of the first DFFR unit; the second end of the first inverter is connected to the gate of the first transistor and the first end of the second inverter; the drain of the first transistor is connected to the first end of the third resistor;

[0098] The first end of the first resistor is connected to the first end of the first bia-current-ref device; the first end of the second resistor is connected to the first end of the first bia-current-ref device; the first end of the first resistor is connected to the first end of the second resistor;

[0099] The second end of the first bia-current-ref device is connected to the first input end of the second control subunit and the second end of the third resistor;

[0100] The first end of the first capacitor is connected between the second end of the third resistor and the first input end of the second control subunit.

[0101] In one embodiment, the second control unit includes: a second operational amplifier and a fourth resistor;

[0102] The first end of the fourth resistor is connected to the second input end of the second operational amplifier; the second end of the fourth resistor is connected to the output end of the second operational amplifier; the first input end of the second operational amplifier is used to receive the first VN signal; the second control signal generated by the second control unit is sent to the second NOT gate unit through the output end of the second operational amplifier.

[0103] The input signal of VIN_PULSE_INPUT is as follows Figure 8 As shown: wherein net063 represents the output signal of the first bia-current-ref device; net026 represents the input signal of the second inverter;

[0104] The overall circuit simulation conclusion and waveform diagram of a COT control circuit provided by the present invention are as follows: Figure 10-11 As shown, Figure 11 The pulse signal net072 in FIG represents the output signal of the second inverter;

[0105] To summarize: 1) First circuit module: input signals VSIN and VSIN_REF obtain COT_CONTROLL (narrow pulse signal); 2) Second circuit module: COT_CONTROLL and input signal VIN_PLUSE obtain VIN_PLUSE_INPUT; 3) Third circuit module: VIN_PLUSE_INPUT and A control the final output VOUT.

[0106] Secondly, according to an embodiment of the present invention, a driver chip is further provided, comprising the COT control circuit according to any one of the aforementioned embodiments of the present invention.

[0107] In addition, according to an embodiment of the present invention, an electronic device is provided, comprising the driver chip described in the foregoing embodiment of the present invention.

[0108] According to an embodiment of the present invention, a driver chip is further provided, comprising the COT control circuit according to any one of the aforementioned embodiments of the present invention.

[0109] According to another embodiment of the present invention, an electronic device is provided, comprising the driver chip described in the foregoing embodiment of the present invention.

[0110] Obviously, those skilled in the art may make various changes and modifications to the present invention without departing from the spirit and scope of the present invention. Thus, if such changes and modifications fall within the scope of the claims and their equivalents, the present invention is intended to include such changes and modifications.

Claims

1. A COT control circuit, characterized in that: include: a first circuit module, a second circuit module, and a third circuit module; wherein the first end of the first circuit module is connected to the first end of the second circuit module, the second end of the second circuit module is connected to the first end of the third circuit module, the second end of the first circuit module is used to input a first input signal and a second input signal; and the second end of the third circuit module is used to output a first controlled signal. the first circuit module; Used to generate a first control signal according to the received first input signal and the second input signal, and send the first control signal to the second circuit module; the second circuit module; for receiving a first external input signal, adjusting a pulse width of the first external input signal according to the received first control signal, generating a first processed signal, and sending the first processed signal to the third circuit module; the third circuit module; for generating a first controlled signal according to the received first processed signal; the first controlled signal is controlled by the first processed signal; wherein the falling edge of the first controlled signal is related to the pulse width of the first processed signal, The first circuit module includes: a first operational amplifier unit, a first inverting unit, a first delay unit and a first NAND gate unit; The first input terminal and the second input terminal of the first operational amplifier unit are respectively used to input the first input signal and the second input signal; the output terminal of the first operational amplifier unit is connected to the first terminal of the first inverting unit and the first terminal of the first delay unit; and is used to generate a first COT_INPUT signal according to the first input signal and the second input signal; and send the first COT_INPUT signal to the first inverting unit and the first delay unit respectively; The second end of the first inverting unit is connected to the first input end of the first NAND gate unit; the first inverting unit is used to obtain a first inverted pulse signal according to the received first COT_INPUT signal, and output the first inverted pulse signal to the first NAND gate unit; The second end of the first delay unit is connected to the second input end of the first NAND gate unit; the first delay unit is used to generate a first delayed pulse signal according to the received first COT_INPUT signal, and send the first delayed pulse signal to the first NAND gate unit; The first NAND gate unit is used to generate a first control signal according to the received first inverted pulse signal and the first delayed pulse signal; the output end of the first NAND gate unit is used to output the first control signal to the second circuit module, The second circuit module includes: a first NOT gate unit, a second delay unit, and a first DFFR unit; The first NOT gate unit; the first input end of the first NOT gate unit is used to receive the first VIN_PLUSE input signal; the second input end of the first NOT gate unit is connected to the output end of the first NAND gate unit, for receiving the first control signal; the first NOT gate unit is used to generate a first voltage signal according to the received first VIN_PLUSE input signal and the first control signal; the output end of the first NOT gate unit is connected to the first input end of the first DFFR unit, and the output end of the first NOT gate unit is used to output the first voltage signal to the first DFFR unit; The first end of the second delay unit is used to receive the first VIN_PLUSE input signal; the second delay unit is used to generate a second voltage signal according to the first VIN_PLUSE input signal; the second end of the second delay unit is connected to the second input end of the first DFFR unit; the second end of the second delay unit is used to output the second voltage signal to the first DFFR unit; The first DFFR unit is used to generate a first processing signal according to the received first voltage signal and the second voltage signal; the output end of the first DFFR unit is used to output the first processing signal to the third circuit module; The rising edge of the first processing signal is controlled by the second voltage signal; the falling edge of the first processing signal is controlled by the first voltage signal. The third circuit module includes: a second NOT gate unit and a first control unit; the first input end of the second NOT gate unit is connected to the output end of the first DFFR unit, and the first end of the first control unit is connected to the output end of the first DFFR unit; the second end of the first control unit is connected to the second input end of the second NOT gate unit; the first control unit receives the first processing signal through the first end of the first control unit, generates a second control signal based on the received first processing signal, and sends the second control signal to the second NOT gate unit; The second NOT gate unit is used to generate the first controlled signal according to the received first processing signal and the second control signal, and output the first controlled signal through the output end of the second NOT gate unit; The first control unit is configured to generate a second control signal according to the received first processed signal, specifically comprising: A first VN signal is generated according to the first processing signal, and a first VP signal is received; the second control signal is generated according to the first VP signal and the first VN signal; wherein, when the first VN signal is greater than the first VP signal, the rising edge of the first controlled signal is adapted to the rising edge of the first processing signal, and the falling edge of the first controlled signal is adapted to the falling edge of the second control signal; when the first VP signal is greater than the first VN signal, the rising edge of the first controlled signal is adapted to the rising edge of the first processing signal; and the falling edge of the first controlled signal is controlled by the falling edge of the first processing signal. The first control signal is a low-level pulse signal, and the width of the low-level pulse is smaller than the width of the high-level pulse of the first external input signal.

2. The COT control circuit according to claim 1, wherein: The first control unit specifically includes: a first control subunit and a second control subunit; a first end of the first control subunit is connected to the output end of the first DFFR unit; a second end of the first control subunit is connected to the first input end of the second control subunit; the first control subunit is configured to generate a first VN signal according to the received first processed signal, and send the first VN signal to the second control subunit; The second input end of the second control subunit is used to input the first VP signal; the output end of the second control subunit is connected to the second input end of the second NOT gate unit; the second control subunit is used to generate a second control signal according to the first VN signal and the first VP signal, and send the second control signal to the second NOT gate unit through the output end of the second control subunit.

3. The COT control circuit according to claim 2, wherein: The first control unit includes: a first operational amplifier, a first bia-current-ref device, a first inverter, a second inverter, a first resistor, a second resistor, a third resistor, a first transistor and a first capacitor; The first end of the first inverter is connected to the output end of the first DFFR unit; the second end of the first inverter is connected to the gate of the first transistor and the first end of the second inverter; the drain of the first transistor is connected to the first end of the third resistor; The first end of the first resistor is connected to the first end of the first bia-current-ref device; the first end of the second resistor is connected to the first end of the first bia-current-ref device; the first end of the first resistor is connected to the first end of the second resistor; The second end of the first bia-current-ref device is connected to the first input end of the second control subunit and the second end of the third resistor; The first end of the first capacitor is connected between the second end of the third resistor and the first input end of the second control subunit.

4. The COT control circuit according to claim 3, wherein: The second control unit includes: a second operational amplifier and a fourth resistor; The first end of the fourth resistor is connected to the second input end of the second operational amplifier; the second end of the fourth resistor is connected to the output end of the second operational amplifier; the first input end of the second operational amplifier is used to receive the first VN signal; the second control signal generated by the second control unit is sent to the second NOT gate unit through the output end of the second operational amplifier.

5. The COT control circuit according to claim 4, wherein: The first NOT gate unit is a NOT gate circuit, the second delay unit is a delay circuit, and the first DFFR unit is a DFFR circuit; the first operational amplifier unit is an operational amplifier, the first inverting unit is an inverter, the first delay unit is a delay circuit, and the first NAND gate unit is a NAND gate circuit.

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