A bidirectional level shifter with automatic detection of transmission direction

Abstract

The application discloses a kind of automatic detection transmission direction's bidirectional level conversion device, it is related to integrated circuit field, comprising: input detection and output control circuit, first P-type MOSFET, first N-type MOSFET, first resistance, second P-type MOSFET, second N-type MOSFET, second resistance, the two input signal ports of input detection and output control circuit are electrically connected with first input / output port P1, second input / output port P2 respectively.The application simultaneously detects the signal change of two input / output ports, generates the signal required to control input / output port, to achieve the function of automatic control transmission direction;By long on switch pull-down output, or short on switch pull-up output to corresponding power supply and parallel pull-up resistance, realize level conversion function, facilitate system design, improve the integration of system, reduce cost.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of integrated circuit technology, more particularly to an apparatus for interfacing between devices operating at two different voltage domains, and also between two devices operating at the same voltage domain, providing stronger driving capability. BACKGROUND

[0002] In system applications, level conversion circuits are often needed to complete the conversion of different logic levels. For example, the logic high level of FPGA is 1.2V, while the logic high level of the controlled device can be 1.8V, 3.3V or 5V. Some logic signals have a fixed direction during transmission, such as clock signals, reset signals, etc., which are usually transmitted from master to slave. However, the transmission direction of some logic signals is not fixed, and the direction of the logic signal transmission needs to be switched during transmission, such as data signals which need to be transmitted from master to slave at some time and from slave to master at some other time.

[0003] Therefore, how to realize bidirectional level conversion, automatically switch the signal transmission direction, improve system integration and reduce cost is a technical problem that needs to be solved by those skilled in the art. SUMMARY

[0004] Therefore, the present application provides a bidirectional level conversion apparatus capable of automatically detecting the transmission direction, which can realize bidirectional level conversion, automatically switch the signal transmission direction, facilitate system design, improve system integration and reduce cost.

[0005] To achieve the above object, the present application provides the following technical scheme:

[0006] The bidirectional level conversion apparatus capable of automatically detecting the transmission direction comprises an input detection and output control circuit, a first P-type MOSFET, a first N-type MOSFET, a first resistor, a second P-type MOSFET, a second N-type MOSFET and a second resistor.

[0007] The two input signal ports of the input detection and output control circuit are electrically connected with a first input / output port P1 and a second input / output port P2 respectively, and a first output signal A1, a second output signal A2, a third output signal B1 and a fourth output signal B2 are electrically connected with the gate of the first P-type MOSFET, the gate of the first N-type MOSFET, the gate of the second P-type MOSFET and the gate of the second N-type MOSFET respectively.

[0008] The source end of the first P-type MOSFET and one end of the first resistor are connected with VCC1 respectively, the drain end of the first P-type MOSFET, the other end of the first resistor and the drain end of the first N-type MOSFET are connected with the first input / output port P1 respectively, and the source end of the first N-type MOSFET is grounded.

[0009] The source end of the second P-type MOSFET and one end of the second resistor are connected with VCC2 respectively, the drain end of the second P-type MOSFET, the other end of the second resistor and the drain end of the second N-type MOSFET are connected with the second input / output port P2 respectively, and the source end of the second N-type MOSFET is grounded. When the first input / output port P1 and the second input / output port P2 have no driving source to pull up and pull down, the first P-type MOSFET, the first N-type MOSFET, the second P-type MOSFET and the second N-type MOSFET are all disconnected, at this time, the first input / output port P1 is pulled up to the logic high level VCC1 through the first resistor, and the second input / output port P2 is pulled up to the logic high level VCC2 through the second resistor.

[0010] Optionally, the input detection and output control circuit comprises a level conversion circuit, a first one-shot circuit, a second one-shot circuit, a first two-input NOR gate, a second two-input NOR gate, a first three-input AND gate and a second three-input AND gate.

[0011] The first input / output port P1 is connected with the input end of the level conversion circuit, and the signal B3 output by the level conversion circuit is connected with one input end of the first one-shot circuit and the first two-input NOR gate respectively, and the second output signal A2 is connected with the other input end of the first two-input NOR gate; the output of the first one-shot circuit is the third output signal B1, which is used to control the second P-type MOSFET; the third output signal B1, the output signal B4 of the first two-input NOR gate and the first output signal A1 are connected with the input ends of the first three-input AND gate respectively, and the output of the first three-input AND gate is the fourth output signal B2, which is used to control the second N-type MOSFET;

[0012] The second input / output port P2 is connected with the second single trigger circuit and one input terminal of the second two-input NOR gate respectively, and the fourth output signal B2 is connected with the other input terminal of the second two-input NOR gate; the output of the second single trigger circuit is the first output signal A1, which controls the first P-type MOSFET through the first output signal A1; the third output signal B1, the first output signal A1 and the output signal A4 of the second two-input NOR gate are connected with the input terminals of the second three-input AND gate respectively, and the output of the second three-input AND gate is the second output signal A2, which controls the first N-type MOSFET through the second output signal A2.

[0013] Optionally, the level conversion circuit comprises: a third P-type MOSFET, a third N-type MOSFET, a fourth P-type MOSFET, a fourth N-type MOSFET, a fifth P-type MOSFET and a fifth N-type MOSFET.

[0014] The input signal IN1 is connected with the gate terminal of the third P-type MOSFET, the gate terminal of the third N-type MOSFET and the gate terminal of the fifth N-type MOSFET respectively, the source terminal of the third P-type MOSFET is connected with VCC1, the source terminal of the fourth P-type MOSFET and the source terminal of the fifth P-type MOSFET are connected with VCC2 respectively; the source terminal of the third N-type MOSFET, the source terminal of the fourth N-type MOSFET and the source terminal of the fifth N-type MOSFET are connected with the ground respectively; the drain terminal of the third P-type MOSFET, the drain terminal of the third N-type MOSFET and the gate terminal of the fourth N-type MOSFET are connected with each other in pairs; the gate terminal of the fourth P-type MOSFET, the drain terminal of the fifth P-type MOSFET and the drain terminal of the fifth N-type MOSFET are connected with each other in pairs.

[0015] The drain terminal of the fourth P-type MOSFET, the drain terminal of the fourth N-type MOSFET and the gate terminal of the fifth P-type MOSFET are connected with each other in pairs and connected with the output signal OUT1; the circuit can complete the level conversion from the input signal IN1 to the output signal OUT1, and the logic high level of the input signal IN1 is VCC1 and the logic high level of the output signal OUT1 is VCC2.

[0016] Optionally, the structure of the first and second one-shot circuits comprises a sixth P-type MOSFET, a third resistor, a sixth N-type MOSFET, a capacitor, and a two-input NAND gate.

[0017] The input signal IN2 is connected to the gate of the sixth P-type MOSFET, the gate of the sixth N-type MOSFET, and one input of the two-input NAND gate, respectively. The drain of the sixth P-type MOSFET, one end of the third resistor, one end of the capacitor, and the other input of the two-input NAND gate are connected to each other. The output signal OUT2 of the two-input NAND gate generates a short low pulse when the input signal IN2 is high, and is high in other cases.

[0018] The source of the sixth P-type MOSFET is connected to VCC, and the drain of the sixth N-type MOSFET is connected to the other end of the third resistor. The source of the sixth N-type MOSFET and the other end of the capacitor are both connected to ground.

[0019] Optionally, the structure of the first and second two-input NOR gates comprises a seventh P-type MOSFET, an eighth P-type MOSFET, a seventh N-type MOSFET, and an eighth N-type MOSFET.

[0020] The input signal IN3 is connected to the gate of the eighth P-type MOSFET and the gate of the eighth N-type MOSFET, and the input signal IN4 is connected to the gate of the seventh P-type MOSFET and the gate of the seventh N-type MOSFET. The drain of the seventh P-type MOSFET is connected to the source of the eighth P-type MOSFET. The drain of the eighth P-type MOSFET, the drain of the seventh N-type MOSFET, and the drain of the eighth N-type MOSFET are connected to each other, and are all connected to the output signal OUT3.

[0021] The source of the seventh P-type MOSFET is connected to VCC, and the source of the seventh N-type MOSFET and the source of the eighth N-type MOSFET are both connected to ground. The output signal OUT3 is high when the input signals IN3 and IN4 are both low, and is low in other cases.

[0022] Optionally, the two-input NAND gate comprises: a ninth P-type MOSFET, a tenth P-type MOSFET, a ninth N-type MOSFET, and a tenth N-type MOSFET.

[0023] The input signal IN5 is connected to the gate of the tenth P-type MOSFET and the gate of the ninth N-type MOSFET, and the input signal IN6 is connected to the gate of the ninth P-type MOSFET and the gate of the tenth N-type MOSFET; the source of the ninth N-type MOSFET is connected to the drain of the tenth N-type MOSFET; the drain of the ninth P-type MOSFET, the drain of the tenth P-type MOSFET, and the drain of the ninth N-type MOSFET are connected to each other in pairs, and are all connected to the output signal OUT4.

[0024] The source of the ninth P-type MOSFET and the source of the tenth P-type MOSFET are connected to VCC, and the source of the tenth N-type MOSFET is connected to ground. When the input signals IN5 and IN6 are both high, the output signal OUT4 becomes low, and in other cases, the output signal OUT4 is high.

[0025] Optionally, the structure of the first three-input AND gate and the second three-input AND gate comprises: an eleventh P-type MOSFET, a twelfth P-type MOSFET, a thirteenth P-type MOSFET, a fourteenth P-type MOSFET, an eleventh N-type MOSFET, a twelfth N-type MOSFET, a thirteenth N-type MOSFET, and a fourteenth N-type MOSFET.

[0026] The input signal IN7 is connected to the gate of the thirteenth P-type MOSFET and the gate of the eleventh N-type MOSFET, the input signal IN8 is connected to the gate of the twelfth P-type MOSFET and the gate of the twelfth N-type MOSFET, and the input signal IN9 is connected to the gate of the eleventh P-type MOSFET and the gate of the thirteenth N-type MOSFET.

[0027] The drain end of the eleventh P-type MOSFET, the drain end of the twelfth P-type MOSFET, the drain end of the thirteenth P-type MOSFET, the drain end of the eleventh N-type MOSFET, the gate end of the fourteenth P-type MOSFET, and the gate end of the fourteenth N-type MOSFET are connected in pairs; the drain end of the fourteenth P-type MOSFET is connected with the drain end of the fourteenth N-type MOSFET, and both are connected to the output signal OUT5;

[0028] The source end of the eleventh N-type MOSFET is connected with the drain end of the twelfth N-type MOSFET, and the source end of the twelfth N-type MOSFET is connected with the drain end of the thirteenth N-type MOSFET; the source end of the eleventh P-type MOSFET, the source end of the twelfth P-type MOSFET, the source end of the thirteenth P-type MOSFET, and the source end of the fourteenth P-type MOSFET are connected with VCC, and the source end of the thirteenth N-type MOSFET and the source end of the fourteenth N-type MOSFET are connected with the ground. When the input signals IN7, IN8, and IN9 are all high, the output signal OUT5 becomes high, and in other cases, the output signal OUT5 is low.

[0029] According to the technical scheme, compared with the prior art, the application provides a bidirectional level conversion device capable of automatically detecting transmission direction, relates to the fields of logic control, digital circuit interface, and level conversion, and the bidirectional level conversion function is realized through a logic circuit, so that the bidirectional level conversion can be realized, the signal transmission direction can be automatically switched, the system design is facilitated, the integration of the system is improved, and the cost is reduced; the application simultaneously detects the signal changes of two input / output ports, generates a required signal for controlling the input / output port, and thus the function of automatically controlling the transmission direction is achieved; in addition, the application realizes the level conversion function through a long-conducting switch for pulling down the output, a short-conducting switch for pulling up the output to a corresponding power supply, and a parallel pull-up resistor. BRIEF DESCRIPTION OF DRAWINGS

[0030] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the following will briefly introduce the drawings needed to be used in the embodiments or the prior art description. Obviously, the drawings in the following description are only the embodiments of the present application, and for those skilled in the art, other drawings can be obtained without creative labor based on the provided drawings.

[0031] Figure 1 Circuit diagram of the bidirectional level conversion device provided by the present application for automatically detecting transmission direction;

[0032] Figure 2 An example diagram of the input detection and output control circuit 101 provided by the present application;

[0033] Figure 3 An example diagram of the level conversion circuit 201 provided by the present application;

[0034] Figure 4 An example diagram of the first one-shot circuit 202 and the second one-shot circuit 203 provided by the present application;

[0035] Figure 5 An example diagram of the first two-input NOR gate 204 and the second two-input NOR gate 205 provided by the present application;

[0036] Figure 6 An example diagram of the two-input NAND gate 405 provided by the present application;

[0037] Figure 7 An example diagram of the first three-input AND gate 206 and the second three-input AND gate 207 provided by the present application;

[0038] Reference numerals: 101 - input detection and output control circuit, 102 - first P-type MOSFET, 103 - first N-type MOSFET, 104 - first resistor, 105 - second P-type MOSFET, 106 - second N-type MOSFET, 107 - second resistor, 201 - level conversion circuit, 202 - first monostable circuit, 203 - second monostable circuit, 204 - first two-input NOR gate, 205 - second two-input NOR gate, 206 - first three-input AND gate, 207 - second three-input AND gate, 301 - third P-type MOSFET, 302 - third N-type MOSFET, 303 - fourth P-type MOSFET, 304 - fourth N-type MOSFET, 305 - fifth P-type MOSFET, 306 - fifth N-type MOSFET, 401 - sixth P-type MOSFET, 402 - third resistor, 403 - sixth N-type MOSFET, 404 - capacitor, 405 - two-input NAND gate, 501 - seventh P-type MOSFET, 502 - eighth P-type MOSFET, 503 - seventh N-type MOSFET, 504 - eighth N-type MOSFET, 601 - ninth P-type MOSFET, 602 - tenth P-type MOSFET, 603 - ninth N-type MOSFET, 604 - tenth N-type MOSFET, 701 - eleventh P-type MOSFET, 702 - twelfth P-type MOSFET, 703 - thirteenth P-type MOSFET, 704 - fourteenth P-type MOSFET, 705 - eleventh N-type MOSFET, 706 - twelfth N-type MOSFET, 707 - thirteenth N-type MOSFET, 708 - fourteenth N-type MOSFET. DETAILED DESCRIPTION

[0039] The technical solutions in the embodiments of the present application will be apparently and completely described below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all the other embodiments obtained by a person of ordinary skill in the art without any creative work, fall within the scope of protection of the present application.

[0040] The embodiments of the present application disclose a bidirectional level conversion device capable of automatically detecting transmission direction, referring to Figure 1, comprising: an input detection and output control circuit 101, a first P-type MOSFET 102, a first N-type MOSFET 103, a first resistor 104, a second P-type MOSFET 105, a second N-type MOSFET 106, a second resistor 107;

[0041] Wherein, two input signal ports of the input detection and output control circuit 101 are electrically connected with the first input / output port P1 and the second input / output port P2 respectively, the first output signal A1, the second output signal A2, the third output signal B1 and the fourth output signal B2 are electrically connected with the gate of the first P-type MOSFET 102, the gate of the first N-type MOSFET 103, the gate of the second P-type MOSFET 105 and the gate of the second N-type MOSFET 106 respectively; the source of the first P-type MOSFET 102 and one end of the first resistor 104 are connected with VCC1 respectively, the drain of the first P-type MOSFET 102, the other end of the first resistor 104 and the drain of the first N-type MOSFET 103 are connected with the first input / output port P1 respectively, the source of the first N-type MOSFET 103 is grounded; the source of the second P-type MOSFET 105 and one end of the second resistor 107 are connected with VCC2 respectively, the drain of the second P-type MOSFET 105, the other end of the second resistor 107 and the drain of the second N-type MOSFET 106 are connected with the second input / output port P2 respectively, the source of the second N-type MOSFET 106 is grounded.

[0042] As shown in Figure 1 When the first input / output port P1 and the second input / output port P2 have no driving source pull-up and pull-down, the first P-type MOSFET 102, the first N-type MOSFET 103, the second P-type MOSFET 105 and the second N-type MOSFET 106 are all disconnected, at this time, the first input / output port P1 is pulled up to the logic high level VCC1 through the first resistor 104, and the second input / output port P2 is pulled up to the logic high level VCC2 through the second resistor 107.

[0043] Next, the technical solutions of this part will be further understood through specific embodiments.

[0044] Assume that at the beginning, the first input / output port P1 and the second input / output port P2 are both high level, the signal B3 is high level, the signal B4 is low level, the third output signal B1 is high level, the fourth output signal B2 is low level, the signal A4 is low level, the first output signal A1 is high level, and the second output signal A2 is low level.

[0045] When the first input / output port P1 is pulled low by the signal driving source, the signal B3 changes from high level to low level, the third output signal B1 of the first one-shot trigger circuit 202 remains high level, Figure 1 the second P-type MOSFET 105 in the second one-shot trigger circuit 203 remains off. The signal B4 changes from low level to high level, causing the fourth output signal B2 to change from low level to high level, Figure 1 the second N-type MOSFET 106 in the second one-shot trigger circuit 203 turns on, thereby pulling the second input / output port P2 low; since the fourth output signal B2 changes to high level, the signal A4 remains low level, the second output signal A2 also remains low level, the first N-type MOSFET 103 remains off, the first output signal A1 of the second one-shot trigger circuit 203 remains high level, and the first P-type MOSFET 102 remains off.

[0046] Then, the first input / output port P1 is pulled high by the driving source, the signal B3 changes from low level to high level, the signal B4 changes from high level to low level, the fourth output signal B2 changes from high level to low level, and the second N-type MOSFET 106 turns off. The third output signal B1 of the first one-shot trigger circuit 202 generates a low level pulse, causing Figure 1 the second P-type MOSFET 105 in the second one-shot trigger circuit 203 to turn on for a period of time and then turn off, thereby quickly pulling the second input / output port P2 high to VCC2; during the short low level pulse of the third output signal B1, the second output signal A2 remains low level, and since the second input / output port P2 is pulled high before the third output signal B1 changes to high level, the signal A4 is low level, and the second output signal A2 remains low level, the first N-type MOSFET 103 remains off throughout the process, the first output signal A1 of the second one-shot trigger circuit 203 remains high level, and the first P-type MOSFET 102 remains off.

[0047] When the second input / output port P2 is pulled low by the signal driving source, the first output signal A1 of the second one-shot trigger circuit 203 remains high level, the signal A4 changes from low level to high level, causing the second output signal A2 to change from low level to high level, Figure 1The first N-type MOSFET 103 in the first input / output port P1 is turned on, thereby pulling down the first input / output port P1; due to the second output signal A2 becoming high, the signal B4 remains low, the fourth output signal B2 also remains low, the second N-type MOSFET 106 remains off, the third output signal B1 of the first one-shot circuit 202 remains high, and the second P-type MOSFET 105 remains off.

[0048] Next, the second input / output port P2 is pulled high by the signal driving source, the signal A4 changes from high to low, the second output signal A2 changes from high to low, and the first N-type MOSFET 103 is turned off. The first output signal A1 of the second one-shot circuit 203 generates a low pulse, causing Figure 1 The first P-type MOSFET 102 in the first input / output port P1 is turned on and then turned off, thereby quickly pulling up the first input / output port P1 to VCC2; during the short low pulse of the first output signal A1, the fourth output signal B2 remains low, due to the first input / output port P1 being pulled high before the first output signal A1 becomes high, the signal B3 becomes high, the signal B4 is low, and the fourth output signal B2 remains low, therefore, during the whole process, the second N-type MOSFET 106 remains off, the third output signal B1 of the first one-shot circuit 202 remains high, and the second P-type MOSFET 105 remains off.

[0049] Further, as shown in Figure 2 Fig. 1 shows a structural example of the input detection and output control circuit 101, which comprises a level conversion circuit 201, a first one-shot circuit 202, a second one-shot circuit 203, a first two-input NOR gate 204, a second two-input NOR gate 205, a first three-input AND gate 206, and a second three-input AND gate 207.

[0050] The first input / output port P1 is connected to the input end of the level conversion circuit 201, and the signal B3 output by the level conversion circuit 201 is connected to an input end of the first one-shot circuit 202 and an input end of the first two-input NOR gate 204, respectively, and the second output signal A2 is connected to the other input end of the first two-input NOR gate 204; the output of the first one-shot circuit 202 is the third output signal B1, which controls the second P-type MOSFET 105 through the third output signal B1; the third output signal B1, the output signal B4 of the first two-input NOR gate 204, and the first output signal A1 are connected to the input ends of the first three-input AND gate 206, respectively, and the output of the first three-input AND gate 206 is the fourth output signal B2, which controls the second N-type MOSFET 106 through the fourth output signal B2.

[0051] The second input / output port P2 is connected to one input terminal of the second single-trigger circuit 203 and the second two-input NOR gate 205, respectively, and the fourth output signal B2 is connected to the other input terminal of the second two-input NOR gate 205; the output of the second single-trigger circuit 203 is the first output signal A1, which controls the first P-type MOSFET 102; the third output signal B1, the first output signal A1, and the output signal A4 of the second two-input NOR gate 205 are connected to the input terminal of the second three-input AND gate 207, and the output of the second three-input AND gate 207 is the second output signal A2, which controls the first N-type MOSFET 103.

[0052] Furthermore, such as Figure 3 The diagram shown is an example of the structure of a level conversion circuit 201, including: a third P-type MOSFET 301, a third N-type MOSFET 302, a fourth P-type MOSFET 303, a fourth N-type MOSFET 304, a fifth P-type MOSFET 305, and a fifth N-type MOSFET 306;

[0053] The input signal IN1 is connected to the gate of the third P-type MOSFET 301, the gate of the third N-type MOSFET 302, and the gate of the fifth N-type MOSFET 306, respectively. The source of the third P-type MOSFET 301 is connected to VCC1, and the source of the fourth P-type MOSFET 303 and the source of the fifth P-type MOSFET 305 are connected to VCC2, respectively. The source of the third N-type MOSFET 302, the source of the fourth N-type MOSFET 304, and the source of the fifth N-type MOSFET 306 are all connected to ground. The drain of the third P-type MOSFET 301, the drain of the third N-type MOSFET 302, and the gate of the fourth N-type MOSFET 304 are connected to each other in pairs. The gate of the fourth P-type MOSFET 303, the drain of the fifth P-type MOSFET 305, and the drain of the fifth N-type MOSFET 306 are connected to each other in pairs. The drain of the fourth P-type MOSFET 303, the drain of the fourth N-type MOSFET 304, and the gate of the fifth P-type MOSFET 305 are connected to each other in pairs and are connected to the output signal OUT1. The level conversion circuit 201 can complete the level conversion of the input signal IN1 to the output signal OUT1. The logic high level of the input signal IN1 is VCC1, and the logic high level of the output signal OUT1 is VCC2.

[0054] Further, as shown in FIG. 2, the first single trigger circuit 202 and the second single trigger circuit 203 are connected to the level conversion circuit 201. The first single trigger circuit 202 and the second single trigger circuit 203 are connected to the level conversion circuit 201 in parallel. The first single trigger circuit 202 and the second single trigger circuit 203 are connected to the level conversion circuit 201 in parallel. Figure 4 As shown in FIG. 3, the structure of the first single trigger circuit 202 and the second single trigger circuit 203 includes a sixth P-type MOSFET 401, a third resistor 402, a sixth N-type MOSFET 403, a capacitor 404, and a two-input NAND gate 405.

[0055] The input signal IN2 is connected to the gate of the sixth P-type MOSFET 401, the gate of the sixth N-type MOSFET 403 and one input port of the two-input NAND gate 405, respectively; the drain of the sixth P-type MOSFET 401, one end of the third resistor 402, one end of the capacitor 404 and the other input port of the two-input NAND gate 405 are connected to each other, and the output signal OUT2 of the two-input NAND gate 405 generates a short low-level pulse when the input signal IN2 is high, and the output signal OUT2 is high in other cases; the source of the sixth P-type MOSFET 401 is connected to VCC, and the drain of the sixth N-type MOSFET 403 is connected to the other end of the third resistor 402; the source of the sixth N-type MOSFET 403 and the other end of the capacitor 404 are both connected to ground.

[0056] Further, as shown in FIG. 2, the structure of the first two-input NAND gate 204 and the second two-input NAND gate 205 includes a seventh P-type MOSFET 501, an eighth P-type MOSFET 502, a seventh N-type MOSFET 503 and an eighth N-type MOSFET 504. Figure 5

[0057] The input signal IN3 is connected to the gate of the eighth P-type MOSFET 502 and the gate of the eighth N-type MOSFET 504, and the input signal IN4 is connected to the gate of the seventh P-type MOSFET 501 and the gate of the seventh N-type MOSFET 503; the drain of the seventh P-type MOSFET 501 is connected to the source of the eighth P-type MOSFET 502; the drain of the eighth P-type MOSFET 502, the drain of the seventh N-type MOSFET 503 and the drain of the eighth N-type MOSFET 504 are connected to each other and to the output signal OUT3; the source of the seventh P-type MOSFET 501 is connected to VCC; the source of the seventh N-type MOSFET 503 and the source of the eighth N-type MOSFET 504 are both connected to ground. When the input signals IN3 and IN4 are both low, the output signal OUT3 becomes high, and in other cases, the output signal OUT3 is low.

[0058] Further, as shown in FIG. 2, the structure of the first two-input NAND gate 204 and the second two-input NAND gate 205 includes a seventh P-type MOSFET 501, an eighth P-type MOSFET 502, a seventh N-type MOSFET 503 and an eighth N-type MOSFET 504. Figure 6 ​A structure example of two-input NAND gate 405 is shown, including: a ninth P-type MOSFET 601, a tenth P-type MOSFET 602, a ninth N-type MOSFET 603, a tenth N-type MOSFET 604;

[0059] Wherein, input signal IN5 is connected to the gate of the tenth P-type MOSFET 602 and the gate of the ninth N-type MOSFET 603 respectively, input signal IN6 is connected to the gate of the ninth P-type MOSFET 601 and the gate of the tenth N-type MOSFET 604 respectively; the source of the ninth N-type MOSFET 603 is connected to the drain of the tenth N-type MOSFET 604; the drain of the ninth P-type MOSFET 601, the drain of the tenth P-type MOSFET 602 and the drain of the ninth N-type MOSFET 603 are connected to each other in pairs, and are connected to output signal OUT4; the source of the ninth P-type MOSFET 601 and the source of the tenth P-type MOSFET 602 are connected to VCC; the source of the tenth N-type MOSFET 604 is connected to ground. When input signals IN5 and IN6 are high at the same time, the output signal OUT4 will be low, and in other cases, the output signal OUT4 is high.

[0060] Further, as Figure 7 A structure example of three-input AND gate is shown, and the structure of the first three-input AND gate 206 and the second three-input AND gate 207 includes: an eleventh P-type MOSFET 701, a twelfth P-type MOSFET 702, a thirteenth P-type MOSFET 703, a fourteenth P-type MOSFET 704, an eleventh N-type MOSFET 705, a twelfth N-type MOSFET 706, a thirteenth N-type MOSFET 707, a fourteenth N-type MOSFET 708;

[0061] Wherein, input signal IN7 is connected to the gate of the thirteenth P-type MOSFET 703 and the gate of the eleventh N-type MOSFET 705, input signal IN8 is connected to the gate of the twelfth P-type MOSFET 702 and the gate of the twelfth N-type MOSFET 706, input signal IN9 is connected to the gate of the eleventh P-type MOSFET 701 and the gate of the thirteenth N-type MOSFET 707;

[0062] The drain end of the eleventh P-type MOSFET 701, the drain end of the twelfth P-type MOSFET 702, the drain end of the thirteenth P-type MOSFET 703, the drain end of the eleventh N-type MOSFET 705, the gate end of the fourteenth P-type MOSFET 704, and the gate end of the fourteenth N-type MOSFET 708 are connected to each other in pairs; the drain end of the fourteenth P-type MOSFET 704 and the drain end of the fourteenth N-type MOSFET 708 are connected to each other and connected to the output signal OUT5; the source end of the eleventh N-type MOSFET 705 and the drain end of the twelfth N-type MOSFET 706 are connected to each other, and the source end of the twelfth N-type MOSFET 706 and the drain end of the thirteenth N-type MOSFET 707 are connected to each other; the source end of the eleventh P-type MOSFET 701, the source end of the twelfth P-type MOSFET 702, the source end of the thirteenth P-type MOSFET 703, and the source end of the fourteenth P-type MOSFET 704 are connected to VCC, and the source end of the thirteenth N-type MOSFET 707 and the source end of the fourteenth N-type MOSFET 708 are connected to ground. When the input signals IN7, IN8 and IN9 are all high, the output signal OUT5 becomes high, and in other cases, the output signal OUT5 is at a low level.

[0063] Some logic signals have a certain direction in the transmission process, but the transmission direction of some logic signals is uncertain, and the direction of the logic signal transmission needs to be switched in the transmission process, and the application discloses a bidirectional level conversion device capable of automatically detecting the transmission direction, relates to the fields of logic control, digital circuit interface and level conversion, and realizes the bidirectional level conversion function through a logic circuit, so that the signal transmission direction can be automatically switched, system design is facilitated, and the integration of the system is improved and the cost is reduced.

[0064] The above description of disclosed embodiments enables one of ordinary skill in the art to make or use the application. Various modifications to these embodiments will be readily apparent to those of ordinary skill in the art, and the generic principles defined herein can be applied to other embodiments without departing from the spirit or scope of the application. Thus, the present application is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A bidirectional level shifter device that automatically detects transmission direction, characterized by, The application relates to an input detection and output control circuit, which comprises: an input detection and output control circuit (101), a first P-type MOSFET (102), a first N-type MOSFET (103), a first resistor (104), a second P-type MOSFET (105), a second N-type MOSFET (106) and a second resistor (107); two input signal ports of the input detection and output control circuit (101) are electrically connected with a first input / output port P1 and a second input / output port P2 respectively, and a first output signal A1, a second output signal A2, a third output signal B1 and a fourth output signal B2 are electrically connected with a gate end of the first P-type MOSFET (102), a gate end of the first N-type MOSFET (103), a gate end of the second P-type MOSFET (105) and a gate end of the second N-type MOSFET (106) respectively; a source end of the first P-type MOSFET (102) and one end of the first resistor (104) are connected with VCC1 respectively, a drain end of the first P-type MOSFET (102), the other end of the first resistor (104) and a drain end of the first N-type MOSFET (103) are connected with the first input / output port P1 respectively, and a source end of the first N-type MOSFET (103) is grounded; a source end of the second P-type MOSFET (105) and one end of the second resistor (107) are connected with VCC2 respectively, a drain end of the second P-type MOSFET (105), the other end of the second resistor (107) and a drain end of the second N-type MOSFET (106) are connected with the second input / output port P2 respectively, and a source end of the second N-type MOSFET (106) is grounded; when the first input / output port P1 and the second input / output port P2 have no driving source up pull and down pull, the first P-type MOSFET (102), the first N-type MOSFET (103), the second P-type MOSFET (105) and the second N-type MOSFET (106) are all disconnected, at this time, the first input / output port P1 is pulled up to a logic high level VCC1 through the first resistor (104), and the second input / output port P2 is pulled up to a logic high level VCC2 through the second resistor (107); the input detection and output control circuit (101) comprises: a level conversion circuit (201), a first single-shot circuit (202), a second single-shot circuit (203), a first two-input NOR gate (204), a second two-input NOR gate (205), a first three-input AND gate (206) and a second three-input AND gate (207). The first input / output port P1 is connected with the input end of the level conversion circuit (201), and the signal B3 output by the level conversion circuit (201) is connected with the first one-shot trigger circuit (202) and one input end of the first two-input NOR gate (204) respectively, and the second output signal A2 is connected with the other input end of the first two-input NOR gate (204); the output of the first one-shot trigger circuit (202) is the third output signal B1, and the second P-type MOSFET (105) is controlled through the third output signal B1; the third output signal B1, the output signal B4 of the first two-input NOR gate (204) and the first output signal A1 are connected with the input ends of the first three-input AND gate (206) respectively, and the output of the first three-input AND gate (206) is the fourth output signal B2, and the second N-type MOSFET (106) is controlled through the fourth output signal B2; The second input / output port P2 is connected with the second one-shot trigger circuit (203) and one input end of the second two-input NOR gate (205) respectively, and the fourth output signal B2 is connected with the other input end of the second two-input NOR gate (205); the output of the second one-shot trigger circuit (203) is the first output signal A1, and the first P-type MOSFET (102) is controlled through the first output signal A1; the third output signal B1, the first output signal A1 and the output signal A4 of the second two-input NOR gate (205) are connected with the input ends of the second three-input AND gate (207) respectively, and the output of the second three-input AND gate (207) is the second output signal A2, and the first N-type MOSFET (103) is controlled through the second output signal A2.

2. The bidirectional level shifter of claim 1, wherein, The level conversion circuit (201) comprises a third P-type MOSFET (301), a third N-type MOSFET (302), a fourth P-type MOSFET (303), a fourth N-type MOSFET (304), a fifth P-type MOSFET (305) and a fifth N-type MOSFET (306). The input signal IN1 is connected to the gate of the third P-type MOSFET (301), the gate of the third N-type MOSFET (302), and the gate of the fifth N-type MOSFET (306) respectively, the source of the third P-type MOSFET (301) is connected to VCC1, the source of the fourth P-type MOSFET (303) and the source of the fifth P-type MOSFET (305) are connected to VCC2 respectively; the source of the third N-type MOSFET (302), the source of the fourth N-type MOSFET (304), and the source of the fifth N-type MOSFET (306) are all connected to ground; the drain of the third P-type MOSFET (301), the drain of the third N-type MOSFET (302), and the gate of the fourth N-type MOSFET (304) are connected to each other in pairs; the gate of the fourth P-type MOSFET (303), the drain of the fifth P-type MOSFET (305), and the drain of the fifth N-type MOSFET (306) are connected to each other in pairs; The drain of the fourth P-type MOSFET (303), the drain of the fourth N-type MOSFET (304), and the gate of the fifth P-type MOSFET (305) are connected to each other in pairs and are all connected to the output signal OUT1; the logic high level of the input signal IN1 is VCC1, and the logic high level of the output signal OUT1 is VCC2.

3. The bidirectional level shifter of claim 1, wherein, The structure of the first one-shot circuit (202) and the second one-shot circuit (203) includes a sixth P-type MOSFET (401), a third resistor (402), a sixth N-type MOSFET (403), a capacitor (404), and a two-input NAND gate (405); The input signal IN2 is connected to the gate of the sixth P-type MOSFET (401), the gate of the sixth N-type MOSFET (403), and one of the input ports of the two-input NAND gate (405) respectively; the drain of the sixth P-type MOSFET (401), one end of the third resistor (402), one end of the capacitor (404), and the other input port of the two-input NAND gate (405) are connected to each other in pairs, and the output signal OUT2 of the two-input NAND gate (405) generates a short low-level pulse when the input signal IN2 is high, and the output signal OUT2 is high in other cases; The source terminal of the sixth P-type MOSFET (401) is connected to VCC, and the drain terminal of the sixth N-type MOSFET (403) is connected to the other terminal of the third resistor (402); the source terminal of the sixth N-type MOSFET (403) and the other terminal of the capacitor (404) are both grounded.

4. The bidirectional level shifter of claim 1, wherein, The structure of the first two-input NOR gate (204) and the second two-input NOR gate (205) comprises a seventh P-type MOSFET (501), an eighth P-type MOSFET (502), a seventh N-type MOSFET (503), and an eighth N-type MOSFET (504); The input signal IN3 is connected to the gate terminal of the eighth P-type MOSFET (502) and the gate terminal of the eighth N-type MOSFET (504), and the input signal IN4 is connected to the gate terminal of the seventh P-type MOSFET (501) and the gate terminal of the seventh N-type MOSFET (503); the drain terminal of the seventh P-type MOSFET (501) is connected to the source terminal of the eighth P-type MOSFET (502); the drain terminals of the eighth P-type MOSFET (502), the seventh N-type MOSFET (503), and the eighth N-type MOSFET (504) are connected to each other in pairs, and are all connected to the output signal OUT3; The source terminal of the seventh P-type MOSFET (501) is connected to VCC; the source terminals of the seventh N-type MOSFET (503) and the eighth N-type MOSFET (504) are both grounded.

5. The automatic detection of transmission direction bidirectional level shifter of claim 3, wherein, The two-input NOR gate (405) comprises a ninth P-type MOSFET (601), a tenth P-type MOSFET (602), a ninth N-type MOSFET (603), and a tenth N-type MOSFET (604); The input signal IN5 is connected to the gate of the tenth P-type MOSFET (602) and the gate of the ninth N-type MOSFET (603) respectively, the input signal IN6 is connected to the gate of the ninth P-type MOSFET (601) and the gate of the tenth N-type MOSFET (604) respectively; the source of the ninth N-type MOSFET (603) is connected to the drain of the tenth N-type MOSFET (604); the drain of the ninth P-type MOSFET (601), the drain of the tenth P-type MOSFET (602) and the drain of the ninth N-type MOSFET (603) are connected to each other in pairs and are all connected to the output signal OUT4; The source of the ninth P-type MOSFET (601) and the source of the tenth P-type MOSFET (602) are connected to VCC; the source of the tenth N-type MOSFET (604) is connected to the ground.

6. The automatic detection of transmission direction bidirectional level shifter of claim 1, wherein, The structure of the first three-input AND gate (206) and the second three-input AND gate (207) comprises: an eleventh P-type MOSFET (701), a twelfth P-type MOSFET (702), a thirteenth P-type MOSFET (703), a fourteenth P-type MOSFET (704), an eleventh N-type MOSFET (705), a twelfth N-type MOSFET (706), a thirteenth N-type MOSFET (707) and a fourteenth N-type MOSFET (708); The input signal IN7 is connected to the gate of the thirteenth P-type MOSFET (703) and the gate of the eleventh N-type MOSFET (705) respectively, the input signal IN8 is connected to the gate of the twelfth P-type MOSFET (702) and the gate of the twelfth N-type MOSFET (706) respectively, and the input signal IN9 is connected to the gate of the eleventh P-type MOSFET (701) and the gate of the thirteenth N-type MOSFET (707) respectively; The drain of the eleventh P-type MOSFET (701), the drain of the twelfth P-type MOSFET (702), the drain of the thirteenth P-type MOSFET (703), the drain of the eleventh N-type MOSFET (705), the gate of the fourteenth P-type MOSFET (704), and the gate of the fourteenth N-type MOSFET (708) are connected in pairs; the drain of the fourteenth P-type MOSFET (704) is connected to the drain of the fourteenth N-type MOSFET (708), and both are connected to an output signal OUT5; The source of the eleventh N-type MOSFET (705) is connected to the drain of the twelfth N-type MOSFET (706), and the source of the twelfth N-type MOSFET (706) is connected to the drain of the thirteenth N-type MOSFET (707); the source of the eleventh P-type MOSFET (701), the source of the twelfth P-type MOSFET (702), the source of the thirteenth P-type MOSFET (703), and the source of the fourteenth P-type MOSFET (704) are connected to VCC, and the source of the thirteenth N-type MOSFET (707) and the source of the fourteenth N-type MOSFET (708) are connected to ground.

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