Decompression circuit, circuit generation method and IC chip
By designing the decompression circuit and using the CA circuit and the phase shifter to extend the test signal, the problem of long test time and high cost of IC chips is solved, and efficient and rapid testing of IC chip devices is achieved.
Patent Information
- Application Number
- CN202080106498.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2020-10-23
- Publication Date
- 2025-03-25
- Estimated Expiration
- 2040-10-23
AI Technical Summary
During the IC chip testing process, the existing technology has a limited number of input and output pins, which requires serial input and a large number of test excitations and compare test results when testing as many devices as possible in the IC chip, which consumes a lot of time and leads to high testing costs.
By designing a decompression circuit, using multiple sub-circuits, cellular automaton CA circuits and phase shifters, the randomness and expansion of the test signals are realized, and a large number of test signals are output to achieve efficient testing of IC chip devices.
This technology can significantly reduce IC chip testing time, improve testing efficiency, reduce test costs, and achieve rapid and comprehensive testing of IC chip devices.
Smart Images
Figure CN116368389B_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the field of integrated circuit (IC) chip testing, and in particular to a decompression circuit, a circuit generation method and an IC chip. Background Art
[0002] When testing an IC chip, one way is to electrically connect the input pins and output pins of the IC chip to automatic test equipment (ATE). The ATE inputs test stimuli to the input pins of the IC chip, measures the test results output by the IC chip, and compares them with the expected test results to determine whether the IC chip has design defects.
[0003] IC chips can integrate hundreds of millions of devices in one chip, but the number of input and output pins provided by IC chips is limited. If you want to test as many devices as possible in the IC chip, you need to input a large number of test stimuli in series and compare a large number of test results, which will take a lot of time. Testing through ATE is charged by the hour, which will lead to high testing costs. Summary of the invention
[0004] The embodiments of the present application provide a decompression circuit, a circuit generation method and an IC chip, which are used to test the components of the IC chip by outputting a large number of test signals through the decompression circuit.
[0005] To achieve the above objectives, the embodiments of the present application adopt the following technical solutions:
[0006] In a first aspect, a decompression circuit is provided, comprising a plurality of sub-circuits, each of which comprises a plurality of cellular automaton CA circuits and a phase shifter, wherein the CA circuit comprises a first XOR circuit and a register, wherein the first XOR circuit comprises a first input terminal; a data input terminal of the register is coupled to an output terminal of the first XOR circuit; a data output terminal of the register is coupled to a first input terminal of the first XOR circuit and an input terminal of the phase shifter; the data output terminal of the register is also coupled to a second input terminal of the first XOR circuit in at least one other CA circuit; and the phase shifter is used to output a test signal.
[0007] The decompression circuit provided by the embodiment of the present application includes multiple sub-circuits, the sub-circuits include multiple CA circuits and phase shifters, the CA circuit includes a first XOR circuit and a register, the first XOR circuit includes a first input end and a second input end; the data input end of the register is coupled to the output end of the first XOR circuit; the data output end of the register is coupled to the first input end of the first XOR circuit and an input end of the phase shifter; the data output end of the register is also coupled to the second input end of the first XOR circuit in at least one other CA circuit; the phase shifter is used to output a test signal. In the decompression circuit, the randomness of the test signal is realized by the CA circuit, and a large number of test signals are expanded and output by the phase shifter to realize the testing of the device of the IC chip.
[0008] In a possible implementation, the first XOR circuit further includes a second input terminal, the CA circuit further includes a first AND gate circuit and a control circuit, the output terminal of the first AND gate circuit is coupled to the second input terminal of the first XOR circuit of the CA circuit to which it belongs, the first AND gate circuit includes a third input terminal and a fourth input terminal, the third input terminal is coupled to the data output terminal of the register in at least one other CA circuit, and the fourth input terminal is coupled to an output terminal of the control circuit. The control circuit can control the data outputted from the data output terminal of the register in the other CA circuit through the first AND gate circuit, whether to participate in the XOR operation of the CA circuit to which it belongs. When the output terminal of the control circuit is at a low level (or zero, "0"), no matter what value is outputted from the data output terminal of the register in at least one other CA circuit to which it is coupled, the first AND gate circuit outputs a low level (or "zero", "0"), that is, the data output terminal of the register is invalid; when the output terminal of the control circuit is at a high level (or "one", "1"), the first AND gate circuit outputs the value outputted from the data output terminal of the register in at least one other CA circuit to which it is coupled, that is, the data output terminal of the register is valid.
[0009] In a possible implementation, the first AND gate circuit includes a plurality of third input terminals, which are respectively coupled to data output terminals of registers in a plurality of other CA circuits. The control circuit can control, through the first AND gate circuit, whether the data outputted from the data output terminals of the registers in the plurality of other CA circuits participates in the exclusive OR operation of the corresponding CA circuit.
[0010] In a possible implementation, the first XOR circuit includes a plurality of second input terminals, the CA circuit also includes a second AND gate circuit, the output terminal of the first AND gate circuit and the output terminal of the second AND gate circuit are respectively coupled to the plurality of second input terminals of the first XOR circuit in the CA circuit; the second AND gate circuit includes a fifth input terminal and a sixth input terminal, the fifth input terminal is grounded, and the sixth input terminal is coupled to an output terminal of the control circuit. The output of the second AND gate circuit is always at a low level (or "zero", "0").
[0011] In a possible implementation, the sub-circuit further includes a second XOR circuit, the second XOR circuit includes a seventh input terminal and an eighth input terminal, the seventh input terminal is used to input a test stimulus, the eighth input terminal is coupled to a data output terminal of a register in at least one other CA circuit, and the output terminal of the second XOR circuit is coupled to the third input terminal. The test stimulus is introduced into the sub-circuit through the second XOR circuit.
[0012] In a possible implementation, the control circuit includes a decoder; the decoder includes multiple output terminals, the decoder is used to receive a control signal, decode the control signal to obtain a decoding result, and output the decoding result through the multiple output terminals. This implementation introduces a possible structure of the control circuit.
[0013] In a possible implementation, the register is a multi-bit register. This can save IC chip area. For example, multiple CA circuits can share a multi-bit register, and each CA circuit occupies a data input terminal and a data output terminal of one bit. In addition, in addition to the data input terminals and data output terminals of some bits of the multi-bit register being occupied by the above-mentioned decompression circuit, the data input terminals and data output terminals of other bits can also be used for the compression circuit.
[0014] In a second aspect, an integrated circuit chip is provided, comprising a decompression circuit and a circuit to be tested as described in the first aspect and any embodiment thereof, wherein the output end of the phase shifter of the decompression circuit is coupled to the input end of the circuit to be tested through a scan chain.
[0015] In a third aspect, a circuit generation method is provided, comprising: obtaining the number of input channels and the number of scan chains fanned out by a decompression circuit; and generating a decompression circuit as described in the first aspect and any embodiment thereof according to the number of input channels and the number of scan chains.
[0016] In a possible implementation, the method further includes: generating a circuit of the integrated circuit chip as described in the second aspect according to the number of input channels and the number of scan chains.
[0017] In a fourth aspect, a computer-readable storage medium is provided. The computer-readable storage medium is non-volatile and stores computer-readable instructions. When the computer-readable instructions are executed on a computer, the computer executes the method described in the third aspect and any one of its embodiments.
[0018] In a fifth aspect, a computer program product is provided, which includes computer-readable instructions. When the computer-readable instructions are executed on a computer, the computer executes the method described in the third aspect and any embodiment thereof.
[0019] Regarding the technical effects of the second to fifth aspects, refer to the technical effects of the first aspect and any embodiment thereof. BRIEF DESCRIPTION OF THE DRAWINGS
[0020] Figure 1 A schematic diagram of the structure of an IC chip provided in an embodiment of the present application;
[0021] Figure 2 A schematic diagram of a decompression circuit provided in an embodiment of the present application Figure 1 ;
[0022] Figure 3 A schematic diagram of a decompression circuit provided in an embodiment of the present application Figure 2 ;
[0023] Figure 4 A schematic diagram of the structure of a CA circuit provided in an embodiment of the present application;
[0024] Figure 5 A schematic diagram of the structure of a phase shifter provided in an embodiment of the present application;
[0025] Figure 6 A schematic diagram of a decompression circuit provided in an embodiment of the present application Figure 3 ;
[0026] Figure 7 A schematic diagram of a decompression circuit provided in an embodiment of the present application Figure 4 ;
[0027] Figure 8 A schematic diagram of a decoding output of a control circuit provided in an embodiment of the present application;
[0028] Fig. 9 A schematic diagram of the structure of a multi-bit register provided in an embodiment of the present application;
[0029] Fig.10 A schematic diagram of a decompression circuit and a compression circuit sharing a multi-bit register provided in an embodiment of the present application. DETAILED DESCRIPTION
[0030] In the electronic design automation (EDA) design process of IC chips, users input configurations into EDA software, which generates logic circuits, and then obtains IC chips through plate making and tape-out. In the process of testing IC chips, the IC chips are installed on ATE, which inputs test stimuli to the input pins of the IC chips, measures the test results output by the IC chips, and compares them with the expected test results, thereby determining whether the IC chips have design defects.
[0031] In order to reduce testing costs and improve testing efficiency, EDA software can be used to implement deterministic automatic test pattern generation (ATPG). Figure 1 As shown, when designing an IC chip, the EDA software not only generates a circuit to be tested 11 in the IC chip, but also generates a decompression circuit 12 and a compression circuit 13 in the IC chip. In addition, multiple groups of test vectors for testing can be generated, each group of test vectors includes a test stimulus and an expected test result. Each group of test vectors can be used to detect some manufacturing defects inside the IC chip. Determinism means that the input (test stimulus) and output (expected test result) of the circuit to be tested in the IC chip are determined, and these inputs and outputs are designed for specific defects.
[0032] ATE inputs test stimulus to the decompression circuit 12 of the IC chip through a small number of input pins of the IC chip. The decompression circuit 12 on the IC chip expands the test stimulus into a large number of scan chain test signals, which are input to the circuit to be tested 11 on the IC chip. The circuit to be tested 11 then inputs a large number of test results into the compression circuit 13. The compression circuit 13 compresses the test results and outputs them through a small number of output pins of the IC chip. The test results are compared with the expected test results to determine whether there are design defects in the circuit to be tested 11.
[0033] To this end, the present application provides a decompression circuit, such as Figure 2 and Figure 3 As shown, the decompression circuit includes a plurality of sub-circuits 30, each of which includes a plurality of cellular automata (CA) circuits 301 and a phase shifter 302. Optionally, the sub-circuit 30 further includes a second XOR circuit XOR2.
[0034] Each subcircuit 30 may be independent of each other, for example, the input end of any CA circuit in the first subcircuit has no coupling relationship with the output end of any CA circuit in the second subcircuit, and the output end of any CA circuit in the first subcircuit has no coupling relationship with the input end of any CA circuit in the second subcircuit. Figure 2 or Figure 3 As shown, the sub-circuits 30 can be coupled to each other, for example, the output end of a CA circuit of the first sub-circuit is coupled to the input end of a CA circuit of the second sub-circuit, and the input end of a CA circuit of the first sub-circuit is coupled to the output end of a CA circuit of the second sub-circuit.
[0035] Figure 2It can be called a one-dimensional decompression circuit, that is, the mutual coupling between each CA circuit is realized through a specific CA circuit; for example, each CA circuit in a subcircuit 30 is coupled in series, and the last CA circuit can be coupled with the first CA circuit in another subcircuit 30. From another perspective, each CA circuit 301 between different subcircuits 30 is connected in series. Figure 3 It can be called a two-dimensional decompression circuit, and the CA circuit at any position may be coupled with the CA circuit in other sub-circuits 30. In other words, the CA circuits 301 are connected in parallel.
[0036] It should be noted that the left, right, up and down directions in the embodiment of the present application refer to the directions specified in the schematic diagram for the convenience of describing the coupling relationship. In the actual IC chip, due to reasons such as wiring layout, their positional relationship is not limited and is still based on the actual circuit coupling relationship.
[0037] like Figure 4 As shown, the figure describes the basic structure of the sub-circuit 30, and the sub-circuit 30 includes a plurality of CA circuits 301 and a phase shifter 302. Optionally, the sub-circuit 30 also includes a second XOR circuit XOR2.
[0038] The CA circuit 301 includes a register R and a first XOR gate XOR1. The CA circuit 301 includes an output terminal and at least one input terminal. The data output terminal Q of the register R is coupled to the output terminal of the CA circuit 301. At least one input terminal of the first XOR gate XOR1 is coupled to at least one input terminal of the CA circuit 301.
[0039] The data output terminal Q of the register R is coupled to the first input terminal of the first XOR gate XOR1, the output terminal of the first XOR gate XOR1 is coupled to the data input terminal D of the register R, and the second input terminal of the first XOR gate XOR1 is coupled to the data output terminal Q of the register of at least one other CA circuit. In other words, the output of the register R is related to the output of the register and the output of the register of the other CA circuits at the previous clock cycle of the clock signal, so as to achieve the randomness of the output of the register R.
[0040] In the same sub-circuit 30 , an output terminal of one CA circuit 301 is coupled to an input terminal of the phase shifter 302 and an input terminal of at least one other CA circuit 301 .
[0041] The phase shifter 302 includes a plurality of input terminals and a plurality of output terminals. The phase shifter 302 is used to perform XOR calculation on the data input from the input terminals and then output the test signal through the plurality of output terminals.
[0042] like Figure 5As shown, a possible structure of the phase shifter 302 is shown. The phase shifter 302 includes a plurality of third XOR circuits XOR3, each of which includes at least two input terminals, each of which is coupled to a data output terminal Q of a register R of a CA circuit 301, and at least one of the input terminals of any two third XOR circuits XOR3 is coupled to a different data output terminal Q, that is, any two third XOR circuits XOR3 are independent of each other and may output different values, which can better reflect the randomness of the output value of the phase shifter 302.
[0043] Optional, such as Figure 4 As shown, the data output terminal Q of the register R of one CA circuit 301 may also be coupled to an input terminal of another CA circuit 301 through a second XOR circuit XOR2.
[0044] Specifically, the second XOR circuit XOR2 includes an output end and two input ends, one input end of the second XOR circuit XOR2 is used to input a test stimulus through an input channel, the other input end of the second XOR circuit XOR2 is coupled to an output end of at least one other CA circuit 301, and the output end of the second XOR circuit XOR2 is coupled to an input end of the first XOR circuit XOR1.
[0045] The second XOR circuit XOR2 is used to perform XOR operation on the data input from the two input terminals, and then output the XOR calculation result through the output terminal of the second XOR circuit XOR2. That is, the second XOR circuit XOR2 introduces the test stimulus into the decompression circuit, and by controlling the test stimulus, the output of the CA circuit 301 can be controlled, and then the output of the phase shifter 302 can be controlled. The test stimulus input to each sub-circuit 30 is independent of each other, and can be the same or different, and the test stimulus can be input to any CA circuit 301.
[0046] In the same subcircuit 30, each CA circuit 301 can be coupled to the same clock signal source. Optionally, each CA circuit 301 can also be coupled to the same debugging tool chain, for example, a joint test action group (JTAG) chain, an Internet JTAG (IJTAG) chain, etc. The debugging tool chain is used to output control signals to each CA circuit to configure the CA circuit, which will be described in detail later.
[0047] It should be noted that although Figure 2 and Figure 3 There are multiple output ends of a CA circuit, but the signal sources are the same, and they are all coupled to the data output ends of the registers in the CA circuit, which will be described in detail later.
[0048] In the above decompression circuit, the CA circuit and the phase shifter of the same subcircuit can be arranged adjacent to each other, and the adjacent CA circuits of the same subcircuit are coupled, so there will not be a long cross-line, thus reducing the difficulty of layout and wiring. In addition, different test stimuli can be input into any CA circuit of different subcircuits through the second XOR gate, thereby ensuring the decompression encoding capability. In addition, Figure 3 and Figure 2 In comparison, that is, compared with the CA circuit 301 connected in parallel and the CA circuit connected in series, only fewer clock signal cycles are required, that is, a random test signal can be output.
[0049] Below Figure 6 right Figure 2 The specific circuit and coupling relationship are described in detail. Figure 7 right Figure 3 The specific circuit and coupling relationship are described in detail.
[0050] like Figure 6 and Figure 7 As shown, the CA circuit 301 includes a first XOR circuit XOR1 and a register R. Optionally, the CA circuit 301 also includes a first AND gate circuit AND1, a second AND gate circuit AND2 and a control circuit CTRL.
[0051] The first XOR circuit XOR1 includes an output terminal, a first input terminal, and a second input terminal. The first XOR circuit XOR1 is used to perform an XOR operation on the data input from the first input terminal and the second input terminal, and output the XOR calculation result through the output terminal of the first XOR circuit XOR1. The first XOR circuit XOR1 may have multiple second input terminals.
[0052] A first input terminal of the first XOR circuit XOR1 is coupled to a data output terminal Q of the register R. A second input terminal of the first XOR circuit XOR1 is coupled to a data output terminal Q of the register R in at least one other CA circuit through a first AND gate circuit AND1. That is, the value outputted by the data output terminal Q of the register R and the value outputted by the data output terminal Q of the register R in at least one other CA circuit coupled thereto participate in an XOR operation.
[0053] Specifically, the output end of the first AND gate circuit AND1 is coupled to the second input end of the first XOR circuit XOR1 of the CA circuit to which it belongs, the third input end of the first AND gate circuit AND1 is coupled to the data output end Q of the register R in at least one other CA circuit, and the fourth input end of the first AND gate circuit AND1 is coupled to an output end of the control circuit CTRL.
[0054] When the first XOR circuit XOR1 includes a plurality of second input terminals, the output terminal of the first AND gate circuit AND1 and the output terminal of the second AND gate circuit AND2 are respectively coupled to the plurality of second input terminals of the first XOR circuit in the corresponding CA circuit.
[0055] The register R includes a data input terminal D, a data output terminal Q and a clock input terminal CLK. Taking the register R as a D flip-flop as an example, each time a rising edge of a clock signal is input to the clock input terminal CLK, the data output terminal Q outputs the data of the data input terminal D.
[0056] The data input terminal D of the register R is coupled to the output terminal of the first XOR circuit XOR1, that is, the first XOR circuit XOR1 feeds back the XOR result to the register R. On the one hand, the data output terminal Q of the register R is coupled to the first input terminal of the first XOR circuit XOR1, that is, the value output by the data output terminal Q of the register R participates in the XOR operation of the first XOR circuit XOR1 in the CA circuit 301 to which it belongs. On the other hand, the data output terminal Q of the register R, as the output terminal of the CA circuit to which it belongs, is coupled to an input terminal of the phase shifter 302, and is also coupled to the second input terminal of the first XOR circuit XOR1 in at least one other CA circuit, that is, the value output by the data output terminal Q of the register R also participates in the XOR operation of the first XOR circuit XOR1 in at least one other CA circuit to which it is coupled.
[0057] The first AND gate circuit AND1 includes an output terminal, a third input terminal and a fourth input terminal. The first AND gate circuit AND1 is used to perform an AND operation on the data input from the third input terminal and the fourth input terminal, and output the result of the AND operation through the output terminal of the first AND gate circuit AND1. The first AND gate circuit AND1 may have multiple third input terminals.
[0058] In the embodiment of the present application, the third input terminal of the first AND gate circuit AND1 is coupled to the data output terminal Q of the register R in at least one other CA circuit, and the fourth input terminal of the first AND gate circuit AND1 is coupled to an output terminal of the control circuit CTRL. When the first AND gate circuit AND1 includes multiple third input terminals, the multiple third input terminals are respectively coupled to the data output terminals Q of the registers R in multiple other CA circuits.
[0059] The output of the first AND gate circuit AND1 is controlled by an output terminal of the coupled control circuit CTRL: when the output terminal of the control circuit CTRL is at a low level (or zero, "0"), no matter what value the data output terminal Q of the register R in at least one other coupled CA circuit outputs, the first AND gate circuit AND1 outputs a low level (or "zero", "0"), that is, the data output terminal Q of the register R is invalid; when the output terminal of the control circuit CTRL is at a high level (or "one", "1"), the first AND gate circuit AND1 outputs the value output by the data output terminal Q of the register R in at least one other coupled CA circuit, that is, the data output terminal Q of the register R is effective.
[0060] The second AND gate circuit AND2 includes an output terminal, a fifth input terminal and a sixth input terminal. The second AND gate circuit AND2 is used to perform an AND operation on the data input from the fifth input terminal and the sixth input terminal, and then output the result of the AND operation through the output terminal of the second AND gate circuit AND2. In the embodiment of the present application, the fifth input terminal of the second AND gate circuit AND2 is grounded, and the sixth input terminal is coupled to an output terminal of the control circuit CTRL. The output of the second AND gate circuit AND2 is always a low level (or "zero", "0").
[0061] The second XOR circuit XOR2 includes an output terminal, a seventh input terminal and an eighth input terminal, wherein the seventh input terminal is used to input a test stimulus, the eighth input terminal is coupled to a data output terminal Q of a register R in at least one other CA circuit, and the output terminal of the second XOR circuit XOR2 is coupled to the third input terminal of the first AND gate circuit AND1.
[0062] It should be noted that, instead of the third input terminal of the first AND gate circuit AND1 of each CA circuit being coupled to the output terminal of XOR2, each sub-circuit 30 includes at least one second XOR circuit XOR2, and the test stimulus input to the second XOR circuit XOR2 in the same sub-circuit 30 may be the same or different.
[0063] The control circuit CTRL includes a decoder, the decoder includes at least one input terminal and multiple output terminals, and the input terminal of the decoder is coupled to the debugging tool chain. The decoder is used to receive a control signal through the input terminal, decode the control signal to obtain a decoding result, and output the decoding result through multiple output terminals. Exemplarily, the decoder is a 2-4 decoder, that is, the decoder includes two input terminals and four output terminals. Please do not limit the truth table (decoding rule) of the decoder in this document.
[0064] In a possible implementation manner, the truth table of the 2-4 decoder is shown in Table 1.
[0065] Table 1
[0066]
[0067]
[0068] In another possible implementation, the truth table of the two-four decoder is shown in Table 2.
[0069] Table 2
[0070] Control Signal Output decoding (left, right, up, down) Effective direction 00 1100 about 01 0011 up and down
[0071] As shown in Table 1 and Figure 7 As shown in the decompression circuit, combined with the first AND gate circuit AND1 and the second AND gate circuit AND2 described above, the four bits in the decoding result can be realized from high to low, and the data output ends of the registers R of other CA circuits in the four directions of left, right, up and down can be realized in turn, that is, whether they participate in the XOR operation of the first XOR circuit XOR1 in the CA circuit to which they belong. As shown in Table 2 and Figure 6 As shown in the decompression circuit, combined with the first AND gate circuit AND1 and the second AND gate circuit AND2, the two bits in the decoding result from high to low can realize in turn whether the data output ends of the register R of other CA circuits in the left and right (also called up and down) directions are effective, that is, whether they participate in the XOR operation of the first XOR circuit XOR1 in the CA circuit to which they belong. Figure 7 The decompression circuit is taken as an example, but is not intended to be limiting.
[0072] For example, as shown in Table 1 and Figure 8 As shown: Figure 8 A in the figure and the output decode 1110 in Table 1 represent the values outputted by the data output terminal Q of the register R of the CA circuit in the three directions of left, right and top, and participate in the XOR operation of the first XOR circuit XOR1 in the CA circuit. Figure 8 B in FIG. 1 and the output decode 1101 in Table 1 represent the values outputted by the data output terminal Q of the register R of the CA circuit in the three directions of left, right and bottom, and participate in the XOR operation of the first XOR circuit XOR1 in the CA circuit. Figure 8 C in the figure and the output decode 1011 in Table 1 represent the values outputted by the data output terminal Q of the register R of the CA circuit in the three directions of left, up and down, and participate in the XOR operation of the first XOR circuit XOR1 in the CA circuit. Figure 8 D in the table and the output decode 0111 in Table 1 represent the values outputted by the data output terminal Q of the register R of the CA circuit in the right and up and down directions, and participate in the XOR operation of the first XOR circuit XOR1 in the CA circuit.
[0073] In addition to the values outputted by the data output terminals Q of the registers R of the other CA circuits having at most three directions mentioned above, which participate in the XOR operation of the first XOR circuit XOR1 in this CA circuit, the values outputted by the data output terminals Q of the registers R in this CA circuit also participate in the XOR operation of the first XOR circuit XOR1. Assuming that the data output terminals Q of each register R output two states of "0" and "1", the data output terminals Q of the four registers R output a total of 16 states.
[0074] In the circuit, the XOR operation is used to represent the binary addition operation. Assuming that the output values of the data output terminals Q of the four registers R are a, b, c, and d respectively, the output value of the first XOR circuit XOR1 is f(a, b, c, d)=a+b+c+d as shown in Table 3.
[0075] Table 3
[0076] abcd 0000 0001 0010 0011 0100 0101 0110 0111 f(a, b, c, d) = a+b+c+d 0 1 1 0 1 0 0 1 abcd 1000 1001 1010 1011 1100 1101 1110 1111 f(a, b, c, d) = a+b+c+d 1 0 0 1 0 1 1 0
[0077] The debugging tool chain can send a two-bit control signal to each decoder in series in turn. In order to avoid the problem of insufficient encoding capability and cover the manufacturing defects of IC chips as much as possible, each configuration of the decompression circuit can decompress multiple test stimuli to generate multiple groups (for example, 1024 groups) of test signals.
[0078] The decompression circuit provided by the embodiment of the present application includes multiple sub-circuits, the sub-circuits include multiple CA circuits and phase shifters, the CA circuit includes a first XOR circuit and a register, the first XOR circuit includes a first input end and a second input end; the data input end of the register is coupled to the output end of the first XOR circuit; the data output end of the register is coupled to the first input end of the first XOR circuit and an input end of the phase shifter; the data output end of the register is also coupled to the second input end of the first XOR circuit in at least one other CA circuit; the phase shifter is used to output a test signal. In the decompression circuit, the randomness of the test signal is realized by the CA circuit, and a large number of test signals are expanded and output by the phase shifter to realize the testing of the device of the IC chip.
[0079] The register in the embodiment of the present application may also be as follows Fig. 9 The multi-bit register shown can save IC chip area. For example, multiple CA circuits can share a multi-bit register, and each CA circuit occupies a data input terminal (such as D1) and a data output terminal (such as Q1) of one bit.
[0080] In addition, in addition to the data input and data output of some bits in the multi-bit register being occupied by the above-mentioned decompression circuit, the data input and data output of other bits can also be used Figure 1 The compression circuit 13 described in .
[0081] like Fig.10 As shown, the decompression circuit is simplified to Figure 6 Taking a subcircuit 30 in the example, the compression circuit 13 includes an XOR gate compressor 131 and a multiple-input signature register (MISR) 132. The MISR 132 includes a CA circuit 1321. The CA circuit 1321 also includes a register and an XOR gate. The CA circuit 1321 in the compression circuit 13 shares the register with the CA circuit in the decompression circuit, but occupies different bits of the data input and data output. The structure of the CA circuit 1321 is shown in FIG. Figure 4 The description is not repeated here.
[0082] The XOR gate compressor 131 is used to perform an XOR operation on the results output by the circuit to be tested, thereby compressing the test results, and then inputting them into the CA circuit 1321 of the MISR 132 through the fourth XOR circuit XOR4. The MISR 132 is used to reduce the number of output channels and output the compressed test results through the output port of the IC chip.
[0083] It should be noted that Figure 7 The decompression circuit in can also share a multi-bit register with the compression circuit, which will not be described in detail here.
[0084] The embodiment of the present application also provides a circuit generation method, which can be executed by EDA software, and the EDA software can obtain the number of input channels and the number of scan chains fanned out by the decompression circuit, and generate the decompression circuit as described above according to the number of input channels and the number of scan chains fanned out by the decompression circuit. Optionally, a circuit of an IC chip including the decompression circuit as described above can also be generated.
[0085] An embodiment of the present application also provides a computer-readable storage medium, which is non-volatile and stores computer-readable instructions. When the computer-readable instructions are executed on a computer or a processor, the computer or the processor executes the above-mentioned circuit generation method.
[0086] The embodiment of the present application also provides a computer program product including computer-readable instructions. When the computer-readable instructions are executed on a computer or a processor, the computer or the processor executes the above-mentioned circuit generation method.
[0087] The technical effects of the above-mentioned circuit generation method, computer-readable storage medium, and computer program product refer to the technical effects of the decompression circuit and IC chip mentioned above, and will not be repeated here.
[0088] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any person skilled in the art who is familiar with the present technical field can easily think of changes or substitutions within the technical scope disclosed in the present application, which should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.
Claims
1. A decompression circuit, characterized in that: The invention comprises a plurality of sub-circuits, wherein the sub-circuit comprises a plurality of cellular automaton CA circuits and a phase shifter, wherein the CA circuit comprises a first XOR circuit, a register, a first AND gate circuit and a control circuit, wherein the first XOR circuit comprises a first input terminal and a second input terminal; the data input terminal of the register is coupled to the output terminal of the first XOR circuit; the data output terminal of the register is coupled to the first input terminal of the first XOR circuit and an input terminal of the phase shifter; the output terminal of the first AND gate circuit is coupled to the second input terminal of the first XOR circuit of the CA circuit, the first AND gate circuit comprises a third input terminal and a fourth input terminal, the third input terminal is coupled to the data output terminal of the register in at least one other CA circuit, and the fourth input terminal is coupled to an output terminal of the control circuit; The data output terminal of the register is also coupled to the second input terminal of the first XOR circuit in at least one other CA circuit; The phase shifter is used to output a test signal.
2. The decompression circuit according to claim 1, characterized in that: The first AND gate circuit includes a plurality of the third input terminals, which are used to be respectively coupled to data output terminals of registers in a plurality of other CA circuits.
3. The decompression circuit according to claim 1, characterized in that: The first XOR circuit includes a plurality of the second input terminals, the CA circuit further includes a second AND gate circuit, and an output terminal of the first AND gate circuit and an output terminal of the second AND gate circuit are respectively coupled to a plurality of the second input terminals of the first XOR circuit in the CA circuit; The second AND gate circuit includes a fifth input terminal and a sixth input terminal, the fifth input terminal is grounded, and the sixth input terminal is coupled to an output terminal of the control circuit.
4. The decompression circuit according to any one of claims 1 to 3, characterized in that: The sub-circuit also includes a second XOR circuit, which includes a seventh input terminal and an eighth input terminal, the seventh input terminal is used to input test stimulus, the eighth input terminal is coupled to the data output terminal of the register in at least one other CA circuit, and the output terminal of the second XOR circuit is coupled to the third input terminal.
5. The decompression circuit according to any one of claims 1 to 3, characterized in that: The control circuit includes a decoder; the decoder includes a plurality of output terminals, the decoder is used to receive a control signal, decode the control signal to obtain a decoding result, and output the decoding result through the plurality of output terminals.
6. The decompression circuit according to any one of claims 1 to 3, characterized in that: The register is a multi-bit register.
7. An integrated circuit chip, characterized in that: The invention comprises a circuit to be tested and a decompression circuit as claimed in any one of claims 1 to 6, wherein an output end of a phase shifter of the decompression circuit is coupled to an input end of the circuit to be tested through a scan chain.
8. A circuit generation method, characterized in that: include: Get the number of input channels and the number of scan chains fanned out by the decompression circuit; The decompression circuit as claimed in any one of claims 1 to 6 is generated according to the number of the input channels and the number of the scan chains.
9. The method according to claim 8, characterized in that Also includes: The circuit of the integrated circuit chip as claimed in claim 7 is generated according to the number of the input channels and the number of the scan chains.
10. A computer-readable storage medium, characterized in that: The computer-readable storage medium is non-volatile, and stores computer-readable instructions. When the computer-readable instructions are executed on a computer, the computer is enabled to execute the method according to any one of claims 8 to 9.
11. A computer program product, characterized in that The computer program product includes computer-readable instructions, and when the computer-readable instructions are executed on a computer, the computer is enabled to execute the method according to any one of claims 8 to 9.
Citation Information
Patent Citations
Continuous application and decompression of test patterns and selective compaction of test responses
US20180017622A1