Memory with address optional data poisoning circuitry and related systems, apparatuses, and methods

Abstract

Disclosed herein are memories having address selectable data poisoning circuitry, and related systems, devices, and methods. In one embodiment, a memory device includes circuitry operably connected to a memory array. The circuitry can include a memory row address register and / or a memory column address register. A standard access command or a mode register write command can be used to load a memory row address or a memory column address into the memory row address register or the memory column address register, respectively. During a read operation for a second memory row and / or column of the memory array, the circuitry can compare the second memory row to a first memory row and / or compare the second memory column to a first memory column, and can poison data bits read from the memory array before the data bits are output from the memory device if the first and second memory row addresses match and / or if the first and second memory column addresses match.

Description

[0001] Cross-reference of related applications

[0002] This application claims priority to U.S. Provisional Patent Application No. 63 / 295,064, filed December 30, 2021, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] This disclosure relates to memory systems, apparatus, and methods. More specifically, this disclosure relates to memories having address-selectable data poisoning circuitry, and related systems, apparatus, and methods. Background Technology

[0004] Memory devices are widely used to store information associated with various electronic devices, such as computers, wireless communication devices, cameras, digital displays, and the like. Memory devices are often provided as internal semiconductor integrated circuits and / or external removable devices in computers or other electronic devices. Many different types of memory exist, including volatile and non-volatile memory. Volatile memory (including Static Random Access Memory (SRAM), Dynamic Random Access Memory (DRAM), and Synchronous Dynamic Random Access Memory (SDRAM)) requires an external power supply to maintain its data. In contrast, non-volatile memory retains its stored data even without an external power supply. Non-volatile memory can be used in various technologies, including flash memory (such as NAND and NOR), phase-change memory (PCM), ferroelectric random access memory (FeRAM), resistive random access memory (RRAM), and magnetic random access memory (MRAM). Improvements to memory devices typically include increasing memory cell density, increasing read / write speeds or otherwise reducing operational latency, improving reliability, increasing data retention, reducing power consumption or lowering manufacturing costs, and other metrics. Summary of the Invention

[0005] On one hand, this disclosure provides a memory device comprising: a memory array having a plurality of memory rows and a plurality of memory columns; and a circuit system operatively coupled to the memory array, wherein the circuit system includes (a) one or more memory row address registers or (b) one or more memory column address registers, wherein the circuit system is configured to load a memory row address corresponding to a memory row in the plurality of memory rows into the one or more memory row address registers or to load a memory column address corresponding to a memory column in the plurality of memory columns into the one or more memory column address registers, and wherein the circuit system is further configured during a read or write operation for (i) the memory row address loaded into the one or more memory row address registers or (ii) the memory column address loaded into the one or more memory column address registers to change a first data state of the data bit to a second data state different from the first data state before the data bit stored in the memory array and corresponding to the memory row address or the memory column address is output from the memory device as part of the read operation or before the data bit is stored in the memory array as part of the write operation.

[0006] On the other hand, this disclosure further provides a method comprising: identifying at least one memory row or at least one memory column of a memory array of a memory device for data poisoning; performing a read or write operation for a memory row address of a first memory row and a memory column address of a first memory column; determining that the memory row address corresponds to a memory row in the at least one memory row or that the memory column address corresponds to a memory column in the at least one memory column; and in response to the determination and when performing the read or write operation, changing a first data state of the data bit to a second data state, wherein the second data state is different from the first data state, before the data bit read from or written to the memory array is output from the memory device as part of the read operation or before the data bit is stored in the memory array as part of the write operation.

[0007] In another aspect, this disclosure further provides a memory system comprising: a memory controller; and a memory device operatively connected to the memory controller, wherein the memory device includes: a memory array; and a circuit system coupled to the memory array and including (a) one or more memory row address registers or (b) one or more memory column address registers, wherein the circuit system is configured to: load a first memory row address or a first memory column address recognized by the memory controller into the one or more memory row address registers or the one or more memory column address registers respectively; and when the memory device performs a read or write operation for a second memory row address or a second memory column address: compare (a) the second memory row address. The data state of a data bit read from the memory array is changed to a second data state different from the first data state when (i) the second memory row address matches the first memory row address or is included in at least a portion of the memory row address range identified by the first memory row address or (ii) the second memory column address matches the first memory column address or is included in at least a portion of the memory column address range identified by the first memory column address. This causes the data bit to be output from the memory device as a first bit error as part of the read operation or stored in the memory array as a second bit error as part of the write operation. Attached Figure Description

[0008] The following figures may be referenced for a better understanding of many aspects of this disclosure. The components in the figures are not necessarily drawn to scale. The focus is on clearly illustrating the principles of this disclosure. The figures should not be construed as limiting this disclosure to the specific embodiments depicted, but are provided for explanation and understanding only.

[0009] Figure 1A This is a block diagram illustrating a memory system configured according to various embodiments of the present technology.

[0010] Figure 1B This is a block diagram illustrating a memory device configured according to various embodiments of the present technology.

[0011] Figure 1C It is a partial schematic representation of various registers that may be included in an address-selectable data poisoning circuit system configured according to various embodiments of the present technology.

[0012] Figure 1D This is a partial schematic representation of the poisoning control logic circuit system of an address-selectable data poisoning circuit system configured according to various embodiments of the present technology.

[0013] Figure 1E This is a partial schematic representation of the data path poisoning control logic circuit system of the address selectable data poisoning circuit system configured according to various embodiments of the present technology.

[0014] Figure 2 This is a partial schematic representation of the shielding circuit system of an address-selectable data poisoning circuit system configured according to various embodiments of the present technology.

[0015] Figure 3 This is a flowchart illustrating a method for operating address-selectable data poisoning circuit systems according to various embodiments of the present technology.

[0016] Figure 4 This is a schematic diagram of a system comprising a memory device or system configured according to various embodiments of the present technology. Detailed Implementation

[0017] As discussed in more detail below, the technology disclosed herein relates to memories with address-selectable data poisoning circuitry and associated systems, apparatus, and methods. In some embodiments, the memory device may include a circuitry having multiple registers configured to store user-identified memory row address entries, user-identified memory column address entries, and / or user-identified DQ terminals for data bit poisoning. In operation, the circuitry may be configured to poison (e.g., invert) data bits when data bits corresponding to user-identified memory rows, user-identified memory columns, and / or user-identified DQ terminals are read from the memory device. Therefore, the circuitry can be used to output known bit errors via selected DQ terminals of the memory device, which can be used to verify, debug, and / or decode various operations of the memory device and / or the corresponding memory system. Those skilled in the art will understand that this technology may have additional embodiments and may not require further reference below. Figures 1A to 4 The present technology is practiced in accordance with several details of the described embodiments.

[0018] In the embodiments described below, the memory devices and systems are primarily described in the context of devices incorporating DRAM storage media. However, memory devices configured according to other embodiments of the present technology may include other types of memory devices and systems incorporating other types of storage media, including PCM, SRAM, FRAM, RRAM, MRAM, read-only memory (ROM), erasable programmable ROM (EPROM), electrically erasable programmable ROM (EEROM), ferroelectric, magnetoresistive and other storage media, including non-volatile flash (e.g., NAND and / or NOR) storage media.

[0019] A. Overview

[0020] Many memory systems are configured to identify and respond to conditions that cause them to exhibit errors or failures. For example, many memory systems employ error correction code (ECC) schemes to identify and / or correct bit errors in data read from memory cells of the memory device. As another example, many memory systems employ post-packaging repair (PPR) operations to replace defective memory lines with redundant memory lines by remapping the logical address of the defective memory line (e.g., a word line) to the physical address of a redundant memory line.

[0021] Memory systems typically perform operations in response to errors, but rarely provide users with insight into whether the operation was performed as expected and / or whether the operation successfully corrected the error. For example, when a memory system uses a Pre-Process Rectification (PPR) operation to replace a defective memory line with a redundant one or more, or an ECC operation to correct one or more bit errors, the system typically performs the PPR or ECC operation without notifying the user that: (a) the error was identified; (b) the type, location, and / or other information about the error; (c) the PPR or ECC operation was performed; (d) the PPR or ECC operation was performed appropriately and / or accurately; and / or (e) the PPR or ECC operation successfully corrected the identified error. In other words, users of these memory systems typically cannot confirm that: (i) the memory system accurately identified the fault; (ii) the memory system accurately performed the appropriate operation in response to the identified fault; and / or (iii) the operation performed by the memory system successfully corrected the fault.

[0022] Therefore, many users request sample memory devices and / or systems from manufacturers that have known faults that allow them to verify various operational aspects of the memory device and / or system. In response, manufacturers typically provide defective memory devices and / or systems with known faults. However, such defective memory devices and / or systems represent a small subset of all memory devices and / or systems manufactured by the manufacturer, and it is relatively expensive for the manufacturer to intentionally produce (i) defective memory devices and / or systems and / or (ii) memory devices and / or systems produced solely for the purpose of verifying device / system operation.

[0023] To address these issues, a memory device and / or system configured according to this technology may include an address-selectable data poisoning circuit system configured to poison data bits when user-identified data bits are read from the memory device. For example, a user may identify (a) a target memory row or range of a memory array, (b) a target memory column or range of a memory array, and / or (c) one or more DQ terminals of the memory device from which poisoned data bits can be output. When data bits corresponding to the target memory row and / or target memory column (a) are read from the memory array via internal data lines corresponding to the DQ terminals of the memory device enabled to output poisoned data bits, and when (b) the address-selectable data poisoning circuit system is enabled, the address-selectable data poisoning circuit system may poison the data bits and output the poisoned data bits via the corresponding DQ terminals of the memory device.

[0024] In this manner, memory devices and / or systems configured according to this technology can use an address-selectable data poisoning circuitry to generate known bit errors or faults that can be output from the memory device. These known bit errors or faults can then be used to verify, debug, and / or decode various operations of the memory device and / or system, such as ECC operations, PPR operations, and / or system address and / or DQ scrambling. In some embodiments, the address-selectable data poisoning circuitry can be disabled to allow the corresponding memory device and / or system to operate normally (e.g., without poisoning the data bits read from the memory device). Therefore, memory devices and / or systems of this technology avoid the practice of identifying or intentionally creating defective memory devices with known faults that are provided to users for the purpose of verifying, debugging, and / or decoding various operations of the memory device and / or system.

[0025] B. Selected embodiments of the memory system and associated apparatus and methods

[0026] Figure 1A This is a block diagram illustrating a memory system 102 configured according to various embodiments of the present technology. In one embodiment, the memory system 102 is a dual in-line memory module (DIMM) having one or more memory devices 100 (e.g., one or more DRAM memory devices). Although Figure 1A The image shows a single memory device 100, but in some embodiments, the memory system 102 may comprise one or more modules or layers having multiple memory devices 100. Well-known components of the memory system 102 have been shown in [the original text]. Figure 1A Details are omitted and will not be described in detail below to avoid unnecessarily obscuring aspects of this technology.

[0027] One or more memory devices 100 of the memory system 102 may be connected to an electronic device or component thereof capable of temporarily or permanently storing information using memory. For example, Figure 1A The memory device 100 is operatively connected to the host device 108. The host device 108 may be a computing device, such as a desktop or portable computer, server, handheld device (e.g., mobile phone, tablet computer, digital reader, digital media player), or components thereof (e.g., central processing unit, coprocessor, dedicated memory controller, etc.). The host device 108 may be: a networking device (e.g., switch, router, etc.); a recorder of digital images, audio, and / or video; a vehicle; an electrical appliance; a toy; or any of many other products. In one embodiment, the host device 108 may be directly connected to the memory device 100 (e.g., via a communication bus with signal traces (not shown)). Alternatively or concurrently, the host device 108 may be indirectly connected to the memory device 100 (e.g., via a networking connection or through an intermediate device, such as through the memory controller 101 and / or through the communication bus 117 with signal traces).

[0028] The memory device 100 of the memory system 102 is operably connected to the memory controller 101 via a command / address (CMD / ADDR) bus 118 and a data (DQ) bus 119. (See below for more details.) Figure 1B In more detail, the CMD / ADDR bus 118 and DQ bus 119 can be used by the memory controller 101 to transmit commands, memory addresses, and / or data to the memory device 100. In response, the memory device 100 can execute commands received from the memory controller 101. For example, if a write command is received from the memory controller 101 via the CMD / ADDR bus 118, then the memory device 100 (a) can receive data from the memory controller 101 via the data DQ bus 119 and (b) can write the data to the memory cell corresponding to the memory address received from the memory controller 101 via the CMD / ADDR bus 118. As another example, in the event of a read command being received from the memory controller 101 via the CMD / ADDR bus 118, the memory device 100 can output data from the memory cell corresponding to the memory address received from the memory controller 101 via the CMD / ADDR bus 118 to the memory controller 101 via the data DQ bus 119. As described in more detail below, the memory controller 101 may include an ECC component (not shown) configured to encode and / or decode data sent to or received from the memory device 100 (e.g., detect and / or correct bit errors contained in the data).

[0029] Figure 1B It belongs to Figure 1AAnd a block diagram of the memory device 100 configured according to various embodiments of the present technology. As shown, the memory device 100 may employ multiple external terminals. The external terminals may include command and address terminals, which are operatively connected to the CMD / ADDR bus 118 ( Figure 1A This is to receive the command signal CMD and the address signal ADDR, respectively. External terminals may further include a chip select terminal for receiving the chip select signal CS, a clock terminal for receiving clock signals CK and CKF, and data terminals DQ, DQS, DBI, and DMI (e.g., operably connected to...). Figure 1A The memory device 100 may additionally or alternatively include a DQ bus 119 and / or power supply terminals VDD, VSS, and VDDQ. For example, in embodiments where the memory device 100 is a Double Data Rate (DDR) memory device or a Low Power DDR4 (LPDDR4) memory device, the memory device 100 may include clock terminals CK and CKF for receiving differential clock signals and a bidirectional data strobe terminal DQS for transmitting and / or receiving differential data strobe signals DQS_t and DQS_c. As another example, in embodiments where the memory device 100 is a Graphics DDR (GDDR) or LPDDR5 (LPDDR5) memory device, the memory device 100 may include clock terminals CK and CKF for receiving command / address clock signals, data clock terminals for receiving data clock signals WCK and WCKF, and a unidirectional read data strobe terminal RDQS (e.g., replacing the data strobe DQS terminal).

[0030] The power supply terminal of the memory device 100 can be supplied with a power supply potential V DD and V SS These power supply potentials V DD and V SS It can be supplied to the internal voltage generator circuit 170. The internal voltage generator circuit 170 can be based on the power supply potential V. DD and V SS Various internal potentials V are generated PP V OD V ARY V PERI And similar. Internal potential V PP It can be used in the line decoder 140, internal potential V OD and V ARY It can be used in a sense amplifier included in a memory array 150 of a memory device 100, and the internal potential V PERI It can be used in many other circuit blocks.

[0031] The power supply terminal can also be supplied with a power supply potential V. DDQ Electricity supply potential V DDQ Can be connected to the power supply potential V SS Together, they are supplied to the input / output (I / O) circuit 160. In embodiments of this technology, the power supply potential V DDQ It can be the same as the power supply potential V DD The potential of the power supply. In another embodiment of this technology, the power supply potential V DDQ It can be different from the power supply potential V DD The potential of the dedicated power supply. However, the potential V of the dedicated power supply. DDQ It can be used in I / O circuit 160 to prevent power supply noise generated by I / O circuit 160 from propagating to other circuit blocks.

[0032] The clock terminal, digital clock terminal, and / or additional clock terminal may be supplied with external clock signals and / or complementary external clock signals. External clock signals CK, CKF, WCK, and / or WCKF may be supplied to clock input circuit 133. CK and CKF signals may be complementary, and WCK and WCKF signals may also be complementary. Complementary clock signals may have opposite clock levels and simultaneously transition between opposite clock levels. For example, when the clock signal is at a low clock level, the complementary clock signal is at a high level, and when the clock signal is at a high clock level, the complementary clock signal is at a low clock level. Furthermore, when the clock signal transitions from a low clock level to a high clock level, the complementary clock signal transitions from a high clock level to a low clock level, and when the clock signal transitions from a high clock level to a low clock level, the complementary clock signal transitions from a low clock level to a high clock level.

[0033] In embodiments where the memory device 100 includes both a clock terminal and a data clock terminal, the clock signals CK and CKF received at the clock terminal may have the same or different frequencies than the data clock signals WCK and WCKF received at the data clock terminal. For example, the data clock signals WCK and WCKF may each have frequencies greater than (e.g., twice, four times, etc.) the frequencies of the clock signals CK and CKF, depending on the operating mode of the memory device 100. More specifically, the data clock signals WCK and WCKF: (a) may have frequencies twice the frequencies of the clock signals CK and CKF, respectively, when the memory device 100 operates in a low-power operating mode; and (b) may have frequencies four times the frequencies of the clock signals CK and CKF, respectively, when the memory device 100 operates in a high-speed or high-data-transfer operating mode. In these and other embodiments, the data strobe signal output via the read data strobe terminal RDQS may be generated using or at least partially based on the data clock signals WCK and WCKF. In embodiments where the memory device 100 does not include a data clock terminal, the data strobe signal output and / or received via the DQS terminal may be generated using or at least partially based on clock signals CK and CKF.

[0034] An input buffer included in clock input circuit 133 can receive an external clock signal. For example, when enabled by the CKE signal from command decoder 115, the input buffer can receive CK and CKF signals and / or WCK and WCKF signals. Clock input circuit 133 can receive an external clock signal to generate an internal clock signal ICLK. The internal clock signal ICLK can be supplied to internal clock circuit 130. Internal clock circuit 130 can provide various phase and frequency control internal clock signals based on the internal clock signal ICLK received from command decoder 115 and the clock enable signal CKE. For example, internal clock circuit 130 may include a clock path ( Figure 1B (Not shown), it receives the internal clock signal ICLK and provides various clock signals (not shown) to the command decoder 115. The internal clock circuit 130 can further provide input / output (I / O) clock signals. The I / O clock signals can be supplied to I / O circuit 160 and can be used, for example, to determine the clock signal via the DQ bus 119 ( Figure 1AThe timing signals for the output timing and / or input timing of the transmitted data. The I / O clock signal can be provided at multiple clock frequencies, allowing data to be output from and input to the memory device 100 at different data rates. Higher clock frequencies are desired when high memory speed is required. Lower clock frequencies are desired when low power consumption and / or more relaxed timing margins are required. The internal clock signal ICLK can also be supplied to the timing generator 135, thus generating various internal clock signals that can be used by the command decoder 115, column decoder 145, I / O circuitry 160, and / or other components of the memory device 100.

[0035] Memory device 100 may include an array of memory cells, such as memory array 150. The memory cells of memory array 150 may be arranged in multiple memory regions, and each memory region may include multiple word lines (WLs), multiple bit lines (BLs), and multiple memory cells arranged at the intersections of word lines and bit lines. In some embodiments, a memory region may be one or more banks or another arrangement of memory cells (e.g., half-banks, subarrays within banks, etc.). In these and other embodiments, the memory regions of memory array 150 may be arranged in one or more groups (e.g., one or more banks, one or more logical memory layers, or dies, etc.). The memory cells in memory array 150 may include any of several different memory media types (including capacitive, magnetoresistive, ferroelectric, phase-change, or similar). The selection of word lines WLs may be performed by row decoder 140, and the selection of bit lines BLs may be performed by column decoder 145. A sense amplifier (SAMP) may be provided for a corresponding bit line BL and connected to at least one corresponding local I / O line pair (LIOT / B), which may in turn be coupled to at least one corresponding main I / O line pair (MIOT / B) via a transmission gate (TG) (which may be used as a switch). The memory array 150 may also include board lines and corresponding circuitry for managing its operation.

[0036] The command terminal and address terminal can respectively supply address signals and memory address signals from outside the memory device 100. The address signals and memory address signals supplied to the address terminals can be transmitted to the address decoder 110 via the command / address input circuit 105. The address decoder 110 can receive address signals and supply the decoded row address signal (XADD) to the row decoder 140 and the decoded column address signal (YADD) to the column decoder 145. The address decoder 110 can also receive address signals and supply the memory address signal (BADD) to both the row decoder 140 and the column decoder 145.

[0037] Command and address terminals may be supplied with command signal CMD, address signal ADDR, and chip select signal CS (e.g., from memory controller 101 and / or host device 108). Command signals may represent various memory commands (e.g., access commands, which may include read and write commands). The select signal CS can be used to select memory device 100 to respond to commands and addresses provided to the command and address terminals. When a valid CS signal is provided to memory device 100, commands and addresses can be decoded and memory operations can be performed. Command signal CMD may be provided as internal command signal ICMD to command decoder 115 via command / address input circuitry 105. Command decoder 115 may include circuitry to decode internal command signal ICMD to generate various internal signals and commands for performing memory operations, such as row command signals for selecting word lines and column command signals for selecting bit lines. Internal command signals may also include output and input activation commands, such as timing commands (not shown) to command decoder 115. The command decoder 115 may further include one or more registers 128 for tracking various counts or values, such as the number of times a memory region (e.g., a memory row) has been activated.

[0038] When a read command is issued to a memory bank with open memory rows (e.g., memory rows opened in response to a previous activation command) and the column address is supplied in a timely manner, read data can be read from the memory cell in memory array 150 specified by the row address and column address. The read command can be received by command decoder 115, which can provide internal commands to I / O circuitry 160, such that read data can be output from data terminals DQ, DBI, and DMI via read / write (RW) amplifier 155 and I / O circuitry 160 according to read data strobe timing signals output from memory device 100 via DQS or RDQS terminals. As a specific example, memory device 100 can (a) transmit the read data strobe timing signals to memory controller 101 (… Figure 1A (a) and (b) the read data is transferred to the memory controller 101 via the DQ terminal of the memory device 100. The read data strobe timing signal can be used as a clock to strobe the read data to the memory controller 101. In other words, the read data strobe timing signal can be used to indicate when the memory controller 101 samples the read data it receives from the memory device 100.

[0039] In some embodiments, data can be read from a memory device 100 that is programmable (e.g., programmed into a mode register). Figure 1BThe read delay information RL is provided for a time period not shown in the diagram. The read delay information RL can be defined based on the clock cycle of the CK clock signal. For example, the read delay information RL can be the number of clock cycles of the CK signal after the read command is received by the memory device 100 when the associated read data is provided.

[0040] When a write command is issued to a memory bank with open memory rows (e.g., memory rows opened in response to a previous activation command) and the column address is supplied in a timely manner, write data can be supplied to the data terminals DQ, DBI, and DMI according to the DQS, WCK, and / or WCKF clock signals. The write command can be received by a command decoder 115, which can provide an internal command to I / O circuitry 160, such that write data can be received by the data receiver in I / O circuitry 160 and supplied to memory array 150 via I / O circuitry 160 and RW amplifier 155. Write data can be written to memory cells specified by row and column addresses. In some embodiments, write data can be supplied to the data terminals at a time defined by write delay WL information. The write delay WL information can be programmed into memory device 100, for example, programmed into a mode register (…). Figure 1B (Not shown in the text). The write delay information WL can be defined based on the clock cycle of the CK clock signal. For example, the write delay information WL can be the number of clock cycles of the CK signal after the write command is received by the memory device 100 when the associated write data is received.

[0041] As a specific instance of a write operation, memory controller 101 ( Figure 1A The memory controller 101 can (a) supply an external DQS signal (e.g., a differential write data strobe (WDQS) signal including DQS_t and DQS_c) to the DQS terminal of the memory device 100 and (b) supply write data to the DQ terminal of the memory device 100. The external DQS signal can be used as a clock to strobe write data into the memory device 100 via the DQ terminal. In other words, the external DQS signal can be used to indicate when the memory device 100 samples the write data received at the DQ terminal of the memory device 100. In some embodiments, when the memory controller 101 ( Figure 1A When initiating a write operation, the memory controller 101 may begin switching the external DQS signal during the write preamble cycle to notify the memory device 100 that write data will soon begin to be transferred to the DQ terminals of the memory device 100. After the preamble cycle, the memory controller 101 may supply write data to the DQ terminals of the memory device 100 according to the external DQS signal. The memory device 100 may also latch and register the write data received at the DQ terminals at at least partially based on the rising and / or falling edges of the internal DQS signal generated by the external DQS signal.

[0042] As shown, memory device 100 further includes address-selectable data poisoning circuitry 180 (“circuitry 180”). In the illustrated embodiment, circuitry 180 is operatively connected to row decoder 140, column decoder 145, and I / O circuitry 160 of memory device 100. Therefore, Figure 1B The circuit system 180 can receive physical row addresses from the row decoder 140, physical column addresses from the column decoder 145, and / or information (e.g., I / O, burst bits, etc.) from the I / O circuit 160 via the DQ terminal of the memory device 100. In these and other embodiments, the circuit system 180 can output one or more signals to the I / O circuit 160 that cause the I / O circuit 160 to 'poison' (e.g., invert, change, alter, destroy, etc.) the selected data bits read from the memory array 150 during a read operation of the memory device 100.

[0043] By configuring circuitry 180 to receive physical row addresses from row decoder 140, circuitry 180 can utilize the redundancy matching circuitry (not shown) of memory device 100, making circuitry 180 redundancy-aware (e.g., aware of any redundant memory rows that have already been used in a PPR operation to replace defective memory rows of memory array 150). In other embodiments, circuitry 180 can be configured to receive logical memory row addresses (e.g., row address signals XADD) before the logical memory row addresses are decoded by row decoder 140. In such embodiments, circuitry 180 may be non-redundancy-aware. In these and other embodiments, circuitry 180 can be configured to receive logical memory column addresses (e.g., column address signals YADD) before the logical memory column addresses are decoded by column decoder 145.

[0044] As discussed in more detail below, circuit system 180 may contain multiple registers. Figure 1C ), poisoning control logic circuit system ( Figure 1D ) and a data path poisoning control logic circuit system that can be used to poison the selected data bits read from the memory device 100. Figure 1EMore specifically, the memory row address and / or memory column address may be loaded into one or more registers of the circuit system 180. The circuit system 180 may also instruct the I / O circuitry 160 of the memory device 100 to poison one or more data bits corresponding to the memory row address and / or memory column address loaded into the registers of the circuit system 180 during a read operation of the memory device 100. In some embodiments, data poisoning may occur before the data bits are decoded and / or cleared from the ECC circuitry 157 of the memory device 100 (e.g., to enable verification and / or debugging of the ECC operation of the memory device 100). The ECC circuitry 157 in... Figure 1B It is shown as being outside the I / O circuitry 160, but in some embodiments it may be included within the I / O circuitry 160 of the memory device 100 or elsewhere. Figure 1B Other locations within the memory device 100 besides those shown in the image. Alternatively, data poisoning may occur after the ECC circuit 157 of the data bit clearing memory device 100 but before the data bit is output from the DQ terminal, such that at least one bit error is included in the data output from the memory device 100. In other words, the circuit system 180 can be used to generate and / or output known bit errors via a user-selected DQ pin and / or in user-selected data bits corresponding to user-selected memory rows and / or user-selected memory columns of the memory array 150. Known bit errors can then be used to verify, debug, and / or decode various operations of the memory device 100 and / or memory system 102 (e.g., ECC operation, PPR operation, system address scrambling, system DQ scrambling, etc.).

[0045] Figure 1C It can be included in Figure 1B The diagram illustrates portions of various registers 181 to 186 in the circuit system 180. As shown, the circuit system 180 includes a control register 181, memory row address registers 182a to 182c (“Row Address Registers 182a to 182c”), memory row address mask registers 183a to 183c (“Row Address Mask Registers 183a to 183c”), memory column address registers 184a and 184b (“Column Address Registers 184a and 184b”), memory column address mask registers 185a and 185b (“Column Address Mask Registers 185a and 185b”), and I / O register 186. In some embodiments, the circuit system 180 does not include row address mask registers 183a to 183c, column address mask registers 185a and 185b, and / or I / O register 186. Alternatively or additionally, the circuit system 180 may include, in addition to, other registers. Figure 1COne or more other or additional registers not specified herein. For example, circuit system 180 may include one or more sets (not shown) of additional memory row address mask registers and / or one or more sets (not shown) of additional memory column address mask registers (e.g., to facilitate poisoning of non-contiguous ranges of memory rows and / or memory columns).

[0046] Control register 181 can be used to control the operation of circuitry 180. In some embodiments, control register 181 is user-programmable, for example, by writing MRW commands via a mode register. As shown, control register 181 includes six utilization bits: (a) reset RST bit, (b) enable EN bit, (c) program PGM bit, (d) bit BIT bit, (e) column COL bit, and (f) row ROW bit. The EN bit of control register 181 can be used to enable or disable circuitry 180. For example, when the EN bit is asserted (e.g., written to a "high" or "1" state), memory device 100 can enter an error generation mode in which memory device 100 can interact with and / or utilize circuitry 180 to poison select data bits read from memory array 150. On the other hand, when the EN bit is not asserted (e.g., written to a "low" or "0" state), the memory device 100 can operate under normal operation (e.g., the memory device 100 can read data from the memory array 150 and / or the memory device 100 can read data without the memory device 100 loading other registers of the circuit system 180 and / or without using the circuit system 180 to poison the data bits).

[0047] The PGM bit of control register 181 can be used to enable or disable programming of one or more registers of circuit system 180 using standard access operations (described in more detail below). For example, asserting that the PGM bit of control register 181 can enable programming of row address registers 182a to 182c, column address registers 184a and 184b, and / or I / O register 186 using standard access operations. In embodiments where circuit system 180 includes row address mask registers 183a to 183c and / or column address mask registers 185a and 185b, asserting the PGM bit can enable programming of row address mask registers 183a to 183c and / or column address mask registers 185a and 185b using standard access operations. On the other hand, whenever the PGM bit is not asserted, programming of row address registers 182a to 182c, row address mask registers 183a to 183c, column address registers 184a and 184b, column address mask registers 185a and 185b, and / or I / O register 186 can be disabled using standard access operations. In some embodiments, row address registers 182a to 182c, column address registers 184a and 184b, I / O register 186, row address mask registers 183a to 183c, and / or column address mask registers 185a and 185b can be additionally or alternatively programmed using MRW commands (e.g., regardless of the state of the PGM bit in control register 181).

[0048] The RST bit of control register 181 is used to reset one or more registers of circuit system 180 (e.g., to an all-low or "0" state or another desired state). For example, when the RST bit of control register 181 is asserted, circuit system 180 may reset row address registers 182a to 182c and / or column address registers 184a and 184b. In some embodiments, asserting the RST bit may additionally reset row address mask registers 183a to 183c, column address mask registers 185a and 185b, and / or I / O register 186.

[0049] The COL, ROW, and BIT bits of control register 181 are used to specify which data bits will be poisoned by circuitry 180 during a read operation of memory device 100. For example, when all COL, ROW, and BIT bits are asserted, circuitry 180 may be configured to poison only the data bits corresponding to the intersection of the memory row and the memory column when the data bits are read from memory array 150 and before the data bits are output from the DQ terminal of memory device 100 during a read operation of memory device 100 for memory rows identified in row address registers 182a to 182c and memory columns identified in column address registers 184a and 184b. As another example, when the COL and ROW bits of control register 181 are asserted but the BIT bit is left unasserted, circuitry 180 can poison data bits during a read operation of memory device 100, which is identified in row address registers 182a to 182c and in column address registers 184a and 184b, when (a) each of the data bits corresponding to the memory row and (b) each of the data bits corresponding to the memory column are read from memory array 150 and before the data bits are output from one or more DQ terminals of memory device 100. In other words, asserting the COL and ROW bits of control register 181 without asserting the BIT bit can cause circuitry 180 to poison a cross-shaped pattern of data bits corresponding to the memory rows and memory columns loaded into row address registers 182a to 182c and column address registers 184a and 184b, respectively. As yet another example, when only the COL bit of control register 181 is asserted while the ROW and BIT bits are not asserted, circuit system 180 (a) effectively ignores the memory row addresses loaded into row address registers 182a to 182c and (b) poisons each of the data bits corresponding to the memory column during a read operation for memory device 100 identified in column address registers 184a and 184b, when the data bits are read from memory array 150 and before the data bits are output from one or more DQ terminals of memory device 100. Similarly, when only the ROW bit of control register 181 is asserted while the COL and BIT bits are not asserted, circuit system 180 (a) effectively ignores the memory column addresses loaded into column address registers 184a and 184b and (b) poisons each of the data bits corresponding to the memory row during a read operation for memory device 100 identified in row address registers 182a to 182c, when the data bits are read from memory array 150 and before the data bits are output from one or more DQ terminals of memory device 100.

[0050] In some embodiments, the control register 181 may include, except for Figure 1CAdditional utilization bits beyond those shown in the table. For example, control register 181 may contain mask bits. When the mask bits are not asserted but the PGM bits are asserted, circuitry 180 (a) may load memory row addresses into row address registers 182a to 182c and / or (b) may load memory column addresses into column address registers 184a and 184b. On the other hand, when the mask bits are asserted (e.g., while the PGM bits are not asserted), circuitry 180 (a) may load memory row addresses into row address mask registers 183a to 183c and / or (b) may load memory column addresses into column address mask registers 185a and 185b. As another example, control register 181 may contain mask utilization bits. When the mask utilization bit is asserted, circuit system 180(a) can use the memory row address entries loaded into row address mask registers 183a to 183c to mask the memory row address entries loaded into row address mask registers 182a to 182c to define a target memory row range and / or (b) can use the memory column address entries loaded into column address mask registers 185a and 185b to mask the memory column address entries loaded into column address registers 184a and 184b to define a target memory column range. On the other hand, when the mask utilization bit is not asserted, circuit system 180(a) can ignore the memory row address entries loaded into row address mask registers 183a to 183c and only use the memory row address entries loaded into row address registers 182a to 182c to identify the target memory row and / or (b) can ignore the memory column address entries loaded into column address mask registers 185a and 185b and only use the memory column address entries loaded into column address registers 184a and 184b to identify the target memory column.

[0051] As discussed above, when the PGM bit of control register 181 is asserted, the memory row address is loaded into row address registers 182a to 182c and / or row address mask registers 183a to 183c. In embodiments where circuitry 180 does not include row address mask registers 183a to 183c, the memory row address loaded into row address registers 182a to 182c identifies a single target memory row for data poisoning during read operations of memory device 100, and data poisoning corresponding to one or more data bits of the target memory row is enabled when the EN bit and ROW bit of control register 181 are asserted. In embodiments where circuitry 180 includes row address mask registers 183a to 183c, the memory row address loaded into row address registers 182a to 182c and the memory row address loaded into row address mask registers 183a to 183c can be used to identify a target memory row range (hereinafter referred to as...). Figure 2(For more details) Data poisoning is performed during a read operation of the memory device 100, and data poisoning corresponding to one or more data bits contained in the memory row within the target range is enabled when the EN bit and ROW bit of the control register 181 are asserted.

[0052] As shown, each memory row address loaded into row address registers 182a to 182c is a set of 23 bits that identifies a specific memory bank and a specific memory row within a specific group of memory banks in memory array 150. The memory row addresses loaded into row address mask registers 183a to 183c may contain a similar number and structure of bits. In some embodiments where row address registers 182a to 182c and / or row address mask registers 183a to 183c are programmed (e.g., only) using standard access operations of memory device 100 (described in more detail below), the memory row addresses loaded into row address registers 182a to 182c and / or row address mask registers 183a to 183c may omit the bank address and / or bank group, because standard access operations can be repeated across each bank of memory array 150.

[0053] Other embodiments of this technology may include memory row addresses containing different numbers and / or structures of bits. For example, unused bits in row address registers 182c and / or row address mask registers 183c may be used to specify whether the address loaded into row address registers 182a to 182c and / or row address mask registers 183a to 183c (a) corresponds to a defective memory row of memory array 150 and / or (b) is the address of a redundant memory row of memory array 150 used to replace the defective memory row. This redundancy identifier bit may be used by circuitry 180 to ensure that appropriate data bits are poisoned during read operations of memory device 100 when data is read from a redundant memory row of memory array 150 (e.g., not a user-selected defective memory row).

[0054] As discussed above, memory column addresses are loaded into column address registers 184a and 184b and / or column address mask registers 185a and 185b. In embodiments where circuitry 180 does not include column address mask registers 185a and 185b, the memory column addresses loaded into column address registers 184a and 184b identify a single target memory column for data poisoning during read operations of memory device 100, and data poisoning corresponding to one or more data bits of the target memory column is enabled when the EN and COL bits of control register 181 are asserted. In embodiments where circuitry 180 includes column address mask registers 185a and 185b, the memory column addresses loaded into column address registers 184a and 184b and the memory column addresses loaded into column address mask registers 185a and 185b can be used to identify a range of target memory columns (hereinafter referred to as...). Figure 2 (For more details) Data poisoning is performed during a read operation of the memory device 100, and data poisoning corresponding to one or more data bits contained in the memory column within the target range is enabled when the EN bit and COL bit of the control register 181 are asserted.

[0055] As shown, each memory column address loaded into column address registers 184a and 184b is a set of 16 bits that identifies a specific memory bank and a specific memory column within a specific group of memory banks in memory array 150. The memory column addresses loaded into column address mask registers 185a and 185b may contain a similar number and structure of bits. In some embodiments where column address registers 184a and 184b and / or column address mask registers 185a and 185b are programmed (e.g., only) using standard access operations of memory device 100 (described in more detail below), the memory column addresses loaded into column address registers 184a and 184b and / or column address mask registers 185a and 185b may omit the bank address and / or bank group, since standard access operations can be repeated across each bank of memory array 150. In other embodiments of this technology, the memory column addresses may contain different... Figure 1C The number of bits and / or the structure shown in the document.

[0056] As discussed above, the memory row address can be loaded into the row address registers 182a to 182c and / or the row address mask registers 183a to 183c using standard access operations of the memory device 100. For example, the memory device 100 can receive the memory row address and an activation ACT command (e.g., from...). Figure 1AThe memory controller 101 and / or host device 108). Assuming the EN bit and PGM bit of the control register 181 are asserted, the circuit system 180 can perform an ACT operation (e.g., a dummy ACT operation) and receive the memory row address (or the slave row decoder 140 corresponding to the received memory row address). Figure 1B The output physical memory row address is loaded into row address registers 182a to 182c.

[0057] Similarly, the memory column address can be loaded into column address registers 184a and 184b and / or column address mask registers 185a and 185b using standard access operations of memory device 100. For example, memory device 100 can receive the memory column address and a write WR command or a write-auto precharge WR-AP command (e.g., from memory controller 101 and / or host device 108). Assuming the EN bit and PGM bit of control register 181 are asserted, circuitry 180 can perform WR operations and / or WR-AP operations (e.g., dummy WR operations and / or dummy WR-AP operations) and load the received memory column address (or the corresponding slave column decoder 145) into the column address registers 184a and 184b. Figure 1B The output physical memory column address is loaded into column address registers 184a and 184b.

[0058] In embodiments where circuitry 180 includes row address mask registers 183a to 183c, circuitry 180 may be configured to load memory row addresses into row address mask registers 183a to 183c after receiving a second or another ACT command. In some embodiments, a 1-bit counter (or a bit in control register 181) may be used to track whether row address registers 182a to 182c or row address mask registers 183a to 183c are loaded after receiving an ACT command. Similarly, in embodiments where circuitry 180 includes column address mask registers 185a and 185b, circuitry 180 may be configured to load column address mask registers 185a and 185b after receiving a second or another WR command or WR-AP command. A 1-bit counter (or a bit in control register 181) may be used to track whether column address registers 184a and 184b or column address mask registers 185a and 185b are loaded after receiving a WR command or WR-AP command.

[0059] Alternatively, the memory row address can be directly written to row address registers 182a to 182c and / or row address mask registers 183a to 183c using the MRW command of memory device 100. In these and other embodiments, the memory column address can be directly written to column address registers 184a and 184b and / or column address mask registers 185a and 185b using the mode register write MRW command of memory device 100. When using circuit system 180 to decode memory system 102 ( Figure 1A The MRW command can be particularly useful when scrambling the address and / or DQ scrambling of a device.

[0060] The I / O register 186 of the circuit system 180 can be used to specify internal data lines of the memory device 100 on which data bits are poisoned (e.g., data read / write DRW lines). In some embodiments, the I / O register 186 is user-programmable. For example, the I / O register 186 can be used via... Figure 1A The information is transmitted to the memory device 100 via the DQ bus 119 or another data bus for programming. More specifically, the memory controller 101 and / or the host device 108 ( Figure 1A Information about the memory device 100 can be provided via the DQ bus 119 for (a) the memory controller 101 to provide WR or WR-AP commands and memory column addresses to the memory device 100 (e.g., via...). Figure 1A The I / O register 186 is programmed when the EN bit and PGM bit of the CMD / ADDR bus 118 and control register 181 are asserted. Alternatively, the I / O register 186 can be programmed directly via the MRW command.

[0061] As shown, I / O register 186 contains eight bits corresponding to the eight DQ terminals DQ0 to DQ7 of memory device 100. In other embodiments where memory device 100 includes a different number of DQ terminals, I / O register 186 may include a different number of bits and / or circuitry 180 may include multiple I / O registers 186. In some embodiments, when a bit of I / O register 186 is not asserted, circuitry 180 prevents data bits read from memory device 100 from being poisoned on the internal data lines corresponding to the respective DQ terminals of memory device 100. In these and other embodiments, when a bit of I / O register 186 is asserted, circuitry 180 is able to poison the data bit read from memory device 100 on the internal data line corresponding to the respective DQ terminal (e.g., assuming the data bit corresponds to (a) a memory row address loaded into row address registers 182a to 182c, (b) a range of memory row addresses defined by row address registers 182a to 182c and row address mask registers 183a to 183c, (c) a memory column address loaded into column address registers 184a and 184b and / or (d) a range of memory column addresses defined by column address registers 184a and 184b and column address mask registers 185a and 185b).

[0062] A user can use the I / O register 186 of the circuit system 180 to select which memory device 100 of the memory system 102 to read the poisoned data bit from. For example, the controller 101 of the memory system 102 can be configured to transmit command / address signals to each of the memory devices 100 of the memory system 102, such that the memory devices 100 share the command / address signals. In these embodiments, one or more of the memory devices 100 cannot read the poisoned data bit by programming the corresponding I / O register 186 of one or more memory devices 100 such that all bits of the I / O register 186 are not asserted. On the other hand, one or more memory devices 100 of the memory system 102 can read the poisoned data bit by programming the corresponding I / O register 186 of one or more memory devices 100 such that one or more bits of the I / O register 186 are asserted. In other words, the I / O register 186 of memory device 100 allows the user to specify (a) which memory device(s) of memory system 102 will read the poisoned data bits from and (b) via which DQ terminals of each of the memory devices 100.

[0063] Figure 1DThis is a partial schematic representation of a poisoning control logic circuit system 190 (“logic circuit system 190”) belonging to circuit system 180 and configured according to various embodiments of the present technology. As shown, logic circuit system 190 includes three main branches: a first branch 141 corresponding to the processing of memory row address information, a second branch 142 corresponding to the processing of memory column address information, and a third branch 143 corresponding to the processing of DQ information. For clarity and understanding, row address mask registers 183a to 183c and column address mask registers 185a and 185b have been removed from... Figure 1D Omitted, but the following text is about Figure 2 A more detailed discussion is provided. Those skilled in the art will find it easily understandable. Figure 1D The logic circuit system 190 described herein may provide the same or similar functions but includes, except for Figure 1D A simplified circuit diagram of one or more other more complex circuits, in addition to or alternative to the circuit components or arrangements shown in the diagram. Such other circuits are within the scope of this technology.

[0064] refer to Figure 1D The first branch 141 of the logic circuit system 190 described herein includes row address registers 182a to 182c, AND gate 187, XNOR gate 188, and AND gate 189. AND gate 187 is configured to generate the ACT command and control register 181. Figure 1C The logical product or logical AND of the PGM bits of the control register 181 is used. The output of AND gate 187 is fed as a clock signal into row address registers 182a to 182c. Therefore, when the PGM bit of the control register 181 is asserted and the memory device 100 receives an ACT command, the output of AND gate 187 is timed to transfer the memory row address entries output from the row decoder 140 of the memory device 100 into row address registers 182a to 182c. These memory row address entries are then fed from row address registers 182a to 182c into the first input of XNOR gate 188. After row address registers 182a to 182c are loaded with memory row address entries from the row decoder 140, the PGM bit of the control register 181 can be unasserted to prevent row address registers 182a to 182c from being updated with newly passed memory row address entries after receiving subsequent ACT commands.

[0065] In some embodiments, the first branch 141 of the logic circuit system 190 may additionally include an OR gate (not shown) having a first input connected to the output of the AND gate 187, a second input fed with the MRW command, and an output connected to row address registers 182a through 182c (e.g., not making the output of the AND gate 187 directly connected to row address registers 182a through 182c). In this way, the MRW command can be used to load memory row address entries into row address registers 182a through 182c (e.g., regardless of the state of the PGM bit).

[0066] XNOR gate 188 of the first branch 141 determines when a memory row address entry loaded into row address registers 182a-182c matches a newly incoming memory row address entry output from row decoder 140 (e.g., after receiving a subsequent ACT command). When a memory row address entry loaded into row address registers 182a-182c matches a newly incoming memory row address entry output from row decoder 140 and the PGM bit is not asserted (e.g., indicating a read operation for memory device 100 for a memory row identified by a memory row address entry loaded into row address registers 182a-182c), XNOR gate 188 outputs a logic high value to AND gate 189. AND gate 189 then outputs the logical product or logical AND of the output of XNOR gate 188 with the ROW bit of control register 181. The output of AND gate 189 is fed into AND gate 195 and OR gate 196 of logic circuit system 190, each of which is discussed in more detail below.

[0067] Referring now to the second branch 142 of the logic circuit system 190, the second branch 142 includes column address registers 184a and 184b, AND gate 191, XNOR gate 192, and AND gate 193. The second branch 142 operates similarly to the first branch 141. Specifically, AND gate 191 is configured to generate WR or WR-AP commands and control register 181 (…). Figure 1C The logical product or logical AND of the PGM bits of the memory device 100 is used. The output of AND gate 191 is fed as a clock signal into column address registers 184a and 184b. Therefore, when the PGM bit of control register 181 is asserted and memory device 100 receives a WR or WR-AP command, the output of AND gate 191 will store the memory column address entries (e.g., from the column decoder 145 of memory device 100) as a clock signal. Figure 1BThe output timing data is transferred to column address registers 184a and 184b. These memory column address entries are then fed from column address registers 184a and 184b to the first input of XNOR gate 192. After column address registers 184a and 184b are loaded with memory column address entries, the PGM bit of control register 181 can be unassertively prevented from updating column address registers 184a and 184b with newly passed memory column address entries after receiving subsequent WR or WR-AP commands.

[0068] In some embodiments, the second branch 142 of the logic circuit system 190 may additionally include an OR gate (not shown) having a first input connected to the output of the AND gate 191, a second input fed with the MRW command, and an output connected to column address registers 184a and 184b (e.g., not making the output of the AND gate 191 directly connected to column address registers 184a and 184b). In this way, the MRW command can be used to load memory column address entries into column address registers 184a and 184b (e.g., regardless of the state of the PGM bit).

[0069] The XNOR gate 192 of the second branch 142 determines when a memory column address entry loaded into column address registers 184a and 184b matches a newly passed memory column address entry (e.g., after receiving a subsequent WR or WR-AP command). When a memory column address entry loaded into column address registers 184a and 184b matches a newly passed memory column address entry and the PGM bit is not asserted (e.g., indicating a read operation for memory device 100 identified by the memory column entries loaded into column address registers 184a and 184b), the XNOR gate 192 outputs a logic high value to the AND gate 193. The AND gate 193 then outputs the output of the XNOR gate 192 and the logical product or logical AND of the COL bit of the control register 181. The output of the AND gate 193 is fed to the AND gate 195 and the OR gate 196 of the logic circuit system 190.

[0070] The AND gate 195 of logic circuit system 190 produces a logical product or logical AND of the output of AND gate 189 of the first branch 141 and the output of AND gate 193 of the second branch 142. Therefore, the output of AND gate 195 is only available if (a) the memory row address entries loaded into row address registers 182a to 182c match the newly entered memory row address entry, and (b) the control register 181 ( Figure 1C(c) the ROW bit of the AND gate 181 is asserted, the memory column address entries loaded into column address registers 184a and 184b match the newly passed memory column address entries, and (d) the COL bit of the control register 181 is asserted to be high. Otherwise, the output of the AND gate 195 is low. The output of the AND gate 195 is fed into the first input of the multiplexer 197 of the logic circuit system 190, as discussed in more detail below.

[0071] The OR gate 196 of logic circuit system 190 generates a logical summation or logical disjunction between the output of the AND gate 189 of the first branch 141 and the output of the AND gate 193 of the second branch 142. Therefore, the output (a) of OR gate 196 matches the newly entered memory row address entry in the memory row address registers 182a to 182c, and the control register 181 ( Figure 1C The output of OR gate 196 is high when (a) the ROW bit of OR gate 196 is asserted and / or (b) the memory column address entries loaded into column address registers 184a and 184b match the newly passed memory column address entries and the COL bit of control register 181 is asserted. Otherwise, the output of OR gate 196 is low. The output of OR gate 196 is fed into the second input of multiplexer 197 of logic circuit system 190.

[0072] Multiplexer 194(a) receives the outputs of AND gate 195 and OR gate 196 as inputs and (b) outputs either the output of AND gate 195 or the output of OR gate 196 as a FORCE_FAIL signal, depending on whether the bit of control register 181 is asserted. Specifically, when the bit of control register 181 is not asserted, multiplexer 197 outputs the output of OR gate 196. When the bit of control register 181 is asserted, multiplexer 197 outputs the output of AND gate 195. (See below for more details.) Figure 1E In more detail, the FORCE_FAIL signal, when asserted, poisons the data bits corresponding to the memory row address entries in row address registers 182a to 182c and / or the memory column address entries in column address registers 184a and 184b. Therefore, the first branch 141 and the second branch 142 of logic circuit system 190 enable circuit system 180 to poison data bits only when (a) the output of AND gate 195 is high and the bit of control register 181 is asserted, or (b) the output of OR gate 196 is high and the bit is not asserted. In other words, circuit system 180 poisons the memory array 150 of memory device 100 only when the following occurs: Figure 1BData bit poisoning occurs when the read data is read as follows: (a) The BIT bit is asserted, the memory row address entries loaded into row address registers 182a to 182c match the newly passed memory row address entries, the ROW bit of control register 181 is asserted, the memory column address entries loaded into column address registers 184a and 184b match the newly passed memory column address entries, and the COL bit of control register 181 is asserted; (b) The BIT bit is not asserted, the memory row address entries loaded into row address registers 182a to 182c match the newly passed memory row address entries, and the ROW bit of control register 181 is poisoned. Assert; (c) the BIT bit is not asserted, the memory column address entries loaded into column address memories 184a and 184b match the newly passed memory column address entries, and the COL bit of control register 181 is asserted; and / or (d) the BIT bit is not asserted, the memory row address entries loaded into row address registers 182a to 182c match the newly passed memory row address entries, the ROW bit of control register 181 is asserted, the memory column address entries loaded into column address registers 184a and 184b match the newly passed memory column address entries, and the COL bit of control register 181 is asserted.

[0073] Referring now to the third branch 143 of the logic circuit system 190, the third branch 143 includes an I / O register 186, an AND gate 191, and a data input latch 194. When I / O and / or burst bits are received serially via the DQ pins of the memory device 100, the input latch 194 for each DQ pin parallelizes the I / O and / or burst bits and passes them to the I / O register 186. Then, when the PGM bit of the control register 181 is asserted and the memory device 100 receives a WR or WR-AP command, the I / O and / or burst bits are timed and transferred to the I / O register 186 via the output of the AND gate 191. The I / O and / or burst bits loaded into the I / O register 186 are then fed back to the data path poisoning control logic circuit system of the memory device 100. Figure 1E The IO_FAIL signal is used to select which internal DRW lines of the memory device 100 should be poisoned with data bits.

[0074] In embodiments where the MRW command is used to program memory column address entries, memory column mask address entries, and / or DQ entries to registers, the third branch 143 of the logic circuit system 190 may include, in addition to Figure 1DAdditional registers beyond those shown in the diagram. For example, the third branch 143 may contain a set of additional registers (not shown) that can be programmed to have the following combinations: (a) individual memory column address entries (e.g., CA[2:0] or burst bit entries) from column address registers 184a and 184b, (b) individual memory column mask address entries (e.g., CA[2:0] or burst bit entries) from column address mask registers 185a and 185b, and / or (c) DQ entries from I / O register 186. Entries loaded into the additional register set can be used to force specific data write (DW) bits in the DW position. Figure 1D The output of the input latch 194.

[0075] Figure 1E This is a partial schematic representation of a data path poisoning control logic circuit system 165 (“data path poisoning control circuit system 165”) belonging to circuit system 180 and configured according to various embodiments of the present technology. As shown, the data path poisoning control circuit system 165 includes a plurality of AND gates 166 (in Figure 1E Individually identified as AND gates 166a to 166h and multiple XOR gates 167 (individually identified as XOR gates 167a to 167h). More specifically, the data path poisoning control circuit system 165 includes AND gates 166 and XOR gates 167 for each DQ terminal DQ0 to DQ7 of the memory device 100.

[0076] Each of AND gates 166a to 166h is configured to receive data from logic circuit system 190. Figure 1D The FORCE_FAIL signal output from the multiplexer 197 and the signal from the I / O register 186 ( Figure 1D The corresponding IO_FAIL signal is output. Each of the AND gates 166a to 166h is configured to generate a logical product or logical AND of FORCE_FAIL and the corresponding IO_FAIL signal. Therefore, the output of one of the AND gates 166a to 166h is high only when (a) the FORCE_FAIL signal is high (indicating that a read operation of memory device 100 is targeted at the memory row, memory column, and / or memory bit of interest in control register 181, row address registers 182a to 182c, column address registers 184a and 184b, row address mask registers 183a to 183c and / or column address mask registers 185a and 185b) and (b) the corresponding IO_FAIL signal is high (indicating that the corresponding portion of the read data path or the corresponding DQ terminal has been enabled for data poisoning). Otherwise, the output of one of the AND gates 166a to 166h is low.

[0077] Each of the XOR gates 167a to 167h is configured to receive (a) the output of its counterpart among the AND gates 166a to 166h and (b) a data bit read from the memory array 150 of the memory device 100 via an internal DRW line of the memory device 100. Each of the XOR gates 167a to 167h is configured to generate a mutual exclusion decomposition of its input. Therefore, each of the XOR gates 167a to 167h is configured to poison the data bit received via the corresponding internal DRW line when the output of its counterpart among the AND gates 166a to 166h is high (indicating that (a) the data bit read from the memory array 150 via the corresponding internal DRW line corresponds to a target memory row, target memory column, and / or target memory cell identified by an entry in registers 181 to 185b loaded into the circuit system 180 and (b) the corresponding internal DRW line / DQ terminal of the memory device 100 is enabled for data poisoning by an entry loaded into I / O register 186). Otherwise, each of XOR gates 167a to 167h is configured to pass data bits without poisoning them (indicating that (a) data bits read from memory array 150 via the corresponding internal DRW line do not correspond to the target memory row, target memory column, and / or target memory cell identified by the entries in registers 181 to 185b loaded into circuit system 180 and / or (b) the corresponding internal DRW line / DQ terminal is not enabled for data poisoning by the entry loaded into I / O register 186). The data bits output from XOR gates 167a to 167h are then passed to I / O circuit 160 and / or read from the corresponding DQ terminals DQ0 to DQ7 of memory device 100.

[0078] As discussed above, circuit system 180 may include row address mask registers 183a to 183c and / or column address mask registers 185a and 185b to define memory row ranges and / or memory column ranges for poisoning data bits, respectively. In these embodiments, additional masking circuit systems may be used. Figure 1D Add to position 114 and / or position 116 Figure 1D The logic circuit system 190. An example of the shielding circuit system 214 is in Figure 2 The following is an explanation. For clarity and understanding, the masking circuit system 214(a) compares two 4-bit memory row address entries A[3:0] with B[3:0] and (b) uses the data loaded into the circuit system 180 ( Figure 1B and 1C The result of the masking comparison of the 4-bit memory row address entries M[3:0] in the row address mask registers 183a to 183c. Figure 2 The logic described herein can be extended to any number of bits in a memory row address entry.

[0079] like Figure 2As shown, the shielding circuit system 214 includes multiple XNOR gates 288 (in Figure 2 Some of these are identified as XNOR gates 288a to 288d. XNOR gates 288a to 288d are similar to those discussed above. Figure 1D The XNOR gate 188 generally functions. Specifically, XNOR gates 288a to 288d determine the load into row address registers 182a to 182c. Figure 1C and 1D During a read operation of the memory row address entry in the memory device 100, the bits B[3:0] of the newly passed memory row address entry are checked to see if they match the corresponding bits A[3:0]. When the bits match, the output of the corresponding XNOR gate 288 is high. Otherwise, the output of the corresponding XNOR gate 288 is low.

[0080] Next, the outputs of XNOR gates 288a to 288d are fed into the corresponding OR gate 299 (in Figure 2 The individual gates are identified as OR gates 299a to 299d. OR gates 299a to 299d generate a logical sum or logical disjunction between the output of XNOR gates 288a to 288d and the corresponding bits M[3:0] of the memory row address entries loaded into row address mask registers 183a to 183c. Therefore, the output of OR gates 299a to 299d is high when (a) the corresponding bits B[3:0] of the memory row address entries loaded into row address registers 182a to 182c of circuit system 180 match the corresponding bits A[3:0] of the newly passed memory row address entries and / or (b) the corresponding bits M[3:0] of the memory row address entries loaded into row address mask registers 183a to 183c are "high". Next, the output of OR gates 299a to 299d is fed into AND gate 289, which is similar to the one described above. Figure 1D The AND gate 189 works in a similar way.

[0081] In this way, memory row address entries loaded into row address registers 182a to 182c and memory row address mask registers 183a to 183c can be used to define a target memory row range for data poisoning. For example, when memory row address entries B[3:0] loaded into row address registers 182a to 182c are “1000” and memory row address entries M[3:0] loaded into row address mask registers 183a to 183c are “1011”, all newly entered memory row address entries A[3:0] falling within “1000” and “1011” will cause the output of AND gate 289 to be “high” (assuming the ROW bit of control register 181 is asserted). All other newly entered memory row address entries A[3:0] falling outside this range (e.g., “1000”) will cause the output of AND gate 289 to be “low”.

[0082] Similar to Figure 2 The logic shown in the middle can be found in Figure 1D Position 116 is used to define the memory column address range for poisoning. For example, Figure 2 The row address mask registers 183a to 183c described herein can be replaced by column address mask registers 185a and 185b, and control register 181 ( Figure 1C The COL bit can replace the ROW bit of control register 181 as input. Figure 2 In AND gate 289. Next, the memory column address entries B[3:0] loaded into column address registers 184a and 184b can be compared with the newly passed column address entries A[3:0], and the result can be masked using the memory column address entries M[3:0] loaded into column address mask registers 185a and 185b.

[0083] As discussed above, circuit system 180 can use various methods to determine when to load memory row address entries into row address mask registers 183a to 183c (e.g., not into row address registers 182a to 182c) and / or when to load memory column address entries into column address mask registers 185a and 185b (e.g., not into column address registers 184a and 184b). For example, when control register 181 ( Figure 1C When the PGM bit of control register 181 is asserted and the mask bit (not shown) of control register 181 is not asserted, circuit system 180 can load memory row address entries into row address registers 182a to 182c. Continuing this example, when the mask bit (not shown) of control register 181 is asserted, circuit system 180 can load memory row address entries into row address mask registers 183a to 183c. The PGM bit and mask bit can be similarly used to load memory column address entries into column address registers 184a and 184b and / or column address mask registers 185a and 185b.

[0084] As another example, whenever the ACT command is received and the PGM bit of control register 181 is asserted, circuit system 180 may sequentially load memory row address entries into row address registers 182a to 182c and row address mask registers 183a to 183c, or alternatively between row address registers 182a to 182c and row address mask registers 183a to 183c. More specifically, circuit system 180 may: (a) load memory row address entries into row address registers 182a to 182c when circuit system 180 receives a first ACT command and the PGM bit of control register 181 is asserted; (b) load row address entries into row address mask registers 183a to 183c when circuit system 180 receives a second ACT command and the PGM bit of control register 181 is asserted; (c) load memory row address entries into row address registers 182a to 182c when circuit system 180 receives a third ACT command and the PGM bit of control register 181 is asserted; and (d) and so on. A counter (e.g., a 1-bit counter) may be used to count ACT commands and / or determine whether to load row address registers 182a to 182c or row address mask registers 183a to 183c. Registers 182a to 183c may be reset at any time by asserting the RST bit of control register 181. A similar method can be used to load memory column address entries into column address registers 184a and 184b and / or column address mask registers 185a and 185b.

[0085] Similar to the examples described above, in some embodiments, whenever an ACT command is received and the PGM bit of control register 181 is asserted, circuitry 180 may sequentially load memory row address entries into row address registers 182a to 182c and row address mask registers 183a to 183c, or alternatively, between row address registers 182a to 182c and row address mask registers 183a to 183c. However, unlike the examples described above, whenever circuitry 180 loads memory row address entries into row address registers 182a to 182c, circuitry 180 may clear or reset row address mask registers 183a to 183c. A similar method may be used to load memory column address entries into column address registers 184a and 184b and / or column address mask registers 185a and 185b.

[0086] As another example, circuit system 180 can use a 1-bit counter to sequentially load memory row address entries into row address registers 182a to 182c and thereby define the memory row address entries loaded into row address mask registers 183a to 183c. More specifically, when circuit system 180 receives the first ACT command and the PGM bit of control register 181 is asserted, circuit system 180 can (a) load memory row address entries into row address registers 182a to 182c, (b) feed memory row address entries to the first input of an XOR gate (not shown), and (c) clear or reset the memory row address entries loaded into row address mask registers 183a to 183c. When circuit system 180 subsequently receives a second ACT command and the PGM bit of control register 181 is asserted, circuit system 180 may (a) load the newly passed memory row address entry into row address registers 182a to 182c, (b) feed the newly passed memory row address entry into the second input of the XOR gate, and (c) load the output of the XOR gate into row address mask registers 183a to 183c. A similar method may be used to load memory column address entries into column address registers 184a and 184b and / or column address mask registers 185a and 185b.

[0087] Although discussed above in the context of poisoning data bits read from memory array 150 of memory device 100, circuitry 180 can be used to poison data bits as they are written to memory array 150 of memory device 100. For example, when data bits are received via the DQ terminal of memory device 100, circuitry 180 can poison the selected data bits before they are written to memory array 150. Poisoning can occur before or after the ECC circuitry 157 of memory device 100 encodes the data bits during a write operation. If poisoning occurs before the ECC circuitry 157 of memory device 100 processes or encodes the data bits during a write operation, then poisoning can be used to test and / or determine whether the ECC operation correctly identifies and / or corrects bit errors before the data bits are stored in memory array 150. If poisoning occurs after the ECC circuitry 157 of memory device 100 processes or encodes the data bits during a write operation, then the data bits can be stored in memory array 150 as bit errors. In these embodiments, bit errors stored in memory array 150 can be used to test and / or determine whether an ECC operation (or other operation of memory device 100, such as a PPR operation) correctly identifies and / or corrects the resulting bit errors when data bits are subsequently read from memory array 150.

[0088] Figure 3 This describes an operational address-selectable data poisoning circuit system (e.g., according to various embodiments of the present technology). Figures 1B to 2The flowchart of method 300 (circuit system 180). Method 300 is described as a set of steps or blocks 301 to 309. All or a subset of one or more of blocks 301 to 309 may be generated by a memory system (e.g., Figure 1A The components or devices of the memory system 102) perform the operation. For example, all or a subset of one or more of blocks 301 to 309 may be performed by: (i) memory devices (e.g., Figure 1A and 1B (i) memory device 100), (ii) memory controller (e.g. Figure 1A (iii) memory controller 101) and / or (iii) host device (e.g. Figure 1A (The host device 108). Furthermore, any one or more of boxes 301 to 309 may be configured according to the above. Figures 1A to 2 The execution of the argument.

[0089] Method 300 begins at block 301 with resetting various registers of the address-selectable data poisoning circuitry. In some embodiments, resetting the registers may include resetting the memory row address register, memory row address mask register, memory column address register, memory column address mask register, and / or I / O registers. In these and other embodiments, resetting the registers may include asserting the RST bit of the control register of the address-selectable data poisoning circuitry. In these and other embodiments, resetting the registers may include (a) asserting the EN bit of the control register and / or (b) not asserting the RST bit of the control register after the various registers are reset.

[0090] In block 302, method 300 then programs the memory row address register of the address-selectable data poisoning circuitry. In some embodiments, programming the memory row address register includes (a) asserting the PGM bit of the control register and / or (b) programming the memory row address register when the PGM bit is asserted. In these and other embodiments, programming the memory row address register includes loading a memory row address entry into the memory row address register in response to receiving an ACT command and / or a memory row address entry (e.g., from a memory controller and / or a host device). In some embodiments, the memory row address entry loaded into the memory row address register may include a memory row address entry output from the row decoder of the memory device or a memory row address entry fed into the row decoder. The memory row address entry loaded into the memory row address register can identify a target memory row for data poisoning.

[0091] At block 303, method 300 then programs the memory column address register of the address-selectable data poisoning circuitry. In some embodiments, programming the memory column address register includes (a) asserting the PGM bit of the control register and / or (b) programming the memory column address register when the PGM bit is asserted. In these and other embodiments, programming the memory column address register includes loading a memory column address entry into the memory column address register in response to receiving a WR or WR-AP command and / or a memory column address entry (e.g., from a memory controller and / or a host device). In some embodiments, the memory column address entry loaded into the memory column address register may include a memory column address entry output from the column decoder of the memory device or a memory column address entry fed into the column decoder. The memory column address entry loaded into the memory column address register can identify a target memory column for data poisoning.

[0092] At block 304, method 300 then programs the I / O registers of the address-selectable data poisoning circuitry. In some embodiments, programming the I / O registers includes (a) asserting a PGM bit in a control register and / or (b) programming the I / O registers while the PGM bit is asserted. In these and other embodiments, programming the I / O registers includes loading I / O items into the I / O registers in response to receiving a WR or WR-AP command and / or an I / O item (e.g., from a memory controller and / or a host device). In some embodiments, the I / O items loaded into the I / O registers may include I / O items received via a DQ bus operatively connecting the memory device to the memory controller and / or the host device. The I / O items loaded into the I / O registers may identify portions of data paths (e.g., DRW lines) within the memory device and / or enabled DQ terminals for data poisoning.

[0093] In block 305, method 300 then programs the memory row address mask register of the address-selectable data poisoning circuitry. In some embodiments, programming the memory row address mask register includes (a) asserting the PGM bit and / or one or more other bits (e.g., mask bits) of the control register and / or (b) programming the memory row address register while the PGM bit and / or one or more other bits are asserted. In these and other embodiments, programming the memory row address mask register includes loading memory row address entries into the memory row address mask register in response to receiving an ACT command and / or memory row address entries (e.g., from a memory controller and / or a host device). The ACT command may be an ACT command received before or after the ACT command in block 302. In some embodiments, the memory row address entries loaded into the memory row address mask register may include memory row address entries output from the row decoder of the memory device or memory row address entries fed into the row decoder. The memory row address entries loaded into the memory row address mask register can be used to identify a target range of memory rows for data poisoning.

[0094] At block 306, method 300 then proceeds to program the memory column address mask register of the address-selectable data poisoning circuitry. In some embodiments, programming the memory column address mask register includes (a) asserting the PGM bit and / or one or more other bits (e.g., mask bits) of the control register and / or (b) programming the memory row address register while the PGM bit and / or one or more other bits are asserted. In these and other embodiments, programming the memory column address mask register includes loading a memory column address entry into the memory column address mask register in response to receiving a WR or WR-AP command and / or a memory column address entry (e.g., from a memory controller and / or a host device). The WR or WR-AP command may be a WR or WR-AP command received before or after the WR or WR-AP command at block 303. In some embodiments, the memory column address entry loaded into the memory column address mask register may include a memory column address entry output from the column decoder of the memory device or a memory column address entry fed into the column decoder. The memory column address entries loaded into the memory column address mask register can be used to identify the target range of memory columns used for data poisoning.

[0095] In block 307, method 300 then identifies target memory rows, target memory columns, and / or target memory cells for data poisoning. In some embodiments, one or more target memory rows are identified to contain ROW bits of the assertion control register. In these and other embodiments, one or more target memory columns are identified to contain COL bits of the assertion control register. In these and other embodiments, one or more selected memory cells corresponding to the target memory rows and target memory columns are identified to contain BIT bits of the assertion control register.

[0096] In block 308, method 300 then poisons the data bits corresponding to the target memory row, target memory column, and / or target memory cell. In some embodiments, poisoning the data bits corresponding to the target memory row includes determining, at least when the ROW bit of the control register is asserted, that a newly incoming memory row address entry (a) matches a memory row address entry loaded into the memory row address register in block 302 and / or (b) is included in the range of target memory row address entries identified by the memory row address entries loaded into the memory row address register in block 302 and the memory row address entries loaded into the memory row address mask register in block 305. In these and other embodiments, poisoning the data bits corresponding to the target memory column includes determining, at least when the COL bit of the control register is asserted, that a newly incoming memory column address entry (a) matches a memory column address entry loaded into the memory column address register in block 303 and / or (b) is included in the range of target memory column address entries identified by the memory row address entries loaded into the memory column address register in block 303 and the memory column address mask register in block 306. In these and other embodiments, poisoning the data bits corresponding to the target memory cell includes determining, at least when the ROW bit, COL bit, and BIT bit of the control register are asserted, that (a) a newly incoming memory row address entry (i) matches a memory row address entry loaded into the memory row address register in block 302 and / or (ii) is included within the range of target memory row address entries identified by the memory row address entries loaded into the memory row address register in block 302 and the memory row address entries loaded into the memory row address mask register in block 305, and (b) a newly incoming memory column address entry (i) matches a memory column address entry loaded into the memory column address register in block 303 and / or (ii) is included within the range of target memory column address entries identified by the memory column address entries loaded into the memory column address register in block 303 and the memory column address mask register in block 306.

[0097] In some embodiments, poisoning data bits corresponding to a target memory row, target memory column, and / or target memory cell includes poisoning data bits when they are read from the memory array of the memory device. In these and other embodiments, poisoning data bits corresponding to a target memory row, target memory column, and / or target memory cell includes poisoning data bits read on the internal DRW line of the memory device enabled for data poisoning by an I / O register. In these and other embodiments, poisoning data bits corresponding to a target memory row, target memory column, and / or target memory cell includes (a) inverting data bits before or after the data bits are processed by the ECC circuitry of the memory device and / or (b) before the data bits are read from the DQ terminal of the memory device.

[0098] In block 309, method 300 then uses poisoned data bits to verify, debug, and / or decode various operations of the memory device and / or memory system. In some embodiments, the poisoned data bits are used to verify and / or debug the ECC operation of the memory device. For example, data bits may be poisoned in block 308 before the data bits are processed by the ECC circuitry of the memory device, such that the ECC circuitry receives one or more poisoned data bits. The poisoned data bits can also be used to verify that the ECC operation correctly identifies and / or corrects one or more bit errors corresponding to the poisoned data bits. In these and other embodiments, the poisoned data bits can be used to verify and / or debug the ECC operation of the memory system (not the ECC operation of the memory device). For example, data bits may be poisoned in block 308 after the data bits are processed by the ECC circuitry of the memory device but before the data bits are processed by the ECC component of the memory system (e.g., located on the memory controller), such that the ECC component of the memory system receives one or more poisoned data bits. The poisoned data bits can also be used to verify that the ECC component of the memory system correctly identifies and / or corrects one or more bit errors corresponding to the poisoned data bits. In these and other embodiments, the poisoned data bits can be used to verify and / or debug PPR operations of the memory device and / or memory system. For example, the data bits can be used to trigger PPR operations of the memory device and / or memory system and / or verify that redundant memory rows of the memory array have been successfully used to replace defective memory rows of the memory array. In these and other embodiments, the poisoned data bits can be used to decode memory address scrambling and / or DQ scrambling of the memory system (e.g., by hard-coding one or more registers of the address-optional data poisoning circuitry using MRW commands, monitoring the output of the memory device, and using the output to decode the address and / or DQ scrambling between the logical structure of the address and / or data seen by the user from outside the memory device and the physical or topological internal structure of the address and / or data within the memory device).

[0099] Although boxes 301 to 309 of method 300 are discussed and explained in a specific order, Figure 3 The method 300 described herein is not limited thereto. In other embodiments, method 300 may be performed in a different order. In these and other embodiments, any of blocks 301 to 309 of method 300 may be performed before, during, and / or after any of the other blocks 301 to 309 of method 300. Furthermore, those skilled in the art will recognize that the described method 300 may be modified while remaining within these and other embodiments of the present technology. For example, in some embodiments, certain elements may be omitted and / or repeated. Figure 3 One or more boxes 301 to 309 of the method 300 described herein. As a particular example, boxes 304, 305 and / or 306 may be omitted in some embodiments.

[0100] The above reference Figures 1A to 3 Any of the aforementioned memory systems, devices, and / or methods can be incorporated into any of a variety of larger and / or more complex systems, a representative example of which is... Figure 4 The system 490 is shown schematically in the diagram. System 490 may include a semiconductor device assembly 400, a power supply 492, a driver 494, a processor 496, and / or other subsystems and components 498. The semiconductor device assembly 400 may include components generally similar to those described in the reference above. Figures 1A to 3 The described memory system, apparatus, and / or method are characterized by features. The resulting system 490 can perform any of a variety of functions, such as memory storage, data processing, and / or other suitable functions. Therefore, representative system 490 may include (but is not limited to) handheld devices (e.g., mobile phones, tablet computers, digital readers, and digital audio players), computers, vehicles, electrical appliances, and other products. Components of system 490 may be housed in a single unit or distributed across multiple interconnected units (e.g., via a communication network). Components of system 490 may also include remote devices and any of a variety of computer-readable media.

[0101] C. in conclusion

[0102] As used herein, the terms "memory system" and "memory device" refer to systems and devices configured to temporarily and / or permanently store information relating to various electronic devices. Thus, the term "memory device" can refer to a single memory die and / or a memory package containing one or more memory dies. Similarly, the term "memory system" can refer to a system containing one or more memory dies (e.g., a memory package) and / or a system containing one or more memory packages (e.g., a dual in-line memory module (DIMM)).

[0103] Where the context permits, singular or plural items may also contain plural or singular items, respectively. Furthermore, unless the word “or” is explicitly limited to meaning that only a single item in a list of two or more items excludes the others, “or” as used in this list shall be interpreted as including (a) any single item in the list, (b) all items in the list, or (c) any combination of items in the list. Additionally, as used herein, the phrase “and / or” in “A and / or B” refers to only A, only B, and both A and B. Furthermore, the terms “including,” “comprising,” “having,” and “possessing” are used throughout to mean including at least the stated features, such that no larger number of identical features and / or other features of additional types are excluded. Furthermore, as used herein, the phrase “based on” should not be construed as referring to a closed set of conditions. For example, without departing from the scope of this disclosure, an exemplary step described as “based on condition A” may be based on both condition A and condition B. In other words, as used herein, the phrase “based on” should be interpreted in the same manner as the phrase “at least partially based on.”

[0104] The information and signals described herein can be represented using any of a variety of different processes and technologies. For example, data, instructions, commands, information, signals, bits, symbols, and chips referred to throughout the above description can be represented by voltage, current, electromagnetic waves, magnetic fields or magnetic particles, optical fields or optical particles, or any combination thereof. Some diagrams may illustrate a signal as a single signal; however, those skilled in the art will understand that a signal can represent a signal bus, where the bus can have various bit widths.

[0105] The functionality described herein can be implemented in hardware, software implemented by a processor, firmware, or any combination thereof. Other examples and implementations are within the scope of this disclosure and the appended claims. Features implementing the functionality can also be physically located at various locations, including distributed implementations such that portions of the functionality are implemented at different physical locations.

[0106] The above detailed description of embodiments of this technology is not intended to be exhaustive or to limit the technology to the precise forms disclosed above. Although specific embodiments and examples of this technology have been described above for illustrative purposes, those skilled in the art will recognize that various equivalent modifications are within the scope of this technology. For example, although steps are presented and / or discussed in a given order, alternative embodiments may perform the steps in a different order. Furthermore, the various embodiments described herein may also be combined to provide other embodiments.

[0107] It should be understood from the foregoing that specific embodiments of the present technology have been described herein for illustrative purposes, but well-known structures and functions have not been shown or described in detail so as not to unnecessarily obscure the description of the embodiments of the present technology. It should also be understood from the foregoing that various modifications can be made without departing from the present technology. For example, various components of the present technology may be further divided into sub-components, or various components and functions of the present technology may be combined and / or integrated. Furthermore, although advantages associated with certain embodiments of the present technology have been described in the context of those embodiments, other embodiments may also exhibit such advantages, and not all embodiments need to necessarily exhibit such advantages to fall within the scope of the present technology. Therefore, this disclosure and related technologies may cover other embodiments not explicitly shown or described herein.

Claims

1. A memory device comprising: A memory array having multiple memory rows and multiple memory columns; and A circuit system operatively coupled to the memory array. The circuit system described herein includes (a) one or more memory row address registers or (b) one or more memory column address registers. The circuitry is configured to load memory row addresses corresponding to memory rows in the plurality of memory rows into one or more memory row address registers, or to load memory column addresses corresponding to memory columns in the plurality of memory columns into one or more memory column address registers. The circuitry is further configured during a read or write operation for (i) the memory row address loaded into the one or more memory row address registers or (ii) the memory column address loaded into the one or more memory column address registers to change a first data state of the data bit to a second data state different from the first data state before the data bit stored in the memory array and corresponding to the memory row address or the memory column address is output from the memory device as part of the read operation or before the data bit is stored in the memory array as part of the write operation.

2. The memory device of claim 1, wherein the circuitry is configured to change the first data state to the second data state such that the data bit is output from the memory device as a bit error.

3. The memory device according to claim 2, wherein: The memory device further includes error correction code (ECC) circuitry; and The circuit system is configured to change the first data state to the second data state after the data bits are processed by the ECC circuit.

4. The memory device according to claim 2, wherein: The memory device further includes error correction code (ECC) circuitry; and The circuit system is configured to change the first data state to the second data state before the ECC circuit processes the data bits.

5. The memory device according to claim 1, wherein: The memory device further includes a row decoder; and The circuit system is configured to receive the memory row address from the row decoder.

6. The memory device of claim 1, wherein the circuitry is further configured to (a) load the memory row address into the one or more memory row address registers when the memory device receives an activation command or (b) load the memory column address into the one or more memory column address registers when the memory device receives a write command or a write-auto-precharge command.

7. The memory device according to claim 6, wherein: The activation command, the write command, or the write-auto precharge command is part of the first set of access commands; and The memory device is configured to perform the read or write operation in response to a second set of access commands different from the first set.

8. The memory device of claim 1, wherein the circuitry is further configured to (a) load the memory row address into the one or more memory row address registers when the memory device receives a first mode register write command or (b) load the memory column address into the one or more memory column address registers when the memory device receives a second mode register write command.

9. The memory device according to claim 1, wherein: The memory row address is the first memory row address, the memory row is the first memory row, the memory column address is the first memory column address, and the memory column is the first memory column; The read or write operation is directed to (a) the address of a second memory row corresponding to a second memory row among the plurality of memory rows, or (b) the address of a second memory column corresponding to a second memory column among the plurality of memory columns; and The circuit system is further configured to: Compare (a) the first memory row address with the second memory row address or (b) the first memory column address with the second memory column address, and The first data state of the data bit is changed to the second data state only if (a) the first memory row address matches the second memory row address, (b) the first memory column address matches the second memory column address, or (c) the first memory row address matches the second memory row address and the first memory column address matches the second memory column address.

10. The memory device according to claim 1, wherein: The memory row address is the first memory row address, the memory row is the first memory row, the memory column address is the first memory column address, and the memory column is the first memory column; and The circuit system further includes: (a) one or more memory row address mask registers configured to store a second memory row address corresponding to a second memory row among the plurality of memory rows; or (b) one or more memory column address mask registers configured to store a second memory column address corresponding to a second memory column among the plurality of memory columns.

11. The memory device according to claim 10, wherein: The first memory row address and the second memory row address identify a memory row address range corresponding to the memory row range of the plurality of memory rows, or the first memory column address and the second memory column address identify a memory column address range corresponding to the memory column range of the plurality of memory columns; and The read or write operation is directed to (a) the address of the third memory row corresponding to the third memory row among the plurality of memory rows, or (b) the address of the third memory column corresponding to the third memory column among the plurality of memory columns; and The circuit system is further configured to: Compare (a) the third memory row address with the memory row address range or (b) the third memory column address with the memory column address range, and The first data state of the data bit is changed to the second data state only if (a) the third memory row address falls within the range of the memory row address, (b) the third memory column address falls within the range of the memory column address, or (c) the third memory row address falls within the range of the memory row address and the third memory column address falls within the range of the memory column address.

12. The memory device according to claim 1, wherein: The memory device includes an external DQ terminal; The circuit system includes an input / output I / O register having at least one bit corresponding to the external DQ terminal; The memory device is configured to output the data bits from the memory device via the external DQ terminal; and The circuit system is configured to change the first data state of the data bit to the second data state only when at least one bit of the I / O register is asserted.

13. A method implemented by a memory device, comprising: Identify at least one memory row or at least one memory column of the memory array of the memory device for data poisoning; Perform read or write operations on the memory row address of the first memory row and the memory column address of the first memory column; The memory row address is determined to correspond to a memory row in the at least one memory row, or the memory column address is determined to correspond to a memory column in the at least one memory column; and In response to the determination and during the execution of the read or write operation, the first data state of the data bit is changed to a second data state, wherein the second data state is different from the first data state, before the data bit read from or written to the memory array is output from the memory device as part of the read operation or before the data bit is stored in the memory array as part of the write operation.

14. The method of claim 13, wherein identifying the at least one memory row or the at least one memory column comprises loading the first memory row address or the first memory column address into one or more memory row address registers or one or more memory column address registers respectively before performing the read or write operation.

15. The method of claim 14, wherein: Loading the first memory row address into the one or more memory row address registers includes loading the first memory row address into the one or more memory row address registers in response to receiving an activation command or a first mode register write command; or Loading the first memory column address into the one or more memory column address registers includes loading the first memory column address into the one or more memory column address registers in response to receiving a write command, a write-auto-precharge command, or a second mode register write command.

16. The method of claim 14, wherein identifying the at least one memory row or the at least one memory column comprises: Before performing the read or write operation, the second memory row address or the second memory column address is loaded into one or more memory row address mask registers or one or more memory column address mask registers, respectively; and The first memory row address is masked by the second memory row address to identify the range of memory row addresses corresponding to the at least one memory row, or the first memory column address is masked by the second memory column address to identify the range of memory column addresses corresponding to the at least one memory column.

17. The method of claim 14, wherein: The method further includes: when performing the read or write operation, comparing (a) the memory row address with the first memory row address or (b) the memory column address with the first memory column address; and The first data state of the data bit is changed to the second data state only if (1) the memory row address matches the first memory row address or is included in at least part of the memory row address range identified by the first memory row address, (2) the memory column address matches the first memory column address or is included in at least part of the memory column address range identified by the first memory column address, or (3) the memory row address matches the first memory row address or is included in the memory row address range and the memory column address matches the first memory column address or is included in the memory column address range.

18. The method of claim 13, wherein: Performing the read or write operation includes performing the read operation; Performing the read operation includes outputting the data bits from the memory device via an external DQ terminal of the memory device; The method further includes enabling the external DQ terminal for data poisoning; and Changing the first data state of the data bit to the second data state includes changing the first data state of the data bit to the second data state only when the external DQ terminal is enabled for data poisoning.

19. The method of claim 13, wherein: The read or write operation is the first read or write operation; Changing the first data state of the data bit to the second data state includes using the data poisoning circuitry of the memory device and changing the first data state of the data bit to the second data state only when the data poisoning circuitry is enabled. and The method further includes: Disconnect the data poisoning circuit system; and When the data poisoning circuit system is deactivated, a second read or write operation is performed on the memory row address of the first memory row or the memory column address of the first memory column, such that the data bit is (a) read from the memory array and output from the memory device with the first data state as part of the second read operation or (b) written to the memory array with the first data state as part of the second write operation.

20. A memory system comprising: Memory controller; and A memory device operatively connected to the memory controller, wherein the memory device comprises: Memory array; and A circuit system coupled to the memory array and comprising (a) one or more memory row address registers or (b) one or more memory column address registers, The circuit system described therein is configured to: The first memory row address or the first memory column address identified by the memory controller is loaded into one or more memory row address registers or one or more memory column address registers, respectively. When the memory device performs a read or write operation targeting a second memory row address or a second memory column address: Compare (a) the second memory row address with the first memory row address or (b) the second memory column address with the first memory column address; and When (i) the second memory row address matches the first memory row address or is included in at least a portion of the memory row address range identified by the first memory row address, or (ii) the second memory column address matches the first memory column address or is included in at least a portion of the memory column address range identified by the first memory column address, the first data state of the data bit read from the memory array is changed to a second data state different from the first data state, such that the data bit is output from the memory device as a first bit error as part of the read operation or stored in the memory array as a second bit error as part of the write operation.

21. The memory system of claim 20, wherein the memory controller is configured to: Issue an activation command or a first mode register write command to load the first memory row address into one or more memory row address registers; or Issue a write command, a write-auto-precharge command, or a second-mode register write command to load the first memory column address into the one or more memory column address registers.

Images