A method for preparing a thin high-resistance silicon epitaxial wafer for a photomultiplier tube device

Abstract

The present application relates to a kind of preparation methods of thin layer high resistance silicon epitaxial wafer for photomultiplier tube device, by before the silicon substrate piece is mounted, design and carry out etching and polycrystalline silicon coating layer cycle cleaning process to reaction cavity and graphite base multiple hydrogen chloride gas, the growth environment of reaction cavity is purified, and by accurately adjusting the flow of process hydrogen, the flow of trichlorosilane, the temperature process parameter of silicon epitaxial layer reaction growth in the process of silicon epitaxial layer growth, the growth rate of silicon epitaxial layer is significantly reduced, to extend the reaction process of thin layer silicon epitaxial layer, expand the proportion of steady-state growth phase, realize the high uniformity distribution of thin layer high resistance silicon epitaxial layer, finally obtain a kind of preparation method of thin layer high resistance silicon epitaxial layer, the thickness of silicon epitaxial layer is in 1 μm order of magnitude, process is simple, strong compatibility, greatly improve production efficiency, save production cost, suitable for industrialized continuous production, meet the production order delivery requirements of thin layer high resistance silicon epitaxial wafer for photomultiplier tube device.

Description

Technical Field

[0001] This invention relates to the field of semiconductor silicon epitaxial material preparation technology, and more particularly to a method for preparing a thin-layer high-resistivity silicon epitaxial wafer for photomultiplier tube devices. Background Technology

[0002] Silicon epitaxial wafers are semiconductor materials in which a single-crystal silicon thin film (silicon epitaxial layer) is grown on a single-crystal silicon substrate along its original crystal orientation. As an information functional material, silicon epitaxial wafers are used to fabricate integrated circuits, semiconductor devices, and photodetectors. Their structure, thickness, resistivity, and the uniformity of their distribution directly determine the performance of the fabricated devices.

[0003] Silicon photomultiplier tubes (SMTs) are a new type of high-performance photodetector. They not only meet the performance requirements of various low-light detection applications but also possess significant technological advantages, better satisfying the development needs of various industries for digitized, functional, and intelligent detectors. Their key feature is the ability to generate high internal gain at low operating voltages, enabling single-photon detection. They offer stable, accurate, high-sensitivity, and high-speed ranging capabilities, and are currently primarily used in deep space mapping, remote sensing, reconnaissance, and precision tracking measurements. SMTs operate in Geiger mode; when a certain reverse bias voltage is applied, they can rapidly amplify the photocurrent. Therefore, the controllability of the structure, thickness, resistivity, and uniformity of the silicon epitaxial layer, which serves as the substrate material, is extremely stringent.

[0004] Firstly, structurally, the silicon epitaxial layer is required to be a thin, high-resistivity layer, which is significantly different from the structure of conventional silicon epitaxial layers. Its characteristic is that the silicon epitaxial layer is only on the order of a thin silicon epitaxial layer with a thickness of only 1 μm, and the resistivity value is higher than the thickness value.

[0005] Secondly, in terms of parameters, with the large-scale use of area array photomultiplier tube devices, clear requirements have been put forward for the thickness, resistivity, and uniformity of thin-layer high-resistivity silicon epitaxial layers. When each pixel of the photomultiplier tube array is illuminated by a uniform light source, poor uniformity of the thickness and resistivity of the silicon epitaxial layer will directly lead to poor uniformity of device sensitivity and gain, generating interference noise, which is not conducive to subsequent target recognition and will seriously affect the detection quality of photoelectric signals.

[0006] Therefore, based on the current process technology and performance requirements of photomultiplier tube devices, a silicon epitaxial wafer with a diameter of 150 mm is required. The silicon epitaxial layer has thin-layer parameters of (1.0~1.4) μm thickness, and the thickness non-uniformity at 5 conventional points within the wafer is required to be <2% (at a position 10 mm from the edge). The resistivity of the silicon epitaxial layer is required to be 2~3 orders of magnitude higher than that of the silicon substrate, reaching (3~10) Ω·cm. The resistivity value of the silicon epitaxial layer is higher than the thickness value, and the resistivity non-uniformity at 5 conventional points within the wafer is required to be <3% (at a position 10 mm from the edge). The structural characteristics and parameter distribution requirements of the thin-film high-resistivity silicon epitaxial layer described above are consistent with those of Chinese Patent ZL202010341314.3 (achieving an average silicon epitaxial layer thickness of 3.5~4.0 μm and an average resistivity of 0.8~1.2 Ω·cm using a growth temperature of 1115~1125℃) and Chinese Patent ZL201510287364.7 (achieving an average silicon epitaxial layer thickness of 8.0 μm using a high-temperature rapid intrinsic growth method at 1090℃). The resistivity of silicon epitaxial layers (with a resistivity of 1.7 Ω·cm and a thickness of μm) disclosed in existing patents differs significantly from conventional parameters (resistivity values ​​lower than thickness values), resulting in a significant increase in the difficulty of implementation. The main reason is that during high-temperature epitaxial growth at temperatures above 1050°C, heavily doped silicon substrates with resistivity <0.02 Ω·cm continuously release impurities into the reaction chamber, becoming self-doping factors. This severely affects the resistivity ramp-up rate and uniform distribution of the silicon epitaxial layer, which will have a serious negative impact on the preparation of the thin-layer high-resistivity silicon epitaxial wafer of this invention. Simply using the disclosed conventional high-temperature growth and rapid intrinsic growth processes cannot achieve the goals of this invention. A new technical solution is needed to solve the above problems, comprehensively suppressing the self-doping effect of impurities volatilized from the heavily doped silicon substrate from the reaction chamber environment to the early stage of the reaction, increasing the resistivity ramp-up rate of the silicon epitaxial layer, so as to achieve a thin-layer high-resistivity structure of the silicon epitaxial layer, and achieving the implementation effect of high uniformity of thickness and resistivity parameter distribution.

[0007] Currently, the technical means to achieve thin-layer high-resistivity silicon epitaxial layers in the industry include the preparation methods disclosed in Chinese patents ZL201110320451.X (silicon epitaxial layer thickness of 7μm, resistivity of 15Ω·cm) and ZL201710253915.7 (silicon epitaxial layer thickness of 1~3μm, resistivity >1.5Ω·cm). These methods employ a method of reducing the pressure in the reaction chamber (i.e., depressurized epitaxy) combined with dichlorosilane dihydrogen hydrate (DCS) as the silicon source for the growth of the silicon epitaxial layer, ultimately achieving the structural design requirements of thin-layer high-resistivity silicon epitaxial layers. However, because domestic epitaxial manufacturers mainly use trichlorosilane (SiHCl3) as the silicon source for growth, and grow silicon epitaxial layers under atmospheric pressure epitaxial conditions, as disclosed in several Chinese invention patents ZL200810023330.7, ZL201010120709.7, ZL201310152949.9, ZL201410570481.X, ZL201810332575.1, and ZL202110883669.X, the reduced pressure epitaxial process is incompatible with the trichlorosilane (SiHCl3) production materials and atmospheric pressure epitaxial equipment conditions used in conventional mass production. This will result in material switching and discharge, modification of process equipment conditions, and significant losses in production capacity, as well as a significant increase in production costs. It is not suitable for the continuous industrial production requirements and affects the delivery of production orders.

[0008] To address the issue that atmospheric pressure epitaxial growth processes primarily involve the continuous volatilization of impurities into the reaction chamber during high-temperature epitaxial growth of heavily doped silicon substrates, affecting the resistivity rise and distribution characteristics of the silicon epitaxial layer, Chinese patent ZL201810332575.1 discloses a preparation method that utilizes periodic and rapid alternation of hydrogen flow rate, ranging from 40 L / min to 400 L / min, to purge the reaction chamber multiple times. This method can achieve the preparation of high-resistivity silicon epitaxial layers on heavily doped silicon substrates. However, this variable-flow hydrogen cyclic purging method is very complex, requiring a total of 6 switching of hydrogen flow rates and repeated cyclic purging, which will significantly increase production costs and is not suitable for the cost control requirements of continuous industrial production.

[0009] Therefore, a new technical solution is needed to address the structural, thickness, resistivity, and uniformity requirements of thin-layer high-resistivity silicon epitaxial layers for photomultiplier tube devices. This solution should ensure control over the thickness and resistivity of the silicon epitaxial layer while maintaining good compatibility with existing conventional silicon epitaxial layers that commonly use trichlorosilane (SiHCl3) as the silicon source. It should also employ atmospheric pressure silicon epitaxial growth equipment and processes, simplify the process, reduce production costs, and enable continuous industrial production. Summary of the Invention

[0010] The existing publicly available technology for thin-layer high-resistivity silicon epitaxial wafers requires dichlorosilane dihydrogen hydrate (DCS) as the silicon source for growth and reduced pressure epitaxy as the equipment process condition. This is incompatible with the conventional mass production of silicon epitaxial layers, which uses trichlorosilane dihydrogen hydrate (SiHCl3) as the silicon source and atmospheric pressure epitaxy equipment as the process condition. This results in significant modifications to equipment and process conditions, changes in production materials, increased production complexity due to material handling issues, substantial increases in production costs, and lost production capacity. Typically, resolving these issues and restoring production capacity takes three days, significantly impacting capacity and affecting the delivery requirements of orders for thin-layer high-resistivity silicon epitaxial wafers used in photomultiplier tube devices. The purpose of this invention is to overcome the above-mentioned problems. By designing a process of repeatedly etching the reaction chamber and graphite substrate with hydrogen chloride gas and cyclically cleaning the polycrystalline silicon coating layer before silicon substrate mounting, and by precisely adjusting the process parameters of hydrogen flow rate, trichlorosilane flow rate, and silicon epitaxial layer reaction growth temperature under atmospheric pressure epitaxial conditions, the growth rate of silicon epitaxial layer is significantly reduced, thereby prolonging the reaction process of thin silicon epitaxial layer, increasing the proportion of steady-state growth stage, and achieving a high uniformity distribution of thickness and resistivity of thin high-resistivity silicon epitaxial layer. Finally, a thin high-resistivity silicon epitaxial layer with a thickness on the order of 1 μm and a high uniformity distribution of thickness and resistivity is obtained. The process is simple and suitable for industrial continuous production, which significantly improves production efficiency and greatly meets the production order delivery requirements of thin high-resistivity silicon epitaxial wafers for photomultiplier tube devices.

[0011] The technical problem to be solved by the present invention is achieved through the following solution: a method for preparing a thin high-resistivity silicon epitaxial wafer for a photomultiplier tube device, comprising the following steps:

[0012] Step 1: The reaction chamber is an atmospheric pressure reaction chamber. The temperature of the reaction chamber is set to 1130~1150℃. Hydrogen chloride gas is introduced to etch the reaction chamber and graphite substrate. The flow rate of hydrogen chloride gas is set to 18~20 L / min and the etching time is set to 1~2 min.

[0013] Step 2: Cool the reaction chamber to 1110~1130℃, and introduce gaseous trichlorosilane carried by hydrogen as the growth material. The hydrogen flow rate is set to 330~350 L / min, and the flow rate of gaseous trichlorosilane is set to 30~33 L / min. Deposit a polycrystalline silicon coating layer on the graphite substrate in the reaction chamber. The deposition time is set to 60~80 sec.

[0014] Step 3: Heat the reaction chamber to 1130~1150℃, and introduce hydrogen chloride gas to etch the reaction chamber and graphite substrate. The hydrogen chloride gas flow rate is set to 18~20 L / min, and the etching time is set to 1~2 min.

[0015] Step 4: Cool the reaction chamber to 1110~1130℃, introduce gaseous trichlorosilane carried by hydrogen as the growth material, set the hydrogen flow rate to 330~350 L / min, set the gaseous trichlorosilane flow rate to 30~33 L / min, deposit a polycrystalline silicon coating layer on the graphite substrate in the reaction chamber, and set the deposition time to 60~80 sec.

[0016] Step 5: Heat the reaction chamber to 1130~1150℃, and introduce hydrogen chloride gas to etch the reaction chamber and graphite substrate. The hydrogen chloride gas flow rate is set to 18~20 L / min, and the etching time is set to 1~2 min.

[0017] Step 6: Cool the reaction chamber to 1110~1130℃, introduce gaseous trichlorosilane carried by hydrogen as the growth material, set the hydrogen flow rate to 330~350 L / min, set the gaseous trichlorosilane flow rate to 30~33 L / min, deposit a polycrystalline silicon coating layer on the graphite substrate in the reaction chamber, and set the deposition time to 60~80 sec.

[0018] Step 7: Cool the reaction chamber to 40~60 ℃, place the silicon substrate in the pit of the graphite base of the reaction chamber, heat the reaction chamber to 1130~1150 ℃, set the hydrogen flow rate to 330~350 L / min, and use hydrogen to bake the polished surface of the silicon substrate at high temperature for 120~180 sec.

[0019] Step 8: Cool the reaction chamber to 1090~1110℃, introduce gaseous trichlorosilane carried by hydrogen as a growth material, and grow a silicon epitaxial layer on the polished surface of the silicon substrate to form a silicon epitaxial wafer. The hydrogen flow rate is set to 330~350L / min, the gaseous trichlorosilane flow rate is set to 3~5 L / min, and the silicon epitaxial layer growth rate is set to 0.3~0.4 μm / min.

[0020] Step 9: Reduce the temperature of the reaction chamber to 40~60℃ and remove the silicon epitaxial wafer from the pit in the graphite substrate.

[0021] The silicon substrate has a diameter of 150 mm, a resistivity of less than 0.02 Ω·cm, a polished front surface, and a tightly packed silicon dioxide layer on the back side with a thickness of 400~600 nm.

[0022] The target growth thickness of the silicon epitaxial layer is 1.0~1.4 μm, with an intra-wafer thickness distribution non-uniformity of no more than 2%, and the target resistivity of the silicon epitaxial layer is 3~10 Ω·cm, with an intra-wafer resistivity distribution non-uniformity of no more than 3%.

[0023] The variation in the radial temperature distribution within the wafer during the growth process of the silicon epitaxial layer is no higher than 5°C.

[0024] The beneficial effects of this invention compared to the prior art are as follows: Compared with existing methods for preparing thin-layer high-resistivity silicon epitaxial wafers of the same specifications, this invention first achieves compatibility with the trichlorosilane (SiHCl3) raw material and atmospheric pressure epitaxial equipment process conditions used in conventional silicon epitaxial layer production. It overcomes the problem that existing preparation methods require the use of dichlorosilane (DCS) as the silicon source for growth and the switching of vacuum epitaxial equipment as the process conditions, significantly reducing the production cost waste and serious capacity loss caused by the switching of growth materials and the modification of process equipment.

[0025] Secondly, this invention, by designing a process of repeatedly etching the reaction chamber and graphite substrate with hydrogen chloride gas and cyclically cleaning the polysilicon coating layer before silicon substrate mounting, purifies the reaction chamber and provides the clean growth environment required for thin-layer high-resistivity silicon epitaxial layers. This significantly reduces the negative impact of the self-doping effect caused by the thermal volatilization of impurities in the heavily doped silicon substrate on the resistivity ramp-up process of the silicon epitaxial layer. Furthermore, by precisely adjusting the flow rates of process hydrogen, trichlorosilane, and the reaction growth temperature of the silicon epitaxial layer, the growth rate of the silicon epitaxial layer is reduced, and the steady-state reaction time is extended, thus achieving thin-layer high-resistivity silicon epitaxial wafers on the order of 1 μm, and obtaining good thickness and resistivity uniformity distribution.

[0026] In summary, this invention has good compatibility with existing growth raw materials and process conditions, a simple growth process, and strong stability. It can achieve continuous industrial production without process condition modification or production material switching, saving the 3 days of production preparation time usually required for conventional equipment process condition modification and production material switching. It greatly saves production materials, improves production efficiency, and meets the production order delivery requirements for thin-layer high-resistivity silicon epitaxial wafers for photomultiplier tube devices. Attached Figure Description

[0027] Figure 1 This is a 5-point distribution diagram of the intra-chip thickness in Embodiment 1 of the invention;

[0028] Figure 2 This is a 5-point distribution diagram of the on-chip resistivity of Embodiment 1 of the invention;

[0029] Figure 3 This is a 5-point distribution diagram of the intra-chip thickness in Embodiment 2 of the invention;

[0030] Figure 4 This is a 5-point distribution diagram of the on-chip resistivity of Embodiment 2 of the invention;

[0031] Figure 5 This is a 5-point distribution diagram of the intra-chip thickness in Embodiment 3 of the invention;

[0032] Figure 6 This is a 5-point distribution diagram of the on-chip resistivity of Embodiment 3 of the invention;

[0033] Figure 7 This is a 5-point distribution diagram of the intra-chip thickness in Embodiment 4 of the invention;

[0034] Figure 8 This is a 5-point distribution diagram of the on-chip resistivity of Embodiment 4 of the invention;

[0035] Figure 9 For comparison, the on-chip resistivity distribution at 5 points is shown in Example 1;

[0036] Figure 10 For comparison, the on-chip resistivity distribution at 5 points is shown in Example 2;

[0037] Figure 11 For comparison, the on-chip resistivity distribution at 5 points in Example 3;

[0038] Figure 12 For comparison, the on-chip resistivity distribution at 5 points in Example 4;

[0039] Figure 13 The image shows a 5-point distribution of the on-chip resistivity in Example 5 for comparison. Detailed Implementation

[0040] The specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings, but the embodiments of the invention are not limited thereto.

[0041] A method for fabricating a thin, high-resistivity silicon epitaxial wafer for photomultiplier tube devices is disclosed. The target parameters require the growth of a 1.0–1.4 μm thin silicon epitaxial layer on a heavily doped silicon substrate with a resistivity <0.02 Ω·cm to form a silicon epitaxial wafer. The resistivity of the silicon epitaxial layer needs to achieve a rapid jump of 2–3 orders of magnitude from below 0.02 Ω·cm to the order of 3–10 Ω·cm. At the same time, a high uniformity distribution effect is achieved, with the thickness distribution non-uniformity of the silicon epitaxial layer not exceeding 2% and the resistivity distribution non-uniformity not exceeding 3%.

[0042] The heavily doped silicon substrate used in this invention has a diameter of 150 mm, a polished front surface, and a tightly packed silicon dioxide layer on the back side with a thickness of 500 nm. The growth process uses trichlorosilane (SiHCl3) as the raw material and employs an atmospheric pressure reaction chamber compatible with existing conventional silicon epitaxial wafer growth processes. During the silicon epitaxial layer growth process, the radial temperature distribution variation within the wafer is maintained at 2-5 °C. The thickness and resistivity of the silicon epitaxial layer are tested using the conventional 5-point test method, recording test data at the center point and at positions 10 mm from the edge around the perimeter, and evaluating the uniformity of the silicon epitaxial layer parameters.

[0043] Example 1; Step 1: The reaction chamber is an atmospheric pressure reaction chamber. The temperature of the reaction chamber is set to 1135°C. Hydrogen chloride gas is introduced to etch the reaction chamber and the graphite substrate. The flow rate of hydrogen chloride gas is set to 19 L / min and the etching time is set to 1 min.

[0044] Step 2: Cool the reaction chamber to 1110℃, and introduce gaseous trichlorosilane carried by hydrogen as the growth material. The hydrogen flow rate is set to 335L / min, and the gaseous trichlorosilane flow rate is set to 32L / min. Deposit a polycrystalline silicon coating layer on the graphite substrate in the reaction chamber, and the deposition time is set to 65 seconds.

[0045] Step 3: Heat the reaction chamber to 1135℃, and introduce hydrogen chloride gas to etch the reaction chamber and graphite substrate. The hydrogen chloride gas flow rate is set to 19 L / min, and the etching time is set to 1 min.

[0046] Step 4: Cool the reaction chamber to 1110℃, introduce gaseous trichlorosilane carried by hydrogen as the growth material, set the hydrogen flow rate to 335 L / min, and the gaseous trichlorosilane flow rate to 32 L / min, deposit a polycrystalline silicon coating layer on the graphite substrate in the reaction chamber, and set the deposition time to 65 seconds.

[0047] Step 5: Heat the reaction chamber to 1135℃, and introduce hydrogen chloride gas to etch the reaction chamber and graphite substrate. The hydrogen chloride gas flow rate is set to 19 L / min, and the etching time is set to 1 min.

[0048] Step 6: Cool the reaction chamber to 1110℃, introduce gaseous trichlorosilane carried by hydrogen as the growth material, set the hydrogen flow rate to 335 L / min, and the gaseous trichlorosilane flow rate to 32 L / min, deposit a polycrystalline silicon coating layer on the graphite substrate in the reaction chamber, and set the deposition time to 65 sec.

[0049] Step 7: Cool the reaction chamber to 45 ℃, place the silicon substrate in the pit of the graphite base of the reaction chamber, heat the reaction chamber to 1135 ℃, set the hydrogen flow rate to 335 L / min, and use hydrogen to bake the polished surface of the silicon substrate at high temperature for 125 sec.

[0050] Step 8: Cool the reaction chamber to 1095℃, introduce gaseous trichlorosilane carried by hydrogen as a growth material, and grow a silicon epitaxial layer on the polished surface of the silicon substrate to form a silicon epitaxial wafer. The hydrogen flow rate is set to 335 L / min, the gaseous trichlorosilane flow rate is set to 5 L / min, and the silicon epitaxial layer growth rate is set to 0.37 μm / min.

[0051] Step 9: Reduce the temperature of the reaction chamber to 45°C and remove the silicon epitaxial wafer from the pit in the graphite substrate.

[0052] The silicon epitaxial layers obtained in Example 1 had thicknesses of 1.288 μm, 1.301 μm, 1.312 μm, 1.277 μm, and 1.289 μm, respectively. Figure 1 As shown, the resistivity of the silicon epitaxial layers are 3.225 Ω·cm, 3.104 Ω·cm, 3.092 Ω·cm, 3.128 Ω·cm, and 3.136 Ω·cm, respectively. Figure 2 As shown.

[0053] Example 2; Step 1: The reaction chamber is an atmospheric pressure reaction chamber. The temperature of the reaction chamber is set to 1135°C. Hydrogen chloride gas is introduced to etch the reaction chamber and the graphite substrate. The flow rate of hydrogen chloride gas is set to 19 L / min and the etching time is set to 2 min.

[0054] Step 2: Cool the reaction chamber to 1115℃, introduce gaseous trichlorosilane carried by hydrogen as the growth material, set the hydrogen flow rate to 335 L / min, and the gaseous trichlorosilane flow rate to 31 L / min, deposit a polycrystalline silicon coating layer on the graphite substrate in the reaction chamber, and set the deposition time to 75 sec.

[0055] Step 3: Heat the reaction chamber to 1135℃, and introduce hydrogen chloride gas to etch the reaction chamber and graphite substrate. The hydrogen chloride gas flow rate is set to 19 L / min, and the etching time is set to 2 min.

[0056] Step 4: Cool the reaction chamber to 1115℃, introduce gaseous trichlorosilane carried by hydrogen as the growth material, set the hydrogen flow rate to 335 L / min and the gaseous trichlorosilane flow rate to 31 L / min, deposit a polycrystalline silicon coating layer on the graphite substrate in the reaction chamber, and set the deposition time to 75 sec.

[0057] Step 5: Heat the reaction chamber to 1135℃, and introduce hydrogen chloride gas to etch the reaction chamber and graphite substrate. The hydrogen chloride gas flow rate is set to 19 L / min, and the etching time is set to 2 min.

[0058] Step 6: Cool the reaction chamber to 1115℃, introduce gaseous trichlorosilane carried by hydrogen as the growth material, set the hydrogen flow rate to 335 L / min, and the gaseous trichlorosilane flow rate to 31 L / min, deposit a polycrystalline silicon coating layer on the graphite substrate in the reaction chamber, and set the deposition time to 75 sec.

[0059] Step 7: Cool the reaction chamber to 45 ℃, place the silicon substrate in the pit of the graphite base of the reaction chamber, heat the reaction chamber to 1138 ℃, set the hydrogen flow rate to 340 L / min, and use hydrogen to bake the polished surface of the silicon substrate at high temperature for 170 sec.

[0060] Step 8: Cool the reaction chamber to 1110℃, introduce gaseous trichlorosilane carried by hydrogen as a growth material, and grow a silicon epitaxial layer on the polished surface of the silicon substrate to form a silicon epitaxial wafer. The hydrogen flow rate is set to 335 L / min, the gaseous trichlorosilane flow rate is set to 4 L / min, and the silicon epitaxial layer growth rate is set to 0.35 μm / min.

[0061] Step 9: Reduce the temperature of the reaction chamber to 45°C and remove the silicon epitaxial wafer from the pit in the graphite substrate.

[0062] The silicon epitaxial layers obtained in Example 2 had thicknesses of 1.297 μm, 1.322 μm, 1.334 μm, 1.303 μm, and 1.295 μm, respectively. Figure 3 As shown, the resistivity of the silicon epitaxial layers are 4.543 Ω·cm, 4.758 Ω·cm, 4.587 Ω·cm, 4.612 Ω·cm, and 4.623 Ω·cm, respectively. Figure 4 As shown.

[0063] Example 3; Step 1: The reaction chamber is an atmospheric pressure reaction chamber. The temperature of the reaction chamber is set to 1148°C. Hydrogen chloride gas is introduced to etch the reaction chamber and the graphite substrate. The flow rate of hydrogen chloride gas is set to 20 L / min, and the etching time is set to 2 min.

[0064] Step 2: Cool the reaction chamber to 1112℃, and introduce gaseous trichlorosilane carried by hydrogen as the growth material. The hydrogen flow rate is set to 330 L / min, and the gaseous trichlorosilane flow rate is set to 33 L / min. Deposit a polycrystalline silicon coating layer on the graphite substrate in the reaction chamber, and the deposition time is set to 80 sec.

[0065] Step 3: Heat the reaction chamber to 1148℃, and introduce hydrogen chloride gas to etch the reaction chamber and graphite substrate. The hydrogen chloride gas flow rate is set to 20 L / min, and the etching time is set to 2 min.

[0066] Step 4: Cool the reaction chamber to 1112℃, introduce gaseous trichlorosilane carried by hydrogen as the growth material, set the hydrogen flow rate to 330 L / min, and the gaseous trichlorosilane flow rate to 33 L / min, deposit a polycrystalline silicon coating layer on the graphite substrate in the reaction chamber, and set the deposition time to 80 sec.

[0067] Step 5: Heat the reaction chamber to 1148℃, and introduce hydrogen chloride gas to etch the reaction chamber and graphite substrate. The hydrogen chloride gas flow rate is set to 20 L / min, and the etching time is set to 2 min.

[0068] Step 6: Cool the reaction chamber to 1112℃, introduce gaseous trichlorosilane carried by hydrogen as the growth material, set the hydrogen flow rate to 330 L / min, and the gaseous trichlorosilane flow rate to 33 L / min, deposit a polycrystalline silicon coating layer on the graphite substrate in the reaction chamber, and set the deposition time to 80 sec.

[0069] Step 7: Cool the reaction chamber to 55 ℃, place the silicon substrate in the pit of the graphite base in the reaction chamber, heat the reaction chamber to 1138 ℃, set the hydrogen flow rate to 335 L / min, and use hydrogen to bake the polished surface of the silicon substrate at high temperature for 150 sec.

[0070] Step 8: Cool the reaction chamber to 1090℃, introduce gaseous trichlorosilane carried by hydrogen as a growth material, and grow a silicon epitaxial layer on the polished surface of the silicon substrate to form a silicon epitaxial wafer. The hydrogen flow rate is set to 332 L / min, the gaseous trichlorosilane flow rate is set to 4 L / min, and the silicon epitaxial layer growth rate is set to 0.33 μm / min.

[0071] Step 9: Reduce the temperature of the reaction chamber to 40°C and remove the silicon epitaxial wafer from the pit in the graphite substrate.

[0072] The silicon epitaxial layers obtained in Example 3 had thicknesses of 1.310 μm, 1.335 μm, 1.344 μm, 1.308 μm, and 1.302 μm, respectively. Figure 5 As shown, the resistivity of the silicon epitaxial layers are 5.417 Ω·cm, 5.568 Ω·cm, 5.302 Ω·cm, 5.462 Ω·cm, and 5.335 Ω·cm, respectively. Figure 6 As shown.

[0073] Example 4; Step 1: The reaction chamber is an atmospheric pressure reaction chamber. The temperature of the reaction chamber is set to 1145°C. Hydrogen chloride gas is introduced to etch the reaction chamber and the graphite substrate. The flow rate of hydrogen chloride gas is set to 20 L / min and the etching time is set to 1 min.

[0074] Step 2: Cool the reaction chamber to 1118℃, and introduce gaseous trichlorosilane carried by hydrogen as the growth material. The hydrogen flow rate is set to 335 L / min, and the gaseous trichlorosilane flow rate is set to 32 L / min. Deposit a polycrystalline silicon coating layer on the graphite substrate in the reaction chamber, and the deposition time is set to 70 sec.

[0075] Step 3: Heat the reaction chamber to 1145℃, and introduce hydrogen chloride gas to etch the reaction chamber and graphite substrate. The hydrogen chloride gas flow rate is set to 20 L / min, and the etching time is set to 2 min.

[0076] Step 4: Cool the reaction chamber to 1118℃, introduce gaseous trichlorosilane carried by hydrogen as the growth material, set the hydrogen flow rate to 335 L / min, and the gaseous trichlorosilane flow rate to 32 L / min, deposit a polycrystalline silicon coating layer on the graphite substrate in the reaction chamber, and set the deposition time to 70 sec.

[0077] Step 5: Heat the reaction chamber to 1145℃, and introduce hydrogen chloride gas to etch the reaction chamber and graphite substrate. The hydrogen chloride gas flow rate is set to 20 L / min, and the etching time is set to 2 min.

[0078] Step 6: Cool the reaction chamber to 1118℃, introduce gaseous trichlorosilane carried by hydrogen as the growth material, set the hydrogen flow rate to 335 L / min, and the gaseous trichlorosilane flow rate to 32 L / min, deposit a polycrystalline silicon coating layer on the graphite substrate in the reaction chamber, and set the deposition time to 70 sec.

[0079] Step 7: Cool the reaction chamber to 60°C, place the silicon substrate in the pit of the graphite base in the reaction chamber, heat the reaction chamber to 1145°C, set the hydrogen flow rate to 350 L / min, and use hydrogen to bake the polished surface of the silicon substrate at high temperature for 125 seconds.

[0080] Step 8: Cool the reaction chamber to 1095℃, introduce gaseous trichlorosilane carried by hydrogen as a growth material, and grow a silicon epitaxial layer on the polished surface of the silicon substrate to form a silicon epitaxial wafer. The hydrogen flow rate is set to 350 L / min, the gaseous trichlorosilane flow rate is set to 3 L / min, and the silicon epitaxial layer growth rate is set to 0.3 μm / min.

[0081] Step 9: Reduce the temperature of the reaction chamber to 40°C and remove the silicon epitaxial wafer from the pit in the graphite substrate.

[0082] The silicon epitaxial layers obtained in Example 4 had thicknesses of 1.325 μm, 1.346 μm, 1.369 μm, 1.326 μm, and 1.322 μm, respectively. Figure 7 As shown, the resistivity of the silicon epitaxial layers are 8.204 Ω·cm, 8.433 Ω·cm, 8.165 Ω·cm, 8.112 Ω·cm, and 8.170 Ω·cm, respectively. Figure 8 As shown.

[0083] Comparative Example 1; Step 1: The reaction chamber is an atmospheric pressure reaction chamber. The temperature of the reaction chamber is set to 1130°C. Hydrogen chloride gas is introduced to etch the reaction chamber and the graphite substrate. The flow rate of hydrogen chloride gas is set to 18 L / min, and the etching time is set to 1 min.

[0084] Step 2: Cool the reaction chamber to 1110℃, introduce gaseous trichlorosilane carried by hydrogen as the growth material, set the hydrogen flow rate to 330 L / min, and the gaseous trichlorosilane flow rate to 30 L / min, deposit a polycrystalline silicon coating layer on the graphite substrate in the reaction chamber, and set the deposition time to 60 sec.

[0085] Step 3: Cool the reaction chamber to 60°C, place the silicon substrate in the pit of the graphite base in the reaction chamber, heat the reaction chamber to 1130°C, set the hydrogen flow rate to 330 L / min, and use hydrogen to bake the polished surface of the silicon substrate at high temperature for 12 seconds.

[0086] Step 4: Cool the reaction chamber to 1110℃, introduce gaseous trichlorosilane carried by hydrogen as the growth material, and grow a silicon epitaxial layer on the polished surface of the silicon substrate to form a silicon epitaxial wafer. The hydrogen flow rate is set to 330 L / min, the gaseous trichlorosilane flow rate is set to 5 L / min, and the silicon epitaxial layer growth rate is set to 0.4 μm / min.

[0087] Step 5: Reduce the temperature of the reaction chamber to 40°C and remove the silicon epitaxial wafer from the pit in the graphite substrate.

[0088] The resistivity of the silicon epitaxial layers obtained in Comparative Example 1 were 1.008 Ω·cm, 1.265 Ω·cm, 1.023 Ω·cm, 1.109 Ω·cm, and 1.126 Ω·cm, respectively. Figure 9 As shown, the resistivity does not meet the target requirement of 3~10 Ω·cm, indicating poor quality. This suggests that the heavy doped silicon substrate in the reaction chamber volatilized a large amount of impurities, which affected the resistivity ramp-up rate in the subsequent silicon epitaxial layer growth process.

[0089] Comparative Example 2; Step 1: The reaction chamber is an atmospheric pressure reaction chamber. The temperature of the reaction chamber is set to 1130°C. Hydrogen chloride gas is introduced to etch the reaction chamber and the graphite substrate. The flow rate of hydrogen chloride gas is set to 18 L / min, and the etching time is set to 1 min.

[0090] Step 2: Cool the reaction chamber to 1110℃, and introduce gaseous trichlorosilane carried by hydrogen as the growth material. The hydrogen flow rate is set to 330 L / min, and the gaseous trichlorosilane flow rate is set to 30 L / min. Deposit a polycrystalline silicon coating layer on the graphite substrate in the reaction chamber, and the deposition time is set to 60 sec.

[0091] Step 3: Heat the reaction chamber to 1130℃, and introduce hydrogen chloride gas to etch the reaction chamber and graphite substrate. The hydrogen chloride gas flow rate is set to 18 L / min, and the etching time is set to 1 min.

[0092] Step 4: Cool the reaction chamber to 1110℃, introduce gaseous trichlorosilane carried by hydrogen as the growth material, set the hydrogen flow rate to 330 L / min and the gaseous trichlorosilane flow rate to 30 L / min, deposit a polycrystalline silicon coating layer on the graphite substrate in the reaction chamber, and set the deposition time to 60 sec.

[0093] Step 5: Cool the reaction chamber to 60°C, place the silicon substrate in the pit of the graphite base in the reaction chamber, heat the reaction chamber to 1130°C, set the hydrogen flow rate to 330 L / min, and use hydrogen to bake the polished surface of the silicon substrate at high temperature for 120 seconds.

[0094] Step 6: Cool the reaction chamber to 1110℃, introduce gaseous trichlorosilane carried by hydrogen as a growth material, and grow a silicon epitaxial layer on the polished surface of the silicon substrate to form a silicon epitaxial wafer. The hydrogen flow rate is set to 330 L / min, the gaseous trichlorosilane flow rate is set to 5 L / min, and the silicon epitaxial layer growth rate is set to 0.4 μm / min.

[0095] Step 7: Reduce the temperature of the reaction chamber to 40°C and remove the silicon epitaxial wafer from the pit in the graphite substrate.

[0096] The resistivity of the silicon epitaxial layer prepared in Comparative Example 2 was 1.664 Ω·cm, 1.807 Ω·cm, 1.722 Ω·cm, 1.643 Ω·cm, and 1.691 Ω·cm, respectively. Figure 10 As shown, the resistivity does not meet the target requirement of 3~10 Ω·cm, indicating poor quality. This suggests that the heavy doped silicon substrate in the reaction chamber volatilized a large amount of impurities, which affected the resistivity ramp-up rate in the subsequent silicon epitaxial layer growth process.

[0097] Comparative Example 3; Step 1: The reaction chamber is an atmospheric pressure reaction chamber. The temperature of the reaction chamber is set to 1130°C. Hydrogen chloride gas is introduced to etch the reaction chamber and the graphite substrate. The flow rate of hydrogen chloride gas is set to 18 L / min, and the etching time is set to 1 min.

[0098] Step 2: Cool the reaction chamber to 1110℃, introduce gaseous trichlorosilane carried by hydrogen as the growth material, set the hydrogen flow rate to 330 L / min and the gaseous trichlorosilane flow rate to 30 L / min, deposit a polycrystalline silicon coating layer on the graphite substrate in the reaction chamber, and set the deposition time to 60 sec.

[0099] Step 3: Heat the reaction chamber to 1130℃, and introduce hydrogen chloride gas to etch the reaction chamber and graphite substrate. The hydrogen chloride gas flow rate is set to 18 L / min, and the etching time is set to 1 min.

[0100] Step 4: Cool the reaction chamber to 1110℃, introduce gaseous trichlorosilane carried by hydrogen as the growth material, set the hydrogen flow rate to 330 L / min and the gaseous trichlorosilane flow rate to 30 L / min, deposit a polycrystalline silicon coating layer on the graphite substrate in the reaction chamber, and set the deposition time to 60 sec.

[0101] Step 5: Heat the reaction chamber to 1130℃, and introduce hydrogen chloride gas to etch the reaction chamber and graphite substrate. The hydrogen chloride gas flow rate is set to 18 L / min, and the etching time is set to 1 min.

[0102] Step 6: Cool the reaction chamber to 1110℃, introduce gaseous trichlorosilane carried by hydrogen as the growth material, set the hydrogen flow rate to 330 L / min, and the gaseous trichlorosilane flow rate to 30 L / min, deposit a polycrystalline silicon coating layer on the graphite substrate in the reaction chamber, and set the deposition time to 60 sec.

[0103] Step 7: Cool the reaction chamber to 60°C, place the silicon substrate in the pit of the graphite base in the reaction chamber, heat the reaction chamber to 1130°C, and use HCl gas with a flow rate of 3L / min to polish the surface of the silicon substrate for 60 seconds.

[0104] Step 8: Cool the reaction chamber to 1110℃, introduce gaseous trichlorosilane carried by hydrogen as a growth material, and grow a silicon epitaxial layer on the polished surface of the silicon substrate to form a silicon epitaxial wafer. The hydrogen flow rate is set to 330 L / min, the gaseous trichlorosilane flow rate is set to 5 L / min, and the silicon epitaxial layer growth rate is set to 0.4 μm / min.

[0105] Step 9: Reduce the temperature of the reaction chamber to 40°C and remove the silicon epitaxial wafer from the pit in the graphite substrate.

[0106] The resistivity of the silicon epitaxial layer obtained in Comparative Example 3 were 2.865 Ω·cm, 3.084 Ω·cm, 2.760 Ω·cm, 2.889 Ω·cm, and 2.905 Ω·cm, respectively. Figure 11As shown, the requirement that all test points meet the target resistivity requirement of 3~10 Ω·cm is not met. This indicates that the process of polishing the silicon substrate surface with HCl gas at a flow rate of 3L / min instead of the process of high-temperature baking the polished surface of the silicon substrate with hydrogen gas accelerates the volatilization rate of impurities on the surface of the heavily doped silicon substrate, causing a more serious self-doping effect and affecting the resistivity ramp-up rate at the edge of the silicon epitaxial layer.

[0107] Comparative Example 4; Step 1: The reaction chamber is an atmospheric pressure reaction chamber. The temperature of the reaction chamber is set to 1130°C. Hydrogen chloride gas is introduced to etch the reaction chamber and the graphite substrate. The flow rate of hydrogen chloride gas is set to 18 L / min, and the etching time is set to 1 min.

[0108] Step 2: Cool the reaction chamber to 1110℃, introduce gaseous trichlorosilane carried by hydrogen as the growth material, set the hydrogen flow rate to 330 L / min and the gaseous trichlorosilane flow rate to 30 L / min, deposit a polycrystalline silicon coating layer on the graphite substrate in the reaction chamber, and set the deposition time to 60 sec.

[0109] Step 3: Heat the reaction chamber to 1130℃, and introduce hydrogen chloride gas to etch the reaction chamber and graphite substrate. The hydrogen chloride gas flow rate is set to 18 L / min, and the etching time is set to 1 min.

[0110] Step 4: Cool the reaction chamber to 1110℃, introduce gaseous trichlorosilane carried by hydrogen as the growth material, set the hydrogen flow rate to 330 L / min, and the gaseous trichlorosilane flow rate to 30 L / min, deposit a polycrystalline silicon coating layer on the graphite substrate in the reaction chamber, and set the deposition time to 60 sec.

[0111] Step 5: Heat the reaction chamber to 1130℃, and introduce hydrogen chloride gas to etch the reaction chamber and graphite substrate. The hydrogen chloride gas flow rate is set to 18 L / min, and the etching time is set to 1 min.

[0112] Step 6: Cool the reaction chamber to 1110℃, introduce gaseous trichlorosilane carried by hydrogen as the growth material, set the hydrogen flow rate to 330 L / min, and the gaseous trichlorosilane flow rate to 30 L / min, deposit a polycrystalline silicon coating layer on the graphite substrate in the reaction chamber, and set the deposition time to 60 sec.

[0113] Step 7: Cool the reaction chamber to 60°C, place the silicon substrate in the pit of the graphite base in the reaction chamber, heat the reaction chamber to 1130°C, set the hydrogen flow rate to 330 L / min, and use hydrogen to bake the polished surface of the silicon substrate at high temperature for 120 seconds.

[0114] Step 8: Cool the reaction chamber to 1110℃, introduce gaseous trichlorosilane carried by hydrogen as a growth material, and grow a silicon epitaxial layer on the polished surface of the silicon substrate to form a silicon epitaxial wafer. The hydrogen flow rate is set to 330 L / min, the gaseous trichlorosilane flow rate is set to 7 L / min, and the silicon epitaxial layer growth rate is set to 0.6 μm / min.

[0115] Step 9: Reduce the temperature of the reaction chamber to 40°C and remove the silicon epitaxial wafer from the pit in the graphite substrate.

[0116] The resistivity of the silicon epitaxial layers obtained in Comparative Example 4 were 2.683 Ω·cm, 2.765 Ω·cm, 2.694 Ω·cm, 2.772 Ω·cm, and 2.756 Ω·cm, respectively. Figure 12 As shown, the target resistivity does not meet the requirement of 3~10 Ω·cm, indicating that when the silicon epitaxial layer growth rate is set to 0.6 μm / min, the rate is too fast and the silicon epitaxial layer growth time is too short, resulting in a short reaction stabilization time ratio, which fails to provide sufficient ramp-up time required for the silicon epitaxial layer to reach the target resistivity.

[0117] Comparative Example 5; Step 1: The reaction chamber is an atmospheric pressure reaction chamber. The temperature of the reaction chamber is set to 1130°C. Hydrogen chloride gas is introduced to etch the reaction chamber and the graphite substrate. The flow rate of hydrogen chloride gas is set to 18 L / min, and the etching time is set to 1 min.

[0118] Step 2: Cool the reaction chamber to 1110℃, introduce gaseous trichlorosilane carried by hydrogen as the growth material, set the hydrogen flow rate to 330 L / min and the gaseous trichlorosilane flow rate to 30 L / min, deposit a polycrystalline silicon coating layer on the graphite substrate in the reaction chamber, and set the deposition time to 60 sec.

[0119] Step 3: Heat the reaction chamber to 1130℃, and introduce hydrogen chloride gas to etch the reaction chamber and graphite substrate. The hydrogen chloride gas flow rate is set to 18 L / min, and the etching time is set to 1 min.

[0120] Step 4: Cool the reaction chamber to 1110℃, introduce gaseous trichlorosilane carried by hydrogen as the growth material, set the hydrogen flow rate to 330 L / min, and the gaseous trichlorosilane flow rate to 30 L / min, deposit a polycrystalline silicon coating layer on the graphite substrate in the reaction chamber, and set the deposition time to 60 sec.

[0121] Step 5: Heat the reaction chamber to 1130℃, and introduce hydrogen chloride gas to etch the reaction chamber and graphite substrate. The hydrogen chloride gas flow rate is set to 18 L / min, and the etching time is set to 1 min.

[0122] Step 6: Cool the reaction chamber to 1110℃, introduce gaseous trichlorosilane carried by hydrogen as the growth material, set the hydrogen flow rate to 330 L / min, and the gaseous trichlorosilane flow rate to 30 L / min, deposit a polycrystalline silicon coating layer on the graphite substrate in the reaction chamber, and set the deposition time to 60 sec.

[0123] Step 7: Cool the reaction chamber to 60 ℃, place the silicon substrate in the pit of the graphite base of the reaction chamber, heat the reaction chamber to 1130 ℃, set the hydrogen flow rate to 330 L / min, and use hydrogen to bake the polished surface of the silicon substrate at high temperature for 120 sec.

[0124] Step 8: Cool the reaction chamber to 1130℃, introduce gaseous trichlorosilane carried by hydrogen as a growth material, and grow a silicon epitaxial layer on the polished surface of the silicon substrate to form a silicon epitaxial wafer. The hydrogen flow rate is set to 330 L / min, the gaseous trichlorosilane flow rate is set to 5 L / min, and the silicon epitaxial layer growth rate is set to 0.5 μm / min.

[0125] Step 9: Reduce the temperature of the reaction chamber to 40°C and remove the silicon epitaxial wafer from the pit in the graphite substrate.

[0126] The resistivity of the silicon epitaxial layers obtained in Comparative Example 5 were 2.812 Ω·cm, 2.904 Ω·cm, 2.854 Ω·cm, 2.755 Ω·cm, and 2.783 Ω·cm, respectively. Figure 13 As shown, the target resistivity does not meet the requirement of 3~10 Ω·cm, indicating that when the silicon epitaxial layer growth rate is set to 0.5 μm / min, the reaction rate is too fast and the silicon epitaxial layer growth time is too short, resulting in an insufficient proportion of reaction stabilization time, which fails to provide sufficient ramp-up time required for the silicon epitaxial layer to reach the target resistivity.

[0127] The parameter detection results of the silicon epitaxial layer in Examples 1-4 and Comparative Examples 1-5 show that the silicon epitaxial wafers prepared using the preparation technology of Examples 1-4 of the present invention have consistent implementation effects. The thickness and resistivity of the silicon epitaxial layer parameters, as well as the uniformity of their distribution, meet the template requirements. However, Comparative Examples 1-5 cannot fully meet the target requirements in terms of resistivity parameter control of the silicon epitaxial layer.

[0128] However, the present invention is not limited to the specific details of the above embodiments. Within the scope of the technical concept of the present invention, various simple modifications can be made to the technical solution of the present invention, and these simple modifications all fall within the protection scope of the present invention.

Claims

1. A method for fabricating a thin-film high-resistivity silicon epitaxial wafer for a photomultiplier tube device, characterized in that, Includes the following steps: Step 1: The reaction chamber is an atmospheric pressure reaction chamber. The temperature of the reaction chamber is set to 1130~1150℃. Hydrogen chloride gas is introduced to etch the reaction chamber and graphite substrate. The flow rate of hydrogen chloride gas is set to 18~20 L / min, and the etching time is set to 1~2min. Step 2: Cool the reaction chamber to 1110~1130℃, and introduce gaseous trichlorosilane carried by hydrogen as the growth material. The hydrogen flow rate is set to 330~350 L / min, and the flow rate of gaseous trichlorosilane is set to 30~33 L / min. Deposit a polycrystalline silicon coating layer on the graphite substrate in the reaction chamber. The deposition time is set to 60~80 sec. Step 3: Heat the reaction chamber to 1130~1150℃, and introduce hydrogen chloride gas to etch the reaction chamber and graphite substrate. The hydrogen chloride gas flow rate is set to 18~20 L / min, and the etching time is set to 1~2 min. Step 4: Cool the reaction chamber to 1110~1130℃, introduce gaseous trichlorosilane carried by hydrogen as the growth material, set the hydrogen flow rate to 330~350 L / min, set the gaseous trichlorosilane flow rate to 30~33 L / min, deposit a polycrystalline silicon coating layer on the graphite substrate in the reaction chamber, and set the deposition time to 60~80 sec. Step 5: Heat the reaction chamber to 1130~1150℃, and introduce hydrogen chloride gas to etch the reaction chamber and graphite substrate. The hydrogen chloride gas flow rate is set to 18~20 L / min, and the etching time is set to 1~2 min. Step 6: Cool the reaction chamber to 1110~1130℃, introduce gaseous trichlorosilane carried by hydrogen as the growth material, set the hydrogen flow rate to 330~350 L / min, set the gaseous trichlorosilane flow rate to 30~33 L / min, deposit a polycrystalline silicon coating layer on the graphite substrate in the reaction chamber, and set the deposition time to 60~80 sec. Step 7: Cool the reaction chamber to 40~60 ℃, place the silicon substrate in the pit of the graphite base of the reaction chamber, heat the reaction chamber to 1130~1150 ℃, set the hydrogen flow rate to 330~350 L / min, and use hydrogen to bake the polished surface of the silicon substrate at high temperature for 120~180 sec. Step 8: Cool the reaction chamber to 1090~1110℃, introduce gaseous trichlorosilane carried by hydrogen as a growth material, and grow a silicon epitaxial layer on the polished surface of the silicon substrate to form a silicon epitaxial wafer. The hydrogen flow rate is set to 330~350 L / min, the gaseous trichlorosilane flow rate is set to 3~5 L / min, and the silicon epitaxial layer growth rate is set to 0.3~0.4 μm / min. Step 9: Reduce the temperature of the reaction chamber to 40~60℃ and remove the silicon epitaxial wafer from the pit in the graphite substrate.

2. The method for fabricating a thin-film high-resistivity silicon epitaxial wafer for a photomultiplier tube device as described in claim 1, characterized in that: The silicon substrate has a diameter of 150 mm, a resistivity of less than 0.02 Ω·cm, a polished front surface, and a tightly packed silicon dioxide layer on the back side with a thickness of 400~600 nm.

3. The method for fabricating a thin-film high-resistivity silicon epitaxial wafer for a photomultiplier tube device as described in claim 1, characterized in that: The target growth thickness of the silicon epitaxial layer is 1.0~1.4 μm, with an intra-wafer thickness distribution non-uniformity of no more than 2%, and the target resistivity of the silicon epitaxial layer is 3~10 Ω·cm, with an intra-wafer resistivity distribution non-uniformity of no more than 3%.

4. The method for fabricating a thin-film high-resistivity silicon epitaxial wafer for a photomultiplier tube device as described in claim 1, characterized in that: The variation in the radial temperature distribution within the wafer during the growth process of the silicon epitaxial layer is no higher than 5°C.

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