Test method, test device, test system and storage medium for electrical properties

Abstract

The application discloses a kind of electrical performance test method, testing device, testing system and storage medium, wherein, electrical performance test method is used to the combination of heterogeneous class carrier board, including: the PAD point in IC part to be tested is short-circuited to form a network;The electrical performance of the part except the middle point in network in network is tested in section.This electrical performance test method of the application improves the electrical performance test ability of the combination of heterogeneous class carrier board, and can provide new detection ideas for other products.

Description

Technical Field

[0001] This invention relates to the field of circuit board technology, and in particular to a method, apparatus, system and storage medium for testing electrical performance. Background Technology

[0002] Current methods for testing the electrical performance of multi-part-number composite boards typically require cutting the entire board into multiple single-part-number boards, and then sequentially placing these single-part-number boards into a flying probe testing device for testing. With continuous product updates and upgrades, heterogeneous composite substrate-like boards are becoming increasingly diversified, with more and more product structures and processes. These different combination designs present new challenges for inspection and testing. The increasing fineness of circuitry, the complexity of processes such as copper paste sintering and stepped designs, and the diversification of structures such as circular boards and heterogeneous structures, all contribute to the widespread application of substrate-like board types formed by combining these various characteristics.

[0003] In the existing technology, the diversified development of heterogeneous substrate-like boards is constantly increasing the difficulty of inspection and testing. In particular, for industry-specific equipment, the products are subject to comprehensive requirements such as product size, board thickness, PAD size, and pitch, making them undetectable. Conventional inspection solutions often cannot meet the inspection requirements of such products, and special treatment and new inspection solutions need to be designed for such products. Summary of the Invention

[0004] This invention aims to at least solve one of the technical problems existing in the prior art. Therefore, the first objective of this invention is to propose a method for testing electrical performance, improving the testing capability for the electrical performance of heterogeneous substrate-like PCBs, and providing new testing approaches for other products.

[0005] The second objective of this invention is to provide an electrical performance testing device.

[0006] The third objective of this invention is to provide a testing system.

[0007] The fourth objective of this invention is to provide a non-transitory computer-readable storage medium.

[0008] To achieve the above objectives, the electrical performance testing method proposed in the first aspect of the present invention, for heterogeneous substrate-like boards, includes: short-circuiting PAD points in the IC to be tested to form a network; and performing segmented testing on the electrical performance of the portion of the network excluding the midpoint of the network.

[0009] According to the electrical performance testing method proposed in this embodiment of the invention, a network is formed by short-circuiting the PAD points in the IC under test section, thereby modifying the network design of the IC under test section to enable effective testing. By short-circuiting the PAD points in the IC under test section, test points exceeding the testing capabilities of the flying probe tester can become the network's intermediate points. When testing this network, testing of the intermediate points can be avoided, and other parts of the substrate-like board can be tested first to achieve the desired testing effect. The electrical performance testing method of this embodiment of the invention can greatly improve the testing capability for the electrical performance of heterogeneous substrate-like boards, and can also provide new testing approaches for other products.

[0010] In some embodiments of the present invention, the IC under test includes a plurality of test units, each of the test units including at least one PAD point; short-circuiting the PAD points in the IC under test to form a network includes: short-circuiting the PAD points in the plurality of test units to form a test endpoint, wherein the test endpoint is the midpoint of the network.

[0011] In some embodiments of the present invention, the test unit further includes an outer layer line, a blind hole, an inner layer line, and a PTH hole, wherein the PAD point, the outer layer line, the blind hole, the inner layer line, and the PTH hole are connected sequentially.

[0012] In some embodiments of the present invention, the size of the PAD point is 40 μm.

[0013] In some embodiments of the present invention, the electrical performance of the portion of the network excluding the midpoint of the network is tested in segments, including: using a flying probe tester to perform open circuit and short circuit tests on the other segments excluding the midpoint of the network.

[0014] In some embodiments of the present invention, open-circuit and short-circuit tests are performed on segments other than the network midpoint, including: performing open-circuit tests on the lines between the outer layer lines and blind vias; performing open-circuit tests on the lines between the inner layer lines and a portion of the PTH vias; and performing open-circuit tests on the lines between a portion of the PTH vias and another portion of the PTH vias.

[0015] In some embodiments of the present invention, open-circuit and short-circuit tests are performed on segments other than the network midpoint, including: performing short-circuit tests on segments other than the network midpoint.

[0016] To achieve the above objectives, a second aspect of the present invention provides an electrical performance testing device for a heterogeneous substrate-like board, comprising: a shorting module for shorting PAD points in the IC to be tested to form a network; and a testing module for performing segmented testing on the electrical performance of the portion of the network excluding the midpoint of the network.

[0017] According to the electrical performance testing apparatus proposed in this embodiment of the invention, the shorting module forms a network by shorting the PAD points in the IC under test section. Test points exceeding the testing capabilities of the flying probe tester become the network's intermediate points. By modifying the network design of the IC under test section, effective testing of the IC under test can be achieved. When testing this network, the testing module can bypass testing the network's intermediate points and test other parts of the PCB first to achieve the desired testing effect. This significantly improves the testing capability for the electrical performance of heterogeneous PCBs and provides new testing approaches for other products.

[0018] To achieve the above objectives, a third aspect of the present invention also provides a testing system, comprising: the electrical performance testing apparatus of claim 8; a processor; a memory communicatively connected to the processor; the memory storing a computer program executable by the processor, wherein the computer program, when executed by the processor, implements the electrical performance testing method of any one of the above claims.

[0019] According to the test system proposed in the embodiments of the present invention, the electrical performance testing device, when the processor executes the computer program stored in the memory, executes the electrical performance testing method of the above embodiments, which can improve the detection capability of the test system for electrical testing, and can analyze the detection capability of the electrical performance testing device by analyzing the testing principle of the electrical performance testing device, so as to confirm the improvement direction of the entire system and make it more widely applicable to the detection of electrical performance of various types of substrates.

[0020] To achieve the above objectives, a fourth aspect of the present invention also provides a non-transitory computer storage medium having a computer program stored thereon, wherein the computer, when executed by a processor, implements the electrical performance testing method described in any of the preceding claims.

[0021] According to the embodiments of the present invention, a non-temporary computer storage medium stores a computer program that can be executed by a processor. It takes into account the difficulty of testing the electrical performance of heterogeneous substrate-like structures. First, the PAD points in the IC under test are short-circuited to form a network. Then, a flying probe tester is used to perform open-circuit and short-circuit tests on the other parts except the midpoint of the network. This can improve the testing capability of the electrical performance of heterogeneous substrate-like structures.

[0022] Additional aspects and advantages of the invention will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. Attached Figure Description

[0023] The above and / or additional aspects and advantages of the present invention will become apparent and readily understood from the description of the embodiments taken in conjunction with the following drawings, in which:

[0024] Figure 1 This is a front view of a carrier plate according to an embodiment of the present invention;

[0025] Figure 2 A side view of a carrier plate according to an embodiment of the present invention;

[0026] Figure 3 This is a top view of a carrier plate according to an embodiment of the present invention;

[0027] Figure 4 A flowchart of a method for testing electrical performance according to an embodiment of the present invention;

[0028] Figure 5 This is a schematic diagram of the IC under test before shorting according to an embodiment of the present invention;

[0029] Figure 6 This is a schematic diagram of a network after shorting according to another embodiment of the present invention;

[0030] Figure 7 This is a schematic diagram of the network relationships before short-circuiting according to an embodiment of the present invention;

[0031] Figure 8 This is a schematic diagram of the network relationship after shorting according to an embodiment of the present invention;

[0032] Figure 9 A flowchart of a method for testing electrical performance according to another embodiment of the present invention;

[0033] Figure 10 This is a schematic diagram of a test process according to an embodiment of the present invention;

[0034] Figure 11 This is a schematic diagram of a test process according to another embodiment of the present invention;

[0035] Figure 12 A flowchart of a method for testing electrical performance according to yet another embodiment of the present invention;

[0036] Figure 13 The diagram shown is a block diagram of an electrical performance testing apparatus according to an embodiment of the present invention.

[0037] Figure 14This is a block diagram of a test system according to an embodiment of the present invention.

[0038] Figure label:

[0039] Test system 100;

[0040] Electrical performance testing device 10, processor 20, memory 30;

[0041] Short-circuit module 1, test module 2. Detailed Implementation

[0042] The embodiments of the present invention are described in detail below. The embodiments described with reference to the accompanying drawings are exemplary. The embodiments of the present invention are described in detail below.

[0043] The following is for reference. Figures 1-12 A method for testing electrical performance according to an embodiment of the present invention is described.

[0044] In some embodiments of the present invention, the electrical performance testing method is used for heterogeneous substrate-like PCBs. For PCBs, heterogeneous bonding refers to a special structure formed by stacking finished PCBs of different thicknesses and shapes together through a special process such as copper paste sintering. A substrate-like PCB refers to a product structure that incorporates the characteristics of both a PCB and a carrier board, such as large size, high thickness, stepped surfaces, and fine lines. The fine lines have a linewidth and spacing between 25 / 25 and 50 / 50 mm, and the PAD point size is less than 100 μm. Electrical performance testing is performed before product shipment, including open and short circuit tests, to ensure that the product's electrical performance meets customer requirements.

[0045] Specifically, it can be combined with Figure 1-3 Taking the PCB board shown as an example, we can understand the heterogeneous combination carrier board of this invention embodiment. Figure 1 This is a front view of a carrier plate according to an embodiment of the present invention; Figure 2 A side view of a carrier plate according to an embodiment of the present invention; Figure 3 This is a top view of a carrier plate according to an embodiment of the present invention. Figure 1-3 As shown, the PCB is circular, and its heterogeneous structure forms a boss design. The thickness H2 of the lower layer is 8.7mm, and the diameter L of the lower layer is 297mm, so the size of the lower layer is 297*297mm. The height H1 of the boss on the board is 2.47mm. The area of ​​fine circuit design of this type of carrier board is concentrated at the IC position at the top of the component step, which is the IC to be tested part. The network design in other positions is a normal PCB design.

[0046] Based on the above, embodiments of the present invention propose a method for testing the electrical performance of the aforementioned substrate. For example... Figure 4The diagram shows a flowchart of a method for testing electrical performance according to an embodiment of the present invention. The method includes steps S1 and S2, as detailed below.

[0047] S1, short-circuit the PAD points in the IC to be tested to form a network.

[0048] In some embodiments, the IC under test includes a plurality of test units, each test unit including at least one PAD point. Wherein, Figure 1-3 Taking the heterogeneous substrate-like PCB as an example, the network design of this PCB is characterized by the IC to be tested at the top of the component side steps in the fine circuit design. Several PAD points in the test cells are short-circuited to form a test endpoint, which is the network midpoint.

[0049] Specifically, it can be combined with Figure 5 and Figure 6 Understand the case where the PAD points in the IC under test are shorted into a network according to the embodiments of the present invention. Figure 5 This is a schematic diagram of the IC under test before shorting according to an embodiment of the present invention; Figure 6 This is a schematic diagram of a network after shorting according to another embodiment of the present invention. Figure 5 The size of the PAD points in the IC under test section is taken as 40μm. Before shorting, the networks of the IC under test section are independent and form a dense circuit. The pitch of the IC under test section before shorting is 6mil, the PAD points are 2mil, and each PAD point is a network endpoint. For example... Figure 6 As shown, after shorting, the networks are merged into one network, forming a large PAD point, which is the test endpoint. Specifically, the network design of the IC under test can be changed by using an intermediate medium to perform effective testing.

[0050] More specifically, the entire network can be short-circuited by applying conductive adhesive to it. However, if conductive cloth is used for the short-circuiting, there is a risk of adhesive residue. Therefore, the evaluation material must meet the quality requirement of not leaving adhesive residue. Thus, by applying conductive adhesive, the overall state of the network can be changed to meet the testing requirements of this embodiment of the invention.

[0051] S2 performs segmented testing on the electrical performance of the portion of the network excluding the midpoint.

[0052] Among them, the application of heterogeneous substrate-like board electrical performance testing is a new product development project, a first in the industry, with no such technology available from competitors or even the entire industry. This type of product represents a future development trend, with a large potential market order volume. There are various testing methods for electrical performance testing, such as general testing and flying probe testing. When using general testing methods to perform electrical performance testing on a multi-point board, the resistance method is typically used, which has high testing efficiency but requires fixtures and has high testing costs. When using the flying probe testing method to perform electrical performance testing on substrate-like boards, single-point testing can be achieved. It uses the resistance method or electric field method, which has lower testing efficiency but requires no fixtures and has advantages such as flexible film replacement and low testing costs. For the technical requirements brought about by the characteristics of common PCB products, the individual indicators of flying probe testers in the industry can meet them. However, due to the limitations of different models, they have specific application scenarios. For example, flying probe testers can be used to test PCBs or carrier boards. However, for heterogeneous carrier boards, which combine all the characteristics of PCBs and carrier boards, there is currently no flying probe tester model in the industry that can meet all the above characteristic requirements. Therefore, there is no processing capability for this type of product in the industry.

[0053] In some embodiments of the present invention, such as Figure 5 The carrier board shown is analyzed based on its structural characteristics. No single device can meet all the product testing requirements after considering all its characteristics. Through analysis of the testing capabilities of different types of equipment in the industry, flying probes meet the highest proportion of requirements. The limitation on our company's flying probe testing and processing capabilities is the size of the PAD. If the influence of the PAD size can be effectively resolved, we will have the capability to process and test it.

[0054] Specifically, such as Figure 5 As shown, in this embodiment, the 40μm test PAD point of the IC under test exceeds the capabilities of flying probe testing. Figure 6 As shown, after short-circuiting the PAD points in the IC under test to form a network, the networks are merged into one network, forming a large PAD point, which is the test endpoint. At this point, the super-powerful test point becomes the network midpoint. In some embodiments, flying probe testing can be used to perform open-circuit and short-circuit tests on segments other than the network midpoint.

[0055] More specifically, based on TRIZ's 24th inventive principle, "using an intermediary," and according to the testing mechanism and rules, network midpoints do not need to be tested. Therefore, super-capable test points can be avoided during testing. Furthermore, since all networks are shorted together, short circuits cannot be detected. Therefore, segmented testing is required for open-circuit and short-circuit tests. For example, in the first test of this type of carrier board, the continuity of all shorted networks can be tested first. And in the second test of this type of carrier board, the area already tested in the first step can be avoided, and normal open-short circuit tests can be performed.

[0056] Furthermore, the short-circuit solution will not introduce the risk of missing defects during the first continuity test. If the contact is poor, it will appear as a false point in the continuity test. Therefore, the short-circuit continuity test should be placed in the first test and should not be interchanged with the second test. In this way, if a short circuit risk occurs during the first test, the second test can effectively intercept it.

[0057] According to the electrical performance testing method proposed in this embodiment of the invention, a network is formed by short-circuiting the PAD points in the IC under test section, thereby modifying the network design of the IC under test section to enable effective testing. By short-circuiting the PAD points in the IC under test section, test points exceeding the testing capabilities of the flying probe tester can become the network's intermediate points. When testing this network, testing of the intermediate points can be avoided, and other parts of the substrate-like board can be tested first to achieve the desired testing effect. The electrical performance testing method of this embodiment of the invention can greatly improve the testing capability for the electrical performance of heterogeneous substrate-like boards, and can also provide new testing approaches for other products.

[0058] In some embodiments of the present invention, the network relationship of the fine circuit is consistent. The network relationship in the test unit consists of outer layer lines, blind vias, inner layer lines, and PTH (Plating Through Hole) holes, with PAD points, outer line lines, blind vias, inner line lines, and PTH holes connected sequentially. Figure 7 The diagram shown is a schematic representation of the network relationship before short-circuiting according to an embodiment of the present invention. Seed pin 1 represents the IC portion of a fine-line circuit. For example, the size of the PAD point in the IC portion can be designed to be 40μm. However, due to the excessive size of the PAD point 1, it cannot be tested, resulting in a detection blind zone for the entire network conductivity. Figure 7 The shaded areas shown, as well as the outer lines, that is, a portion of the outer lines and blind holes, will not be able to detect their conductivity or open circuits.

[0059] like Figure 8 The diagram illustrates the network relationship after shorting according to an embodiment of the present invention. Taking two test units as an example, after shorting the PAD points in the IC to be tested to form a network, the networks are merged into one network. The PAD points of the two test units at the shorting position form a large PAD point. This PAD point may exceed the testing capability of the flying probe tester and become the network midpoint. When performing the first test on this network, the test on this PAD point can be avoided, and the part between the seed needle point 2 and the seed needle point 3 can be tested directly. When performing the second test on the network, the parts on both sides of the seed needle point 2 are tested in segments to achieve the test effect.

[0060] In some embodiments of the present invention Figure 9 The flowchart is a method for testing electrical performance according to another embodiment of the present invention, wherein open-circuit and short-circuit tests are performed on segments other than the midpoint of the network, specifically including steps S21-S23.

[0061] S21, perform an open-circuit test on the wiring between the outer layer lines and the blind vias.

[0062] like Figure 10 The diagram illustrates a test procedure according to an embodiment of the present invention. The open-circuit test in this step is the first test described above, primarily used to test network connectivity. The test points in this step are seed pin 2 and seed pin 2. Specifically, the portion between seed pin 2 and seed pin 2 can be tested directly, avoiding the testing of PAD points. In other words, the outer layers and blind vias of the network are tested, while the inner layers and PTH are not tested at this stage.

[0063] S22, performs an open-circuit test on the wiring between the inner layer lines and a portion of the PTH via.

[0064] like Figure 11 The diagram shown is a schematic of a test procedure according to another embodiment of the present invention. The open-circuit test data in this step is the second test mentioned above, and the test points in this step are seed pin point 2 and seed pin point 3. Specifically, the portion between seed pin point 2 and seed pin point 3 can be tested directly. This step tests a portion of the inner layer lines and a portion of the PTH holes in the network, where the other portion of the PTH holes, i.e., the shaded area, is not tested in this step.

[0065] S23, perform an open-circuit test on the wiring between one part of the PTH hole and another part of the PTH hole.

[0066] The open-circuit test in this step is also part of the second test mentioned above, and the test points for this step are seeding point 3 and seeding point 4. Specifically, it can be directly performed on... Figure 11 The portion between seed pin points 3 and 4 in the network is tested. This step involves testing another part of the PTH holes in the network. Figure 11 The shaded area shown in the figure represents the open-circuit test of the entire network using the segmented testing method described above.

[0067] In other embodiments of the present invention Figure 12 The flowchart of a method for testing electrical performance according to another embodiment of the present invention includes a step S24, wherein open-circuit and short-circuit tests are performed on segments other than the network midpoint.

[0068] S24, perform short-circuit tests on all parts of the network except for the intermediate points.

[0069] When performing short-circuit testing on the network, it is not necessary to apply conductive adhesive. The test points in this step are any test point on the network and other test points on the network. The monitoring point is the insulation of the entire network. In this step, the entire network can be directly short-circuited tested.

[0070] Furthermore, the short-circuit continuity test must be performed as the first test and cannot be interchanged with the second test. The short-circuit solution will not introduce the risk of missing defects in the first continuity test. If the contact is not good, it will appear as a false point in the continuity test. Moreover, if a short circuit risk is generated, it can be effectively intercepted in the second test.

[0071] Based on the above, the electrical performance testing method of this invention has fully analyzed the structure and network design of the product, grasped its regularity, and changed the network design of the IC to be tested by using an intermediate medium. When testing the network, the testing of the network midpoint can be avoided, and the testing of other parts of the substrate can be performed first. This can greatly improve the testing capability of the electrical performance of heterogeneous substrates and provide new testing ideas for other products.

[0072] In some embodiments of the present invention, an electrical performance testing apparatus is also provided, wherein the electrical performance testing apparatus 10 is used for heterogeneous composite substrates, wherein the composite substrates are capable of being combined with... Figure 1-3 The heterogeneous combination of the carrier board in the embodiments of the present invention is understood in conjunction with the above content, and will not be repeated here.

[0073] like Figure 13 The diagram shown is a block diagram of an electrical performance testing apparatus according to an embodiment of the present invention. The electrical performance testing apparatus 10 includes a shorting module 1 and a testing module 2.

[0074] The shorting module 1 is used to short-circuit the PAD points in the IC under test to form a network. More specifically, conductive adhesive can be applied to the network to short-circuit the entire network. After short-circuiting, the individual networks are merged into one network, forming a large PAD point, which is the test endpoint.

[0075] Test module 2 is used to perform segmented testing of the electrical performance of the network, excluding the network midpoint. Test module 2 can be a flying probe tester, which can perform testing based on the TRIZ innovative method. The flying probe tester performs open-circuit and short-circuit tests on the segments other than the network midpoint. Furthermore, during segmented testing, the test can be divided into a first test and a second test. The first test can check the continuity of all short-circuited network segments. The second test can bypass the area checked in the first test and perform normal open-short-circuit tests.

[0076] According to the electrical performance testing apparatus 10 proposed in this embodiment of the invention, the shorting module 1 forms a network by shorting the PAD points in the IC under test section. Test points exceeding the testing capabilities of the flying probe tester become the network's intermediate points. By modifying the network design of the IC under test section, effective testing of the IC under test can be achieved. When testing this network, the testing module 2 can bypass testing the network's intermediate points and test other parts of the substrate-like board first to achieve the desired testing effect. This greatly improves the testing capability for the electrical performance of heterogeneous substrate-like boards and provides new testing approaches for other products.

[0077] In some embodiments of the present invention, a testing system is also proposed, such as Figure 14 The diagram shown is a block diagram of a test system according to an embodiment of the present invention. The test system 100 includes an electrical performance test device 10, a processor 20, and a memory 30 as described in the embodiment above.

[0078] The electrical performance testing apparatus 10 can be used to short-circuit the PAD points in the IC under test to form a network, and to perform segmented testing of the electrical performance of the portion of the network excluding the midpoint. Specifically, the electrical performance testing apparatus 10 of this embodiment can be combined with... Figure 12 The above content is for reference only and will not be elaborated upon here.

[0079] The memory 30 is communicatively connected to the processor 20. The memory 30 stores a computer program that can be executed by the processor 20. When the computer program is executed by the processor 20, it implements the test method for the electrical performance of any of the above items.

[0080] According to the embodiments of the present invention, the test system 100 employs an electrical performance test device 10. When the processor 20 executes the computer program stored in the memory 30, it executes the electrical performance test method of the above embodiment, thereby improving the detection capability of the test system 100 in electrical testing. Furthermore, by analyzing the test principle of the electrical performance test device 10, its detection capability can be analyzed, making it easier to identify the direction of improvement for the entire system and enabling it to be more widely applied to the detection of electrical performance of various types of substrates.

[0081] In some embodiments of the present invention, a non-transitory computer storage medium is also proposed, on which a computer program is stored, and when the computer is executed by a processor, a method for testing the electrical performance of any of the above-mentioned items is implemented.

[0082] According to the embodiments of the present invention, a non-temporary computer storage medium stores a computer program that can be executed by a processor. It takes into account the difficulty of testing the electrical performance of heterogeneous substrate-like structures. First, the PAD points in the IC under test are short-circuited to form a network. Then, a flying probe tester is used to perform open-circuit and short-circuit tests on the other parts except the midpoint of the network. This can improve the testing capability of the electrical performance of heterogeneous substrate-like structures.

[0083] Other configurations and operations of the test system 100 and the electrical performance test apparatus 10 according to embodiments of the present invention are known to those skilled in the art and will not be described in detail here.

[0084] The terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this application, unless otherwise stated, "a plurality of" means two or more.

[0085] In the description of this specification, references to terms such as "one embodiment," "some embodiments," "illustrative embodiment," "example," "specific example," or "some examples," etc., refer to specific features, structures, materials, or characteristics described in connection with that embodiment or example, which are included in at least one embodiment or example of the present invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example.

[0086] Although embodiments of the invention have been shown and described, those skilled in the art will understand that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of the invention, the scope of which is defined by the claims and their equivalents.

Claims

1. A method for testing electrical performance, characterized in that, For heterogeneous bonding, the IC under test includes several test units, each test unit including at least one PAD point, and the test method includes: The PAD points in several test units are short-circuited to form a test endpoint, so that the test units form a network, and the test endpoint is the network midpoint; The electrical performance of the portion of the network excluding the midpoint of the network is tested in segments using the flying probe test method. The segmented test includes a first test and a second test performed sequentially. The first test includes a continuity test of the network, and the second test includes an open-short circuit test that avoids the area tested in the first test.

2. The method for testing electrical performance according to claim 1, characterized in that, The test unit also includes an outer layer line, a blind hole, an inner layer line, and a PTH hole, with the PAD point, the outer layer line, the blind hole, the inner layer line, and the PTH hole connected sequentially.

3. The method for testing electrical performance according to claim 2, characterized in that, The size of the PAD point is 40 μm.

4. The method for testing electrical performance according to claim 2, characterized in that, The electrical performance of the portion of the network excluding the midpoints is tested in segments, including: A flying probe tester was used to perform open-circuit and short-circuit tests on segments of the network, excluding the midpoints.

5. The method for testing electrical performance according to claim 4, characterized in that, Open-circuit and short-circuit tests are performed on segments other than the network midpoints, including: An open-circuit test was performed on the circuit between the outer layer lines and the blind vias; An open-circuit test was performed on the circuit between the inner layer lines and a portion of the PTH holes; An open-circuit test is performed on the circuit between one part of the PTH hole and another part of the PTH hole.

6. The method for testing electrical performance according to claim 4, characterized in that, Open-circuit and short-circuit tests are performed on segments other than the network midpoints, including: Short-circuit tests are performed on all parts of the network except for the intermediate points.

7. An electrical performance testing device, characterized in that, A substrate-like PCB for heterogeneous bonding, wherein the IC under test includes several test units, each test unit including at least one PAD point, and the test apparatus includes: A shorting module is used to short-circuit the PAD points of several test units in the IC under test into a test endpoint, so that the test units form a network, and the test endpoint is the network midpoint of the network. The testing module is used to perform segmented testing of the electrical performance of the portion of the network excluding the midpoint of the network using the flying probe testing method. The segmented testing includes a first test and a second test performed sequentially. The first test includes a continuity test of the network, and the second test includes an open-short circuit test that avoids the area detected in the first test.

8. A testing system, characterized in that, include: The electrical performance testing apparatus as described in claim 7; processor; The memory is communicatively connected to the processor; The memory stores a computer program that can be executed by the processor, and when the computer program is executed by the processor, it implements the electrical performance testing method according to any one of claims 1-6.

9. A non-transitory computer storage medium having a computer program stored thereon, characterized in that, When the computer is executed by the processor, it implements the electrical performance testing method according to any one of claims 1-6.

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