A method for extracting lithography test patterns from a full chip layout

Abstract

The application provides a method for extracting a lithography test pattern from a full-chip layout, comprising the following steps: step S1: finding all CD mutation points possibly existing in a non-corner in the full-chip layout; step S2: calculating a direction with the maximum local layout weighted density of light intensity affecting all the CD mutation points, a relative value of the weighted density of the direction, and a dispersion index value representing a local layout around the CD mutation point; and step S3: selecting a lithography test pattern according to the CD of the pattern layout at the position of the CD mutation point, the direction with the maximum local layout weighted density, the relative value of the weighted density, and the dispersion index value, so that the extracted lithography test pattern is very suitable for verifying the accuracy of an OPC model and the effectiveness of an OPC recipe, and can also clear a part of obstacles for improving the yield of a chip in a later stage.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of semiconductor technology, in particular to a method for extracting lithography test patterns from a full chip layout. BACKGROUND

[0002] Test patterns are widely used in various stages of semiconductor manufacturing. For the lithography stage, test patterns appear in process development, mask lithography verification, OPC (Optical Proximity Correction) development and verification, etc. For example, in lithography process development, the first thing to be confirmed is whether the process window of the critical dimension and the process weak pattern meets the requirements, which needs to be verified by the lithography results of the corresponding test patterns. For another example, the comparison of manufacturing capabilities between different mask factories is most intuitive in the comparison of lithography results of the same set of test patterns. For another example, in OPC development, a large number of test patterns are needed to train and debug the model, and after the model and OPC recipe are developed, the accuracy of the model and the effectiveness of the OPC recipe are verified by comparing the simulation results with the lithography results of the test patterns. In other words, the more the test patterns can reflect the various situations of the actual chip layout, the more comprehensive the development of the lithography process, the more perfect the development and verification of the OPC, and the more simple and smooth the application and expansion of the subsequent lithography process.

[0003] Generally, the existing lithography test patterns are divided into three types: 1. simple regular symmetrical arrangement patterns composed of bars and squares; 2. layout of some very small memory cells; 3. logic circuit layout selected by lithography engineers based on experience. For memory chip circuits with relatively simple and repetitive layout patterns, the above three types of test patterns are sufficient for the requirements of the lithography process, but for a new chip with a large proportion of logic circuit area, the complexity of the pattern distribution may be far beyond the above three types. If the lithography test patterns only use the above three types, it may cause hidden dangers for the yield improvement of the chip in the later stage. SUMMARY

[0004] The purpose of the present application is to provide a method for extracting lithography test patterns from a full chip layout, which can extract lithography test patterns that are very suitable for verifying the accuracy of the OPC model and the effectiveness of the OPC recipe, and can also clear some obstacles for improving the yield of the chip in the later stage.

[0005] In order to solve the above problems, the present application provides a method for extracting lithography test patterns from a full chip layout, comprising the following steps:

[0006] Step S1: find all CD mutation points that may exist in the full chip layout except the corners;

[0007] Step S2: calculating the direction of the maximum local layout weighted density affecting the light intensity of all the CD mutation points and the relative value of the weighted density of the direction, and calculating the dispersion index value of the local layout around the CD mutation point;

[0008] Step S3: selecting a lithography test pattern according to the CD of the graphic layout at the position of the CD mutation point, the direction of the maximum local layout weighted density, the relative value of the weighted density and the dispersion index value.

[0009] Optionally, step S1 comprises:

[0010] providing a full-chip layout;

[0011] creating an OPC optical model and simulating the full-chip layout by using the OPC optical model to obtain a full-chip profile;

[0012] setting the size of an angle edge radius, taking the top corner of each graphic layout as the center, excluding the graphic profile part within the radius range with the angle edge radius as the radius, and calculating the slope distribution of the remaining graphic profile relative to the respective edge.

[0013] Further, the method for obtaining the full-chip profile specifically comprises:

[0014] creating an OPC optical model according to the lithography parameters of a lithography process and optical principles, and simulating the full-chip layout by using the OPC optical model to obtain a full-chip profile.

[0015] Further, the method for calculating the slope distribution of the remaining graphic profile relative to the respective edge specifically comprises:

[0016] taking the angle edge radius as the radius, excluding the corner part of the edge of the graphic layout and the part of the graphic profile corresponding to the edge, and calculating the slope of the remaining part of the graphic profile relative to the remaining part of the corresponding edge.

[0017] Further, the method for calculating the direction of the maximum local layout weighted density affecting the light intensity of all the CD mutation points and the relative value of the weighted density of the direction comprises:

[0018] taking each non-corner CD mutation point as the center to intercept a local layout of a square area around the CD mutation point;

[0019] taking each non-corner CD mutation point as the origin to sample the local layout to obtain a sampling point;

[0020] A contribution component value of the light intensity at the origin of a sampling point on the pattern layout is calculated as a modulus of a vector by using the OPC optical model, so as to obtain a vector corresponding to the sampling point.

[0021] All the vectors in the local layout are added to obtain a vector sum, wherein a direction of the vector sum is a direction pointing to a maximum weighted density of the local layout, and a size of the vector sum represents a degree that the direction has a higher weighted density than other directions in the local layout.

[0022] Further, the vector r i satisfies the following formula:

[0023] r i = f model (M i )

[0024] wherein M i is an equivalent mask of only the sampling point i with the same area as the local layout.

[0025] Further, the vector sum (θ, r) satisfies the following formula:

[0026] (θ,r)=∑(θ i ,r i )

[0027] wherein θ i is a direction of the sampling point i relative to the center point in the local layout; and r i is a vector size corresponding to the sampling point i.

[0028] Further, the method for calculating the dispersion index value of the local layout around the CD mutation point comprises:

[0029] A modulus of the vector sum is obtained according to the vector sum, and a degree that a direction with a maximum weighted density of the local layout has a higher weighted density than other directions in the local layout is calculated.

[0030] Further, the dispersion index value J satisfies the following formula:

[0031]

[0032] wherein r i is a vector size corresponding to the sampling point i; and r is a modulus of a sum of vectors corresponding to all the sampling points in the local layout.

[0033] Further, the step S3 comprises:

[0034] According to the CD of the graphic layout where the CD mutation point is located, the direction of the maximum local layout weighted density, the relative value of the weighted density, the dispersion index value and the slope of the graphic profile on the non-corner side where the CD mutation point is located, the above parameters are classified and counted, and the corresponding graphic layout is selected as a test graphic according to the classification and counting results.

[0035] Compared with the prior art, the present application has the following beneficial effects:

[0036] The present application provides a method for extracting a lithography test graphic from a full-chip layout, comprising the following steps: step S1: finding all CD mutation points of non-corners possibly existing in the full-chip layout; step S2: calculating the direction of the maximum local layout weighted density and the relative value of the weighted density of the direction affecting the light intensity of all the CD mutation points, and calculating a dispersion index value of the local layout around the CD mutation point; and step S3: selecting a lithography test graphic according to the CD of the graphic layout where the CD mutation point is located, the direction of the maximum local layout weighted density, the relative value of the weighted density and the dispersion index value, so that the extracted lithography test graphic is very suitable for verifying the accuracy of an OPC model and verifying the effectiveness of an OPC recipe, and can also clear a part of obstacles for improving the yield of a chip in the later stage. BRIEF DESCRIPTION OF DRAWINGS

[0037] Figure 1 A flowchart of a method for extracting a lithography test graphic from a full-chip layout according to an embodiment of the present application is provided;

[0038] Figure 2 A structural schematic diagram of a full-chip layout according to an embodiment of the present application is provided;

[0039] Figure 3 A structural schematic diagram of a full-chip profile according to an embodiment of the present application is provided;

[0040] Figure 4 A structural schematic diagram of a CD mutation point of non-corners according to an embodiment of the present application is provided;

[0041] Figure 5 A schematic diagram of the slope of a CD mutation point of non-corners relative to a non-corner side according to an embodiment of the present application is provided;

[0042] Figure 6 A structural schematic diagram of a local layout according to an embodiment of the present application is provided;

[0043] Figure 7 A structural schematic diagram of a local layout during sampling according to an embodiment of the present application is provided;

[0044] Figure 8A structure diagram for obtaining a vector in a local layout according to an embodiment of the present application;

[0045] Figure 9 A diagram for classifying a direction with the maximum weighted density of a local layout of a pattern layout according to an embodiment of the present application.

[0046] Legend of reference signs:

[0047] 100 - pattern layout; 110 - first pattern layout; 120 - second pattern layout; 130 - third pattern layout; 140 - fourth pattern layout; 200 - pattern contour; 210 - first pattern contour; 220 - second pattern contour; 230 - third pattern contour; 240 - fourth pattern contour. DETAILED DESCRIPTION

[0048] A method for extracting a lithography test pattern from a full chip layout according to the present application will be described in further detail below. The present application will be described in further detail below with reference to the accompanying drawings, in which the preferred embodiments of the present application are shown. It should be understood that those skilled in the art can modify the present application described herein while still implementing the advantageous effects of the present application. Accordingly, the following description should be understood as a broad teaching to those skilled in the art and not as a limitation on the present application.

[0049] For clarity, not all of the features of an actual implementation are described in this document. In the following description, numerous specific details are set forth to provide a thorough understanding of the present application. However, it will be apparent to those skilled in the art that the present application can be practiced without such specific details. In other instances, well-known structures and functions have not been described in detail in order to avoid obscuring the present application. It should be understood that the detailed description and specific examples, while indicating preferred embodiments of the present application, are intended for purposes of illustration only and are not intended to limit the scope of the present application.

[0050] In order to make the objectives, features and advantages of the present application more obvious and easy to understand, the specific embodiments of the present application will be further described below with reference to the accompanying drawings. It should be noted that the drawings are all in a very simplified form and all use non-precise ratios, only to facilitate, clearly assist in the purpose of illustrating the embodiments of the present application.

[0051] Figure 1 A flow diagram of a method for extracting a lithography test pattern from a full chip layout according to the present embodiment. As shown in FIG. 1, the method for extracting a lithography test pattern from a full chip layout according to the present embodiment is for a line layer (as distinguished from a hole layer, and the line layer is, for example, an AA region, poly, Metal, etc.). The method for extracting a lithography test pattern from a full chip layout includes the following steps: Figure 1 As shown in FIG. 1, the method for extracting a lithography test pattern from a full chip layout according to the present embodiment is for a line layer (as distinguished from a hole layer, and the line layer is, for example, an AA region, poly, Metal, etc.). The method for extracting a lithography test pattern from a full chip layout includes the following steps:

[0052] Step S1: finding out all CD (critical dimension) mutation points possibly existing in the non-corner of the full-chip layout;

[0053] Step S2: calculating the direction θ of the maximum local layout weighted density of the light intensity affecting all the CD mutation points, the relative value r of the weighted density of the direction θ, and the dispersion index value J representing the local layout dispersion around the CD mutation points;

[0054] Step S3: selecting the lithography test pattern according to the CD, the direction θ of the maximum local layout weighted density, the relative value r of the weighted density, and the dispersion index value J of the pattern layout at the position of the CD mutation point.

[0055] The following will be described in detail Figures 2-9 A method for extracting a lithography test pattern from a full-chip layout provided by the embodiment will be described in detail.

[0056] Firstly, step S1 is performed to find out all CD (critical dimension) mutation points possibly existing in the non-corner of the full-chip layout, so as to find out the layout positions possibly existing in the OPC optical model prediction error.

[0057] This step specifically includes:

[0058] As shown in Figure 2 , firstly, a full-chip layout is provided, which is a layout conforming to the basic critical dimension design specification and having a real circuit function.

[0059] As shown in Figure 3 , then, an OPC optical model is created, and the full-chip layout is simulated by using the OPC optical model to obtain a full-chip contour. In detail, an OPC optical model is created according to the lithography parameters of the lithography process and the optical principle, and the full-chip layout is simulated by using the OPC optical model to obtain a full-chip contour. The full-chip contour includes a plurality of pattern contours 200, each of which is arranged in a pattern layout 100. The pattern contour 200 includes two oppositely arranged non-corner sides and a connecting side connecting the two ends of the two non-corner sides. The non-corner side can be a straight line or a broken line, and the connecting side is an arc.

[0060] In this embodiment, there are four graphic layouts and four graphic outlines. The four graphic layouts are a first graphic layout 110, a second graphic layout 120, a third graphic layout 130, and a fourth graphic layout 140. The four graphic outlines are a first graphic outline 210, a second graphic outline 220, a third graphic outline 230, and a fourth graphic outline 240.

[0061] like Figure 4 As shown, next, the size of the corner_side (m) is set, and with the vertex corner of each graphic layout as the center and the corner_side (m) as the radius, the corner portions of the edges of the graphic layout and the corner portions of the graphic contours corresponding to the edges within this radius are excluded (i.e., the two connecting edges of the graphic contours and the portions of each non-corner edge are excluded). The slope of the remaining portion of the graphic contour relative to the remaining portion of its corresponding edge (i.e., the remaining portions of the two non-corner edges) is calculated, and the extreme point of the slope on each graphic contour is defined as the CD abrupt change point of the non-corner. This step only calculates the extreme point of the slope of each graphic contour at the non-corner edge, where the slope is the slope of the contour line calculated with the edge of the graphic layout corresponding to the contour as the horizontal reference. The size of the corner_side (m) can be adjusted as needed.

[0062] Please continue reading. Figure 3 and Figure 4 In this embodiment, in each graphic layout, with each vertex as the center, the corner portions of the edges of graphic layouts 210, 220, 230, and 240 and portions of the graphic contours 110, 120, 130, and 140 corresponding to the edges are arranged, resulting in the remaining portions of edges 111 and 112 of graphic contour 110, the remaining portions of edges 121 and 122 of graphic contour 120, and the remaining portions of edges 131 and 132 of graphic contour 130. The lower part, the remaining part of edge 141 of the graphic outline 140, the remaining part of edge 142, the remaining edge of non-corner edge 211 of graphic layout 210, the remaining edge of non-corner edge 212 of graphic layout 210, the remaining edge of non-corner edge 222 of graphic layout 220, the remaining edge of non-corner edge 231 of graphic layout 230, the remaining edge of non-corner edge 232 of graphic layout 230, the remaining edge of non-corner edge 241 of graphic layout 240, and the remaining edge of non-corner edge 242 of graphic layout 240;

[0063] and the rest of the edge 112 corresponding to the rest of the non-corner edge 212 has no slope extreme point; the rest of the edge 122 corresponding to the rest of the non-corner edge 222 has no slope extreme point; the rest of the edge 131 of the graphic contour 130 corresponding to the rest of the non-corner edge 231 has no slope extreme point; the rest of the edge 132 corresponding to the rest of the non-corner edge 232 has no slope extreme point; the rest of the edge 141 of the graphic contour 140 corresponding to the rest of the non-corner edge 241 has no slope extreme point; the rest of the edge 142 corresponding to the rest of the non-corner edge 242 has no slope extreme point. Only the rest of the edge 121 of the graphic contour 120 corresponding to the rest of the non-corner edge 212 has a slope extreme point at point A, i.e. a non-corner CD mutation point, i.e. a slope k (as shown in Figure 5

[0064] Then, step S2 is performed to calculate the direction θ of the maximum local layout weighted density of the light intensity affecting all the CD mutation points and the relative value r of the weighted density of the direction θ, and to calculate an index value J representing the local layout dispersion degree around the CD mutation point.

[0065] This step specifically includes:

[0066] Step S21 is performed to calculate the direction θ of the maximum local layout weighted density of the light intensity affecting all the CD mutation points and the relative value r of the weighted density of the direction θ, so as to quantify the influence of the graphic distribution on the light intensity of a certain point of the layout.

[0067] In detail, as shown in Figure 6 , first, the local layout of a square region of 2R*2R centered on the CD mutation point (i.e. the slope extreme point) of each non-corner is intercepted and taken as the layout corresponding to each CD mutation point of the non-corner (i.e. the first layout), wherein R=OD (optical distance).

[0068] As shown in Figure 7 , then, the intercepted local layout (i.e. the first layout) is sampled with the CD mutation point (i.e. the slope extreme point) of each non-corner as the origin to obtain a sampling point i; and the contribution component value of the sampling point i to the light intensity at the origin is calculated by using the OPC optical model to obtain a vector r i , so that the vector r i corresponding to the sampling point i is obtained. The direction of the vector is from the origin A to the sampling point i.

[0069] Please continue to refer to Figure 6 and Figure 7In the embodiment, the local layout where the slope extremum point A is located includes the first graphic layout 110, the second graphic layout 120 and the third graphic layout 130. The sampling point i representing a mask pixel is obtained by sampling the intercepted local layout. Then, the vector corresponding to the sampling point i is calculated. It is assumed that there is a mask M Figure 1 i with the same area as the first layout and only the graphic (i.e. the sampling point i) on the mask M i The light intensity at the point A is the size of the vector corresponding to the sampling point i, and the direction from the point A to the sampling point i is the direction of the vector corresponding to the sampling point i.

[0070] Therefore, taking the sampling point i as an example, the size of the vector corresponding to all the sampling points i coinciding with the graphic layout on the local layout is calculated. i The vector r i satisfies the following formula:

[0071] r model = f i (M i )

[0072] where M i is an equivalent mask with the same area as the local layout and only the sampling point i.

[0073] As shown in the formula, then, all the vectors in the local layout are added to obtain the vector sum (θ, r), where the direction θ of the vector sum (θ, r) is the direction pointing to the maximum weighted density of the local layout, and the size r of the vector sum (θ, r) represents the degree to which the direction θ has a higher weighted density than other directions in the local layout. Figure 8 The vector sum (θ, r) satisfies the following formula:

[0074] (θ, r) = ∑ (θ i , r i )

[0075] where θ i is the direction of the sampling point i relative to the center point in the local layout, and r i is the size of the vector corresponding to the sampling point i.

[0076] Step S22: Calculate the local layout dispersion index value J representing the dispersion degree of the local layout around the CD mutation point to quantify the dispersion degree of the local layout around the CD mutation point in the graphic layout.

[0077] This step specifically includes:

[0078] ​The magnitude of the vector sum (θ, r) is obtained from the vector sum, and the degree to which the weighted density of the direction with the largest weighted density in the local map is higher than that of other directions in the local map is calculated. The magnitude of the vector sum is used as the dispersion index J to measure the distribution characteristics of the local map around the CD mutation point. The larger the dispersion index J is, the looser the local map distribution around the CD mutation point is, and vice versa.

[0080] The dispersion index value J satisfies the following formula:

[0081]

[0082] Where, r i Let be the size of the vector corresponding to sampling point i; and r be the magnitude of the sum of the vectors corresponding to each sampling point in the local layout.

[0083] Next, in step S3, a photolithographic test pattern is selected based on the CD of the graphic layout at the location of the CD mutation point, the direction θ with the largest local layout weighted density, the relative value of the weighted density r, and the dispersion index value J.

[0084] In detail, based on the CD of the graphic layout at the location of the CD mutation point, the direction θ with the maximum weighted density of the local layout, the relative value of the weighted density r, the dispersion index value J, and the slope k of the graphic contour at the CD mutation point with respect to the non-corner edge, the above parameters are classified and statistically analyzed, and the corresponding graphic layout is selected as the test graphic based on the classification and statistical results.

[0085] like Figure 9 As shown, in this embodiment, the graphic layout is first classified according to CD, and the top 10% of the slope k values ​​are retained. Under each CD classification of the graphic layout, it is further classified according to the range of the direction θ with the highest local layout weight density, for example, into 8 categories (i.e., 0~15°, 16°~45°, 46°~75°, 76°~105°, 106°~135°, 136°~165°, 167°~195°, 196°~225°, 226°~255°, 256°~285°, 286°~315°, 316°~345°, 346°~360°).

[0086] After classification, the distribution of the weighted relative density value r and dispersion index value J for each category is analyzed. The local plots (i.e., the first plots) corresponding to the maximum and minimum values ​​of the weighted relative density value r and dispersion index value J are selected, as well as the local plots of the top ten weighted relative density value r and dispersion index value J with the highest proportion of distributions to the total number, and these are used as the selected test patterns.

[0087] In summary, the present application provides a method for extracting lithography test patterns from full-chip layout for line layers (as distinguished from hole layers), to extract from full-chip layout of line layers (such as AA, POLY, Metal, etc.) a symmetrically arranged pattern with a pattern distribution complexity greater than the simple regularity of current bar and square composition, which can represent the characteristics of actual chip layout and is not dependent on experience-based lithography test patterns. Based on these characteristics, the layout patterns extracted by the method of the present application are very suitable for verification of OPC model accuracy and effectiveness of OPC recipe, and can clear a part of obstacles for later chip yield improvement.

[0088] In addition, it should be noted that, unless specifically described or indicated, the terms "first", "second" in the specification are merely used to distinguish the components, elements, steps, etc. in the specification, and are not used to represent the logical relationship or sequence relationship between the components, elements, steps, etc.

[0089] It can be understood that, although the present application has been disclosed as above with preferred embodiments, the above embodiments are not intended to limit the present application. For any person skilled in the art, many possible variations and modifications, or equivalent embodiments of the above disclosed technical content can be made to the technical solution of the present application without departing from the scope of the technical solution of the present application. Therefore, any simple modification, equivalent change and modification of the above embodiments made according to the technical essence of the present application, without departing from the content of the technical solution of the present application, shall still fall within the scope of protection of the technical solution of the present application.

Claims

1. A method of extracting lithography test patterns from a full chip layout, characterized by, The method comprises the following steps: Step S1: finding all CD mutation points of non-corner in the full-chip layout, wherein the method for finding the CD mutation points of non-corner comprises the following steps: providing the full-chip layout; creating an OPC optical model and simulating the full-chip layout by using the OPC optical model to obtain a full-chip profile; setting the size of an angle side radius, taking the top corner of each pattern layout as the center, excluding the pattern layout edge and the pattern profile within the radius range with the angle side radius as the radius, and calculating the slope distribution of the remaining pattern profile relative to the non-corner side to find the slope extreme point as the CD mutation point of non-corner; Step S2: calculating the direction of the maximum local layout weighted density of the light intensity of all the CD mutation points of non-corner and the relative value of the weighted density of the direction, and calculating the local layout dispersion index value representing the dispersion degree of the local layout around the CD mutation point of non-corner, wherein the method for calculating the direction of the maximum local layout weighted density and the relative value of the weighted density comprises the following steps: taking each CD mutation point of non-corner as the center to intercept the local layout of the surrounding square area; taking each CD mutation point of non-corner as the origin, sampling the local layout to obtain a sampling point; calculating the contribution component of the sampling point to the light intensity at the origin as the modulus of the vector by using the OPC optical model, and taking the direction from the origin to the sampling point as the direction of the vector, thereby obtaining the vector corresponding to the sampling point; and adding all the vectors in the local layout to obtain a vector sum, wherein the direction of the vector sum is the direction of the maximum local layout weighted density, and the size of the vector sum represents the degree to which the direction of the vector sum is higher than other directions in the local layout in terms of the weighted density; the method for calculating the dispersion index value comprises the following steps: calculating the modulus of the vector sum according to the vector sum, and calculating the degree to which the direction of the maximum local layout weighted density is higher than other directions in the local layout in terms of the weighted density; Step S3: selecting a lithography test pattern according to the CD of the pattern layout at the position of the CD mutation point of non-corner, the direction of the maximum local layout weighted density, the relative value of the weighted density, and the dispersion index value.

2. The method of claim 1, wherein the method further comprises: The method for obtaining the full-chip profile comprises the following steps: creating an OPC optical model according to the lithography parameters of the lithography process and optical principles, and simulating the full-chip layout by using the OPC optical model to obtain the full-chip profile.

3. The method of claim 1, wherein the method further comprises: Vector size corresponding to sampling point i satisfies the following formula: ； where M i is the equivalent mask with only sampling point i that is the same as the local layout area.

4. The method of claim 1, wherein the method further comprises: determining a set of test patterns from the full-chip layout; and generating a set of test patterns from the set of test patterns. The vector sum (θ, r) satisfies the following formula: ； wherein, is the direction of the sampling point i in the local layout relative to the origin; is the size of the vector corresponding to the sampling point i; the direction θ of the vector sum (θ, r) is the direction pointing to the maximum weighted density in the local layout; the size r of the vector sum (θ, r) represents the degree to which the direction θ is higher than other directions in the weighted density in the local layout, and r is the modulus of the vector sum corresponding to each sampling point in the local layout.

5. The method of claim 4, wherein the method further comprises: The method for calculating the dispersion index value representing the dispersion degree of the local layout around the CD mutation point of non-corner comprises the following steps: calculating the modulus of the vector sum according to the vector sum, and calculating the degree to which the direction of the maximum local layout weighted density is higher than other directions in the local layout in terms of the weighted density.

6. The method of claim 5, wherein the method further comprises: The dispersion index value J satisfies the following formula: ； wherein, is the vector size corresponding to sampling point i; r represents the degree to which the direction θ is weighted more heavily than other directions in the local layout, and r is the modulus of the sum of the vectors corresponding to each sampling point in the local layout.

7. The method of claim 5, wherein the method further comprises: determining a set of test patterns from the full-chip layout; and generating a set of test patterns from the set of test patterns. 5 Step S3 comprises the following steps: According to the CD of the position where the CD mutation point of the non-corner is located, the maximum direction of the local layout weighted density, the relative value of the weighted density, the dispersion index value and the slope of the graphic profile on the non-corner edge of the layout where the CD mutation point of the non-corner is located, the above parameters are classified and counted, and the corresponding layout is selected as the test layout according to the classification and counting results.

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