A small chip-oriented vlsi standard cell layout method and related device

Abstract

This invention provides a VLSI standard cell layout method and related equipment for chiplets, comprising: Step 1, acquiring the netlist, process library information, and layout constraint information of the target circuit diagram; Step 2, representing the netlist as a hypergraph model, and partitioning the hypergraph model according to the connectivity of the hypergraph model to obtain the partitioning result; Step 3, based on the process library information and layout constraint information, and with the half-circuit line length of the die as the optimization target, performing global layout on the die based on the partitioning result to obtain the standard cell layout result; Step 4, based on the standard cell layout result, laying out interconnect terminals to obtain the layout result of the target circuit diagram on the die; Compared with the prior art, this method improves the yield rate of large chip processing, reduces the design complexity, and accelerates the chip manufacturing cycle.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit layout technology, and in particular to a VLSI standard cell layout method for chiplets. Background Technology

[0002] In the current layout of Very Large Scale Integration (VLSI) circuits, with the continuous development of science and technology, the scale of integrated circuits is constantly increasing, and advanced processes are constantly advancing, causing Moore's Law to gradually become ineffective. The chip layout problem is an NP-hard problem. Layout is a crucial process in physical design, and the quality of the layout directly affects the performance of the entire chip. The rapid increase in the number of standard cells on a chip presents enormous challenges to chip layout design. Therefore, finding new and efficient circuit layout algorithms is extremely important.

[0003] In the post-Moore's Law era, chiplet technology emerged to perpetuate Moore's Law. A chiplet is a miniature integrated circuit (IC) containing a well-defined subset of functions. It is designed to be combined with other chiplets on an interposer layer within a single package; a group of chiplets can be assembled into "Lego-like" components. Chiplet technology is a new chip design approach that emerged after System-on-Chips (SoC) integration reached a certain stage. It divides the SoC into smaller dies, interconnects these modular dies, and uses novel packaging technologies to package chiplets with different functions and manufactured using different processes together into a heterogeneous integrated chip.

[0004] However, in existing 3D layout of integrated circuits, a rough 3D layout result is obtained by first dividing the entire system into layers, and then performing 2D layout, validation, and detailed layout to obtain the overall layout result. Traditional 3D layout cannot apply different processes to each layer during the layout process, and it does not optimize the number of interconnects between layers. Summary of the Invention

[0005] This invention provides a VLSI standard cell layout method and related equipment for chiplets, with the aim of improving the yield rate of large chip processing.

[0006] To achieve the above objectives, the present invention provides a VLSI standard cell layout method for chiplets, comprising:

[0007] Step 1: Obtain the netlist, technology library information, and layout constraint information of the target circuit diagram;

[0008] Step 2: Represent the netlist as a hypergraph model, and partition the hypergraph model according to its connectivity to obtain the partitioning results;

[0009] Step 3: Based on the process library information and layout constraint information, with the half-circle length of the bare die as the optimization target, perform global layout on the partitioning results on the bare die to obtain the standard cell layout results.

[0010] Step 4: Based on the standard cell layout result, the interconnect terminals are laid out to obtain the layout result of the target circuit diagram on the bare die.

[0011] Furthermore, step 2 includes:

[0012] Represent the netlist as a hypergraph model H = {V, E};

[0013] Where V = {v1, v2, ..., v} n} represents the set of standard units, E = {e1, e2, ..., e n} represents a set of wire meshes;

[0014] Detect the connectivity of the hypergraph model H, and divide the hypergraph model H into multiple fully connected first sub-hypergraph models H based on the connectivity. i ;

[0015] According to the first sub-hypergraph model H i The number of nodes is determined by the formula k = min(2 + log2|V|, α), which is used to decompose each first sub-hypergraph model H. i The partitioning process is performed to obtain k-block partitioning results;

[0016] Here, α is a hyperparameter, α = 22.

[0017] Furthermore, prior to step 3, the following steps are also included:

[0018] Aggregate all standard cells within each partition result to obtain multiple aggregation results, and calculate the total area of ​​standard cells in each aggregation result;

[0019] In each aggregation result, remove the nets that only connect to one node and remove duplicates of all identical nets to obtain the deduplicated aggregation result;

[0020] In the deduplicated aggregation result, weights are added to the wire mesh to obtain the second sub-hypergraph model H with k nodes. j .

[0021] Furthermore, prior to step 3, the validity of the second sub-hypergraph model is also determined:

[0022] Enumerate all solutions S of the second sub-hypergraph model. For each solution, calculate the total area consumed by the die under solution S and determine whether the total area exceeds the maximum usable area.

[0023] If the total area is greater than the maximum usable area, the second sub-hypergraph model is deemed invalid.

[0024] If the total area is less than or equal to the maximum usable area, the second sub-hypergraph model is deemed valid, and the valid second sub-hypergraph model is taken as the partitioning result.

[0025] Furthermore, the total area A(S,d) consumed by the bare wafer d under solution S is calculated as follows:

[0026]

[0027] in, COSt d Indicates the area already used, a d,j d represents the area occupied by a standard cell on the die. j This indicates the location of the nude film.

[0028] Furthermore, step 3 includes:

[0029] For pin p connected to net e, p = 1, 2, ..., n;

[0030] For interconnect network e, the area enclosed by all the pins on die d will be denoted as B. d,e Then region B d,e The coordinates are:

[0031]

[0032] The half-circumference length HPWL(m,e) of the wire mesh e on the die is:

[0033] HPWL(m,e)=yur d,e +xur d,e -xll d,e -yll d,e

[0034] The total half-circumference length HPWL(m) on the bare die d is:

[0035]

[0036] Among them, (x p y p ) represents the coordinates of pin p, and d represents the coordinates of pin p. p Let (xll) be the bare die where pin p is located. d,e yll d,e (For region B) d,eThe coordinates of the lower left corner, (xur d,e yur d,e (For region B) d,e The coordinates of the upper right corner;

[0037] Using the total half-circumference line length HPWL(m) on the bare die d as the optimization objective, the layouter is used to perform global layout of the partitioning results on the bare die to obtain the standard cell layout results.

[0038] Furthermore, before laying out the interconnect terminals based on the layout results of the standard cells, the following steps are also included:

[0039] If the spacing between any two interconnect terminals and the die boundary is assumed to satisfy the spacing constraint, then the spacing constraint of the x-axis coordinate of each interconnect terminal is:

[0040]

[0041] The spacing constraint for the y-axis coordinate of each interconnect terminal is then:

[0042]

[0043] Where l represents the side length of the interconnecting terminal, pitch represents the given interval, (x e y e ) indicates interconnection terminal t e The center coordinates are (x, y), which represents the upper right coordinates of the layout area, and a and b represent the subscripts of different interconnects.

[0044] The present invention also provides a VLSI standard cell layout device for chiplets, comprising:

[0045] The acquisition module is used to acquire the netlist, technology library, technology library information, and layout constraint information of the target circuit diagram;

[0046] The partitioning module is used to represent the netlist as a hypergraph model, and to partition the hypergraph model according to its connectivity to obtain the partitioning results;

[0047] The standard cell layout module is used to perform global layout of the partitioning results on the die based on process library information and layout constraint information, with the half-circle line length of the die as the optimization target, to obtain the standard cell layout result.

[0048] The interconnect terminal layout module is used to lay out interconnect terminals based on the layout results of standard cells, so as to obtain the layout result of the target circuit diagram on the bare die.

[0049] The present invention also provides a computer-readable storage medium storing a computer program that, when executed by a processor, implements a VLSI standard cell layout method for chiplets.

[0050] The present invention also provides a terminal device, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the computer program to implement a VLSI standard cell layout method for chiplets.

[0051] The above-described solution of the present invention has the following beneficial effects:

[0052] This invention acquires the netlist, process library information, and layout constraint information of the target circuit diagram; represents the netlist as a hypergraph model; partitions the hypergraph model based on its connectivity to obtain the partitioning result; and, based on the process library information and layout constraint information, performs global layout on the die using the half-circuit length of the bare die as the optimization target to obtain the standard cell layout result. Based on the standard cell layout result, interconnect terminals are then laid out to obtain the layout result of the target circuit diagram on the die. Compared with existing technologies, this invention improves the yield rate of large-scale chips, reduces design complexity, and accelerates the chip manufacturing cycle. Furthermore, it allows for manufacturing using different processes, materials, and nodes, each optimized for its specific function.

[0053] Other beneficial effects of the present invention will be described in detail in the following detailed description section. Attached Figure Description

[0054] Figure 1 This is a flowchart illustrating an embodiment of the present invention;

[0055] Figure 2 This is a schematic diagram of the optimal layout area of ​​the wire mesh in an embodiment of the present invention. Detailed Implementation

[0056] To make the technical problems, solutions, and advantages of this invention clearer, a detailed description will be provided below with reference to the accompanying drawings and specific embodiments. Obviously, the described embodiments are only some, not all, of the embodiments of this invention. All other embodiments obtained by those skilled in the art based on the embodiments of this invention without creative effort are within the scope of protection of this invention.

[0057] In the description of this invention, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing the invention and for simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on the invention. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0058] In the description of this invention, it should be noted that, unless otherwise explicitly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a locking connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection of two components. Those skilled in the art can understand the specific meaning of the above terms in this invention based on the specific circumstances.

[0059] Furthermore, the technical features involved in the different embodiments of the present invention described below can be combined with each other as long as they do not conflict with each other.

[0060] This invention addresses existing problems by providing a VLSI standard cell layout method and related equipment for chiplets.

[0061] like Figure 1 As shown, embodiments of the present invention provide a VLSI standard cell layout method for chiplets, including:

[0062] Step 1: Obtain the netlist, technology library information, and layout constraint information of the target circuit diagram;

[0063] Step 2: Represent the netlist as a hypergraph model, and partition the hypergraph model according to its connectivity to obtain the partitioning results;

[0064] Step 3: Based on the process library information and layout constraint information, with the half-circle length of the bare die as the optimization target, perform global layout on the partitioning results on the bare die to obtain the standard cell layout results.

[0065] Step 4: Based on the layout results of the standard cells, the interconnect terminals are laid out to obtain the layout results of the target circuit diagram on the bare die.

[0066] Specifically, the netlist represents the connection relationship between standard cells, the process library represents the length, width, and pin coordinate set of the standard cells, the die includes the row height, row width, number of rows, size, maximum area utilization and the process used, and the interconnect terminal includes the size and minimum spacing of the interconnect terminal.

[0067] Specifically, step 2 includes:

[0068] Represent the netlist as a hypergraph model H = {V, E};

[0069] Where V = {v1, v2, ..., v} n} represents the set of standard units, E = {e1, e2, ..., e n} represents a set of wire meshes;

[0070] Detect the connectivity of the hypergraph model H, and divide the hypergraph model H into multiple fully connected first sub-hypergraph models H based on the connectivity. i ={V i E i A fully connected hypergraph model is defined as a hypergraph model that can be traversed from any node using a breadth-first search.

[0071] According to the first sub-hypergraph model H i Number of nodes | V i Using the formula k = min(2 + log2|V|, α) from the traditional balanced partitioning algorithm, each first sub-hypergraph model H is partitioned. i The partitioning process is performed to obtain k-block partitioning results;

[0072] Here, α is a hyperparameter. In this embodiment of the invention, α = 22. Increasing the value of α will lengthen the running time of the partitioning process, while decreasing the value of α will reduce the quality of the partitioning results.

[0073] Specifically, before step 3, the following is also included:

[0074] Aggregate all standard cells within each partitioned result to obtain multiple aggregation results, and calculate the total area of ​​standard cells in each aggregation result under both processes;

[0075] In each aggregation result, remove the nets that only connect to one node and remove duplicates of all identical nets to obtain the deduplicated aggregation result;

[0076] In the deduplicated aggregation result, weights are added to the wire mesh to obtain the second sub-hypergraph model H with k nodes. j .

[0077] Specifically, before step 3, the validity of the second sub-hypergraph model is also determined:

[0078] Enumerate all solutions S of the second sub-hypergraph model. For each solution, calculate the total area consumed by the die under solution S and determine whether the total area exceeds the maximum usable area.

[0079] Specifically, the total area A(S,d) consumed by the bare wafer d under solution S is calculated as follows:

[0080]

[0081] Where S∈[0, 2] k -1], COSt d Indicates the area already used, a d,j d represents the area occupied by a standard cell on the die. j This indicates the bare slice where the node is located.

[0082] If the total area is less than or equal to the maximum usable area, the second sub-hypergraph model is deemed valid, and the valid second sub-hypergraph model is taken as the partitioning result.

[0083] In this embodiment of the invention, when A(S,d)≤a d *util d At that time, the number of interconnect nets (Cuts) is calculated. An interconnect net is defined as a net connecting two bare dies. For the net e in the second sub-hypergraph model... j Let j = 1, 2, ..., n, and let w be the integer part of the string. j For the network e j If the weights are determined, then the number of interconnections is:

[0084]

[0085] in, Indicates the wire mesh e j The two different standard units connected, i.e., when the wire mesh e j When it is an interconnect network, β(e) j If the value is 1, then the value is 0; otherwise, the value is 0.

[0086] If the total area is greater than the maximum usable area, then the second sub-hypergraph model is deemed invalid; that is, when A(S,d)>a d *util d If so, skip that solution.

[0087] Record the minimum number of interconnects and its corresponding solution S, map solution S back to the hypergraph model H, and extract the next second sub-hypergraph model H. j+1 If all enumerated solutions do not satisfy A(S,d)≤a d *util d Then, they reassemble.

[0088] Specifically, step 3 includes:

[0089] For pin p connected to net e, p = 1, 2, ..., n;

[0090] For interconnect network e, the area enclosed by all the pins on die d will be denoted as B. d,e Then region B d,e The coordinates are:

[0091]

[0092] The half-circumference length HPWL(m,e) of the wire mesh e on the die is:

[0093] HPWL(m,e)=yur d,e +xur d,e -xll d,e -yll d,e

[0094] The half-circumference line length HPWL(m) on the bare die d is:

[0095]

[0096] Among them, (x p y p ) represents the coordinates of pin p, and d represents the coordinates of pin p. p Let (xll) be the bare die where pin p is located. d,e yll d,e (For region B) d,e The coordinates of the lower left corner, (xur d,e yur d,e (For region B) d,e The coordinates of the upper right corner;

[0097] Using the half-circuit length HPWL(m) on the bare die d as the optimization target, the layouter is used to perform global layout of the partitioning results on the bare die. The global layout results are then validated and detailed using ntuplace3 to obtain the standard cell layout results.

[0098] Specifically, before laying out the interconnect terminals based on the layout results of the standard cells, the following steps are also included:

[0099] In this embodiment of the invention, an interconnect terminal t needs to be allocated to each interconnect network e. e Inter-die communication and interconnection are performed through the interconnect terminals, (x) e y e ) is the interconnection terminal t e The center coordinates of the interconnect terminal t are used to calculate the connection. eThe change in the semicircular length of the x-axis on the bare die d is then:

[0100]

[0101] Add interconnecting terminals t e The change in half-circumference length of the mesh e on the y-axis is the same as that on the x-axis. When considering two dies, the change in half-circumference length of the mesh e is:

[0102]

[0103] For interconnect network e, the area enclosed by all the pins on die d will be denoted as B. d,e When the interconnecting terminal t e Within the optimal layout region, the change in the half-circle length of wire mesh e is minimized. Therefore, the optimal layout region is as follows: Figure 2 As shown, the coordinates of the optimal layout region are:

[0104]

[0105] When laying out interconnect terminals, it is necessary to pre-determine the spacing between any two interconnect terminals and the die boundary to satisfy the spacing constraint. The spacing constraint is defined as the spacing between any two interconnect terminals or between any terminal and the layout boundary. For the layout area R, its size is the same as the die size, and its lower left coordinate is regarded as the origin (0, 0) and its upper right coordinate is (x, y). Each terminal is a square of the same size, and its side length is denoted as l. Then the spacing constraint of the x-axis coordinate of each interconnect terminal is:

[0106]

[0107] The spacing constraint for the y-axis coordinate of each interconnect terminal is then:

[0108]

[0109] Where l represents the side length of the interconnecting terminal, pitch represents the given interval, (x e y e ) indicates interconnection terminal t e The center coordinates are (x, y), which represents the upper right coordinates of the layout area, and a and b represent the subscripts of different interconnects.

[0110] In this embodiment of the invention, the interconnect terminal layout optimizes the half-circle length variation value while satisfying the spacing constraint. The specific steps are as follows:

[0111] The first step is to initialize the placement area as a grid with m*n grids, where each grid is a square with a side length of 1 + pitch. This ensures that each grid can hold exactly one interconnect terminal. m and n are calculated using the following formula:

[0112]

[0113] For any grid b i,j Let i = 1, 2, ..., m; j = 1, 2, ..., n; and let w be the number of the numbers in the w_i_j ... i,j Let x be the congestion weight of grid b. i,j y i,j ) for grid b i,j The center coordinates of grid b are then... i,j The coordinates are:

[0114]

[0115] If the number of interconnect terminals is greater than m*n, then the layout area R cannot accommodate all the interconnect terminals, there is no valid solution, and the algorithm exits.

[0116] The second step is when grid b i,j coordinates (x) i,j y i,j When the network is within the optimal layout area of ​​interconnect network e, the congestion weight is added to the weight w of interconnect network e. e Traverse all interconnected networks e, calculate the optimal layout region for each interconnected network e, and increase the congestion weight of all networks whose center coordinates fall within the optimal layout region by w. e If there are no grids within the optimal layout area, find the grid whose coordinates are closest to the optimal layout area and increase its congestion weight by w. e .

[0117] The third step is to traverse all interconnect nets e and set their interconnect terminals t. e The grid b with the lowest congestion weight and no markings is placed within the optimal layout area. i,j Inside, t e Coordinates equal to grid b i,j The coordinates, marking the grid b i,j This indicates that an interconnect terminal has already been placed in this grid. If all grids within the optimal layout area are marked, a breadth-first search algorithm is used to progressively traverse the nearest grid outside the optimal layout area, then the grid with the smallest congestion weight that is not marked is searched. If all grids are still marked, the search continues outward until the interconnect terminal t is placed. e Place it on the grid, mark the grid, and exit the breadth-first traversal; complete the optimization of the total half-circle length change value.

[0118] This invention acquires the netlist, process library information, and layout constraint information of the target circuit diagram; represents the netlist as a hypergraph model; divides the hypergraph model according to its connectivity to obtain the division result; based on the process library information and layout constraint information, and with the half-circuit length of the die as the optimization target, performs global layout on the die based on the division result to obtain the standard cell layout result; and lays out interconnect terminals based on the standard cell layout result to obtain the layout result of the target circuit diagram on the die. Compared with the prior art, this improves the yield rate of large chips, reduces the design complexity, and accelerates the chip manufacturing cycle; at the same time, it can be manufactured using different processes, materials, and nodes, each optimized for its specific function.

[0119] This invention also provides a VLSI standard cell layout device for chiplets, comprising:

[0120] The acquisition module is used to acquire the netlist, technology library, technology library information, and layout constraint information of the target circuit diagram;

[0121] The partitioning module is used to represent the netlist as a hypergraph model, and to partition the hypergraph model according to its connectivity to obtain the partitioning results;

[0122] The standard cell layout module is used to perform global layout of the partitioning results on the die based on process library information and layout constraint information, with the half-circle line length of the die as the optimization target, to obtain the standard cell layout result.

[0123] The interconnect terminal layout module is used to lay out interconnect terminals based on the standard cell layout results, so as to obtain the layout result of the target circuit diagram on the die.

[0124] It should be noted that the information interaction and execution process between the above-mentioned devices / units are based on the same concept as the method embodiments in the present invention. For details on their specific functions and technical effects, please refer to the method embodiments section, which will not be repeated here.

[0125] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the above-described division of functional units and modules is merely an example. In practical applications, the above functions can be assigned to different functional units and modules as needed, that is, the internal structure of the device can be divided into different functional units or modules to complete all or part of the functions described above. The functional units and modules in the embodiments can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit. Furthermore, the specific names of the functional units and modules are only for easy differentiation and are not intended to limit the scope of protection of the embodiments of the present invention. The specific working process of the units and modules in the above system can be referred to the corresponding process in the foregoing method embodiments, and will not be repeated here.

[0126] This invention also provides a computer-readable storage medium storing a computer program that, when executed by a processor, implements a VLSI standard cell layout method for chiplets.

[0127] If the integrated unit is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the embodiments of the present invention can implement all or part of the processes in the methods described above by instructing related hardware through a computer program. The computer program can be stored in a computer-readable storage medium, and when executed by a processor, it can implement the steps of the various method embodiments described above. The computer program includes computer program code, which can be in the form of source code, object code, executable files, or certain intermediate forms. The computer-readable medium can include at least: any entity or device capable of carrying the computer program code to a building device / terminal device, a recording medium, a computer memory, a read-only memory (ROM), a random access memory (RAM), an electrical carrier signal, a telecommunication signal, and a software distribution medium. Examples include USB flash drives, portable hard drives, magnetic disks, or optical disks. In some jurisdictions, according to legislation and patent practice, computer-readable media cannot be electrical carrier signals or telecommunication signals.

[0128] This invention also provides a terminal device, including a memory, a processor, and a computer program stored in the memory and executable on the processor. When the processor executes the computer program, it implements a VLSI standard cell layout method for chiplets.

[0129] It should be noted that the terminal device can be a mobile phone, tablet computer, laptop computer, Ultra-mobile Personal Computer (UMPC), netbook, Personal Digital Assistant (PDA), etc. For example, the terminal device can be a station (ST) in a WLAN, a cellular phone, cordless phone, Session Initiation Protocol (SIP) phone, Wireless Local Loop (WLL) station, PDA, handheld device with wireless communication capabilities, computing device or other processing device connected to a wireless modem, computer, laptop computer, handheld communication device, handheld computing device, satellite wireless device, etc. This embodiment of the invention does not impose any restrictions on the specific type of terminal device.

[0130] The processor referred to can be a Central Processing Unit (CPU), but it can also be other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. A general-purpose processor can be a microprocessor or any conventional processor.

[0131] In some embodiments, the memory may be an internal storage unit of the terminal device, such as a hard drive or RAM. In other embodiments, the memory may be an external storage device of the terminal device, such as a plug-in hard drive, Smart Media Card (SMC), Secure Digital Card (SD), or Flash Card. Furthermore, the memory may include both internal and external storage units of the terminal device. The memory is used to store the operating system, applications, bootloader, data, and other programs, such as the program code of the computer program. The memory can also be used to temporarily store data that has been output or will be output.

[0132] It should be noted that the information interaction and execution process between the above-mentioned devices / units are based on the same concept as the method embodiments in the present invention. For details on their specific functions and technical effects, please refer to the method embodiments section, which will not be repeated here.

[0133] The above description represents the preferred embodiments of the present invention. It should be noted that those skilled in the art can make various improvements and modifications without departing from the principles of the present invention, and these improvements and modifications should also be considered within the scope of protection of the present invention.

Claims

1. A VLSI standard cell layout method for chiplets, characterized in that, include: Step 1: Obtain the netlist, technology library information, and layout constraint information of the target circuit diagram; Step 2: Represent the netlist as a hypergraph model, and partition the hypergraph model according to its connectivity to obtain the partitioning result; Step 3: Based on the process library information and the layout constraint information, with the half-circle line length of the die as the optimization target, perform global layout on the partitioning results on the die to obtain the standard cell layout result; Step 4: Based on the standard cell layout result, the interconnect terminals are laid out to obtain the layout result of the target circuit diagram on the bare die; Step 3 includes: for the wire mesh Connected pins , ; For Internet It will be in the nude film The area enclosed by all the pins on the surface is denoted as Then the region The coordinates are: ； Net Half-circumference on the nude film for: ； nude film Total half-circle length for: ； in, For pins coordinates For pins The nude film in question, For the region The coordinates of the lower left corner, For the region The coordinates of the upper right corner; With the aforementioned bare die Total half-circle length To optimize the target, a layouter is used to perform a global layout of the partitioning results on the bare die, resulting in a standard cell layout.

2. The VLSI standard cell layout method for chiplets according to claim 1, characterized in that, Step 2 includes: The netlist is represented as a hypergraph model H={V, E}; Where V = {v1, v2, ..., v} n } represents the set of standard units, E={e1,e2,...,e n } represents a set of wire meshes; Detect the connectivity of the hypergraph model H, and divide the hypergraph model H into multiple fully connected first sub-hypergraph models based on the connectivity. ; Based on the first sub-hypergraph model The number of nodes, using the formula Each of the first sub-hypergraph models Divide into, and obtain Block partitioning results; in, As a hyperparameter, .

3. The VLSI standard cell layout method for chiplets according to claim 2, characterized in that, Before step 3, the following is also included: Aggregate all standard units within each partition result to obtain multiple aggregation results, and calculate the total area of ​​the standard units in each aggregation result; In each aggregation result, remove the nets that only connect to one node and remove duplicates of all identical nets to obtain the deduplicated aggregation result; In the deduplicated aggregation result, weights are added to the wire mesh to obtain a second sub-hypergraph model with k nodes. .

4. The VLSI standard cell layout method for chiplets according to claim 3, characterized in that, Before step 3, the validity of the second sub-hypergraph model is also determined: Enumerate all solutions S of the second sub-hypergraph model. For each solution, calculate the total area consumed by the die under solution S, and determine whether the total area exceeds the maximum usable area. If the total area is greater than the maximum usable area, then the second sub-hypergraph model is deemed invalid. If the total area is less than or equal to the maximum usable area, the second sub-hypergraph model is determined to be valid, and the valid second sub-hypergraph model is taken as the partitioning result.

5. The VLSI standard cell layout method for chiplets according to claim 4, characterized in that, Calculate the bare die under solution S. Total area consumed for: ； in, , Indicates the area already used. This indicates the area occupied by a standard cell on the die. This indicates the location of the nude film.

6. The VLSI standard cell layout method for chiplets according to claim 1, characterized in that, Before laying out the interconnect terminals based on the layout result of the standard cells, the following steps are also included: If the spacing between any two interconnect terminals and the die boundary is assumed to satisfy the spacing constraint, then the spacing constraint of the x-axis coordinate of each interconnect terminal is: ； The spacing constraint for the y-axis coordinate of each interconnect terminal is then: ； in, Indicates the side length of the interconnecting terminal. Indicates a given interval, Indicates interconnection terminals The center coordinates, This indicates the top-right coordinates of the layout area. , Subscripts indicating different interconnect networks.

7. A VLSI standard cell layout device for chiplets, characterized in that, include: The acquisition module is used to acquire the netlist, technology library information, and layout constraint information of the target circuit diagram; The partitioning module is used to represent the netlist as a hypergraph model, partition the hypergraph model according to the connectivity of the hypergraph model, and obtain the partitioning result; The standard cell layout module is used to perform global layout of the partitioning results on the die based on the process library information and the layout constraint information, with the half-circumference line length of the die as the optimization target, to obtain the standard cell layout result. An interconnect terminal layout module is used to lay out interconnect terminals based on the standard cell layout result, so as to obtain the layout result of the target circuit diagram on the die. The standard cell layout module includes: For wire mesh Connected pins , ; For Internet It will be in the nude film The area enclosed by all the pins on the surface is denoted as Then the region The coordinates are: ； Net Half-circumference on the nude film for: ； nude film Total half-circle length for: ； in, For pins coordinates For pins The nude film in question, For the region The coordinates of the lower left corner, For the region The coordinates of the upper right corner; With the aforementioned bare die Total half-circle length To optimize the target, a layouter is used to perform a global layout of the partitioning results on the bare die, resulting in a standard cell layout.

8. A computer-readable storage medium storing a computer program, characterized in that, When the computer program is executed by the processor, it implements the VLSI standard cell layout method for chiplets as described in any one of claims 1 to 6.

9. A terminal device, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that, When the processor executes the computer program, it implements the VLSI standard cell layout method for chiplets as described in any one of claims 1 to 6.

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