A method for simulating equivalent fault injection in integrated circuit single-event soft error (SIF) simulation

Abstract

An equivalent fault injection method for simulating single-event soft errors (SEE) in integrated circuits is proposed. Based on the analysis of particle injection location distribution and fault introduction mechanism in ground accelerator tests, the analysis of the proportion of single-event sensitive areas in each unit circuit of the chip integration, and the quantity proportion analysis, the method provides support for determining the input conditions for chip-level SEE simulation through an equivalent fault injection sample set sampling method, thereby more accurately simulating the cross-section of SEE in integrated circuits caused by ground test particles.

Description

Technical Field

[0001] This invention relates to an equivalent fault injection method for single-event soft error simulation of integrated circuits, belonging to the field of radiation protection technology for aerospace components. Background Technology

[0002] Integrated circuits used in spacecraft operate in the space radiation environment. High-energy particles in space can enter the device and ionize it along their path. Circuit nodes absorb the electrons and holes generated by ionization, forming current pulses. These current pulses propagate through cascaded gate circuits, leading to output errors in the integrated circuit, known as single-event soft errors (SEE). To ensure long lifespan and high reliability of spacecraft, it is necessary to evaluate the SEE characteristics of integrated circuits. In engineering, this is mainly achieved through simulation experiments conducted on ground-based accelerators to obtain the soft error cross-section of integrated circuits, i.e., the number of soft errors per unit particle fluence. However, due to the scarcity of accelerator resources in China, simulation of the SEE cross-section using integrated circuit simulation software such as TCAD, SPICE, and VCS has become an important research and supplementary method.

[0003] Improving the accuracy and objectivity of single-event soft error (SEE) simulations for integrated circuits is a crucial issue that needs to be addressed to advance the application of radiation effect simulations for aerospace electronic devices in ruggedized device development and aerospace systems engineering. The equivalence of fault injection during SEE simulations determines the equivalence and accuracy of simulation results with ground-based test evaluation methods.

[0004] In ground-based accelerator experiments, test particles, at a specific particle fluence, simultaneously irradiate all gate circuit units within the entire chip. Considering the different gate circuit units integrated within the chip, their number of units, single-particle sensitive areas, and transient pulse morphologies caused by the incident particles all vary. This leads to different contributions of each gate unit's single-particle soft error (SPOF) to the integrated circuit. Furthermore, particles in SPOF experiments may bombard any location within the device, resulting in different transient pulse responses depending on the particle's location. Therefore, to obtain simulation results of the soft error cross-section of the integrated circuit under incident particle irradiation, it is necessary to perform equivalent selection of the number of fault injection samples and the transient pulse injection morphology for each gate unit node in the simulation.

[0005] Current simulation methods mainly determine single-event sensitive nodes and critical propagation paths by injecting pulses into the circuit nodes of each gate unit inside the integrated circuit and observing whether this causes changes in the device's logic function. However, since the fault injection mode of the integrated circuit under ground accelerator irradiation is not considered, the simulation results are not comparable to the soft error cross-section results of the ground accelerator. Summary of the Invention

[0006] The technical problem solved by this invention is: to address the error in the simulation and observation results obtained by traditional methods in the current technology, a single-event soft error simulation equivalent fault injection method for integrated circuits is proposed.

[0007] The present invention solves the above-mentioned technical problem through the following technical solution:

[0008] A method for simulating equivalent fault injection in integrated circuit single-event soft error (SIF) simulation includes:

[0009] Selected test particles from a ground-based accelerator;

[0010] Extract the number of gate circuits from the list of integrated circuit gate units;

[0011] Count the types of integrated circuit gate circuits and obtain the instantiation name and gate area of ​​each type of gate unit;

[0012] Determine the total number of all types of gate circuits in the integrated circuit to be analyzed;

[0013] Based on the type and energy parameters of any ground accelerator test particle, select the corresponding type of gate unit to perform particle injection simulation, and determine the area of ​​the single particle sensitive region and the width and height of the output response pulse;

[0014] Determine the injection probability of each type of gate cell, and randomly select the gate cells to be injected based on the proportion of the area of ​​each gate cell to the total area of ​​the integrated circuit;

[0015] Fault injection is performed by randomly selecting an injection node within the injected gate unit.

[0016] Simulation was performed to determine the number of soft errors in each gate circuit node of the injected gate unit;

[0017] Calculate the single-event soft error cross section of the integrated circuit under selected ground accelerator test particles, which is used to calculate the soft error rate of the integrated circuit under a specified satellite orbit.

[0018] The number and types of particles tested by the ground accelerator are selected based on the characteristics of space radiation particles, and at least four types of ground accelerator test particles in each category have LET values ​​between 1 and 37 MeV. 2 Between / mg, at least one ground-based accelerator test particle has a LET value between 65-99.8 MeV.cm. 2 The LET values ​​are between / mg; the LET values ​​of the first, second, third and nth test particles increase sequentially.

[0019] The number of gate circuits extracted from the integrated circuit gate cell list is N, and the number of gate circuit types is M. Gate circuits with completely identical layout structures and fabrication processes are considered to be of the same type. The instantiation names and gate cell areas of each type of gate cell are extracted. The instantiation name of the j-th type of gate cell is selected, and the gate cell area is determined to be A. j .

[0020] The total number of various gate circuits in the integrated circuit to be analyzed is F, where F1, F2, ..., F... M The number of gate circuits of each type, F1+F2+…+F M =N.

[0021] Selecting the i-th type of ground-based accelerator test particle, and based on the type and energy parameters, selecting the corresponding j-th type of gate unit to perform particle injection simulation, the area S of the single-particle sensitive region when the i-th type of particle is incident on the j-th type of gate unit is obtained. i，j and output response pulse width W i，j and height H i，j .

[0022] The injection probability of each gate cell is determined. Injected gate cells are randomly selected based on the proportion of each gate cell's area to the total area of ​​the integrated circuit. Each gate cell contains a transistor and an injection node. The probability of randomly selecting any gate cell is determined based on the proportion of the gate cell's area to the total area. The injection probability of each transistor is Pm. The calculated parameters of the injected gate cell, corresponding to the transistor at the injection node, include:

[0023] Effective number of particles injected into a gate cell, probability of injecting into a certain instantiated gate, probability of a transistor being injected into a gate cell, and effective probability of injected particles into a device.

[0024] The number of fault injections effectively injected into a single gate cell of type j is calculated, specifically as: particle injection quantity. The sensitive area S of the j-th type gate unit i，j ;

[0025] The effective number of particles injected into a gate cell is the product of the number of injected particles, the ratio of the gate cell area to the total area of ​​the integrated circuit;

[0026] The probability of injecting a certain instantiated gate is the ratio of the instantiated gate cell area to the gate cell area.

[0027] The probability of a transistor being injected into a gate cell is the ratio of the transistor area to the gate cell area.

[0028] The effective probability of particle injection within the device is the ratio of the area of ​​the sensitive region to the area of ​​the transistor.

[0029] The fault injection method is specifically as follows:

[0030] The nodes to be injected into the selected gate unit are determined, and fault injection is performed according to the corresponding node lookup table. The different pulse responses caused by the same node injection under different input states are introduced through the lookup table. After fault injection, the correspondence R between the input state and the output state is determined. Under the premise that the injected node, input vector, output load and injected particle energy are determined, the output pulse width correspondence is generated. The number of soft errors of each gate circuit node of the injected gate unit is determined according to the simulation.

[0031] The single-event soft error cross section of the computational integrated circuit under the nth particle type is the sum of the soft error numbers of each gate node and the injection number. The ratio of .

[0032] The specific steps for selecting a corresponding type of gate unit for particle injection simulation are as follows:

[0033] Device-level modeling and single-particle incident simulation are performed on the transistors inside the gate circuit to obtain the transient current generated by the particle incident.

[0034] The transient current waveform is injected into the SPICE-level gate circuit, and the output response pulse square wave is obtained by simulation.

[0035] The response pulse width is determined based on the injection of SPICE-level LET current source, including the output pulse width values ​​corresponding to different input states, injection nodes, and output loads;

[0036] All other types of ground-based accelerator test particles were injected according to the current procedure.

[0037] The advantages of this invention compared to the prior art are:

[0038] (1) The present invention provides an equivalent fault injection method for single-event soft error simulation of integrated circuits, which can more accurately simulate the equivalent fault injection of single-event soft errors in integrated circuits. The method determines the number of faults injected and the shape of the injected pulse for gate cells with different layout designs in integrated circuits according to their single-event sensitive area and current pulse response characteristics after the incident particle. It more comprehensively considers the fault introduction mechanism of particles in ground accelerator test and the differences in single-event sensitivity of each gate cell in integrated circuits, and can solve the problem of equivalence between the simulation results of single-event soft errors of integrated circuits and the evaluation results of ground accelerator tests.

[0039] (2) Based on the analysis of the distribution of particle injection location and fault introduction mechanism in ground accelerator test, the analysis of the proportion of single-particle sensitive areas and the proportion of quantity of each unit circuit in chip integration, this invention can more accurately simulate the cross section of single-particle soft error of integrated circuit caused by ground test particles, and provide support for determining the input conditions for chip-level single-particle soft error simulation.

[0040] (3) This invention also considers the output load of the gate unit during fault injection, so that the electrical characteristics of the circuit can be maintained during fault propagation. During fault injection, the area of ​​each gate unit is considered first, and random selection is made according to the proportion of its area to the total design area. Secondly, the injection node is randomly selected inside the selected gate unit. The random probability of the injection node is proportional to the size of the transistor. Finally, the sensitive area of ​​the selected transistor is introduced, and the effectiveness of the injection point is determined by the proportion of the sensitive area. Through the consideration of the three areas, the particle injection is made more reasonable.

[0041] (4) The current source injected in this invention is taken from the device model simulation, and the circuit output response is taken from the analog circuit simulation, so that the output pulse width injected in the gate cell output of the gate-level netlist conforms to the actual propagation characteristics. At the same time, the timing of the netlist can be reversed by using the post-synthesis delay or the post-placement and routing delay, so that the circuit has a delay that is more in line with the physical implementation. Attached Figure Description

[0042] Figure 1 A schematic diagram of the equivalent fault injection method provided for the invention;

[0043] Figure 2 A schematic diagram of single-particle transient pulse simulation of a transistor within a gate unit provided for the invention;

[0044] Figure 3 A simulation diagram of the transient impulse response of the gate circuit level provided for the invention;

[0045] Figure 4 A simulation diagram of the transient pulse injection response of a circuit-level gate circuit provided for the invention; Detailed Implementation

[0046] An equivalent fault injection method for simulating single-event soft errors (SEE) in integrated circuits is proposed. Based on the analysis of particle injection location distribution and fault introduction mechanism in ground accelerator tests, the analysis of the proportion of single-event sensitive areas in each unit circuit of the chip integration, and the quantity proportion analysis, the method provides support for determining the input conditions for chip-level SEE simulation through an equivalent fault injection sample set sampling method, thereby more accurately simulating the cross-section of SEE in integrated circuits caused by ground test particles.

[0047] The specific process of the equivalent fault injection method for single-event soft error simulation in integrated circuits is as follows:

[0048] Selected test particles from a ground-based accelerator;

[0049] Extract the number of gate circuits from the list of integrated circuit gate units;

[0050] Count the types of integrated circuit gate circuits and obtain the instantiation name and gate area of ​​each type of gate unit;

[0051] Determine the total number of all types of gate circuits in the integrated circuit to be analyzed;

[0052] Based on the type and energy parameters of any ground accelerator test particle, select the corresponding type of gate unit to perform particle injection simulation, and determine the area of ​​the single particle sensitive region and the width and height of the output response pulse;

[0053] Determine the injection probability of each type of gate cell, and randomly select the gate cells to be injected based on the proportion of the area of ​​each gate cell to the total area of ​​the integrated circuit;

[0054] Fault injection is performed by randomly selecting an injection node within the injected gate unit.

[0055] Simulation was performed to determine the number of soft errors in each gate circuit node of the injected gate unit;

[0056] Calculate the single-event soft error cross section of the integrated circuit under selected ground accelerator test particles, which is used to calculate the soft error rate of the integrated circuit under a specified satellite orbit.

[0057] The number and types of particles tested by the ground-based accelerator were selected based on the characteristics of space-radiated particles, with at least four types of ground-based accelerator test particles having LET values ​​between 1 and 37 MeV. 2 Between / mg, at least one ground-based accelerator test particle has a LET value between 65-99.8 MeV.cm. 2 The LET values ​​of the selected test particles, from the first, second, third to the nth test particles, increase sequentially from / mg.

[0058] The number of gates extracted from the integrated circuit gate cell list is N, and the number of gate types is M. Gates with identical layout structure and fabrication process are considered to be of the same type. The instantiation name and gate cell area of ​​each type of gate cell are extracted. The instantiation name of the j-th type of gate cell is selected, and the gate cell area is determined to be A. j ;

[0059] Selecting the i-th type of ground-based accelerator test particle, and based on the type and energy parameters, selecting the corresponding j-th type of gate unit to perform particle injection simulation, the area S of the single-particle sensitive region when the i-th type of particle is incident on the j-th type of gate unit is obtained. i，j and output response pulse width W i，j and height H i，j ;

[0060] The injection probability of each gate cell is determined. Injected gate cells are randomly selected based on the proportion of each gate cell's area to the total area of ​​the integrated circuit. Each gate cell contains a transistor and an injection node. The probability of randomly selecting any gate cell is determined based on the proportion of the gate cell's area to the total area. The injection probability of each transistor is Pm. The calculated parameters of the injected gate cell, corresponding to the transistor at the injection node, include:

[0061] Effective number of particles injected into a gate cell, probability of injecting into a certain instantiated gate, probability of a transistor being injected into a gate cell, and effective probability of injected particles into a device;

[0062] The number of injected particles effectively injected into a single gate cell of type j is calculated as follows: Injection volume The sensitive area S of the j-th type gate unit i，j ;

[0063] The effective number of particles injected into a gate cell is the product of the number of injected particles, the ratio of the gate cell area to the total area of ​​the integrated circuit;

[0064] The probability of injecting a certain instantiated gate is the ratio of the instantiated gate cell area to the gate cell area.

[0065] The probability of a transistor being injected into a gate cell is the ratio of the transistor area to the gate cell area.

[0066] The effective probability of particle injection into the device is the ratio of the area of ​​the sensitive region to the area of ​​the transistor.

[0067] The specific fault injection method is as follows:

[0068] The nodes to be injected into the selected gate unit are determined, and fault injection is performed according to the corresponding node lookup table. The different pulse responses caused by the same node injection under different input states are introduced through the lookup table. The correspondence R between the input state and the output state is determined after fault injection. Under the premise that the injected node, input vector, output load and injected particle energy are determined, the output pulse width correspondence is generated. The number of soft errors of each gate circuit node of the injected gate unit is determined according to the simulation.

[0069] Calculate the single-event soft error cross section of an integrated circuit under the nth type of particle. The single-event soft error cross section is the sum of the soft error numbers of all gate nodes and the flux. The ratio;

[0070] The specific steps for selecting a corresponding type of gate unit for particle injection simulation are as follows:

[0071] Device-level modeling and single-particle incident simulation are performed on the transistors inside the gate circuit to obtain the transient current generated by the particle incident.

[0072] The transient current waveform is injected into the SPICE-level gate circuit, and the output response pulse square wave is obtained by simulation.

[0073] The response pulse width is determined based on the injection of SPICE-level LET current source, including the output pulse width values ​​corresponding to different input states, injection nodes, and output loads;

[0074] All other types of ground-based accelerator test particles were injected according to the current procedure.

[0075] The following description, in conjunction with the accompanying drawings and preferred embodiments, provides further details:

[0076] In the current embodiment, such as Figure 1 As shown, the equivalent fault injection method for single-event soft error simulation in integrated circuits has the following specific process:

[0077] (1) Select n types of ground-based accelerator test particles, namely, the first test particle, the second test particle, the third test particle, the fourth test particle, the fifth test particle, ..., the nth test particle; among the n test particles, at least four types have LET (linear energy transfer) values ​​between 1 and 37 MeV. 2 Between / mg, at least one of the n test particles has a LET value between 65-99.8 MeV.cm 2 The LET values ​​of the first test particle, the second test particle, the third test particle, the fourth test particle, the fifth test particle, ..., the nth test particle increase sequentially.

[0078] (2) Extract the number of gate circuits N based on the integrated circuit gate cell list;

[0079] (3) Statistically determine the types M of gate circuits in integrated circuits. Gate circuits with completely identical layout structure and process can be considered as one type of gate circuit. Extract the instantiation name and gate area A of the j-th type of gate unit. j ;

[0080] (4) Count the number F of each type of gate circuit in the integrated circuit to be analyzed, where F1+F2+…+F M =N;

[0081] (5) For the type and energy of the i-th test particle, particle injection simulation is performed on the j-th gate unit to obtain the area S of the single-particle sensitive region when the i-th particle is incident on the j-th gate unit. i，j and output response pulse width W i，j and height H i，j Where i = 1, 2, 3…n, j = 1, 2, 3…M;

[0082] (6) Determine the injection probability of each gate unit. A single-event event is a probabilistic event. The soft error cross section of a single-event event = number of soft errors / injection volume. Based on the proportion of each gate unit area to the overall design, the injected gate unit is randomly selected, and the probability of randomly selecting the gate unit is determined according to the proportion of the gate unit area to the total area.

[0083] The probability Pm of each transistor inside the gate cell being injected: the probability that the transistor corresponding to the injection node will be bombarded by high-energy particles given that the gate cell has been injected.

[0084]

[0085]

[0086]

[0087]

[0088] The number of injections effectively injected into a single gate cell of type j = injection volume The sensitive area S of the j-th type gate unit i，j

[0089] (7) Within the selected gate unit, internal randomization is performed based on the injection probability of each node to determine the injected node within the injection unit, and fault injection is performed according to the node lookup table. The error is injected into the design. Without affecting the original design structure, different impulse responses caused by the same node injection can be generated under different input states by introducing the lookup table, such as... Figure 3 As shown. The correspondence between input state and output, R: the correspondence between output pulse width under the premise that the injection node, input vector, output load, and injected particle energy are determined. The number of soft errors for each gate node is obtained through simulation.

[0090] (8) Calculate the single-event soft error cross section of the integrated circuit under the nth particle type. Single-event soft error cross section = total number of soft errors for each gate node / number of quantiles

[0091] In step (5), the simulation process of injecting the first type of experimental particle is as follows:

[0092] The first step is to perform device-level modeling and single-event simulation of the transistors inside the gate circuit, such as... Figure 2 As shown, the transient current generated by the particle incident is obtained through simulation;

[0093] The second step involves injecting the transient current waveform obtained in the first step into the SPICE-level gate circuit, and simulating to obtain the output response pulse square wave. The response pulse width is determined based on the SPICE-level LET current source injection, including the output pulse width values ​​corresponding to different input states, injection nodes, and output loads, such as... Figure 3 As shown;

[0094] like Figure 4 The figure shown is a simulation diagram of the transient pulse injection response of a circuit-level gate circuit.

[0095] Similarly, the same method is used to simulate the process of other experimental particles.

[0096] In the current embodiment, the injected current source is taken from the device model simulation, and the circuit output response is taken from the analog circuit simulation, so that the output pulse width injected in the gate cell output of the gate-level netlist conforms to the actual propagation characteristics. At the same time, the timing of the netlist can be reverse-annotated by the post-synthesis delay or the post-placement and routing delay, so that the circuit has a delay that is more consistent with the physical implementation.

[0097] Meanwhile, fault injection based on lookup tables will generate corresponding output pulse widths according to different input values ​​when injecting into the same node. This will take into account signal correlation and avoid redundant injection caused by not considering logic masking. The output load of the gate unit will also be considered during fault injection, so that the electrical characteristics of the circuit can be maintained during fault propagation.

[0098] During fault injection, the area of ​​each gate cell is considered first, and then randomly selected based on its proportion to the total design area. Next, injection nodes are randomly selected within the chosen gate cells, with the random probability of the injection node proportional to the transistor size. Finally, a sensitive region of the selected transistor is introduced, and the effectiveness of the injection point is determined by the proportion of the sensitive region. This three-part area consideration makes particle injection more reasonable.

[0099] Although the present invention has been disclosed above with reference to preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art can make possible changes and modifications to the technical solutions of the present invention by utilizing the methods and techniques disclosed above without departing from the spirit and scope of the present invention. Therefore, any simple modifications, equivalent changes and alterations made to the above embodiments based on the technical essence of the present invention without departing from the content of the technical solutions of the present invention shall fall within the protection scope of the technical solutions of the present invention.

[0100] The contents not described in detail in this specification are common knowledge to those skilled in the art.

Claims

1. A method for simulating equivalent fault injection in integrated circuit single-event soft error (SIF) simulation, characterized in that... include: Selected test particles from a ground-based accelerator; Extract the number of gate circuits from the list of integrated circuit gate units; Count the types of integrated circuit gate circuits and obtain the instantiation name and gate area of ​​each type of gate unit; Determine the total number of all types of gate circuits in the integrated circuit to be analyzed; Based on the type and energy parameters of any ground accelerator test particle, select the corresponding type of gate unit to perform particle injection simulation, and determine the area of ​​the single particle sensitive region and the width and height of the output response pulse; The fault injection method is specifically as follows: The nodes to be injected into the selected gate unit are determined, and fault injection is performed according to the corresponding node lookup table. The different pulse responses caused by the same node injection under different input states are introduced through the lookup table. The correspondence R between the input state and the output state is determined after fault injection. Under the premise that the injected node, input vector, output load and injected particle energy are determined, the output pulse width correspondence is generated. The number of soft errors of each gate circuit node of the injected gate unit is determined according to the simulation. Determine the injection probability of each type of gate cell, and randomly select the gate cells to be injected based on the proportion of the area of ​​each gate cell to the total area of ​​the integrated circuit; Fault injection is performed by randomly selecting an injection node within the injected gate unit. The specific steps for selecting a corresponding type of gate unit for particle injection simulation are as follows: Device-level modeling and single-particle incident simulation are performed on the transistors inside the gate circuit to obtain the transient current generated by the particle incident. The transient current waveform is injected into the SPICE-level gate circuit, and the output response pulse square wave is obtained by simulation. The response pulse width is determined based on the injection of SPICE-level LET current source, including the output pulse width values ​​corresponding to different input states, injection nodes, and output loads; All other types of ground-based accelerator test particles were injected according to the current procedure; Simulation was performed to determine the number of soft errors in each gate circuit node of the injected gate unit; Calculate the single-event soft error cross section of the integrated circuit under selected ground accelerator test particles, which is used to calculate the soft error rate of the integrated circuit under a specified satellite orbit.

2. The method for simulating equivalent fault injection in integrated circuit single-event soft error simulation according to claim 1, characterized in that: The number and types of particles tested by the ground accelerator are selected based on the characteristics of space radiation particles, and at least four types of ground accelerator test particles in each category have LET values ​​between 1 and 37 MeV.cm. 2 Between / mg, at least one ground-based accelerator test particle has a LET value between 65 and 99.8 MeV.cm. 2 The LET values ​​are between / mg; the LET values ​​of the first, second, third and nth test particles increase sequentially.

3. The method for simulating equivalent fault injection in integrated circuit single-event soft error according to claim 2, characterized in that: The number of gate circuits extracted from the integrated circuit gate cell list is N, and the number of gate circuit types is M. Gate circuits with completely identical layout structures and fabrication processes are considered to be of the same type. The instantiation names and gate cell areas of each type of gate cell are extracted. The instantiation name of the j-th type of gate cell is selected, and the gate cell area is determined to be A. j .

4. The method for simulating equivalent fault injection in integrated circuit single-event soft error according to claim 3, characterized in that: The total number of gate circuits of various types in the integrated circuit to be analyzed is F, where F1, F2, ..., F M The number of gate circuits of each type, F1+F2+…+ F M =N.

5. The method for simulating equivalent fault injection in integrated circuit single-event soft error according to claim 4, characterized in that: Selecting the i-th type of ground-based accelerator test particle, and based on the type and energy parameters, selecting the corresponding j-th type of gate unit to perform particle injection simulation, the area S of the single-particle sensitive region when the i-th type of particle is incident on the j-th type of gate unit is obtained. i，j and output response pulse width W i，j and height H i，j .

6. The method for simulating equivalent fault injection in integrated circuit single-event soft error according to claim 5, characterized in that: The injection probability of each gate cell is determined. Injected gate cells are randomly selected based on the proportion of each gate cell's area to the total area of ​​the integrated circuit. Each gate cell contains a transistor and an injection node. The probability of randomly selecting any gate cell is determined based on the proportion of the gate cell's area to the total area. The injection probability of each transistor is Pm. The calculated parameters of the injected gate cell, corresponding to the transistor at the injection node, include: Effective number of particles injected into a gate cell, probability of injecting into a certain instantiated gate, probability of a transistor being injected into a gate cell, and effective probability of injected particles into a device.

7. The method for simulating equivalent fault injection in integrated circuit single-event soft error according to claim 6, characterized in that: The number of fault injections effectively injected into a single gate cell of type j is calculated as: particle injection amount φ × sensitive area S of the gate cell of type j. i，j ; The effective number of particles injected into a gate cell is the product of the number of injected particles, the ratio of the gate cell area to the total area of ​​the integrated circuit; The probability of injecting a certain instantiated gate is the ratio of the instantiated gate cell area to the gate cell area. The probability of a transistor being injected into a gate cell is the ratio of the transistor area to the gate cell area. The effective probability of particle injection within the device is the ratio of the area of ​​the sensitive region to the area of ​​the transistor.

8. The method for simulating equivalent fault injection in integrated circuit single-event soft error according to claim 7, characterized in that: The single-event soft error section of the computational integrated circuit under the nth type of particle is the ratio of the sum of the soft error numbers of each gate node to the flux φ.

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