Method for checking semiconductor device layout design rules

Abstract

The application provides a semiconductor device layout design rule checking method, which comprises the following steps: firstly, judging the area where each edge of the to-be-checked graph is located; then, performing corresponding design rule checking according to the area where each edge of the to-be-checked graph is located, so as to judge whether the to-be-checked graph conforms to the design rule, wherein, if the edge of the to-be-checked graph is located in a storage area, the checking is performed according to the storage area design rule; if the edge of the to-be-checked graph is located in a logic area, the checking is performed according to the logic area design rule; and if the edge of the to-be-checked graph is located in both the storage area and the logic area, the checking is performed according to the storage area design rule. In this way, all edges of the to-be-checked graph can be comprehensively checked according to corresponding design rules, meanwhile, each edge of the to-be-checked graph is checked according to only one design rule, so that the error in the checking process can be reduced, the checking time is shortened, and the design efficiency of the layout is improved.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing technology, and in particular to a method for checking semiconductor device layout design rules. Background Technology

[0002] In integrated circuit manufacturing, wafer fabs need to define geometric constraints for the same process layer and between different process layers to meet chip manufacturing yield requirements based on different process parameters. This collection of geometric constraints is called the Design Rule Manual (DRM). Development engineers are responsible for implementing each constraint in the DRM into the Design Rule Check (DRC) deck. After receiving the DRC deck, layout engineers need to use it to perform a Design Rule Check (DRC) on the designed layout.

[0003] Design Rule Check (DRC) arose alongside the circuit design of semiconductor devices. To ensure the reliability of the layout design process, DRC checks are essential. However, existing DRC methods typically check all edges of the graphic under inspection according to a single design rule, or divide the graphic into two parts by different layout area boundaries, and then check each part according to different rules. This means that a single edge of the graphic might be checked under two different design rules, leading to a higher error rate during the check process, increasing check time, and impacting layout design efficiency. Summary of the Invention

[0004] The purpose of this invention is to provide a method for checking semiconductor device layout design rules, so as to reduce errors during the checking process.

[0005] To address the aforementioned technical problems, this invention provides a method for checking semiconductor device layout design rules, comprising:

[0006] A semiconductor device layout is provided, the semiconductor device layout having a memory area and a logic area, the logic area being arranged around the memory area, the semiconductor device layout including a plurality of patterns to be inspected, each pattern to be inspected having at least four edges, the edges of the patterns to be inspected being located in the memory area and / or the logic area;

[0007] Determine the region where each edge of the graphic to be inspected is located;

[0008] The design rules are checked according to the region where each edge of the graphic to be checked is located to determine whether the graphic to be checked conforms to the design rules. Specifically, if the edge of the graphic to be checked is located in the storage area, it is checked according to the storage area design rules; if the edge of the graphic to be checked is located in the logic area, it is checked according to the logic area design rules; and if the edge of the graphic to be checked is located in both the storage area and the logic area, it is checked according to the storage area design rules.

[0009] Optionally, in the method for checking semiconductor device layout design rules, the method for determining the region where each edge of the pattern to be checked is located includes:

[0010] Determine whether the storage area has the edge of the graphic to be inspected. If not, it is determined that the edge of the graphic to be inspected is located in the logic area. If yes, it is further determined whether the edge of the graphic to be inspected in the storage area is a complete edge. If yes, it is determined that the edge of the graphic to be inspected is located in the storage area. If not, it is determined that the edge of the graphic to be inspected is located in both the storage area and the logic area.

[0011] Optionally, in the method for checking the semiconductor device layout design rules, the method for determining whether the edge of the storage area is a complete edge of the graphic to be checked includes: determining whether the edge of the graphic to be checked in the storage area and the edge of the graphic to be checked in the logic area are spliced ​​together and spliced ​​on the same straight line; if not, the edge of the graphic to be checked in the storage area is determined to be a complete edge; if so, the edge of the graphic to be checked in the storage area is determined to be an incomplete edge.

[0012] Optionally, in the method for checking semiconductor device layout design rules, checking the design rules for each edge of the graphic to be checked includes checking the dimensions of each edge of the graphic to be checked.

[0013] Optionally, in the method for checking semiconductor device layout design rules, the size check includes width checking between two sides of the same pattern to be checked and spacing checking between adjacent patterns to be checked.

[0014] Optionally, in the method for checking semiconductor device layout design rules, the width design rules between the two sides of the pattern to be checked are the same in the design rules of the pattern to be checked in the same area.

[0015] Optionally, in the method for checking semiconductor device layout design rules, the spacing design rules between adjacent patterns to be checked in the same area are the same. Optionally, in the method for checking semiconductor device layout design rules, the shape of the pattern to be checked is rectangular or L-shaped.

[0016] Optionally, in the method for checking semiconductor device layout design rules, the design rules are checked on the pattern to be checked using an electronic design automation physical verification tool.

[0017] Optionally, in the method for checking the layout design rules of the semiconductor device, the semiconductor device is a flash memory or a static random access memory.

[0018] In the semiconductor device layout design rule checking method provided by this invention, the location of each edge of the pattern to be checked is first determined. Then, a corresponding design rule check is performed based on the location of each edge of the pattern to be checked to determine whether the pattern conforms to the design rules. Specifically, if the edge of the pattern to be checked is located in the memory area, it is checked according to the memory area design rules; if the edge of the pattern to be checked is located in the logic area, it is checked according to the logic area design rules; and if the edge of the pattern to be checked is located in both the memory area and the logic area, it is checked according to the memory area design rules. In this way, all edges of the pattern to be checked can be comprehensively checked according to the corresponding design rules. At the same time, each edge of the pattern to be checked is checked according to only one design rule, which can reduce errors during the checking process, shorten the checking time, and improve the layout design efficiency. Attached Figure Description

[0019] Figure 1 This is a flowchart illustrating the method for checking semiconductor device layout design rules according to an embodiment of the present invention.

[0020] Figures 2 to 5 This is a schematic diagram of the layout formed in the method for checking semiconductor device layout design rules according to an embodiment of the present invention;

[0021] The reference numerals in the attached figures are explained as follows:

[0022] 101 - Storage area; 102 - Logic area; 110 - Graphic to be inspected; 110a, 110b, 110c - Edges of the graphic to be inspected. Detailed Implementation

[0023] The method for checking semiconductor device layout design rules proposed in this invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. The advantages and features of this invention will become clearer from the following description. It should be noted that the drawings are all in a very simplified form and use non-precise scales, and are only used to facilitate and clarify the illustration of the embodiments of this invention.

[0024] Figure 1 This is a flowchart illustrating a method for checking semiconductor device layout design rules according to an embodiment of the present invention. Figure 1 As shown, this embodiment provides a method for checking semiconductor device layout design rules, including:

[0025] Step S1: Provide a semiconductor device layout, the semiconductor device layout having a memory area and a logic area, the logic area being arranged around the memory area, the semiconductor device layout including a plurality of patterns to be inspected, the patterns to be inspected having at least four edges, the edges of the patterns to be inspected being located in the memory area and / or the logic area;

[0026] Step S2: Determine the region where each edge of the graphic to be inspected is located;

[0027] Step S3: Perform corresponding design rule checks based on the region where each edge of the graphic to be checked is located to determine whether the graphic to be checked conforms to the design rules. Specifically, if the edge of the graphic to be checked is located in the storage area, it is checked according to the storage area design rules; if the edge of the graphic to be checked is located in the logic area, it is checked according to the logic area design rules; and if the edge of the graphic to be checked is located in both the storage area and the logic area, it is checked according to the storage area design rules.

[0028] Figures 2 to 5 This is a schematic diagram of the layout formed in the semiconductor device layout design rule inspection method of this embodiment of the invention. The following will refer to the attached diagram. Figures 2 to 5 The method for checking semiconductor device layout design rules provided in this embodiment will be described in more detail.

[0029] First, perform step S1, refer to Figure 2 As shown, a semiconductor device layout is provided, the semiconductor device layout having a memory region 101 and a logic region 102, the logic region 102 being disposed around the memory region 101, the semiconductor device layout including a plurality of patterns to be inspected 110, each pattern to be inspected having at least four edges, the edges of the pattern to be inspected 110 being located in the memory region 101 and / or the logic region 102, that is, any edge of the pattern to be inspected 110 can be located in the memory region 101, or in the logic region 102, or extend from the memory region 101 to the logic region 102 (located in both the memory region and the logic region).

[0030] In this embodiment, the semiconductor device can be a flash memory or a static random access memory (SRAM), that is, the semiconductor device layout provided in this embodiment can be applied to a flash memory or a static random access memory (SRAM).

[0031] In this embodiment, as Figure 2 As shown, the shape of the pattern 110 to be inspected is rectangular or L-shaped. The storage area 101 and the logic area 102 each have a rectangular and / or L-shaped pattern 110 to be inspected.

[0032] Next, proceed to step S2, referring to... Figures 3-5As shown, the region where each edge of the graphic to be inspected 110 is located is determined. Specifically, the method for determining the region where each edge of the graphic to be inspected 110 is located includes: determining whether the storage area 101 has an edge of the graphic to be inspected 110; if not, it is determined that the edge of the graphic to be inspected 110 is located in the logic area 102; if yes, it is further determined whether the edge of the graphic to be inspected 110 in the storage area 101 is a complete edge; if yes, it is determined that the edge of the graphic to be inspected 110 is located in the storage area 101; if no, it is determined that the edge of the graphic to be inspected 110 is located in both the storage area 101 and the logic area 102.

[0033] For example, such as Figures 3-5 As shown, storage area 101 has edge 110a of the graphic 110 to be inspected, and logic area has edge 110b and edge 110c of the graphic 110 to be inspected. By determining whether each edge of the graphic 110 to be inspected is located in storage area 101 or logic area 102, the graphic 110 to be inspected can be checked according to the corresponding design rules based on the area where each edge of the graphic 110 to be inspected is located.

[0034] Furthermore, the method for determining whether an edge of the storage area 101 is a complete edge of the graphic 110 to be inspected includes: determining whether the edge of the graphic 110 to be inspected in the storage area 101 and the edge of the graphic 110 to be inspected in the logic area 102 are joined and joined on the same straight line; if not, then the edge of the graphic 110 to be inspected in the storage area 101 is determined to be a complete edge; if so, then the edge of the graphic 110 to be inspected in the storage area 101 is determined to be a non-complete edge. For example, such as... Figure 4 As shown, if the edge 110a of the graphic to be inspected in storage area 101 is joined with the edge 110b of the graphic to be inspected in logic area 110 and they are joined on the same straight line, then the edge 110a of the graphic to be inspected in storage area 101 is determined to be an incomplete edge.

[0035] Next, step S3 is executed, performing corresponding design rule checks based on the region where each edge of the graphic 110 to be checked is located to determine whether the graphic 110 conforms to the design rules. Specifically, if an edge of the graphic 110 to be checked is located in storage area 101, it is checked according to the design rules of storage area 101; if an edge of the graphic 110 to be checked is located in logic area 102, it is checked according to the design rules of logic area 102; and if an edge of the graphic 110 to be checked is located in both storage area 101 and logic area 102, it is checked according to the design rules of storage area 101. In this way, all edges of the graphic 110 to be checked can be comprehensively checked according to the corresponding design rules. At the same time, each edge of the graphic 110 to be checked is checked according to only one design rule, which can reduce errors during the checking process, shorten the checking time, and improve the design efficiency of the layout.

[0036] In this embodiment, the design rules for the storage area are stricter than those for the logic area. Generally, if the edge of the graphic 110 to be inspected extends from the storage area to the logic area 102, then the design of the edge of the graphic to be inspected must meet the design rules of the storage area 101. Therefore, if the edge of the graphic 110 to be inspected is located in both the storage area 101 and the logic area 102, it will be inspected according to the design rules of the storage area 101, which can avoid errors during the inspection process.

[0037] In this embodiment, the corresponding design rule check for each edge of the graphic to be inspected 110 includes: a size check for each edge of the graphic to be inspected 110. The size check includes checking the width 'a' between two edges of the same graphic to be inspected 110 and checking the spacing 'b' between adjacent graphics to be inspected 110. In the design rules of the graphic to be inspected, the width design rule between two edges of the graphic to be inspected 110 in the same region is the same; that is, the width between two edges of the graphic to be inspected 110 in the same region can be different, as long as the width between two edges of the graphic to be inspected 110 in the same region meets the minimum value of the width design rule. For example, the width between two edges of the graphic to be inspected 110 in storage area 101 meets the minimum value of the design rule, but the width between two edges of the graphic to be inspected 110 in storage area 101 can be different. Alternatively, the width between two edges of the graphic to be inspected 110 in logic area 102 meets the minimum value of the width design rule, but the width between two edges of the graphic to be inspected 110 in logic area 102 can be different. The spacing design rules are the same for adjacent graphics 110 to be inspected in the same area. That is, the spacing between adjacent graphics 110 to be inspected in the same area can be different, as long as the spacing between adjacent graphics 110 to be inspected in the same area meets the minimum value of the spacing design rules.

[0038] In this embodiment, design rule checks can be implemented by editing code files using EDA (Electronic Design Automation) physical verification tools (such as calibre).

[0039] In summary, the semiconductor device layout design rule checking method provided in this embodiment of the invention first determines the region where each edge of the graphic to be checked is located, and then performs corresponding design rule checks based on the region where each edge of the graphic to be checked is located to determine whether the graphic to be checked conforms to the design rules. Specifically, if the edge of the graphic to be checked is located in the memory region, it is checked according to the memory region design rules; if the edge of the graphic to be checked is located in the logic region, it is checked according to the logic region design rules; and if the edge of the graphic to be checked is located in both the memory region and the logic region, it is checked according to the memory region design rules. In this way, all edges of the graphic to be checked can be comprehensively checked according to the corresponding design rules. At the same time, each edge of the graphic to be checked is checked according to only one design rule, which can reduce errors during the checking process, shorten the checking time, and improve the layout design efficiency.

[0040] The above description is merely a description of preferred embodiments of the present invention and is not intended to limit the scope of the present invention in any way. Any changes or modifications made by those skilled in the art based on the above disclosure shall fall within the protection scope of the claims.

Claims

1. A method for checking semiconductor device layout design rules, characterized in that, include: A semiconductor device layout is provided, the semiconductor device layout having a memory area and a logic area, the logic area being arranged around the memory area, the semiconductor device layout including a plurality of patterns to be inspected, each pattern to be inspected having at least four edges, the edges of the patterns to be inspected being located in the memory area and / or the logic area; Determine the region where each edge of the graphic to be inspected is located; The design rules are checked according to the region where each edge of the graphic to be checked is located to determine whether the graphic to be checked conforms to the design rules. Specifically, if the edge of the graphic to be checked is located in the storage area, it is checked according to the storage area design rules; if the edge of the graphic to be checked is located in the logic area, it is checked according to the logic area design rules; and if the edge of the graphic to be checked is located in both the storage area and the logic area, it is checked according to the storage area design rules.

2. The method for checking semiconductor device layout design rules as described in claim 1, characterized in that, The method for determining the region where each edge of the graphic to be inspected is located includes: Determine whether the storage area has the edge of the graphic to be inspected. If not, it is determined that the edge of the graphic to be inspected is located in the logic area. If yes, it is further determined whether the edge of the graphic to be inspected in the storage area is a complete edge. If yes, it is determined that the edge of the graphic to be inspected is located in the storage area. If not, it is determined that the edge of the graphic to be inspected is located in both the storage area and the logic area.

3. The method for checking semiconductor device layout design rules as described in claim 2, characterized in that, The method for determining whether the edge of the storage area is a complete edge of the graphic to be inspected includes: determining whether the edge of the graphic to be inspected in the storage area and the edge of the graphic to be inspected in the logic area are spliced ​​together and spliced ​​on the same straight line; if not, the edge of the graphic to be inspected in the storage area is determined to be a complete edge; if so, the edge of the graphic to be inspected in the storage area is determined to be an incomplete edge.

4. The method for checking semiconductor device layout design rules as described in claim 1, characterized in that, The corresponding design rule check for each edge of the graphic to be inspected includes: size check of each edge of the graphic to be inspected.

5. The method for checking semiconductor device layout design rules as described in claim 4, characterized in that, The size inspection includes checking the width between two sides of the same graphic to be inspected, and checking the spacing between adjacent graphics to be inspected.

6. The method for checking semiconductor device layout design rules as described in claim 5, characterized in that, In the design rules of the graphic to be inspected, the width design rules between the two sides of the graphic to be inspected in the same area are the same.

7. The method for checking semiconductor device layout design rules as described in claim 5, characterized in that, In the design rules for the graphics to be inspected, the spacing between adjacent graphics to be inspected in the same area follows the same design rules.

8. The method for checking semiconductor device layout design rules as described in claim 1, characterized in that, The shape of the graphic to be inspected is rectangular or L-shaped.

9. The method for checking semiconductor device layout design rules as described in claim 1, characterized in that, The design rules are checked on the graphic to be inspected using an electronic design automation physical verification tool.

10. The method for checking semiconductor device layout design rules as described in any one of claims 1 to 9, characterized in that, The semiconductor device is a flash memory or a static random access memory.

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