A memory-computing integrated static control configuration method

Abstract

The application discloses a memory-computing integrated static control configuration method, and belongs to the field of memory computing. The method comprises the following steps: S1: before calculation, a compiler completes weight deployment, determines master-slave relationship, and modifies a slave state table and a master state table; S2: in the calculation process, a slave device receives master device data and modifies the slave state table; S3: after the slave device completes calculation, a completion signal is sent to the master device, and the master state table is modified; and S4: after the master device receives completion signals of all slave devices, the current calculation period is immediately ended, and control of the next calculation period is started. After each calculation is completed, the slave device sends a completion signal to the master device, the master device immediately ends the current calculation period after receiving completion signals of all slave devices, and control of the next calculation period is started, so that the complex problem of memory-computing integrated architecture calculation control is effectively solved.

Description

Technical Field

[0001] This invention relates to the field of storage technology, and in particular to a static control configuration method for integrated storage and computing. Background Technology

[0002] With the rapid growth of data volume, greater storage capacity and computing power are needed to support neural network applications. To overcome the memory bandwidth bottleneck caused by the separation of computation and storage in the traditional von Neumann architecture, more and more research is focusing on high-density compute-storage integrated architectures. This architecture maximizes the performance efficiency of the hardware architecture by tightly integrating computation and storage, reducing the additional memory access energy consumption and bandwidth requirements caused by the frequent movement of data between storage and computation components.

[0003] The emerging non-volatile memory, resistive random access memory (ReRAM), stores data using electrical conductance values ​​and achieves in-situ computation through multiplication and accumulation based on Ohm's law—a capability absent in traditional memory. In the traditional von Neumann architecture, weights and features must be transported simultaneously for computation. However, ReRAM-based neural network accelerators convert input vectors into voltages applied to the ReRAM word lines. Another weight input is pre-mapped to the conductance of each ReRAM cell, and the accumulated current on the bit lines represents the dot product of the two vectors, enabling in-situ processing and significantly reducing data bandwidth pressure while improving performance.

[0004] Currently, computational flow control in in-memory computing accelerator architectures remains a significant challenge. Because on-chip weights maintain fixed positions during network inference, a large number of memristor components are required to meet the deployment needs of neural network weights. Mainstream in-memory computing accelerators typically employ hierarchical topologies, dividing the circuit into functional modules of varying sizes from top to bottom. Weight mapping requires consideration of the interconnectivity between modules to optimize data flow, which to some extent limits the design methodology of the accelerator architecture. Summary of the Invention

[0005] The purpose of this invention is to provide a static control configuration method for in-memory computing to solve the technical problem of complex computing control in in-memory computing architecture.

[0006] This invention is achieved using the following technical solution: a static control configuration method for in-memory computing, comprising the following steps:

[0007] S1: Before the calculation begins, the compiler completes the weight deployment, determines the master-slave relationship, and modifies the slave state table and the master state table;

[0008] S2: During the calculation process, the slave device receives data from the master device and modifies the slave status table;

[0009] S3: After the slave device completes the calculation, it sends a completion signal to the master device and modifies the master status table;

[0010] S4: After receiving completion signals from all slave devices, the master device immediately ends the current calculation cycle and begins control of the next calculation cycle.

[0011] Furthermore, the master and slave devices employ a ReRAM-based cross-connected computing array, and control is achieved through a slave status table and a master status table.

[0012] Furthermore, the status table includes a slave device index, a master device index, and a valid signal, wherein the slave device index indicates the current location of the in-memory array; the master device index is used to record the master device information to which the current in-memory array belongs; and the valid signal is used to indicate whether the current in-memory array is valid in the computing cycle.

[0013] Furthermore, the master state table includes a master array index, a state signal, and a completion delay signal. The master array index is used to represent the current in-memory array information; the state signal is represented by a vector, where each bit of the vector represents an in-memory array state; and the completion delay signal indicates whether the computation state is complete.

[0014] Furthermore, step S1 specifically involves: before the calculation begins, the compiler completes the weight deployment, determines the master-slave relationship of the storage array based on the deployment location of the weights, modifies the master device index in the slave status table accordingly, and sets the completion delay signal in the master status table to 1.

[0015] Furthermore, step S2 specifically involves: during the calculation process, when the slave device receives data from the master device, it sets the corresponding valid signal in the status table to 1.

[0016] Furthermore, step S3 specifically involves: after the slave device completes its calculation, it looks up the master device index in the status table and sends a completion signal to the master device. After receiving the signal, the master device sets the corresponding position of the status signal vector in the master status table to 0.

[0017] Furthermore, step S4 specifically involves: when the status signal value in the main status table becomes 0, that is, when all bits in the status signal vector become 0, it indicates that the current in-memory array has completed its calculation. The completion delay signal of the corresponding in-memory array in the main status table is set to 0, the completion trigger signal is output to the main device array, the current calculation cycle ends immediately, and the control of the next calculation cycle begins.

[0018] The beneficial effects of this invention are as follows: After each calculation is completed, the slave device sends a completion signal to the master device. After receiving the completion signals from all slave devices, the master device immediately ends the current calculation cycle and begins the control of the next calculation cycle, effectively solving the complex problem of computing control in in-memory computing architecture. Attached Figure Description

[0019] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on the structures shown in these drawings without creative effort.

[0020] Figure 1 This is a flowchart of the present invention. Detailed Implementation

[0021] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. The components of the embodiments of the present invention described and shown in the accompanying drawings can generally be arranged and designed in various different configurations.

[0022] It should be noted that similar labels and letters in the following figures indicate similar items. Therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures.

[0023] The following detailed description of some embodiments of the present invention is provided in conjunction with the accompanying drawings. Unless otherwise specified, the following embodiments and features can be combined with each other.

[0024] Example 1

[0025] See Figure 1 A method for configuring static control of in-memory computing includes the following steps:

[0026] S1: Before the calculation begins, the compiler completes the weight deployment, determines the master-slave relationship, and modifies the slave state table and the master state table;

[0027] S2: During the calculation process, the slave device receives data from the master device and modifies the slave status table;

[0028] S3: After the slave device completes the calculation, it sends a completion signal to the master device and modifies the master status table;

[0029] S4: After receiving completion signals from all slave devices, the master device immediately ends the current calculation cycle and begins control of the next calculation cycle.

[0030] In this embodiment, the master device and slave device adopt a ReRAM-based cross-connected memory array, and control is achieved through a slave status table and a master status table, wherein:

[0031] See Table 1 for the status table:

[0032] Table 1 is from the status table

[0033]

[0034] Specifically, the status table includes a slave device index, a master device index, and a valid signal. The slave device index indicates the current location of the in-memory array; the master device index records the master device information to which the current in-memory array belongs; and the valid signal indicates whether the current in-memory array is valid during the computing cycle.

[0035] The main status table is shown in Table 2:

[0036] Table 2 Main Status Table

[0037]

[0038] Specifically, the master state table includes a master array index, a state signal, and a completion delay signal. The master array index is used to represent the current in-memory array information. The state signal is represented by a 64-bit vector, where each bit of the vector represents an in-memory array state. The completion delay signal indicates whether the computation state is complete.

[0039] The computational execution logic of this invention is as follows:

[0040] 1. Before the calculation begins, the compiler completes the weight deployment, determines the master-slave relationship of the storage array based on the deployment location of the weights, modifies the master device index in the slave status table accordingly, and sets the completion delay signal in the master status table to 1.

[0041] 2. During the calculation process, when the slave device receives data from the master device, it will set the corresponding valid signal in the status table to 1.

[0042] 3. After the slave device completes its calculation, it looks up the master device index in the status table and sends a completion signal to the master device. After receiving the signal, the master device sets the corresponding position of the status signal vector in the master status table to 0.

[0043] 4. When the status signal value in the master status table becomes 0, that is, when all bits in the status signal vector become 0, it means that the current in-memory array has completed the calculation. The completion delay signal of the corresponding in-memory array in the master status table is set to 0, the completion trigger signal is output to the master device array, the current calculation cycle ends immediately, and the control of the next calculation cycle begins.

[0044] It should be noted that, for the sake of simplicity, the foregoing embodiments are all described as a series of actions. However, those skilled in the art should understand that this application is not limited to the described order of actions, because according to this application, some steps can be performed in other orders or simultaneously. Furthermore, those skilled in the art should also understand that the embodiments described in the specification are preferred embodiments, and the actions involved are not necessarily essential to this application.

[0045] The above embodiments describe the basic principles, main features, and advantages of the present invention. Those skilled in the art should understand that the present invention is not limited to the above embodiments. The embodiments and descriptions in the specification are merely illustrative of the principles of the invention. Modifications and variations made by those skilled in the art without departing from the spirit and scope of the invention should be within the protection scope of the appended claims.

Claims

1. A method for a memory-compute-in-one static control configuration, characterized in that, The method comprises the following steps: S1: before calculation, the compiler completes weight deployment, determines master-slave relationship according to the deployment position of the weight, and modifies the slave state table and the master state table; S2: during calculation, the slave device receives the master device data and modifies the slave state table; S3: after the slave device completes calculation, the master device index is found through the slave state table, and a completion signal is sent to the master device; after receiving the signal, the master device modifies the master state table; S4: after receiving the completion signals of all slave devices, the master device immediately ends the current calculation period and starts the control of the next calculation period; The slave state table comprises a slave device index, a master device index and a valid signal, wherein the slave device index represents the position of the current memory-computing array; the master device index records the master device information to which the slave device belongs; and the valid signal represents whether the current memory-computing array is valid in the calculation period. The master state table comprises a master array index, a state signal and a completion delay signal, wherein the master array index represents the current memory-computing array information; the state signal is represented by a vector, and each bit of the vector represents a memory-computing array state; and the completion delay signal represents whether the calculation state is completed. The modification of the slave state table in step S1 comprises modifying the master device index in the slave state table according to the determined master-slave relationship; and the modification of the master state table comprises setting the completion delay signal in the master state table to 1. The modification of the slave state table in step S2 comprises setting the corresponding valid signal in the slave state table to 1. The modification of the master state table in step S3 comprises setting the position corresponding to the state signal in the master state table to 0 according to the received completion signal.

2. The method of claim 1, wherein, The master device and the slave device adopt a memory-computing array based on a ReRAM cross circuit, and the control is realized through the slave state table and the master state table.

3. The method of claim 1, wherein, In step S4, when the state signal value in the master state table becomes 0, that is, all bits in the state signal vector become 0, it represents that the current memory-computing array is completed, the completion delay signal of the corresponding memory-computing array in the master state table is set to 0, a completion trigger signal is output to the master device array, the current calculation period is immediately ended, and the control of the next calculation period is started.

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